WO2019105086A1 - 显示基板及其制作方法、显示面板、显示装置 - Google Patents

显示基板及其制作方法、显示面板、显示装置 Download PDF

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Publication number
WO2019105086A1
WO2019105086A1 PCT/CN2018/103643 CN2018103643W WO2019105086A1 WO 2019105086 A1 WO2019105086 A1 WO 2019105086A1 CN 2018103643 W CN2018103643 W CN 2018103643W WO 2019105086 A1 WO2019105086 A1 WO 2019105086A1
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Prior art keywords
insulating layer
layer
groove
insulating
sub
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PCT/CN2018/103643
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English (en)
French (fr)
Inventor
辛燕霞
阳智勇
陈飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18880066.8A priority Critical patent/EP3719844A4/en
Priority to US16/465,311 priority patent/US10763450B2/en
Publication of WO2019105086A1 publication Critical patent/WO2019105086A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to a display substrate, a method of fabricating the same, a display panel, and a display device.
  • OLED Organic Light-Emitting Diode
  • LCDs liquid crystal displays
  • advantages such as light weight, small thickness, low power consumption, bright colors, fast response, wide viewing angle, and soft display.
  • Bonding is an important step in the overall process of OLED display. Binding refers to the pad (Pad) and driver integrated circuit in the Bonding area of the OLED panel during the production process of the OLED display.
  • Integrated Circuit, IC is a pin-connected process that is connected and connected by an Anisotropic Conductive Film (ACF) according to a certain workflow.
  • ACF Anisotropic Conductive Film
  • Embodiments of the present disclosure provide a display substrate, a method of fabricating the same, a display panel, and a display device.
  • At least one embodiment of the present disclosure provides a display substrate including a bonding region, a plurality of pads spaced apart in the bonding region, and an insulating layer for spacing the pads. a groove formed in the insulating layer between at least two adjacent pads.
  • the groove is disposed between any two adjacent pads.
  • the pad includes an input pad and an output pad
  • the binding area includes a first area and a second area respectively disposed, where the input pad is located In the first region, the output pad is located in the second region, and the groove is located between the first region and the second region.
  • the insulating layer includes a plurality of sub-insulating layers sequentially disposed on the substrate, the depth of the grooves being greater than or equal to the uppermost of the plurality of sub-insulating layers The thickness of the sub-insulating layer.
  • the depth of the groove is greater than or equal to a sum of thicknesses of the two sub-insulation layers located at the top of the plurality of sub-insulation layers.
  • the depth of the groove is equal to the thickness of the insulating layer.
  • the method further includes a base substrate, and a buffer layer, an active layer, a first insulating layer, a first metal layer, and a second insulating layer disposed on the base substrate in sequence a second metal layer, an interlayer insulating layer, a source/drain metal layer, a flat layer, an anode, a pixel defining layer, a light emitting layer, and a cathode, wherein the groove has a depth greater than or equal to the second insulating layer and the layer The sum of the thicknesses of the insulating layers.
  • At least one embodiment of the present disclosure further provides a display panel, including: a display substrate; the display substrate includes: a binding area; a plurality of pads spaced apart in the binding area; An insulating layer of the pad, a recess formed in the insulating layer between at least two adjacent ones of the pads.
  • the groove is disposed between any two adjacent pads.
  • the pad includes an input pad and an output pad
  • the binding area includes a first area and a second area respectively disposed, where the input pad is located In the first region, the output pad is located in the second region, and the groove is located between the first region and the second region.
  • the insulating layer includes a plurality of sub-insulating layers sequentially disposed on the substrate, the depth of the grooves being greater than or equal to the uppermost of the plurality of sub-insulating layers The thickness of the sub-insulating layer.
  • the depth of the groove is greater than or equal to a sum of thicknesses of the two sub-insulation layers located at the top of the plurality of sub-insulation layers.
  • the depth of the groove is equal to the thickness of the insulating layer.
  • the method further includes a base substrate, and a buffer layer, an active layer, a first insulating layer, a first metal layer, and a second insulating layer disposed on the base substrate in sequence a second metal layer, an interlayer insulating layer, a source/drain metal layer, a flat layer, an anode, a pixel defining layer, a light emitting layer, and a cathode, wherein the groove has a depth greater than or equal to the second insulating layer and the layer The sum of the thicknesses of the insulating layers.
  • At least one embodiment of the present disclosure also provides a display device including the display panel as described above.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, the method comprising:
  • An insulating layer and a plurality of pads are disposed on a bonding region of the display substrate, the plurality of pads are spaced apart, and the plurality of pads are separated by an insulating layer;
  • a recess is formed in the insulating layer between at least two adjacent ones of the pads.
  • the opening the groove includes:
  • an insulating layer having the recess is directly formed.
  • directly forming an insulating layer having the recess includes:
  • a sub-insulating layer is a sub-insulating layer of the insulating layer, and the insulating layer includes a plurality of sub-insulating layers sequentially disposed on the base substrate.
  • directly forming an insulating layer having the recess includes:
  • At least two insulating films are sequentially formed, and when the at least two insulating films are simultaneously patterned, the portion of the at least two insulating films located between at least two adjacent pads is removed.
  • At least two sub-insulating layers the at least two sub-insulating layers being at least two consecutive sub-insulating layers of the insulating layer, the insulating layer comprising a plurality of sub-insulating layers sequentially disposed on the base substrate.
  • the opening the groove includes:
  • a portion of the insulating layer between at least two adjacent pads is removed by a patterning process to form the recess.
  • the opening the groove includes:
  • the groove is formed between any two adjacent pads.
  • the opening the groove includes:
  • a groove is formed between the first area and the second area, the first area and the second area are two areas respectively disposed in the binding area, and the pad includes an input pad and an output pad, The input pad is located in the first area, and the output pad is located in the second area.
  • 1 is a schematic diagram of Bonding of an OLED panel
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • 3A is a schematic structural diagram of a binding area of a display substrate in the related art
  • 3B is a schematic structural view of a display area of a display substrate in the related art
  • FIG. 4 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of Bonding of an OLED panel.
  • reference numeral 10 in Fig. 1 denotes a display substrate (i.e., an OLED substrate), 20 is an ACF, and 30 is a driving IC.
  • the ACF 20 is applied to the binding area of the display substrate 10.
  • the driving IC 30 and the display substrate 10 are pressed together by the heater 40.
  • the pad Pad 101 located at the bonding region of the display substrate 10 and the pad (Pad) 301 of the driving IC 30 are turned on by the action of the ACF 20.
  • embodiments of the present disclosure provide a display substrate capable of flattening an ACF between a display substrate and a driver IC.
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a bonding region 100.
  • the bonding region 100 is provided with a plurality of spaced pads (Pad) 101 separated by an insulating layer 102, at least two adjacent Pads 101.
  • a groove 103 is formed in the insulating layer 102.
  • the groove 103 is opened by the insulating layer 102 between at least two adjacent pads of the Bonding region, so that the ACF can flow to the groove 103 when pressed. It is ensured that the ACF can be evenly distributed in the area between at least two adjacent Pads, thereby solving the problem of unevenness introduced by the ACF debinding between the display substrate and the driving IC, and avoiding the occurrence of bubbles caused by ACF unevenness, and ensuring The electrical connection performance between the display substrate and the driver IC is shown.
  • the foregoing display substrate structure provided by the embodiment of the present disclosure is mainly directed to an active matrix (AM) OLED, that is, the display substrate is an AMOLED display substrate.
  • the display substrate is an AMOLED display substrate.
  • the bonding region is provided with a thick insulating layer 102, which is easy to cause the ACF to be difficult to flatten.
  • the display substrate can also be used for a passive matrix (PM) OLED, that is, the display substrate is a PMOLED display substrate, which is not limited in this application.
  • PM passive matrix
  • a display substrate includes a display area and a binding area disposed around the display area.
  • the display area refers to a light-emitting area in which the display unit is disposed
  • the binding area is an area in which a Pad connected to the IC is disposed.
  • the bonding area 100 referred to in the embodiment of the present disclosure may be a bonding area of a driving IC (display), because the insulating layer 102 of other bonding areas is generally small in thickness, so the ACF is not affected, so generally no groove is required. 103.
  • the structure provided by the embodiment of the present disclosure may also be applied to other Bonding areas, which is not limited by the embodiment of the present disclosure.
  • the display substrate includes, in order from bottom to top, a substrate, a buffer layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second a metal layer, an interlayer insulating layer, a source/drain metal layer, a flat layer, an anode, a pixel defining layer, a light emitting layer, and a cathode.
  • the first metal layer and the second metal layer are used to form a gate line, a gate of a thin film transistor, a lead (including a Pad lead), and a storage capacitor one pole.
  • the first metal layer is used to form the gate line, the gate of the thin film transistor, the lead, and the like, and the second metal layer is used to form the storage capacitor one pole.
  • This design can ensure the realization of the large resolution panel.
  • the first metal layer and the second metal layer can also adopt other design methods.
  • the first metal layer is used to form the odd-numbered gate lines, the gates of the odd-line thin film transistors and the odd-numbered storage capacitors
  • the second metal layer is used to form the even-numbered gate lines, the gates of the even-numbered thin-film transistors, and the even-numbered rows.
  • One pole of the capacitor is formed on either of the first or second metal layers.
  • the source/drain metal layer is used to form a pad, a data line, a source/drain electrode of the thin film transistor, and another pole of the storage capacitor.
  • the insulating layer structure of the display substrate is large and the thickness is thick, which makes the ACF difficult to flatten.
  • the situation is particularly serious. Therefore, for the display substrate of such a structure, the groove 103 is formed in the insulating layer 102 of the bonding region 100, which can solve the problem that the ACF is difficult to flatten.
  • the insulating layer may include a plurality of sub-insulating layers sequentially disposed on the base substrate.
  • the insulating layer may include a buffer layer, a first insulating layer disposed on the base substrate from bottom to top. a second insulating layer and an interlayer insulating layer. At this time, the depth of the groove is greater than or equal to the thickness of the uppermost sub-insulating layer among the plurality of sub-insulating layers.
  • the depth of the groove 103 is greater than or equal to the sum of the thicknesses of the two sub-insulation layers located at the top of the plurality of sub-insulation layers, so that the depth of the groove can ensure smooth discharge of the ACF.
  • the insulating layer includes the foregoing buffer layer, the first insulating layer, the second insulating layer, and the interlayer insulating layer
  • the depth of the groove 103 is greater than or equal to the sum of the thicknesses of the second insulating layer and the interlayer insulating layer.
  • the display substrate can also be a bottom-gate thin film transistor, in which case the film structure is usually a substrate substrate, a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a flat layer, an anode, and a pixel definition. Layer, luminescent layer and cathode.
  • the insulating layer includes a gate insulating layer disposed on the base substrate, the depth of the groove being equal to the depth of the gate insulating layer. In this case, the insulating layer only includes the gate insulating layer, so that the depth of the recess is equal to the thickness of the insulating layer.
  • display substrates are typically designed with two metal layers as gate metal layers in order to cope with high resolution requirements.
  • the display substrate may include only one of the first metal layer and the second metal layer, and accordingly, the display substrate may include only one of the first insulating layer and the second insulating layer.
  • the insulating layer through which the groove passes is correspondingly reduced when the groove of the bonding region is subsequently designed.
  • the insulating layer includes a buffer layer, a gate insulating layer, and an interlayer insulating layer which are sequentially disposed on the base substrate, and the depth of the groove is greater than or equal to a sum of thicknesses of the gate insulating layer and the interlayer insulating layer.
  • the base substrate may be a transparent substrate such as a glass substrate, a silicon substrate, a plastic substrate, or the like.
  • the first metal layer, the second metal layer, and the source/drain metal layer may be made of the same or different materials.
  • the first metal layer, the second metal layer, and the source/drain metal layer may be made of molybdenum (Mo) or titanium (Ti)/aluminum (Al)/Ti, and the above materials can ensure stable metal layer performance and have a small The resistance.
  • the buffer layer, the first insulating layer, the second insulating layer, the gate insulating layer, and the interlayer insulating layer may each be a silicon nitride layer or a silicon oxynitride layer.
  • the above insulating layer is formed by using a silicon nitride layer or a silicon oxynitride layer, and on the other hand, the dielectric constant is high, and on the other hand, the thinning of these layers can be achieved.
  • the flat layer may be a resin layer.
  • the active layer may be made of amorphous silicon, microcrystalline silicon, or polycrystalline silicon.
  • the active layer may include an amorphous silicon layer disposed on the buffer layer and an N-type doped amorphous silicon layer disposed on the amorphous silicon layer.
  • the anode and the cathode may be an Indium Zinc Oxide (IZO) thin film electrode or an Indium Tin Oxide (ITO) thin film electrode.
  • IZO Indium Zinc Oxide
  • ITO Indium Tin Oxide
  • the light emitting layer may include a hole transporting sublayer, an organic light emitting sublayer, and an electron transporting sublayer.
  • the hole transporting sublayer, the organic light emitting sublayer, and the electron transporting sublayer are all made of an organic polymer material or an organic small molecule material.
  • the Pad 101 includes an input Pad and an output Pad.
  • the binding area 100 includes a first area 100A and a second area 100B which are respectively disposed, the input Pad is located in the first area 100A, and the output Pad is located in the second area 100B.
  • the groove 103 is located between the first region 100A and the second region 100B.
  • the Pad 101 since the Pad 101 is centrally disposed in two regions, and has a large vacant area between the two regions, it is possible to arrange only the first region 100A of the input Pad and the layout of the output pad.
  • a groove 103 is formed in a region between the two regions 100B. Since the area of the portion between the first region 100A and the second region 100B is relatively large, the opening of the groove 103 is relatively easy to perform pattern processing.
  • a groove 103 is formed between the pads 101, which causes a decrease in insulation performance between the Pads 101.
  • the Pad of the Bonding area of the driving IC includes the input Pad and the output Pad
  • the Bonding area of the FPC and the Pad of the Bonding area of the touch IC only include the output Pad, so the scheme is mainly For the Bonding area of the driver IC.
  • a groove 103 may be disposed between any two adjacent Pads 101.
  • a groove 103 is formed between any two Pads 101 to ensure that the area of the groove 103 is maximized, thereby ensuring sufficient space for the ACF to flow and avoiding difficulty in flattening the ACF.
  • the respective grooves 103 can communicate with each other to facilitate the flow of the ACF.
  • the recesses may be formed at any position of the insulating layer of the binding region as long as the insulation between the respective pads is not affected.
  • FIG. 3A is a schematic view showing a structure of a film layer of a binding region of a display substrate in the related art.
  • the substrate in the bonded area includes a base substrate 120, a buffer layer 121, a first insulating layer 122, a first metal layer (Pad lead) 125, a second insulating layer 123, an interlayer insulating layer 124, A source/drain metal layer (Pad 101) 126 and a flat layer 127.
  • FIG. 3A shows a film layer structure showing a substrate bonding region.
  • the film layer structure of the display substrate in the display region is as shown in FIG. 3B, and includes: a substrate substrate 120, and a buffer sequentially disposed on the substrate substrate 120.
  • the sequential arrangement means that the above-mentioned film layers are sequentially disposed on the base substrate 120.
  • the insulating layer 102 of the aforementioned bonding region includes the buffer layer 121, the first insulating layer 122, the second insulating layer 123, and the interlayer insulating layer 124 which are sequentially disposed on the base substrate 120.
  • a first metal layer 125 is disposed between the first insulating layer 122 and the second insulating layer 123.
  • the source/drain metal layer 126 and the flat layer 127 are disposed above the interlayer insulating layer 124, and the second insulating layer 123 and the interlayer insulating layer 124 are disposed.
  • a via 134 is provided through which the active drain metal layer 126 passes and is connected to the first metal layer 125.
  • the bonding region 100 is formed in a recess opened in the flat layer 127.
  • FIG. 4 is a schematic structural view of a film layer of a binding region of a display substrate according to an embodiment of the present disclosure, and FIG. 4 is a schematic cross-sectional view of FIG. 2 in the A-A' direction.
  • FIG. 4 differs from FIG. 3A in that a groove 103 is formed in the insulating layer.
  • the depth of the groove 103 is equal to the sum of the thicknesses of the second insulating layer 123 and the interlayer insulating layer 124.
  • the depth of the groove 103 is equal to the sum of the thicknesses of the second insulating layer 123 and the interlayer insulating layer 124, that is, the groove 103 penetrates the second insulating layer 123 and the interlayer insulating layer 124, and the bottom of the groove 103 is located at the first insulating layer 122.
  • a groove 103 is formed in the second insulating layer 123 and the interlayer insulating layer 124. Since the thickness of the interlayer insulating layer 124 is large, the depth of the groove 103 obtained is large, so that the fluidity requirement of the ACF can be satisfied.
  • the groove 103 is formed only on the second insulating layer 123 and the interlayer insulating layer 124, so that the depth requirement of the groove 103 can be satisfied, and at the same time, the process steps required for opening the groove 103 are minimized, and the groove 103 is formed.
  • the detailed process can be referred to the description of the following method embodiments.
  • the buffer layer 121 is disposed on the OLED substrate 120 to buffer the active layer disposed on the substrate 120, the first insulating layer 122, the second insulating layer 123, and the interlayer insulating layer 124.
  • the metal layer comprises the aforementioned first metal layer, second metal layer and source/drain metal layer.
  • FIG. 5 is a schematic view showing a structure of a film layer of a binding region of another display substrate according to an embodiment of the present disclosure
  • FIG. 5 is another schematic cross-sectional view of FIG. 2 in the A-A' direction.
  • the depth of the groove 103 is equal to the thickness of the insulating layer 102.
  • the groove 103 also penetrates the buffer layer 121, the first insulating layer 122, the second insulating layer 123, and the interlayer insulating layer 124 in the insulating layer 102, and the bottom of the groove 103 is located on the substrate substrate 120.
  • the depth of the groove 103 is the largest, thereby maximizing the fluidity of the ACF.
  • the groove 103 has a tendency to gradually widen from the bottom to the opening, and this design facilitates the patterning of the film layer.
  • the groove 103 in order to ensure that the groove 103 does not affect the insulation performance between the pads, there is a certain distance between the opening of the groove 103 and the edge of the Pad, for example, 5 mm or the like.
  • the embodiment of the present disclosure further provides a display panel including the display substrate as shown in any of FIGS. 2, 4, and 5.
  • the ACF can flow to the groove 103 when pressed, ensuring that the ACF can be at least two adjacent The area between the pads is evenly distributed, thereby solving the problem of unevenness introduced by the difficulty in discharging the ACF between the display substrate and the driving IC, avoiding the occurrence of bubbles in the ACF unevenness, and ensuring the electric power between the display substrate and the driving IC. Connection performance.
  • Embodiments of the present disclosure also provide a display device including a display panel as before.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the ACF can flow to the groove 103 when pressed, ensuring that the ACF can be at least two adjacent The area between the pads is evenly distributed, thereby solving the problem of unevenness introduced by the difficulty in discharging the ACF between the display substrate and the driving IC, avoiding the occurrence of bubbles in the ACF unevenness, and ensuring the electric power between the display substrate and the driving IC. Connection performance.
  • An embodiment of the present disclosure further provides a method for fabricating a display substrate, the method comprising: forming a plurality of spaced apart pads on a bonding region of a display substrate, the pads being separated by an insulating layer; at least two adjacent A groove is formed in the insulating layer between the pads.
  • FIG. 6 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present disclosure. Referring to Figure 6, the method includes:
  • Step 201 Providing a substrate.
  • the base substrate may be a transparent substrate such as a glass substrate, a silicon substrate, a plastic substrate, or the like.
  • Step 202 growing each film layer of the display substrate on the base substrate, and forming a groove in the binding region of the display substrate, the binding region is provided with a plurality of spaced Pads, and the Pads are separated by an insulating layer, at least two A groove is formed in the insulating layer between adjacent pads.
  • a groove is formed in the insulating layer between at least two adjacent pads, thereby avoiding difficulty in discharging the ACF.
  • the opening of the groove may include the following two implementations:
  • One implementation is that when the insulating layer is formed, the insulating layer having the groove is directly formed, that is, the insulating layer needs to further form the groove on the basis of the original shape.
  • Another implementation manner is that after the insulating layer is completed, a portion of the insulating layer between at least two adjacent pads is removed by a patterning process to form a recess.
  • the implementation provides two ways of opening the groove.
  • a groove is formed in the process of manufacturing the insulating layer. Since the insulating layer is also required to be patterned during the manufacturing process of the insulating layer, The groove of the portion of the insulating film layer is opened and can be simultaneously performed in the original patterning process. In the original patterning process, the groove is opened, and only the pattern of the mask plate needs to be updated, and no new process steps are required, so that the first method can save the process steps of the groove opening.
  • the second method is used to open the groove, and the groove is opened after the insulating layer is formed. This method does not need to update the pattern of the mask of the insulating film layer, but only needs a new mask to complete the concave.
  • the groove is opened, which can better control the shape and size of the groove formed.
  • the insulating layer having the groove is directly formed, including:
  • the first sub-insulating layer is a sub-insulating layer of the insulating layer, and the insulating layer includes a plurality of sub-insulating layers sequentially disposed on the base substrate.
  • the first sub-insulating layer is any one of the insulating layers, and any one of the insulating layers is treated as described above if a recess is to be formed.
  • the insulating layer having the groove is directly formed, including:
  • At least two insulating films are sequentially formed, and when at least two insulating films are simultaneously patterned, at least two insulating films are disposed at a portion between at least two adjacent pads to obtain at least two sub-insulating layers.
  • the at least two sub-insulating layers are at least two consecutive sub-insulating layers of the insulating layer, and the insulating layer includes a plurality of sub-insulating layers sequentially disposed on the base substrate.
  • the direct formation of the insulating layer having the grooves in the present application includes two ways, one way is to form the grooves layer by layer, and the other way is to form the grooves simultaneously by two or more layers.
  • the depth of the grooves is greater than or equal to the thickness of the uppermost sub-insulating layers of the plurality of sub-insulating layers.
  • the depth of the groove is greater than or equal to the sum of the thicknesses of the two sub-insulation layers located at the top of the plurality of sub-insulation layers, so that the depth of the groove can ensure smooth discharge of the ACF.
  • a groove may be formed on the two sub-insulation layers located at the uppermost among the plurality of sub-insulation layers.
  • the insulating layer having the groove is directly formed, which may include:
  • the first insulating film is formed, and when the first insulating film is patterned, the portion of the first insulating film between the at least two adjacent pads is removed to obtain a first sub-insulating layer, and the first sub-insulating layer is A second sub-insulating layer from top to bottom in the insulating layer.
  • the second sub-insulating layer is the uppermost sub-insulating layer among the plurality of sub-insulating layers. That is to say, in addition to forming the original pattern of the sub-insulating layer, the groove needs to be formed in the above-mentioned patterning process.
  • directly forming the insulating layer having the recess may include:
  • first sub-insulating layer and the second sub-insulating layer Forming a first insulating film and a second insulating film, and patterning the first insulating film and the second insulating film, removing portions of the first insulating film and the second insulating film between at least two adjacent pads And obtaining a first sub-insulating layer and a second sub-insulating layer, wherein the first sub-insulating layer and the second sub-insulating layer are the two sub-insulating layers at the top of the plurality of sub-insulating layers.
  • this method is applicable to the following two cases: First, the first sub-insulating layer and the second sub-insulating layer have the same pattern, and this case can be patterned by using a common mask.
  • the first sub-insulating layer is located under the second sub-insulating layer, and the projection of the pattern of the first sub-insulating layer on the substrate is in a projection of the pattern of the second sub-insulating layer on the substrate, which
  • the pattern processing is implemented by using a gray scale mask, so that part of the pattern can be simultaneously formed on the first sub-insulating layer and the second sub-insulating layer, and part of the pattern is formed only on the second sub-insulating layer.
  • the grooves may be formed on the uppermost two sub-insulating layers.
  • the ACF discharging can be ensured smoothly, and on the other hand, only two layers of the film are required. Layer graphics make it easier to implement. In this manner, the two film layers can be separately patterned, or the two film layers can be patterned together to form two sub-insulating layers.
  • the grooves may be formed on the uppermost four sub-insulating layers.
  • directly forming the insulating layer having the groove may further include:
  • a third insulating film is formed, and when the third insulating film is patterned, the portion of the third insulating film between at least two adjacent pads is removed to obtain a third sub-insulating layer, and the third sub-insulating layer is The fourth sub-insulation layer from top to bottom in the sub-insulation layer.
  • the fourth sub-insulating layer is a third sub-insulating layer from top to bottom among the plurality of sub-insulating layers.
  • the insulating layer having the groove is directly formed, and may further include:
  • the processing manners of the third sub-insulating layer and the fourth sub-insulating layer are the same as those of the first sub-insulating layer and the second sub-insulating layer, and are not described herein again.
  • the grooves can be formed on the uppermost four sub-insulating layers, thereby further ensuring smooth discharge of the ACF.
  • growing the respective film layers of the display substrate on the base substrate may include sequentially growing a buffer layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer on the base substrate. , an interlayer insulating layer, a source/drain metal layer, a flat layer, an anode, a pixel defining layer, a light emitting layer, and a cathode.
  • the first metal layer and the second metal layer are used to form a gate line, a gate of a thin film transistor, a lead (including a Pad lead), and a storage capacitor, for example, a first metal layer is used to form a lead, and the first The two metal layers form a gate line, a gate of the thin film transistor, and a storage capacitor.
  • the source and drain metal layers are used to form the drain and drain electrodes of the pad, the data line, the thin film transistor, and the other pole of the storage capacitor.
  • the thin film transistor is exemplified by a top-gate thin film transistor.
  • the display substrate may also be a bottom-gate thin film transistor, which is not limited in this application.
  • the materials of the respective film layers are as described above and will not be described herein.
  • the insulating layer may include four sub-insulating layers, which are a buffer layer, a first insulating layer, a second insulating layer, and an interlayer insulating layer, respectively.
  • the insulating layer having the groove is directly formed, which may include:
  • the portion of the second insulating layer between at least two adjacent Pads is removed.
  • the portion where the interlayer insulating layer is located between at least two adjacent Pads is removed.
  • directly forming the insulating layer having the groove may include:
  • portions where the second insulating layer and the interlayer insulating layer are located between at least two adjacent Pads are simultaneously removed.
  • the recess is formed on the second insulating layer and the interlayer insulating layer, and there are two ways of opening, one is divided into two steps, and when the second insulating layer is patterned, the second insulating is performed.
  • a groove is formed in the layer, and when the interlayer insulating layer is patterned, a groove is formed in the interlayer insulating layer, which is convenient to manufacture and has low process requirements.
  • the other is to complete the opening of the groove at one time.
  • a groove is formed on the interlayer insulating layer and the second insulating layer at one time, which can be completed in one step by dry etching. It can also be completed by two steps of wet etching (using different etching liquids to etch the interlayer insulating layer and the second insulating layer, respectively).
  • grooves are formed in the second insulating layer and the interlayer insulating layer. Since the thickness of the interlayer insulating layer is large, the depth of the obtained groove is large, so that the fluidity requirement of the ACF can be satisfied.
  • the insulating layer having the groove is directly formed, and may further include:
  • portions of the buffer layer between at least two adjacent Pads are simultaneously removed.
  • portions of the first insulating layer between at least two adjacent Pads are simultaneously removed.
  • the insulating layer having the groove is directly formed, and may further include:
  • the portion where the buffer layer and the first insulating layer are located between at least two adjacent Pads is simultaneously removed.
  • the portion where the buffer layer and the first insulating layer are located between at least two adjacent Pads is simultaneously removed.
  • the patterned patterns are difficult to be the same or satisfy the aforementioned size relationship (the film pattern of the lower film layer pattern on the substrate substrate is above the film layer pattern on the base substrate) In the above projection, it is usually realized by two film layers in one pattern.
  • the recess is formed on the buffer layer, the first insulating layer, the second insulating layer, and the interlayer insulating layer, and the opening manner is various: for example, each layer of the insulating layer is formed on the layer.
  • a groove is formed in the insulating layer.
  • a groove is formed for each of the two insulating layers.
  • grooves are formed in the three insulating layers.
  • grooves are formed in the four insulating layers.
  • dry etching or wet etching may be used, and when two or more layers of grooves are opened at one time, the dry etching may be performed in one step. It can also be done in two or more steps by wet etching (each film layer is etched separately with different etching solutions).
  • the depth of the groove is further deepened to maximize the fluidity of the ACF.
  • a groove is formed between any two adjacent Pads. Grooves are formed between any two Pads to ensure maximum groove area, thus ensuring sufficient space for the ACF to flow and avoiding the ACF being difficult to flatten.
  • the Pad includes an input Pad and an output Pad
  • the binding area includes a first area and a second area respectively set
  • the input Pad is located in the first area
  • the output Pad is located in the second area.
  • the recess is formed by: forming a groove between the first area and the second area, that is, the groove is located between the first area and the second area.

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Abstract

一种显示基板及其制作方法、显示面板、显示装置。显示基板包括绑定区域(100)，在该绑定区域(100)中间隔设置的多个焊盘(101)，该焊盘(101)之间通过绝缘层(102)隔开，至少两个相邻的该焊盘(101)间的该绝缘层(102)上开设有凹槽(103)。

Description

显示基板及其制作方法、显示面板、显示装置
本申请要求于2017年11月30日提交中国国家知识产权局、申请号为201711242317.6、发明名称为“显示基板及其制作方法、显示面板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及一种显示基板及其制作方法、显示面板、显示装置。
背景技术
近年来，有机发光二极管(Organic Light-Emitting Diode，OLED)显示器以其优良的性能，越来越受到业界的关注。与目前占有主要市场的液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有重量轻、厚度小、功耗低、色彩鲜艳、响应速度快、视角宽、可实现柔软显示等一系列优点。
绑定(Bonding)是OLED显示器整机工艺制程中重要的一步，绑定是指在OLED显示器的生产过程中，将OLED面板(Panel)的Bonding区域内的焊盘(Pad)和驱动集成电路(Integrated Circuit，IC)的引脚，通过各向异性导电胶(Anisotropic Conductive Film，ACF)按照一定的工作流程连接到一起并导通的过程。
发明内容
本公开实施例提供了一种显示基板及其制作方法、显示面板、显示装置。
本公开至少一实施例提供了一种显示基板，所述显示基板包括绑定区域；在所述绑定区域中间隔设置的多个焊盘；用于隔开所述焊盘的绝缘层，在至少两个相邻的所述焊盘间的所述绝缘层上开设的凹槽。
在本公开实施例的一种实现方式中，任意相邻的两个所述焊盘之间均设置有所述凹槽。
在本公开实施例的一种实现方式中，所述焊盘包括输入焊盘和输出焊盘，所述绑定区域包括分别设置的第一区域和第二区域，所述输入焊盘位于所述第一区域，所述输出焊盘位于所述第二区域，所述凹槽位于所述第一区域和所述 第二区域之间。
在本公开实施例的一种实现方式中，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的子绝缘层的厚度。
在本公开实施例的一种实现方式中，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的两个子绝缘层的厚度之和。
在本公开实施例的一种实现方式中，所述凹槽的深度等于所述绝缘层的厚度。
在本公开实施例的一种实现方式中，还包括衬底基板，以及依次设置在所述衬底基板上的缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极，其中所述凹槽的深度大于或等于所述第二绝缘层和所述层间绝缘层的厚度之和。
本公开至少一实施例还提供了一种显示面板，包括：显示基板；所述显示基板，包括：绑定区域；在所述绑定区域中间隔设置的的多个焊盘；用于隔开所述焊盘的绝缘层，在至少两个相邻的所述焊盘间的所述绝缘层上开设的凹槽。
在本公开实施例的一种实现方式中，任意相邻的两个所述焊盘之间均设置有所述凹槽。
在本公开实施例的一种实现方式中，所述焊盘包括输入焊盘和输出焊盘，所述绑定区域包括分别设置的第一区域和第二区域，所述输入焊盘位于所述第一区域，所述输出焊盘位于所述第二区域，所述凹槽位于所述第一区域和所述第二区域之间。
在本公开实施例的一种实现方式中，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的子绝缘层的厚度。
在本公开实施例的一种实现方式中，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的两个子绝缘层的厚度之和。
在本公开实施例的一种实现方式中，所述凹槽的深度等于所述绝缘层的厚度。
在本公开实施例的一种实现方式中，还包括衬底基板，以及依次设置在所 述衬底基板上的缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极，其中所述凹槽的深度大于或等于所述第二绝缘层和所述层间绝缘层的厚度之和。
本公开至少一实施例还提供了一种显示装置，所述显示装置包括如前述所述的显示面板。
本公开至少一实施例还提供了一种显示基板制作方法，所述方法包括：
在显示基板的绑定区域设置绝缘层和多个焊盘，所述多个焊盘间隔设置，且所述所述多个焊盘通过绝缘层隔开；
在至少两个相邻的所述焊盘间的所述绝缘层上开设凹槽。
在本公开实施例的一种实现方式中，所述开设凹槽，包括：
在制作所述绝缘层时，直接形成具有所述凹槽的绝缘层。
在本公开实施例的一种实现方式中，所述在制作所述绝缘层时，直接形成具有所述凹槽的绝缘层，包括：
制作一层绝缘薄膜，并在对所述绝缘薄膜进行图形化处理时，除去所述绝缘薄膜位于至少两个相邻的所述焊盘之间的部分，得到第一子绝缘层，所述第一子绝缘层为所述绝缘层的一个子绝缘层，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层。
在本公开实施例的一种实现方式中，所述在制作所述绝缘层时，直接形成具有所述凹槽的绝缘层，包括：
依次制作至少两层绝缘薄膜，并在同时对所述至少两层绝缘薄膜进行图形化处理时，除去所述至少两层绝缘薄膜位于至少两个相邻的所述焊盘之间的部分，得到至少两个子绝缘层，所述至少两个子绝缘层为所述绝缘层中的至少两个连续的子绝缘层，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层。
在本公开实施例的一种实现方式中，所述开设凹槽，包括：
在所述绝缘层制作完成后，采用图形化工艺去除所述绝缘层位于至少两个相邻的所述焊盘之间的部分，形成所述凹槽。
在本公开实施例的一种实现方式中，所述开设凹槽，包括：
在任意相邻的两个所述焊盘之间均形成所述凹槽。
在本公开实施例的一种实现方式中，所述开设凹槽，包括：
在第一区域和第二区域之间开设凹槽，所述第一区域和第二区域为所述绑 定区域内分别设置的两个区域，所述焊盘包括输入焊盘和输出焊盘，所述输入焊盘位于所述第一区域，所述输出焊盘位于所述第二区域。
附图说明
图1是OLED面板的Bonding示意图；
图2是本公开实施例提供的一种显示基板的结构示意图；
图3A是相关技术中显示基板的绑定区域的结构示意图；
图3B是相关技术中显示基板的显示区域的结构示意图；
图4是本公开实施例提供的一种显示基板的结构示意图；
图5是本公开实施例提供的一种显示基板的结构示意图；
图6是本公开实施例提供的一种显示基板制作方法流程图。
具体实施方式
为使本公开的原理和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
为了便于后文的描述，下面先结合附图1对本公开实施例涉及的OLED面板Bonding进行说明。
图1是OLED面板的Bonding示意图。参见图1，图1中标号10是显示基板(也即OLED基板)，20为ACF，30为驱动IC。在Bonding时，在显示基板10的绑定区域涂ACF 20。然后，在加热器40作用下，将驱动IC 30与显示基板10压合到一起。位于显示基板10的绑定区域的焊盘Pad 101和驱动IC 30的焊盘(Pad)301在ACF 20的作用下导通。
在对OLED面板10和驱动IC 30进行Bonding时，由于OLED面板10的Pad和Pad之间绝缘层的高度限制，ACF难以在Pad之间的区域流动(排胶困难)，造成OLED面板和驱动IC之间的ACF难以压平，从而导致ACF中存在气泡的情况出现，影响OLED面板和驱动IC之间的电连接性能。为此，本公开实施例提供了一种显示基板，能够将显示基板和驱动IC之间的ACF压平。
图2是本公开实施例提供的一种显示基板的结构示意图。参见图2，显示基板包括绑定区域100，在绑定区域100设置有多个间隔设置的焊盘(Pad)101，Pad 101之间通过绝缘层102隔开，至少两个相邻的Pad 101间的绝缘层102 上开设有凹槽103。
在本公开实施例通过在Bonding区域的至少两个相邻的Pad间的绝缘层102上开设凹槽103，使得ACF能够在被压时流向凹槽103。保证ACF能够在至少两个相邻的Pad之间的区域均匀分布，从而解决显示基板和驱动IC之间的ACF排胶困难引入的不平整的问题，避免了ACF不平整产生气泡的情况，保证了显示基板和驱动IC之间的电连接性能。
需要说明的是，本公开实施例提供的上述显示基板结构主要是针对有源矩阵(Active Matrix，AM)OLED，也即该显示基板为AMOLED显示基板。因为，AMOLED中设计有薄膜晶体管结构，使得绑定区域设有较厚的绝缘层102，从而容易造成ACF难以压平。当然，该显示基板也可以用于无源矩阵(Passive Matrix，PM)OLED，也即该显示基板为PMOLED显示基板，本申请对此不做限制。
在AMOLED中，显示基板包括显示区域和设置在显示区域周围的绑定区域。显示区域是指布置显示单元的发光区域，而绑定区域则是设置与IC连接的Pad的区域。在AMOLED中，绑定区域可以有三个，分别是驱动IC(显示)的Bonding区域、柔性电路板(Flexible Printed Circuit，FPC)的Bonding区域和触控(touch)IC的Bonding区域等。本公开实施例所指的绑定区域100可以为驱动IC(显示)的Bonding区域，因为其他Bonding区域的绝缘层102通常厚度较小，所以不会影响ACF压片，所以一般不需要开设凹槽103。但本公开实施例提供的结构也可以应用在其他Bonding区域，本公开实施例对此不做限制。
下面先对AMOLED中显示基板的层级结构进行简单说明：显示基板由下至上依次包括：衬底基板、缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极。这里，第一金属层和第二金属层用于形成栅线、薄膜晶体管的栅极、引线(包括Pad引线)和存储电容一极。例如，采用第一金属层形成栅线、薄膜晶体管的栅极、引线等，采用第二金属层形成存储电容一极，这种设计能够保证大分辨率面板的实现。当然第一金属层和第二金属层也可以采用其他设计方式。例如，采用第一金属层形成奇数行栅线、奇数行薄膜晶体管的栅极和奇数行存储电容一极，采用第二金属层形成偶数行栅线、偶数行薄膜晶体管的栅极和偶数行存储电容一极，引线形成在第一或第二金属层中任一层上。 源漏金属层用于形成Pad、数据线、薄膜晶体管的源漏电极和存储电容另一极。
在采用上述具有第一金属层、第二金属层和源漏金属层共三层金属层的顶栅型薄膜晶体管结构时，显示基板的绝缘层结构较多，厚度厚，导致ACF难以压平的情况尤为严重。故对于这种结构的显示基板，在绑定区域100的绝缘层102上开设有凹槽103，能够很好的解决ACF难以压平的问题。
在本发明实施例中，绝缘层可以包括依次设置在衬底基板上的多个子绝缘层，示例性地，绝缘层可以包括由下到上设置在衬底基板上的缓冲层、第一绝缘层、第二绝缘层和层间绝缘层。此时，凹槽的深度大于或等于多个子绝缘层中位于最上方的子绝缘层的厚度。
进一步地，凹槽103的深度大于或等于多个子绝缘层中位于最上方的两个子绝缘层的厚度之和，从而使得凹槽的深度能够保证ACF排胶顺利。例如，当绝缘层包括前述缓冲层、第一绝缘层、第二绝缘层和层间绝缘层时，凹槽103的深度大于或等于第二绝缘层和层间绝缘层的厚度之和。
当然，对于采用其他类型的薄膜晶体管结构的显示基板，也可以采用上述结构：
例如，显示基板也可以采用底栅型薄膜晶体管，此时膜层结构通常为衬底基板、栅极金属层、栅极绝缘层、有源层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极。此时，绝缘层包括设置在衬底基板上的栅极绝缘层，凹槽的深度等于栅极绝缘层的深度。这种情况下绝缘层只包括栅极绝缘层，故也即凹槽的深度等于绝缘层的厚度。
例如，显示基板为了应对高分辨率需求，通常设计两个金属层作为栅金属层。但是当显示基板分辨率不高时，显示基板可以只包括上述第一金属层和第二金属层中的一层，相应地，显示基板可以只包括第一绝缘层和第二绝缘层中的一层。在只设计一层金属层和一层绝缘层的情况下，在后续设计绑定区域的凹槽时，凹槽穿过的绝缘层也相应减少。例如，绝缘层包括依次设置在衬底基板上的缓冲层、栅极绝缘层和层间绝缘层，凹槽的深度大于或等于栅极绝缘层和层间绝缘层的厚度之和。
在本公开实施例中，衬底基板可以为透明衬底，例如玻璃衬底、硅衬底和塑料衬底等。
在本公开实施例中，第一金属层、第二金属层、源漏金属层可以采用相同或者不同的材料制成。例如，第一金属层、第二金属层、源漏金属层可以采用 钼(Mo)或者钛(Ti)/铝(Al)/Ti制成，上述材料能够保证金属层性能稳定，且具有较小的电阻。
在本公开实施例中，缓冲层、第一绝缘层、第二绝缘层、栅极绝缘层、层间绝缘层均可以为氮化硅层或氮氧化硅层。采用氮化硅层或氮氧化硅层制作上述绝缘层，一方面介电常数较高，另一方面可以实现这些膜层的薄化。平坦层可以为树脂层。
在本公开实施例中，有源层可以使用非晶硅、微晶硅或者多晶硅制成。例如，有源层可以包括设置在缓冲层上的非晶硅层和设置在非晶硅层上的N型掺杂非晶硅层。通过在非晶硅层上设置N型掺杂非晶硅层，可以避免非晶硅层与源漏极直接接触，降低非晶硅层与源漏极之间的晶格失配。
在本公开实施例中，阳极和阴极可以为氧化铟锌(Indium Zinc Oxide，IZO)薄膜电极或氧化铟锡(Indium Tin Oxide，ITO)薄膜电极。
在本公开实施例中，发光层可以包括空穴传输子层、有机发光子层和电子传输子层。在本公开实施例中，空穴传输子层、有机发光子层和电子传输子层均采用有机高分子材料或者有机小分子材料制成。
如图2所示，Pad 101包括输入Pad和输出Pad。绑定区域100包括分别设置的第一区域100A和第二区域100B，输入Pad位于第一区域100A，输出Pad位于第二区域100B。凹槽103位于第一区域100A和第二区域100B之间。在这种实现方式中，由于Pad 101是分两个区域集中设置的，且两个区域之间拥有较大的空余面积，因此可以只在布置输入Pad的第一区域100A和布置输出Pad的第二区域100B之间的区域开设凹槽103。由于第一区域100A和第二区域100B之间的这部分区域面积相对较大，开设凹槽103比较容易进行图形化处理，一方面，工艺实现简单，另一方面，避免在同一区域的两个Pad 101间开设凹槽103，造成Pad 101之间绝缘性能下降。值得说明的是，在显示基板中，通常只有驱动IC的Bonding区域的Pad包括输入Pad和输出Pad，FPC的Bonding区域和触控IC的Bonding区域的Pad均只包括输出Pad，所以该方案主要是针对驱动IC的Bonding区域。
在其他实施例中，任意相邻的两个Pad 101之间均可以设置有凹槽103。在任意两个Pad 101之间均开设凹槽103，保证凹槽103面积最大化，从而保证ACF有足够的空间流动，避免ACF难以压平。
进一步地，在这种实现方式中，各个凹槽103可以相互连通，从而便于 ACF的流动。
当然，上述两种实现方式也只是举例，在其他实现方式中，还可以在绑定区域的绝缘层的任意位置开设凹槽，只要不影响各个Pad间的绝缘即可。
图3A是相关技术中显示基板的绑定区域的膜层结构示意图。如图3A所示，在绑定区域显示基板包括衬底基板120、缓冲层121、第一绝缘层122、第一金属层(Pad引线)125、第二绝缘层123、层间绝缘层124、源漏金属层(Pad101)126和平坦层127。图3A所示的是显示基板绑定区域的膜层结构，该显示基板在显示区域的膜层结构如图3B所示，包括：衬底基板120，以及依次设置在衬底基板120上的缓冲层121、有源层128、第一绝缘层122、第一金属层125、第二绝缘层123、第二金属层129、层间绝缘层124、源漏金属层126、平坦层127、阳极130、像素定义层131、发光层132及阴极133。参见图3B，依次设置是指上述膜层是按照顺序设置在衬底基板120上的。
因此，前述绑定区域的绝缘层102包括依次设置在衬底基板120上的缓冲层121、第一绝缘层122、第二绝缘层123和层间绝缘层124。第一绝缘层122和第二绝缘层123间设有第一金属层125，层间绝缘层124上方设有源漏金属层126和平坦层127，第二绝缘层123和层间绝缘层124上开设有供有源漏金属层126通过并与第一金属层125连接的过孔134。绑定区域100形成在平坦层127开设的凹槽内。
图4是本公开实施例提供的一种显示基板的绑定区域的膜层结构示意图，图4为图2在A-A’方向上的一种截面示意图。如图4所示，图4与图3A的区别在于，在绝缘层上开设有凹槽103。在图4所示的显示基板中，凹槽103的深度等于第二绝缘层123和层间绝缘层124的厚度之和。凹槽103的深度等于第二绝缘层123和层间绝缘层124的厚度之和，即该凹槽103贯穿第二绝缘层123和层间绝缘层124，凹槽103的底部位于第一绝缘层122。在第二绝缘层123和层间绝缘层124上开设凹槽103，由于层间绝缘层124的厚度较大，因此得到的凹槽103的深度较大，从而能够满足ACF的流动性需求。只在第二绝缘层123和层间绝缘层124上开设凹槽103，这样既能满足凹槽103的深度需求，同时又使得开设凹槽103所需的工艺步骤最少，制作该凹槽103的详细过程可以参见后文方法实施例的描述。
在该实施例中，缓冲层121设置在OLED衬底基板120上，对设置在衬底基板120上的有源层进行缓冲，第一绝缘层122、第二绝缘层123、层间绝缘 层124主要是用于进行有源层和金属层、金属层和金属层之间的隔离，金属层包括前述第一金属层、第二金属层和源漏金属层。
图5是本公开实施例另一种显示基板的绑定区域的膜层结构示意图，图5为图2在A-A’方向上的另一种截面示意图。如图5所示，凹槽103的深度等于绝缘层102的厚度。也该凹槽103贯穿绝缘层102中的缓冲层121、第一绝缘层122、第二绝缘层123和层间绝缘层124，凹槽103的底部位于衬底基板120上。此时凹槽103的深度最大，从而在最大限度保证ACF的流动性。
如图4和图5所示，该凹槽103从底部到开口呈逐渐变宽的趋势，这种设计方便膜层的图形化。
在本公开实施例中，为了保证凹槽103不对Pad间的绝缘性能产生影响，凹槽103的开口与Pad边缘的之间存在一定距离，例如5mm等。
本公开实施例还提供了一种显示面板，显示面板包括如图2、图4、图5中任一幅所示的显示基板。
在本公开实施例通过在Bonding区域的至少两个相邻的Pad间的绝缘层102上开设凹槽103，使得ACF能够在被压时流向凹槽103，保证ACF能够在至少两个相邻的Pad之间的区域均匀分布，从而解决显示基板和驱动IC之间的ACF排胶困难引入的不平整的问题，避免了ACF不平整产生气泡的情况，保证了显示基板和驱动IC之间的电连接性能。
本公开实施例还提供了一种显示装置，显示装置包括如前的显示面板。
本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例通过在Bonding区域的至少两个相邻的Pad间的绝缘层102上开设凹槽103，使得ACF能够在被压时流向凹槽103，保证ACF能够在至少两个相邻的Pad之间的区域均匀分布，从而解决显示基板和驱动IC之间的ACF排胶困难引入的不平整的问题，避免了ACF不平整产生气泡的情况，保证了显示基板和驱动IC之间的电连接性能。
本公开实施例还提供了一种显示基板制作方法，该方法包括：在显示基板的绑定区域形成多个间隔设置的焊盘，焊盘之间通过绝缘层隔开；在至少两个 相邻的焊盘间的绝缘层上开设凹槽。
下面结合附图6对本公开实施例提供的显示基板制作方法进行详细说明。
图6是本公开实施例提供的一种显示基板制作方法流程图。参见图6，方法包括：
步骤201：提供一衬底基板。
在本公开实施例中，衬底基板可以为透明衬底，例如玻璃衬底、硅衬底和塑料衬底等。
步骤202：在衬底基板生长显示基板的各个膜层，并在显示基板的绑定区域开设凹槽，绑定区域设置有多个间隔设置的Pad，Pad之间通过绝缘层隔开，至少两个相邻Pad间的绝缘层上开设有凹槽。
在本公开实施例中，在至少两个相邻的焊盘间的绝缘层上开设凹槽，从而避免ACF排胶困难。
在本公开实施例中，开设凹槽可以包括如下两种实现方式：
一种实现方式是，在制作绝缘层时，直接形成具有凹槽的绝缘层，也即是说绝缘层在原本的形状基础上需要进一步形成凹槽。另一种实现方式是，在绝缘层制作完成后，采用图形化工艺去除绝缘层位于至少两个相邻的焊盘之间的部分，形成凹槽。
该实现方式提供了两种凹槽开设方式，采用第一种方式在绝缘层的制作过程中开设凹槽，由于在绝缘层的制作过程中，部分绝缘膜层也需要进行图形化处理，而对于这部分绝缘膜层的凹槽开设，可以在原本的图形化处理中同步进行。在原本的图形化处理中开设上述凹槽，只需要更新掩膜板的图案即可，而无需新的工艺步骤，因而采用第一种方式可以节省凹槽开设的工艺步骤。采用第二种方式开设凹槽，在绝缘层制成后实现凹槽开设，这种方式不需要对绝缘膜层的掩膜板的图案进行更新，而只需要采用新的掩膜板来完成凹槽开设，这种方式能够更好的控制形成的凹槽的形状尺寸。
由于第二种方式只需要在最后加一道图形化工艺即可，故在此不做详细说明。下面对第一种方式进行详细说明：
在制作绝缘层时，直接形成具有凹槽的绝缘层，包括：
制作一层绝缘薄膜，并在对绝缘薄膜进行图形化处理时，除去绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第一子绝缘层。第一子绝缘层为绝缘层的一个子绝缘层，绝缘层包括依次设置在衬底基板上的多个子绝缘层。这里 的第一子绝缘层为绝缘层中的任一个子绝缘层，绝缘层中的任一个子绝缘层如果要开设凹槽，都按照上述方式进行处理。
或者，在制作绝缘层时，直接形成具有凹槽的绝缘层，包括：
依次制作至少两层绝缘薄膜，并在同时对至少两层绝缘薄膜进行图形化处理时，除去至少两层绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到至少两个子绝缘层。至少两个子绝缘层为绝缘层中的至少两个连续的子绝缘层，绝缘层包括依次设置在衬底基板上的多个子绝缘层。
可以看出，本申请中直接形成具有凹槽的绝缘层包括两种方式，一种方式是逐层形成凹槽，另一种方式是两层或多层同时形成凹槽。
在绝缘层包括多个子绝缘层时，凹槽的深度大于或等于多个子绝缘层中位于最上方的子绝缘层的厚度。
进一步地，凹槽的深度大于或等于多个子绝缘层中位于最上方的两个子绝缘层的厚度之和，从而使得凹槽的深度能够保证ACF排胶顺利。
例如，可以在多个子绝缘层中位于最上方的两个子绝缘层上开设凹槽。此时，在制作绝缘层时，直接形成具有凹槽的绝缘层，可以包括：
制作第一绝缘薄膜，对第一绝缘薄膜进行图形化处理时，除去第一绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第一子绝缘层，第一子绝缘层为多个子绝缘层中由上至下的第二个子绝缘层。在第一子绝缘层上形成第二绝缘薄膜，对第二绝缘薄膜进行图形化处理时，除去第二绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第二子绝缘层，第二子绝缘层为多个子绝缘层中位于最上方的子绝缘层。也就是说，在上述图形化过程中除了要形成子绝缘层原本的图案外，还需要形成该凹槽。
可替换地，在制作绝缘层时，直接形成具有凹槽的绝缘层可以包括：
制作第一绝缘薄膜和第二绝缘薄膜，对第一绝缘薄膜和第二绝缘薄膜进行图形化处理时，除去第一绝缘薄膜和第二绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第一子绝缘层和第二子绝缘层，第一子绝缘层和第二子绝缘层为多个子绝缘层中位于最上方的两个子绝缘层。需要说明的是，这种方式适用于如下两种情况：第一种，第一子绝缘层和第二子绝缘层图案相同，这种情况采用普通掩膜进行图形化处理即可。第二种，第一子绝缘层位于第二子绝缘层下方，第一子绝缘层的图案在衬底基板上的投影处于位于第二子绝缘层的图案在衬底基板上的投影内，这种情况采用灰度掩膜实现图形化处理，使得部分图 案能够同时形成在第一子绝缘层和第二子绝缘层上，部分图案仅形成在第二子绝缘层上。
在本公开实施例中，当存在多个子绝缘层时，该凹槽可以形成在最上方的两个子绝缘层上，一方面，能够保证ACF排胶顺利，另一方面，只需要对两层膜层图形化，实现更方便。在这种方式中，既可以对两个膜层分别图形化，也可以对两个膜层一起图形化形成两个子绝缘层。
可选地，当子绝缘层的数量大于或等于4时，在制作绝缘层时，还可以在最上方的四个子绝缘层上开设凹槽。此时，直接形成具有凹槽的绝缘层，还可以包括：
制作第三绝缘薄膜，对第三绝缘薄膜进行图形化处理时，除去第三绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第三子绝缘层，第三子绝缘层为多个子绝缘层中由上至下的第四个子绝缘层。在第三子绝缘层上形成第四绝缘薄膜，对第四绝缘薄膜进行图形化处理时，除去第四绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第四子绝缘层，第四子绝缘层为多个子绝缘层中由上至下的第三个子绝缘层。
可替换地，在制作绝缘层时，直接形成具有凹槽的绝缘层，还可以包括：
制作第三绝缘薄膜和第四绝缘薄膜，对第三绝缘薄膜和第四绝缘薄膜进行图形化处理时，除去第三绝缘薄膜和第四绝缘薄膜位于至少两个相邻的焊盘之间的部分，得到第三子绝缘层和第四子绝缘层，第三子绝缘层和第四子绝缘层为多个子绝缘层中由上至下的第四个和第三个子绝缘层。
对于第三子绝缘层和第四子绝缘层的处理方式与前述第一子绝缘层及第二子绝缘层的处理方式相同，这里不再赘述。
当子绝缘层的数量大于或等于4时，该凹槽除了可以形成在最上方的四个子绝缘层上，从而进一步保证ACF排胶顺利。
下面结合显示基板的结构对凹槽的形成进行说明。例如，在衬底基板生长显示基板的各个膜层，可以包括：在衬底基板上依次生长缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极。在上述结构中，第一金属层和第二金属层用于形成栅线、薄膜晶体管的栅极、引线(包括Pad引线)和存储电容一极，例如，采用第一金属层形成引线，采用第二金属层形成栅线、薄膜晶体管的栅极和存储电容一极。源漏金属层用于形成Pad、数据线、薄膜晶体管 的源漏电极和存储电容另一极。上述结构中薄膜晶体管是以顶栅型薄膜晶体管为例进行的说明，在其他实施例中，上述显示基板也可以采用底栅型薄膜晶体管，本申请对此不做限制。各个膜层的材料如前文，这里不再赘述。
在上述结构中，绝缘层可以包括4个子绝缘层，分别为缓冲层、第一绝缘层、第二绝缘层和层间绝缘层。
在制作绝缘层时，直接形成具有凹槽的绝缘层，可以包括：
在对第二绝缘层进行图形化处理时，除去第二绝缘层位于至少两个相邻的Pad之间的部分。在对层间绝缘层进行图形化处理时，除去层间绝缘层位于至少两个相邻的Pad之间的部分。在显示基板的制作过程中，部分绝缘膜层本身需要进行图形化处理，形成图案，而对于这部分绝缘膜层的凹槽开设，可以在原本的图形化处理中同步进行，进而节省工艺步骤。
以这种方式为例，对本公开实施例提供的显示基板制作方法的完整流程进行简单说明，包括：在衬底基板上依次生长缓冲层、有源层、第一绝缘层、第一金属层和第二绝缘层，并且在对第二绝缘层进行图形化处理时，除去第二绝缘层位于至少两个相邻的Pad之间的部分。在图形化处理后的第二绝缘层上依次生长第二金属层和层间绝缘层，并在在对层间绝缘层进行图形化处理时，除去层间绝缘层位于至少两个相邻的Pad之间的部分。在图形化处理后的层间绝缘层上依次生长源漏金属层、平坦层、阳极、像素定义层、发光层及阴极。
可替换地，在制作绝缘层时，直接形成具有凹槽的绝缘层，可以包括：
在对层间绝缘层进行图形化处理时，同时除去第二绝缘层和层间绝缘层位于至少两个相邻的Pad之间的部分。
在该实现方式中，凹槽开设在第二绝缘层和层间绝缘层上，开设方式有两种，一种是分两步，在对第二绝缘层进行图形化处理时，在第二绝缘层上开设凹槽，在对层间绝缘层进行图形化处理时，在层间绝缘层上开设凹槽，这种方式制作方便，工艺要求低。另一种是一次完成该凹槽的开设，例如在对层间绝缘层进行图形化处理时，一次在层间绝缘层和第二绝缘层上开设凹槽，既可以采用干法刻蚀一步完成，也可以采用湿法刻蚀两步完成(利用不同的刻蚀液分别对层间绝缘层和第二绝缘层进行刻蚀)。
另外，在第二绝缘层和层间绝缘层上开设凹槽，由于层间绝缘层的厚度较大，因此得到的凹槽的深度较大，从而能够满足ACF的流动性需求。
在本公开实施例中，在制作绝缘层时，直接形成具有凹槽的绝缘层，还可 以包括：
在对缓冲层进行图形化处理时，同时除去缓冲层位于至少两个相邻的Pad之间的部分。
在对第一绝缘层进行图形化处理时，同时除去第一绝缘层位于至少两个相邻的Pad之间的部分。
可替换地，在制作绝缘层时，直接形成具有凹槽的绝缘层，还可以包括：
在对第一绝缘层进行图形化处理时，同时除去缓冲层和第一绝缘层位于至少两个相邻的Pad之间的部分。
当然，本公开实施例还可以在对第二绝缘层或者层间绝缘层进行图形化处理时，同时除去缓冲层和第一绝缘层位于至少两个相邻的Pad之间的部分。对于三个膜层或者四个膜层而言，其图形化的图案很难相同或者满足前述的大小关系(下方的膜层图案在衬底基板上的投影在上方的膜层图案在衬底基板上的投影内)，故通常采用两个膜层一次图形化的方式实现。
在这种实现方式中，凹槽开设在缓冲层、第一绝缘层、第二绝缘层和层间绝缘层上，开设方式有多种：比如，每制作完一层绝缘层，就在这层绝缘层上开设凹槽。或者，每制作两层绝缘层开设一次凹槽。或者，在连续三层绝缘层制作完后，在这三层绝缘层上开设凹槽。或者，在连续四层绝缘层制作完后，在这四层绝缘层上开设凹槽。在上述制作步骤中，在一层制作完开设凹槽时，既可以采用干刻也可以采用湿刻，而一次进行两层或者多层凹槽开设时，既可以采用干法刻蚀一步完成，也可以采用湿法刻蚀两步或者多步完成(利用不同的刻蚀液分别对各个膜层进行刻蚀)。
另外，在这种实现方式中进一步加深了凹槽的深度，最大限度保证ACF的流动性。
在本公开实施例的一种实现方式中，在任意相邻的两个Pad之间均形成有凹槽。在任意两个Pad之间均开设凹槽，保证凹槽面积最大化，从而保证ACF有足够的空间流动，避免ACF难以压平。
在本公开实施例的另一种实现方式中，Pad包括输入Pad和输出Pad，绑定区域包括分别设置的第一区域和第二区域，输入Pad位于第一区域，输出Pad位于第二区域。开设凹槽，包括：在第一区域和第二区域之间开设凹槽，也即凹槽位于第一区域和第二区域之间。在这种实现方式中，由于Pad是分两个区域集中设置的，且两个区域之间拥有较大的空余面积，因此可以只在输入Pad 和输出Pad之间的区域开设凹槽，这部分区域面积相对较大，开设凹槽比较容易进行图形化处理，一方面，工艺实现简单，另一方面，避免在同一区域的两个Pad间开设凹槽，造成Pad之间绝缘性能下降。
以上仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开所附权利要求书限定的保护范围之内。

Claims (20)

  1. 一种显示基板，包括：绑定区域；在所述绑定区域中间隔设置的多个焊盘；用于隔开所述焊盘的绝缘层，在至少两个相邻的所述焊盘间的所述绝缘层上开设的凹槽。
  2. 根据权利要求1所述的显示基板，其中，任意相邻的两个所述焊盘之间均设置有所述凹槽。
  3. 根据权利要求1所述的显示基板，其中，所述焊盘包括输入焊盘和输出焊盘，所述绑定区域包括分别设置的第一区域和第二区域，所述输入焊盘位于所述第一区域，所述输出焊盘位于所述第二区域，所述凹槽位于所述第一区域和所述第二区域之间。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的子绝缘层的厚度。
  5. 根据权利要求4所述的显示基板，其中，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的两个子绝缘层的厚度之和。
  6. 根据权利要求5所述的显示基板，其中，所述凹槽的深度等于所述绝缘层的厚度。
  7. 根据权利要求1-6任一项所述的显示基板，还包括衬底基板，以及依次设置在所述衬底基板上的缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极，其中所述凹槽的深度大于或等于所述第二绝缘层和所述层间绝缘层的厚度之和。
  8. 一种显示面板，包括：显示基板；
    所述显示基板包括：绑定区域；在所述绑定区域中间隔设置的的多个焊盘；用于隔开所述焊盘的绝缘层，在至少两个相邻的所述焊盘间的所述绝缘层上开设的凹槽。
  9. 根据权利要求8所述的显示面板，其中，任意相邻的两个所述焊盘之间均设置有所述凹槽。
  10. 根据权利要求8所述的显示面板，其中，所述焊盘包括输入焊盘和输出焊盘，所述绑定区域包括分别设置的第一区域和第二区域，所述输入焊盘位 于所述第一区域，所述输出焊盘位于所述第二区域，所述凹槽位于所述第一区域和所述第二区域之间。
  11. 根据权利要求8-10任一项所述的显示面板，其中，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层，所述凹槽的深度大于或等于所述多个子绝缘层中位于最上方的子绝缘层的厚度。
  12. 根据权利要求8-11任一项所述的显示面板，其中，还包括衬底基板，以及依次设置在所述衬底基板上的缓冲层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、源漏金属层、平坦层、阳极、像素定义层、发光层及阴极，其中所述凹槽的深度大于或等于所述第二绝缘层和所述层间绝缘层的厚度之和。
  13. 一种显示装置，包括：如权利要求7-12任一项所述的显示面板。
  14. 一种显示基板制作方法，包括：
    在显示基板的绑定区域设置绝缘层和多个焊盘，所述多个焊盘间隔设置，且所述所述多个焊盘通过绝缘层隔开；
    在至少两个相邻的所述焊盘间的所述绝缘层上开设凹槽。
  15. 根据权利要求14所述的方法，其中，所述开设凹槽，包括：
    在制作所述绝缘层时，直接形成具有所述凹槽的绝缘层。
  16. 根据权利要求15所述的方法，其中，所述在制作所述绝缘层时，直接形成具有所述凹槽的绝缘层，包括：
    制作一层绝缘薄膜，并在对所述绝缘薄膜进行图形化处理时，除去所述绝缘薄膜位于至少两个相邻的所述焊盘之间的部分，得到第一子绝缘层，所述第一子绝缘层为所述绝缘层的一个子绝缘层，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层。
  17. 根据权利要求15所述的方法，其中，所述在制作所述绝缘层时，直接形成具有所述凹槽的绝缘层，包括：
    依次制作至少两层绝缘薄膜，并在同时对所述至少两层绝缘薄膜进行图形化处理时，除去所述至少两层绝缘薄膜位于至少两个相邻的所述焊盘之间的部分，得到至少两个子绝缘层，所述至少两个子绝缘层为所述绝缘层中的至少两个连续的子绝缘层，所述绝缘层包括依次设置在衬底基板上的多个子绝缘层。
  18. 根据权利要求14所述的方法，其中，所述开设凹槽，包括：
    在所述绝缘层制作完成后，采用图形化工艺去除所述绝缘层位于至少两个 相邻的所述焊盘之间的部分，形成所述凹槽。
  19. 根据权利要求14-18任一项所述的方法，其中，所述开设凹槽，包括：
    在任意相邻的两个所述焊盘之间均形成所述凹槽。
  20. 根据权利要求14-18任一项所述的方法，其中，所述开设凹槽，包括：
    在第一区域和第二区域之间开设凹槽，所述第一区域和第二区域为所述绑定区域内分别设置的两个区域，所述焊盘包括输入焊盘和输出焊盘，所述输入焊盘位于所述第一区域，所述输出焊盘位于所述第二区域。
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