WO2019080254A1 - 背沟道蚀刻型氧化物半导体tft基板及其制作方法 - Google Patents

背沟道蚀刻型氧化物半导体tft基板及其制作方法

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Publication number
WO2019080254A1
WO2019080254A1 PCT/CN2017/113547 CN2017113547W WO2019080254A1 WO 2019080254 A1 WO2019080254 A1 WO 2019080254A1 CN 2017113547 W CN2017113547 W CN 2017113547W WO 2019080254 A1 WO2019080254 A1 WO 2019080254A1
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layer
oxide semiconductor
semiconductor layer
drain
oxide
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PCT/CN2017/113547
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English (en)
French (fr)
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余明爵
徐源竣
周星宇
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/742,772 priority Critical patent/US20190386149A1/en
Publication of WO2019080254A1 publication Critical patent/WO2019080254A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a back channel etch type oxide semiconductor TFT substrate and a method of fabricating the same.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • Thin Film Transistor is the main driving component in current liquid crystal display devices and active matrix OLED display devices, and is directly related to the development direction of high performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the thin film transistor for preparing the corresponding structure is also various, and an amorphous silicon (a-Si) material is a relatively common one.
  • the conventional a-Si has a mobility of only about 1 cm 2 /(Vs) which cannot meet the requirements, and indium gallium zinc oxide (IGZO)
  • IGZO indium gallium zinc oxide
  • the metal oxide material represented by the metal oxide has a mobility of more than 10 cm 2 /(Vs) or more, and the preparation of the corresponding thin film transistor is compatible with the existing a-Si semiconductor-driven production line, and has rapidly become a display in recent years.
  • IGZO TFTs Compared to traditional a-Si TFTs, IGZO TFTs have the following advantages:
  • the resolution of the IGZO TFT display backplane can be more than twice that of the a-Si TFT, and the carrier concentration in the IGZO material is high.
  • the mobility is large, which can reduce the size of the TFT and ensure the resolution is improved;
  • IGZO TFT has a leakage current of less than 1pA; the driving frequency is reduced from the original 30-50Hz to 2-5Hz, and even 1Hz can be achieved through a special process.
  • the alignment of the liquid crystal molecules can be maintained without affecting the quality of the picture, thereby reducing the power consumption of the display backplane; in addition, the high mobility of the IGZO semiconductor material allows a smaller size TFT to provide sufficient The charging capacity and the higher capacitance value, and the aperture ratio of the liquid crystal panel is increased, the effective area of light penetration is increased, and the same brightness can be achieved with less backplane components or low power consumption, thereby reducing energy consumption;
  • IGZO as a semiconductor active layer TFT generally adopts an etch barrier (ESL) structure, and an etch barrier layer is used in the source/drain etching process due to the existence of an etch stop layer (Etch Stop Layer).
  • ESL etch barrier
  • Etch Stop Layer an etch stop layer
  • the IGZO active layer can be effectively protected from being affected, and the TFT has excellent semiconductor characteristics.
  • the preparation process of the IGZO TFT of the ESL structure is complicated, and it is necessary to go through 6 times of yellow light process, which is disadvantageous for cost reduction. Therefore, the industry generally pursues the development of an IGZO TFT with a less back channel etching (BCE) structure with a yellow light process.
  • BCE back channel etching
  • IGZO TFT Since the etch barrier layer is not disposed in the IGZO TFT of the BCE structure to block the back channel, the channel region of the IGZO active layer is easily damaged during the etching process of the source and drain electrodes, and the number of film defects due to the IGZO active layer There are many, so IGZO TFT is sensitive to the environment. Light, water vapor (H 2 O), oxygen (O 2 ), hydrogen (H 2 ) and organics (Organics) in the environment are easy to affect the TFT performance, resulting in TFT devices. The reliability is low and the life of the panel is short.
  • An object of the present invention is to provide a method for fabricating a back channel etch-type oxide semiconductor TFT substrate, which can reduce damage to a channel region of an active layer during etching of a drain and a source, thereby effectively reducing active
  • the number of film defects in the layer, while saving the etch barrier reticle, is low in manufacturing cost.
  • Another object of the present invention is to provide a back channel etch-type oxide semiconductor TFT substrate, wherein the active layer not only has a high mobility, but also has a small number of film defects, and the TFT device is less affected by the environment and has a higher Reliability.
  • the present invention provides a method for fabricating a back channel etch-type oxide semiconductor TFT substrate, comprising:
  • a passivation layer covering the drain, the source, and the active layer is formed on the gate insulating layer; and a via hole corresponding to the upper side of the drain is formed on the passivation layer.
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer respectively include one or more of indium gallium zinc oxide and indium zinc tin oxide; the first oxide semiconductor layer and the second oxide
  • the materials of the semiconductor layers are the same or different.
  • the first oxide semiconductor layer has a density of less than 6.4 g/cm 3 and the second oxide semiconductor layer has a density of more than 6.4 g/cm 3 .
  • the thickness of the first oxide semiconductor layer is greater than the thickness of the second oxide semiconductor layer.
  • the material of the gate includes one or more of molybdenum, aluminum, and copper; and the gate insulating layer is a silicon nitride layer, a silicon oxide layer, or a laminated composite film of a silicon nitride layer and a silicon oxide layer.
  • the passivation layer is a silicon nitride layer or a silicon oxide layer; and the drain and source materials include one or more of molybdenum, aluminum, and copper.
  • the present invention also provides a back channel etch-type oxide semiconductor TFT substrate, comprising: a substrate substrate, a gate electrode disposed on the substrate substrate, and a gate electrode disposed on the substrate substrate and covering the gate electrode An insulating layer, an active layer disposed on the gate insulating layer and corresponding to the upper surface of the gate, and a drain provided on the active layer and the gate insulating layer and respectively contacting the two sides of the active layer a pass and a source, a passivation layer disposed on the gate insulating layer and covering the drain, the source, and the active layer, and a via hole disposed on the passivation layer corresponding to the drain ;
  • the active layer includes a first oxide semiconductor layer disposed on the gate insulating layer, and a second oxide semiconductor layer disposed on the first oxide semiconductor layer, the second oxide semiconductor The density of the layer is greater than the density of the first oxide semiconductor layer.
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer respectively include one or more of indium gallium zinc oxide and indium zinc tin oxide; the first oxide semiconductor layer and the second oxide
  • the materials of the semiconductor layers are the same or different.
  • the first oxide semiconductor layer has a density of less than 6.4 g/cm 3 and the second oxide semiconductor layer has a density of more than 6.4 g/cm 3 .
  • the thickness of the first oxide semiconductor layer is greater than the thickness of the second oxide semiconductor layer.
  • the material of the gate includes one or more of molybdenum, aluminum, and copper; and the gate insulating layer is a silicon nitride layer, a silicon oxide layer, or a laminated composite film of a silicon nitride layer and a silicon oxide layer.
  • the passivation layer is a silicon nitride layer or a silicon oxide layer; and the drain and source materials include one or more of molybdenum, aluminum, and copper.
  • the present invention also provides a method for fabricating a back channel etch-type oxide semiconductor TFT substrate, comprising:
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer respectively comprise one or more of indium gallium zinc oxide and indium zinc tin oxide; the first oxide semiconductor layer and the first The materials of the dioxide semiconductor layer are the same or different;
  • the density of the first oxide semiconductor layer is less than 6.4 g/cm 3 and the density of the second oxide semiconductor layer is greater than 6.4 g/cm 3 ;
  • the thickness of the first oxide semiconductor layer is greater than the thickness of the second oxide semiconductor layer
  • the material of the gate includes one or more of molybdenum, aluminum, and copper; and the gate insulating layer is a silicon nitride layer, a silicon oxide layer, or a laminate of a silicon nitride layer and a silicon oxide layer. a composite film; the passivation layer is a silicon nitride layer or a silicon oxide layer; and the material of the drain and source includes one or more of molybdenum, aluminum, and copper.
  • the method for fabricating the back channel etch-type oxide semiconductor TFT substrate of the present invention has the active layer disposed in a two-layer structure, and the first oxide semiconductor layer located in the lower layer is prepared according to normal deposition process parameters, and has a normal Density, the second oxide semiconductor layer located in the upper layer is prepared by changing deposition process parameters, has a higher density; the first oxide semiconductor layer has a lower density and higher mobility, and the second oxide semiconductor The density of the layer is high, thin
  • the number of film defects is small, and has strong etching resistance, which can reduce the damage of the channel region of the active layer during the etching process of the drain and the source, and save the etch barrier reticle, and the manufacturing cost is low; Therefore, the back channel etch type oxide semiconductor TFT substrate produced by the present invention has not only a high mobility of the active layer but also a small number of film defects, and the TFT device is exposed to light, water vapor, oxygen, hydrogen and organic substances in the environment. The impact is small and has high
  • FIG. 1 is a flow chart showing a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step S1 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 3 and FIG. 4 are schematic diagrams showing the step S2 of the method for fabricating the back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 5 is a schematic view showing a step S3 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 6 and FIG. 7 are schematic views showing a step S4 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 7 is a schematic structural view of a back channel etch type oxide semiconductor TFT substrate of the present invention.
  • the present invention provides a method for fabricating a back channel etch type oxide semiconductor TFT substrate, comprising the following steps:
  • Step S1 as shown in FIG. 2, a base substrate 10 is provided, a metal material is deposited on the base substrate 10, and a gate electrode 20 is formed by etching, and a gate covering the gate electrode 20 is formed on the base substrate 10. Insulation layer 30.
  • the base substrate 10 is a glass substrate.
  • the step S1 further includes: cleaning and baking the base substrate 10 before forming the gate electrode 20 on the base substrate 10.
  • the material of the gate electrode 20 includes one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • the gate insulating layer 30 is a laminated silicon composite film of a silicon nitride (SiN x ) layer, a silicon oxide (SiO x ) layer, or a silicon nitride (SiN x ) layer and a silicon oxide (SiO x ) layer. .
  • Step S2 depositing a first oxide semiconductor layer 401 on the gate insulating layer 30, and depositing a second oxide semiconductor layer 402 on the first oxide semiconductor layer 401, the first The density of the dioxide semiconductor layer 402 is greater than the density of the first oxide semiconductor layer 401;
  • the first oxide semiconductor layer 401 and the second oxide semiconductor layer 402 are patterned to obtain an active layer 40.
  • the materials of the first oxide semiconductor layer 401 and the second oxide semiconductor layer 402 respectively include one or more of indium gallium zinc oxide (IGZO) and indium zinc tin oxide (IZTO);
  • the materials of the first oxide semiconductor layer 401 and the second oxide semiconductor layer 402 are the same or different.
  • the density of the first oxide semiconductor layer 401 is less than 6.4 g/cm 3
  • the density of the second oxide semiconductor layer 402 is greater than 6.4 g/cm 3 .
  • the first oxide semiconductor layer 401 is prepared according to a normal deposition process parameter and has a normal density
  • the second oxide semiconductor layer 402 is prepared by changing a deposition process parameter, and has a higher density
  • the present invention passes the first
  • the oxide semiconductor layer 401 is disposed at a lower density, which can ensure a higher mobility, and by setting the second oxide semiconductor layer 402 to a higher density, it has a smaller number of film defects, thereby ensuring that it has a higher density.
  • the strong etching resistance effectively reduces the damage to the channel region 41 of the active layer 40 during the subsequent etching of the drain 51 and the source 52.
  • the thickness of the first oxide semiconductor layer 401 is larger, and the thickness of the second oxide semiconductor layer 402 is smaller, that is, the thickness of the first oxide semiconductor layer 401 is larger than the second oxide.
  • the thickness of the semiconductor layer 402 is such that the active layer 40 has a high mobility.
  • Step S3 as shown in FIG. 5, a metal material is deposited on the active layer 40 and the gate insulating layer 30, and a drain 51 and a source 52 are formed by etching, and the drain 51 and the source 52 are respectively Both sides of the source layer 40 are in contact.
  • the material of the drain 51 and the source 52 includes one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • the drain 51 and the source 52 are defined on the active layer 40 at the drain a channel region 41 between the pole 51 and the source 52, a drain contact region 42 on the side of the channel region 41 and in contact with the drain 51, and another side of the channel region 41 And a source contact region 43 in contact with the source 52.
  • Step S4 as shown in FIG. 6, a passivation layer 60 covering the drain electrode 51, the source electrode 52, and the active layer 40 is formed on the gate insulating layer 30; as shown in FIG. 7, in the passivation A via 61 corresponding to the upper side of the drain 51 is formed on the layer 60.
  • the passivation layer 60 is a silicon nitride (SiN x ) layer or a silicon oxide (SiO x ) layer.
  • the through hole 61 is used to realize an electrical connection between the LCD pixel electrode or the OLED anode and the drain 51 in a subsequent process.
  • FIGS. 5 to 7 are only used to divide the channel region 41, the drain contact region 42, and the source contact region 43 of the active layer 40, and have no other meaning.
  • the method for fabricating the back channel etch type oxide semiconductor TFT substrate of the present invention has the active layer 40 disposed in a two-layer structure, and the first oxide semiconductor layer 401 located in the lower layer is prepared according to normal deposition process parameters, has a normal density, and is located on the upper layer.
  • the second oxide semiconductor layer 402 is prepared by changing deposition process parameters, has a higher density; the first oxide semiconductor layer 401 has a lower density and a higher mobility, and the second oxide semiconductor layer 402
  • the density is higher, the number of film defects is small, and the etching resistance is strong, and the damage of the channel region 41 of the active layer 40 during the etching process of the drain 51 and the source 52 can be reduced, and etching is saved.
  • the barrier reticle is low in manufacturing cost; therefore, the back channel etch type oxide semiconductor TFT substrate produced by the present invention has not only the high mobility of the active layer 40 but also the number of film defects, and the TFT device is exposed to the environment.
  • the light, water vapor, oxygen, hydrogen and organic matter have less influence and have higher reliability.
  • the present invention provides a back channel etch type oxide semiconductor TFT substrate, comprising: a substrate substrate 10 disposed on the substrate, based on the method for fabricating the back channel etch type oxide semiconductor TFT substrate.
  • a gate electrode 20 on the substrate 10 a gate insulating layer 30 disposed on the substrate substrate 10 and covering the gate electrode 20, and an active layer disposed on the gate insulating layer 30 and corresponding to the gate electrode 20 40.
  • the drain 51 and the source 52 respectively disposed on the active layer 40 and the gate insulating layer 30 and in contact with the two sides of the active layer 40 are disposed on the gate insulating layer 30.
  • a passivation layer 60 covering the drain 51, the source 52, and the active layer 40, and a via 61 provided on the passivation layer 60 corresponding to the upper surface of the drain 51;
  • the active layer 40 includes a first oxide semiconductor layer 401 disposed on the gate insulating layer 30 and a second oxide semiconductor layer 402 disposed on the first oxide semiconductor layer 401.
  • the density of the second oxide semiconductor layer 402 is greater than the density of the first oxide semiconductor layer 401.
  • the material of the gate electrode 20 includes molybdenum (Mo), aluminum (Al), and copper (Cu). One or more.
  • the gate insulating layer 30 is a laminated silicon composite film of a silicon nitride (SiN x ) layer, a silicon oxide (SiO x ) layer, or a silicon nitride (SiN x ) layer and a silicon oxide (SiO x ) layer. .
  • the materials of the first oxide semiconductor layer 401 and the second oxide semiconductor layer 402 respectively include one or more of indium gallium zinc oxide (IGZO) and indium zinc tin oxide (IZTO);
  • the materials of the first oxide semiconductor layer 401 and the second oxide semiconductor layer 402 are the same or different.
  • the density of the first oxide semiconductor layer 401 is less than 6.4 g/cm 3
  • the density of the second oxide semiconductor layer 402 is greater than 6.4 g/cm 3 .
  • the thickness of the first oxide semiconductor layer 401 is greater than the thickness of the second oxide semiconductor layer 402, ensuring that the active layer 40 has a higher mobility.
  • the material of the drain 51 and the source 52 includes one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • the active layer 40 includes a channel region 41 between the drain 51 and the source 52, and a drain contact on a side of the channel region 41 and in contact with the drain 51.
  • the back channel etch type oxide semiconductor TFT substrate of the present invention has the active layer 40 disposed in a two-layer structure, the first oxide semiconductor layer 401 located in the lower layer has a normal density, and the second oxide semiconductor layer 402 located in the upper layer has a higher density. High density; the first oxide semiconductor layer 401 has a low density and a high mobility, and the second oxide semiconductor layer 402 has a high density, a small number of film defects, and a strong etching resistance.
  • the damage of the channel region 41 of the active layer 40 during the etching of the drain 51 and the source 52 can be reduced; therefore, the back channel etch type oxide semiconductor TFT substrate of the present invention has not only the active layer 40 but also the active layer 40 thereof.
  • the high mobility and the small number of film defects, TFT devices are less affected by light, water vapor, oxygen, hydrogen and organic matter in the environment, and have high reliability.
  • the present invention provides a back channel etch type oxide semiconductor TFT substrate and a method of fabricating the same.
  • the method for fabricating the back channel etch-type oxide semiconductor TFT substrate of the present invention has the active layer disposed in a two-layer structure, and the first oxide semiconductor layer located in the lower layer is prepared according to normal deposition process parameters, has a normal density, and is located at the upper layer.
  • the dioxide semiconductor layer is prepared by changing deposition process parameters, and has a higher density; the first oxide semiconductor layer has a lower density and a higher mobility, and the second oxide semiconductor layer has a higher density.
  • the back channel etch type oxide semiconductor TFT substrate produced by the present invention has not only a high migration of the active layer thereof
  • the rate and the number of film defects are small, and the TFT device is less affected by light, water vapor, oxygen, hydrogen and organic substances in the environment, and has high reliability.

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Abstract

一种背沟道蚀刻型氧化物半导体TFT基板及其制作方法。背沟道蚀刻型氧化物半导体TFT基板的制作方法将有源层（40）设置为双层结构，位于下层的第一氧化物半导体层（401）按照正常沉积工艺参数制备，具有正常密度，位于上层的第二氧化物半导体层（402）通过改变沉积工艺参数制备，具有较高密度；第一氧化物半导体层（401）的密度较低，具有较高的迁移率，第二氧化物半导体层（402）的密度较高，薄膜缺陷数目少，具有较强的抗蚀刻能力，能够减少在漏极（51）和源极（52）的蚀刻过程中有源层（40）的沟道区（41）受到的损伤，同时节省了刻蚀阻挡层光罩，制作成本低。

Description

背沟道蚀刻型氧化物半导体TFT基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种背沟道蚀刻型氧化物半导体TFT基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置和有源矩阵型OLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，非晶硅(a-Si)材料是比较常见的一种。
随着液晶显示装置和OLED显示装置向着大尺寸和高分辨率的方向发展，传统的a-Si仅有1cm2/(Vs)左右的迁移率已经无法满足要求，以铟镓锌氧化物(IGZO)为代表的金属氧化物材料具备超过10cm2/(Vs)以上的迁移率，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的产线的兼容性好，近年来迅速成为显示领域研发的重点。
相对于传统的a-Si TFT，IGZO TFT具有以下优势：
1、提高显示背板的分辨率，在保证相同透过率的前提下，IGZO TFT显示背板的分辨率可以做到a-Si TFT的2倍以上，IGZO材料中的载流子浓度高，迁移率大，可以缩小TFT的体积，保证分辨率的提升；
2、减少显示器件的能耗，IGZO TFT与a-Si TFT、LTPS TFT相比，漏电流小于1pA；驱动频率由原来的30-50Hz减少到2-5Hz，通过特殊工艺，甚至可以达到1Hz，虽然减少TFT的驱动次数，仍然可以维持液晶分子的配向，不影响画面的质量，从而减少显示背板的耗电量；另外，IGZO半导体材料的高迁移率使得较小尺寸的TFT即可提供足够的充电能力和较高的电容值，而且提高了液晶面板的开口率，光穿透的有效面积变大，可以用较少的背板组件或低功率消耗达到相同的亮度，减少能耗；
3、通过采用间歇式驱动等方式，能够降低液晶显示器驱动电路的噪点对触摸屏检测电路造成的影响，可以实现更高的灵敏度，甚至尖头的圆珠笔笔端也能够响应，而且由于画面无更新时可以切断电源，因此其在节能的效果上表现更为优秀。
目前，IGZO作为半导体有源层的TFT一般采用刻蚀阻挡(ESL)结构，由于有刻蚀阻挡层(Etch Stop Layer)存在，源漏极(Source/Drain)的蚀刻过程中，刻蚀阻挡层可以有效的保护IGZO有源层不受到影响，保证TFT具有优异的半导体特性。但是ESL结构的IGZO TFT的制备过程较为复杂，需要经过6次黄光工艺，不利于降低成本，因此业界普遍追求黄光工艺更少的背沟道蚀刻(BCE)结构的IGZO TFT的开发。
由于BCE结构的IGZO TFT中未设置刻蚀阻挡层来遮挡背沟道，因此在源漏极的蚀刻过程中IGZO有源层的沟道区容易受到损伤，并且由于IGZO有源层的薄膜缺陷数目较多，因此IGZO TFT对环境敏感，环境中的光、水汽(H2O)、氧气(O2)、氢气(H2)及有机物(Organics)等都容易对TFT性能造成影响，导致TFT器件的可靠性较低，面板的使用寿命较短。
发明内容
本发明的目的在于提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，能够减小漏极和源极的蚀刻过程中有源层的沟道区受到的损伤，从而有效降低有源层的薄膜缺陷数目，同时节省了刻蚀阻挡层光罩，制作成本低。
本发明的目的还在于提供一种背沟道蚀刻型氧化物半导体TFT基板，其有源层不仅具有较高的迁移率，而且薄膜缺陷数目较少，TFT器件受环境影响较小，具有较高的可靠性。
为实现上述目的，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在 所述衬底基板上形成覆盖栅极的栅极绝缘层；
在所述栅极绝缘层上沉积第一氧化物半导体层，在所述第一氧化物半导体层上沉积第二氧化物半导体层，所述第二氧化物半导体层的密度大于所述第一氧化物半导体层的密度；
对所述第一氧化物半导体层与第二氧化物半导体层进行图形化处理，得到有源层；
在所述有源层与栅极绝缘层上沉积金属材料并刻蚀形成漏极与源极，所述漏极与源极分别与有源层的两侧相接触；
在所述栅极绝缘层上形成覆盖漏极、源极、及有源层的钝化层；在所述钝化层上形成对应于漏极上方的通孔。
所述第一氧化物半导体层与第二氧化物半导体层的材料分别包括铟镓锌氧化物与铟锌锡氧化物中的一种或多种；所述第一氧化物半导体层与第二氧化物半导体层的材料相同或不同。
所述第一氧化物半导体层的密度小于6.4g/cm3，所述第二氧化物半导体层的密度大于6.4g/cm3。
所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度。
所述栅极的材料包括钼、铝、铜中的一种或多种；所述栅极绝缘层为氮化硅层、氧化硅层、或者氮化硅层与氧化硅层的叠层复合膜；所述钝化层为氮化硅层或氧化硅层；所述漏极与源极的材料包括钼、铝、铜中的一种或多种。
本发明还提供一种背沟道蚀刻型氧化物半导体TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述衬底基板上且覆盖栅极的栅极绝缘层、设于所述栅极绝缘层上且对应于栅极上方的有源层、设于所述有源层与栅极绝缘层上且分别与所述有源层两侧相接触的漏极与源极、设于所述栅极绝缘层上且覆盖所述漏极、源极、及有源层的钝化层、及设于所述钝化层上对应于漏极上方的通孔；
所述有源层包括设于所述栅极绝缘层上的第一氧化物半导体层、及设于所述第一氧化物半导体层上的第二氧化物半导体层，所述第二氧化物半导体层的密度大于所述第一氧化物半导体层的密度。
所述第一氧化物半导体层与第二氧化物半导体层的材料分别包括铟镓锌氧化物与铟锌锡氧化物中的一种或多种；所述第一氧化物半导体层与第二氧化物半导体层的材料相同或不同。
所述第一氧化物半导体层的密度小于6.4g/cm3，所述第二氧化物半导体层的密度大于6.4g/cm3。
所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度。
所述栅极的材料包括钼、铝、铜中的一种或多种；所述栅极绝缘层为氮化硅层、氧化硅层、或者氮化硅层与氧化硅层的叠层复合膜；所述钝化层为氮化硅层或氧化硅层；所述漏极与源极的材料包括钼、铝、铜中的一种或多种。
本发明还提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层；
在所述栅极绝缘层上沉积第一氧化物半导体层，在所述第一氧化物半导体层上沉积第二氧化物半导体层，所述第二氧化物半导体层的密度大于所述第一氧化物半导体层的密度；
对所述第一氧化物半导体层与第二氧化物半导体层进行图形化处理，得到有源层；
在所述有源层与栅极绝缘层上沉积金属材料并刻蚀形成漏极与源极，所述漏极与源极分别与有源层的两侧相接触；
在所述栅极绝缘层上形成覆盖漏极、源极、及有源层的钝化层；在所述钝化层上形成对应于漏极上方的通孔；
其中，所述第一氧化物半导体层与第二氧化物半导体层的材料分别包括铟镓锌氧化物与铟锌锡氧化物中的一种或多种；所述第一氧化物半导体层与第二氧化物半导体层的材料相同或不同；
其中，所述第一氧化物半导体层的密度小于6.4g/cm3，所述第二氧化物半导体层的密度大于6.4g/cm3；
其中，所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度；
其中，所述栅极的材料包括钼、铝、铜中的一种或多种；所述栅极绝缘层为氮化硅层、氧化硅层、或者氮化硅层与氧化硅层的叠层复合膜；所述钝化层为氮化硅层或氧化硅层；所述漏极与源极的材料包括钼、铝、铜中的一种或多种。
本发明的有益效果：本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法将有源层设置为双层结构，位于下层的第一氧化物半导体层按照正常沉积工艺参数制备，具有正常密度，位于上层的第二氧化物半导体层通过改变沉积工艺参数制备，具有较高密度；所述第一氧化物半导体层的密度较低，具有较高的迁移率，所述第二氧化物半导体层的密度较高，薄 膜缺陷数目少，具有较强的抗蚀刻能力，能够减少在漏极和源极的蚀刻过程中有源层的沟道区受到的损伤，同时节省了刻蚀阻挡层光罩，制作成本低；因此本发明制得的背沟道蚀刻型氧化物半导体TFT基板其有源层不仅具有较高的迁移率，而且薄膜缺陷数目较少，TFT器件受环境中的光、水汽、氧气、氢气及有机物的影响较小，具有较高的可靠性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的流程图；
图2为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S1的示意图；
图3与图4为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S2的示意图；
图5为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S3的示意图；
图6与图7为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S4的示意图且图7为本发明的背沟道蚀刻型氧化物半导体TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤S1、如图2所示，提供衬底基板10，在所述衬底基板10上沉积金属材料并刻蚀形成栅极20，在所述衬底基板10上形成覆盖栅极20的栅极绝缘层30。
具体的，所述衬底基板10为玻璃基板。
具体的，所述步骤S1还包括：在所述衬底基板10上形成栅极20之前，对所述衬底基板10进行清洗与烘烤。
具体的，所述栅极20的材料包括钼(Mo)、铝(Al)、铜(Cu)中的一种或多种。
具体的，所述栅极绝缘层30为氮化硅(SiNx)层、氧化硅(SiOx)层、或者氮化硅(SiNx)层与氧化硅(SiOx)层的叠层复合膜。
步骤S2、如图3所示，在所述栅极绝缘层30上沉积第一氧化物半导体层401，在所述第一氧化物半导体层401上沉积第二氧化物半导体层402，所述第二氧化物半导体层402的密度大于所述第一氧化物半导体层401的密度；
如图4所示，对所述第一氧化物半导体层401与第二氧化物半导体层402进行图形化处理，得到有源层40。
具体的，所述第一氧化物半导体层401与第二氧化物半导体层402的材料分别包括铟镓锌氧化物(IGZO)与铟锌锡氧化物(IZTO)中的一种或多种；所述第一氧化物半导体层401与第二氧化物半导体层402的材料相同或不同。
具体的，所述第一氧化物半导体层401的密度小于6.4g/cm3，所述第二氧化物半导体层402的密度大于6.4g/cm3。
具体的，所述第一氧化物半导体层401按照正常沉积工艺参数制备，具有正常密度，所述第二氧化物半导体层402通过改变沉积工艺参数制备，具有较高密度，本发明通过将第一氧化物半导体层401设置为较低密度，可以保证其具有较高迁移率，通过将第二氧化物半导体层402设置为较高密度，使其具有较少的薄膜缺陷数目，从而保证其具有较强的抗蚀刻能力，有效减少在后续的漏极51和源极52的蚀刻过程中有源层40的沟道区41受到的损伤。
优选的，所述第一氧化物半导体层401的厚度较大，所述第二氧化物半导体层402的厚度较小，即所述第一氧化物半导体层401的厚度大于所述第二氧化物半导体层402的厚度，以保证有源层40具有较高的迁移率。
步骤S3、如图5所示，在所述有源层40与栅极绝缘层30上沉积金属材料并刻蚀形成漏极51与源极52，所述漏极51与源极52分别与有源层40的两侧相接触。
具体的，所述漏极51与源极52的材料包括钼(Mo)、铝(Al)、铜(Cu)中的一种或多种。
具体的，所述漏极51与源极52在所述有源层40上限定出位于所述漏 极51与源极52之间的沟道区41、位于所述沟道区41一侧且与所述漏极51相接触的漏极接触区42、以及位于所述沟道区41另一侧且与所述源极52相接触的源极接触区43。
步骤S4、如图6所示，在所述栅极绝缘层30上形成覆盖漏极51、源极52、及有源层40的钝化层60；如图7所示，在所述钝化层60上形成对应于漏极51上方的通孔61。
具体的，所述钝化层60为氮化硅(SiNx)层或氧化硅(SiOx)层。
具体的，所述通孔61用于在后续制程中实现LCD像素电极或者OLED阳极与漏极51之间的电性连接。
值得一提的是，图5至图7中的虚线仅用于对有源层40的沟道区41、漏极接触区42、及源极接触区43进行划分，不具有其它含义。
本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法将有源层40设置为双层结构，位于下层的第一氧化物半导体层401按照正常沉积工艺参数制备，具有正常密度，位于上层的第二氧化物半导体层402通过改变沉积工艺参数制备，具有较高密度；所述第一氧化物半导体层401的密度较低，具有较高的迁移率，所述第二氧化物半导体层402的密度较高，薄膜缺陷数目少，具有较强的抗蚀刻能力，能够减少在漏极51和源极52的蚀刻过程中有源层40的沟道区41受到的损伤，同时节省了刻蚀阻挡层光罩，制作成本低；因此本发明制得的背沟道蚀刻型氧化物半导体TFT基板其有源层40不仅具有较高的迁移率，而且薄膜缺陷数目较少，TFT器件受环境中的光、水汽、氧气、氢气及有机物的影响较小，具有较高的可靠性。
请参阅图7，基于上述背沟道蚀刻型氧化物半导体TFT基板的制作方法，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板，包括：衬底基板10、设于所述衬底基板10上的栅极20、设于所述衬底基板10上且覆盖栅极20的栅极绝缘层30、设于所述栅极绝缘层30上且对应于栅极20上方的有源层40、设于所述有源层40与栅极绝缘层30上且分别与所述有源层40两侧相接触的漏极51与源极52、设于所述栅极绝缘层30上且覆盖所述漏极51、源极52、及有源层40的钝化层60、及设于所述钝化层60上对应于漏极51上方的通孔61；
所述有源层40包括设于所述栅极绝缘层30上的第一氧化物半导体层401、及设于所述第一氧化物半导体层401上的第二氧化物半导体层402，所述第二氧化物半导体层402的密度大于所述第一氧化物半导体层401的密度。
具体的，所述栅极20的材料包括钼(Mo)、铝(Al)、铜(Cu)中的 一种或多种。
具体的，所述栅极绝缘层30为氮化硅(SiNx)层、氧化硅(SiOx)层、或者氮化硅(SiNx)层与氧化硅(SiOx)层的叠层复合膜。
具体的，所述第一氧化物半导体层401与第二氧化物半导体层402的材料分别包括铟镓锌氧化物(IGZO)与铟锌锡氧化物(IZTO)中的一种或多种；所述第一氧化物半导体层401与第二氧化物半导体层402的材料相同或不同。
具体的，所述第一氧化物半导体层401的密度小于6.4g/cm3，所述第二氧化物半导体层402的密度大于6.4g/cm3。
优选的，所述第一氧化物半导体层401的厚度大于所述第二氧化物半导体层402的厚度，保证有源层40具有较高的迁移率。
具体的，所述漏极51与源极52的材料包括钼(Mo)、铝(Al)、铜(Cu)中的一种或多种。
具体的，所述有源层40包括位于所述漏极51与源极52之间的沟道区41、位于所述沟道区41一侧且与所述漏极51相接触的漏极接触区42、以及位于所述沟道区41另一侧且与所述源极52相接触的源极接触区43。
本发明的背沟道蚀刻型氧化物半导体TFT基板将有源层40设置为双层结构，位于下层的第一氧化物半导体层401具有正常密度，位于上层的第二氧化物半导体层402具有较高密度；所述第一氧化物半导体层401的密度较低，具有较高的迁移率，所述第二氧化物半导体层402的密度较高，薄膜缺陷数目少，具有较强的抗蚀刻能力，能够减少在漏极51和源极52的蚀刻过程中有源层40的沟道区41受到的损伤；因此本发明的背沟道蚀刻型氧化物半导体TFT基板其有源层40不仅具有较高的迁移率，而且薄膜缺陷数目较少，TFT器件受环境中的光、水汽、氧气、氢气及有机物的影响较小，具有较高的可靠性。
综上所述，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板及其制作方法。本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法将有源层设置为双层结构，位于下层的第一氧化物半导体层按照正常沉积工艺参数制备，具有正常密度，位于上层的第二氧化物半导体层通过改变沉积工艺参数制备，具有较高密度；所述第一氧化物半导体层的密度较低，具有较高的迁移率，所述第二氧化物半导体层的密度较高，薄膜缺陷数目少，具有较强的抗蚀刻能力，能够减少在漏极和源极的蚀刻过程中有源层的沟道区受到的损伤，同时节省了刻蚀阻挡层光罩，制作成本低；因此本发明制得的背沟道蚀刻型氧化物半导体TFT基板其有源层不仅具有较高的迁移 率，而且薄膜缺陷数目较少，TFT器件受环境中的光、水汽、氧气、氢气及有机物的影响较小，具有较高的可靠性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层；
    在所述栅极绝缘层上沉积第一氧化物半导体层，在所述第一氧化物半导体层上沉积第二氧化物半导体层，所述第二氧化物半导体层的密度大于所述第一氧化物半导体层的密度；
    对所述第一氧化物半导体层与第二氧化物半导体层进行图形化处理，得到有源层；
    在所述有源层与栅极绝缘层上沉积金属材料并刻蚀形成漏极与源极，所述漏极与源极分别与有源层的两侧相接触；
    在所述栅极绝缘层上形成覆盖漏极、源极、及有源层的钝化层；在所述钝化层上形成对应于漏极上方的通孔。
  2. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述第一氧化物半导体层与第二氧化物半导体层的材料分别包括铟镓锌氧化物与铟锌锡氧化物中的一种或多种；所述第一氧化物半导体层与第二氧化物半导体层的材料相同或不同。
  3. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述第一氧化物半导体层的密度小于6.4g/cm3，所述第二氧化物半导体层的密度大于6.4g/cm3。
  4. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度。
  5. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述栅极的材料包括钼、铝、铜中的一种或多种；所述栅极绝缘层为氮化硅层、氧化硅层、或者氮化硅层与氧化硅层的叠层复合膜；所述钝化层为氮化硅层或氧化硅层；所述漏极与源极的材料包括钼、铝、铜中的一种或多种。
  6. 一种背沟道蚀刻型氧化物半导体TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述衬底基板上且覆盖栅极的栅极绝缘层、设于所述栅极绝缘层上且对应于栅极上方的有源层、设于所述有源层与栅极绝缘层上且分别与所述有源层两侧相接触的漏极与源极、设于所述栅极 绝缘层上且覆盖所述漏极、源极、及有源层的钝化层、及设于所述钝化层上对应于漏极上方的通孔；
    所述有源层包括设于所述栅极绝缘层上的第一氧化物半导体层、及设于所述第一氧化物半导体层上的第二氧化物半导体层，所述第二氧化物半导体层的密度大于所述第一氧化物半导体层的密度。
  7. 如权利要求6所述的背沟道蚀刻型氧化物半导体TFT基板，其中，所述第一氧化物半导体层与第二氧化物半导体层的材料分别包括铟镓锌氧化物与铟锌锡氧化物中的一种或多种；所述第一氧化物半导体层与第二氧化物半导体层的材料相同或不同。
  8. 如权利要求6所述的背沟道蚀刻型氧化物半导体TFT基板，其中，所述第一氧化物半导体层的密度小于6.4g/cm3，所述第二氧化物半导体层的密度大于6.4g/cm3。
  9. 如权利要求6所述的背沟道蚀刻型氧化物半导体TFT基板，其中，所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度。
  10. 如权利要求6所述的背沟道蚀刻型氧化物半导体TFT基板，其中，所述栅极的材料包括钼、铝、铜中的一种或多种；所述栅极绝缘层为氮化硅层、氧化硅层、或者氮化硅层与氧化硅层的叠层复合膜；所述钝化层为氮化硅层或氧化硅层；所述漏极与源极的材料包括钼、铝、铜中的一种或多种。
  11. 一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层；
    在所述栅极绝缘层上沉积第一氧化物半导体层，在所述第一氧化物半导体层上沉积第二氧化物半导体层，所述第二氧化物半导体层的密度大于所述第一氧化物半导体层的密度；
    对所述第一氧化物半导体层与第二氧化物半导体层进行图形化处理，得到有源层；
    在所述有源层与栅极绝缘层上沉积金属材料并刻蚀形成漏极与源极，所述漏极与源极分别与有源层的两侧相接触；
    在所述栅极绝缘层上形成覆盖漏极、源极、及有源层的钝化层；在所述钝化层上形成对应于漏极上方的通孔；
    其中，所述第一氧化物半导体层与第二氧化物半导体层的材料分别包括铟镓锌氧化物与铟锌锡氧化物中的一种或多种；所述第一氧化物半导体层与第二氧化物半导体层的材料相同或不同；
    其中，所述第一氧化物半导体层的密度小于6.4g/cm3，所述第二氧化物半导体层的密度大于6.4g/cm3；
    其中，所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度；
    其中，所述栅极的材料包括钼、铝、铜中的一种或多种；所述栅极绝缘层为氮化硅层、氧化硅层、或者氮化硅层与氧化硅层的叠层复合膜；所述钝化层为氮化硅层或氧化硅层；所述漏极与源极的材料包括钼、铝、铜中的一种或多种。
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