WO2020056868A1 - 提高显示清晰度的面板 - Google Patents

提高显示清晰度的面板 Download PDF

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Publication number
WO2020056868A1
WO2020056868A1 PCT/CN2018/113294 CN2018113294W WO2020056868A1 WO 2020056868 A1 WO2020056868 A1 WO 2020056868A1 CN 2018113294 W CN2018113294 W CN 2018113294W WO 2020056868 A1 WO2020056868 A1 WO 2020056868A1
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Prior art keywords
layer
panel
data line
thin film
film transistor
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PCT/CN2018/113294
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English (en)
French (fr)
Inventor
周德利
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深圳市华星光电技术有限公司
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Publication of WO2020056868A1 publication Critical patent/WO2020056868A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of liquid crystal display technology, and in particular, to a panel for improving display definition.
  • the optical module in the display panel has a great influence on the clarity of the display panel.
  • some existing display panels by performing an L48 grayscale picture lighting test on the optical module in the display panel, it was found that The product has a rough screen. This situation is mainly manifested by uneven display of light and dark between different rows. Microscopic observation confirmed that there is a large difference in light and dark between adjacent two rows of pixels. On the macro level, the naked eye will treat such bright and dark dots of two adjacent rows as a bright dot, which will cause the picture of the display panel to be rough. This difference in brightness between two adjacent rows of pixels causes the display screen of the display panel to be rough, which reduces the display effect of the display panel.
  • the present disclosure provides a panel with improved display resolution to solve the problems that the brightness difference between two adjacent rows of pixels in a display panel in the prior art level causes the panel display screen to be rough and the panel definition to be low.
  • a panel for improving display clarity is provided.
  • a plurality of data lines for providing a data signal, a plurality of gate lines for providing a scanning signal provided intersecting the data lines, a plurality of areas surrounded by the data lines and the gate lines, and being disposed in Indium Tin Oxide (ITO) electrodes and shell metals in the area
  • ITO Indium Tin Oxide
  • a plurality of data lines providing data signals and a thin film transistor (Thin Film Transistor, TFT) connected to the data line through a gate lead.
  • TFT Thin Film Transistor
  • the thin film transistor TFTs adjacent to the upper and lower rows are connected to the same side of the data line, and the openings of the thin film transistor TFTs adjacent to the upper and lower rows are the same;
  • the multilayer structure in the thin film transistor TFT further includes a protective layer, and the protective layer is disposed between the G-SiN J1 and the Mo / Al / Mo layer.
  • a panel for improving display clarity provided by the embodiment of the present disclosure, a distance between the data line and the shell metal on both sides of the data line is the same as that on both sides of the data line in the industry The average distance between shelling metals is doubled.
  • a distance between the data line and the shelling metal on both sides of the data line is greater than 2.19 M m.
  • the distance between the data line and the shell metal on both sides of the data line is a multiplication relationship of a preset distance of 2.19 am .
  • each layer is a Mo / Al layer, G-SiN M, Mo / Al / Mo layer, P-SiN jl.
  • a thin film transistor TFT and a pixel electrode ITO electrode are provided in the pixel equivalent circuit area, and the thin film transistor has a gate and a source. Electrode, drain.
  • the thin film transistor TFT of the G-SiN x layer is an insulating layer.
  • the OC layer is a conductive layer
  • the thickness of the G-SiN J1 of the thin film transistor TFT is about 3500 ⁇ .
  • the thickness of the bottom Mo layer is 225 to 325 people, and the thickness of the AL layer is 3150 to 3850 people.
  • Top Mo layer thickness is 450 ⁇ 550
  • the thin film transistor TFT includes a plurality of metal leads, and the metal leads are formed of any one of molybdenum or a molybdenum-containing alloy material.
  • the panel provided by the present disclosure to improve the display definition reduces the influence of other area components on the internal capacitance of the thin film transistor TFT or the influence of the coupling capacitance between the data line and the ITO through different panel structures. Therefore, the brightness of the pixels is improved, the situation of the rough picture caused by the difference between the brightness and darkness of the two adjacent rows of pixels is solved, the same brightness and darkness are displayed on the display panel, and the sharpness is improved.
  • FIG. 1 is a schematic diagram of a TFT structure in an embodiment provided by the present disclosure
  • FIG. 2 is a schematic diagram of each film layer in a design technique
  • FIG. 3 is a schematic diagram of each film layer in another embodiment provided by the present disclosure.
  • FIG. 4 is a schematic diagram of TFT settings on both sides of a data line in the prior art
  • FIG. 5 is a schematic diagram of TFT settings on both sides of a data line in the present disclosure.
  • orientations or positional relationships indicated by “,” “bottom”, “inner”, “outer”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing this disclosure and simplifying the description, rather than indicating or implying
  • the device or element must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
  • the terms “first” and “second” are used for descriptive purposes only, and should not be interpreted as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of "a plurality" is two or more, unless it is specifically and specifically defined otherwise.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a schematic diagram of a TFT structure provided in the present disclosure.
  • a gate line 101, a thin film transistor TFT 102, a Dateline data line 103, a shelling metal 104, and an ITO electrode 105 are provided in a display panel to provide a scanning signal.
  • the distance between the data line 103 and the shelled metal 104 and between the shelled metal 104 and the ITO electrode 105 will affect the value of the coupling capacitance C pd formed inside the TFT, and further affect the pixel voltage between two adjacent rows.
  • the preset distance between the data line 103 and the shelled metal 104 on the left side of the data line 103 is X ld
  • the preset distance d between the shelling metals 104 on the right side of 103 is increased and doubled, so that the distance between them is twice the preset distance d, that is, 2d or nd.
  • the preset distance d is an average distance between the shelled metals on both sides of the data line in the industry.
  • the distance between the data line 103 and the hulled metal 104 on both sides of the data line 103 increases, the preset distance is 2.19 circles, and the multiplication becomes 4.38 circles.
  • the distance between the data line 103 and the shelled metal 104 on the left and right sides of the data line 103 becomes larger, thereby further reducing the influence on the coupling capacitance C pd , the loss of ⁇ V in the line will be reduced. .
  • the pixel voltage v pixd i will increase, thereby further improving the brightness of the pixels in each row.
  • Embodiment two [0035]
  • FIG. 2 is a schematic diagram of layers in the conventional design technology, in which a substrate 201, a Mo / Al layer 202, a G-SiN x insulating layer 203, and a Mo / AL / Mo drain / source electrode layer 205 and P-SiN jl206.
  • the equivalent capacitance formed between the layers has a direct relationship with the distance between the layers.
  • FIG. 3 is a schematic diagram of each layer provided by the present disclosure.
  • the OverCoat (OC) protective layer 3 01 is provided by adding another OC protective layer 301 between the G-SiN x insulating layer 203 and the Mo / AL / Mo electrode layer 205.
  • the thickness of the G-SiNx layer is about 3,500 people.
  • the thickness of the bottom Mo layer is 225 to 325
  • the thickness of the AL layer is 3150 to 3850
  • the thickness of the top Mo layer is 450 to 550 people.
  • the increase of the OC protective layer 301 does not affect the performance of the entire TFT electrode.
  • a capacitor-like upper and lower electrode plate is formed between the upper and lower layers.
  • the coupling capacitance C gd e * s / (; 4jtkd). It can be seen that the larger the distance between the two plates, the smaller the value of the coupling capacitance C gd .
  • FIG. 4 is a schematic diagram of TFT settings on both sides of a data line in the prior art.
  • TFT 401, gate pin line 402, data line 403, the thin film transistor TFT 401 includes a plurality of metal leads, and the metal leads are formed of any one of molybdenum or a molybdenum-containing alloy material.
  • the TFTs 401 in two adjacent rows are arranged left and right along the data line 403. This setting will cause the openings of the main TFTs in the upper and lower rows of the gate pin line to be oriented.
  • the gate layer Gate layer
  • FIG. 5 is a schematic diagram of TFT settings on both sides of a data line in the present disclosure.
  • the setting of the TFT is changed from a common flip-chip design to a non-flip-chip design, so that the two rows of TFTs on the data line are on the same side of the data line, as shown in FIG. 5
  • the opening directions of the main TFTs in the upper and lower rows become the same, and the difference between the coupling capacitances C gd of the adjacent two rows does not occur, and the interlaced display becomes normal.

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Abstract

本揭示提供一种提高显示清晰度的面板，数据线、栅极线，以及ITO电极和脱壳金属，数据线与脱壳金属之间的距离为行业内数据线与两侧的脱壳金属之间距离均值的倍增关系；或者，在TFT的G-SiNx层和Mo/AL/Mo层之间设置一保护层；或者，在现有显示面板的基础上，将倒装式设计中的TFT反向180°设计，使第N行与第N+1行的TFT开口朝向相同。

Description

提高显示清晰度的面板 技术领域
[0001] 本揭示涉及液晶显示技术领域， 尤其涉及一种提高显示清晰度的面板。
背景技术
[0002] 随着科学技术的飞速发展， 人们对显示设备的研究也越来越深入， 同时， 随着 显示面板需求的增加， 人们对显示面板的性能要求也在不断地提高， 希望能进 一步得到各种显示效果优异的显示面板。
[0003] 显示面板内的光学模组对显示面板的清晰度有很大的影响， 在现有的一些显示 面板中， 通过对显示面板内的光学模组进行 L48灰阶画面点灯测试， 发现部分产 品的画面粗糙现象严重， 这种情况主要表现为不同行别间的亮暗显示不均匀， 通过显微镜观察， 确认为相邻两行像素之间的亮暗差异大。 在宏观上， 肉眼就 会将这种相邻两行亮暗的点当作一个亮点， 从而导致显示面板的画面粗糙。 这 种相邻两行像素亮暗的不同导致了显示面板显示画面粗糙， 使得显示面板的显 示效果降低。
[0004] 因此， 针对显示面板中相邻两行像素亮暗的差异导致面板显示画面粗糙， 显示 面板的清晰度低的问题， 有必要提供一种提高显示清晰度的面板， 以解决现有 技术所存在的问题。
发明概述
技术问题
[0005] 本揭示提供一种提高显示清晰度的面板， 以解决现有技术水平上显示面板中相 邻两行像素亮暗的差异导致面板显示画面粗糙， 面板清晰度低的问题。
[0006] 为解决上述技术问题， 本揭示提供的技术方案如下：
[0007] 根据本揭示实施例的第一方面， 提供了一种提高显示清晰度的面板，
[0008] 数个提供数据信号的数据线、 与所述数据线交叉设置的数个提供扫描信号的栅 极线、 所述数据线与所述栅极线相交围成的数个区域、 设置于所述区域内的氧 化铟锡 (Indium Tin Oxide, ITO)电极以及脱壳金属， [0009] 数个提供数据信号的数据线以及通过栅极引线连接在所述数据线上的薄膜晶体 管 (Thin Film Transistor, TFT) 所述的薄膜晶体管 TFT中的多层结构， 各层依次 为 Mo/Al层、 G-SiN M, Mo/Al/Mo层、 P-SiN jl。
[0010] 相邻上下两行的所述薄膜晶体管 TFT连接在所述数据线的同一侧， 相邻上下两 行的所述薄膜晶体管 TFT的开口朝向相同；
[0011] 所述薄膜晶体管 TFT中的多层结构还包括保护层， 所述保护层设置在 G-SiN J1 与 Mo/Al/Mo层之间。
[0012] 本揭示实施例所提供的一种提高显示清晰度的面板， 所述数据线与所述数据线 两侧的所述脱壳金属之间的距离为行业内数据线两侧的所述脱壳金属之间的距 离均值倍增。
[0013] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述数据线与所述数 据线两侧的所述脱壳金属之间的距离大于 2.19 Mm。
[0014] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述数据线与所述数 据线两侧的所述脱壳金属间的距离为预设距离 2.19 am的倍增关系。
[0015] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述的薄膜晶体管 TF T中的多层结构， 各层依次为 Mo/Al层、 G-SiN M, Mo/Al/Mo层、 P-SiN jl。
[0016] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述像素等效电路区 域内设置有包括薄膜晶体管 TFT及像素电极 ITO电极， 所述薄膜晶体管具有栅极 、 源极、 漏极。
[0017] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述薄膜晶体管 TFT 的所述 G-SiN x层为绝缘层。
[0018] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述 OC层为导电层
[0019] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述薄膜晶体管 TFT 的所述 G-SiN J1的厚度为大约 3500入。
[0020] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述 Mo/AL/Mo层中 ， 底 Mo层厚度为 225~325人， AL层厚度为 3150~3850人， 顶 Mo层厚度为 450~550
A [0021] 在本揭示实施例所提供的一种提高显示清晰度的面板中， 所述薄膜晶体管 TFT 包括有多条金属引线， 所述金属引线由钼或含钼合金材料的任意一种构成。
[0022] 综上所述， 本揭示的有益效果为：
[0023] 本揭示提供的提高显示清晰度的面板， 通过不同的面板结构， 降低其他区域部 件对薄膜晶体管 TFT内部电容 0^的影响或者减小数据线线路与 ITO之间的耦合电 容的影响， 从而提高像素的亮度， 解决因相邻两行像素亮暗的差异导致的画面 粗糙的情况， 使显示面板显示的画面亮暗相同， 清晰度提高。
问题的解决方案
发明的有益效果
对附图的简要说明
附图说明
[0024] 为了更清楚地说明实施例或现有技术中的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作简单介绍， 显而易见地， 下面描述中的附图仅仅 是本揭示的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动 的前提下， 还可以根据这些附图获得其他的附图。
[0025] 图 1为本揭示提供的一实施例中的 TFT结构示意图；
[0026] 图 2为 5见有设计技术中各膜层示意图；
[0027] 图 3为本揭示提供的另一实施例中各膜层示意图；
[0028] 图 4为现有技术中数据线两侧 TFT设置示意图；
[0029] 图 5为本揭示中数据线两侧 TFT设置示意图。
发明实施例
本发明的实施方式
[0030] 下面将结合本揭示实施例中的附图， 对本揭示实施例中的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例仅仅是本揭示一部分实施例， 而不是全部 的实施例。 基于本揭示中的实施例， 本领域技术人员在没有作出创造性劳动前 提下所获得的所有其他实施例， 都属于本揭示保护的范围。
[0031] 在本揭示的描述中， 需要理解的是， 术语“中心”、 “纵向”、 “横向”、 “长度”、 “ 宽度”、 “厚度”、 “上”、 “下”、 “前”、 “后”、 “左”、 “右”、 “竖直”、 “水平”、 “顶”
、 “底”、 “内”、 “外”、 等指示的方位或位置关系为基于附图所示的方位或位置关 系， 仅是为了便于描述本揭示和简化描述， 而不是指示或暗示所指的装置或元 件必须具有特定的方位、 以特定的方位构造和操作， 因此不能理解为对本发明 的限制。 此外， 术语“第一”、 “第二”仅用于描述目的， 而不能理解为指示或暗示 相对重要性或者隐含指明所指示的技术特征的数量。 由此， 限定有“第一”、 “第 二”的特征可以明示或者隐含地包括一个或者更多个所述特征。 在本发明的描述 中， “多个”的含义是两个或两个以上， 除非另有明确具体的限定。
[0032] 实施例一：
[0033] 如图 1为本揭示提供的 TFT结构示意图， 显示面板中提供扫描信号的栅极线 101 ， 薄膜晶体管 TFT102， Dateline数据线 103， Shelling Metal脱壳金属 104， ITO电 极 105。 设置的数据线 103与脱壳金属 104以及脱壳金属 104与 ITO电极 105之间的 距离都会影响到 TFT内部形成的耦合电容 Cpd数值大小， 进而对相邻两行之间的 像素电压有影响。 如图 1中所示， 所述数据线 103与所述数据线 103左侧的脱壳金 属 104之间的预设距离为 X ld
， 所述数据线 103与所述数据线 103右侧的脱壳金属 104之间的预设距离为 X ri， 其 中， 距离 X ld=X rd=d, 本揭示通过将数据线 103与数据线 103右侧的脱壳金属 104 之间的预设距离 d增大， 均倍增， 使得他们之间的距离为预设距离 d的两倍， 也 即 2d或者 nd。 预设距离 d为行业内数据线两侧的所述脱壳金属之间的距离均值。
[0034] 于实际中， 所述数据线 103与所述数据线 103两侧的脱壳金属 104间的距离增大 ， 预设距离为 2.19圆， 倍增变为 4.38圆。 这样， 由于所述数据线 103与所述数据 线 103左右两侧的脱壳金属 104之间的距离变大， 进而降低了对耦合电容 Cpd的影 响， 线路中△ V的损耗就会减小。 这样像素电压 vpixdi压就会增加， 从而进一步 提升了各行像素的亮度。
[0035] 实施例二：
[0036] 如图 2所示， 图 2为现有设计技术中各层示意图， 其中， 基板 201， Mo/Al层 202 ， G-SiN x绝缘层 203， Mo/AL/Mo漏 /源电极层 205以及 P-SiN jl206。 其中， 各层 之间形成的等效电容与各层之间的距离有直接的关系。 [0037] 因此， 如图 3所示， 图 3为本揭示提供的各层示意图。 OverCoat (OC) 保护层 3 01 , 通过在 G-SiN x绝缘层 203和 Mo/AL/Mo电极层 205这两层之间再增加一层 OC 保护层 301。 G-SiNx层的厚度为大约 3500人， 在 Mo/AL/Mo的各层结构中， 底 Mo 层厚度为 225~325人， AL层厚度为 3150~3850人， 顶 Mo层厚度为 450~550人。 所 述 OC保护层 301的增加并不会影响整个 TFT电极的性能， 上下层之间形成一个类 似电容的上下极板， 由于 OC保护层 301的增加， 使得 OC保护层 301上下层之间的 距离变大， 其中， 在正常情况下， 根据 TFT内部各个电容与电压之间的关系式： A y= cgd* yd p/( clc+ cs+ cgd) , 耦合电容＜^数值的大小与数据线和 ITO电极之间距 离成反比的关系， 耦合电容 Cgd=e *s/(；4jtkd)， 可知， 两极板之间的距离变大， 耦 合电容 Cgd的数值就会变小， 它们之间的 A VE会减小， 使得各行像素的像素电 压 Vpixd增加。 这样， 由于各行像素电压的提高， 本揭示中各行像素的亮度也会 比现有设计中的亮度高。
[0038] 实施例三：
[0039] 如图 4所示， 图 4为现有技术中数据线两侧 TFT设置示意图。 TFT 401， 栅极引 脚线 402， 数据线 403， 所述薄膜晶体管 TFT 401包括有多条金属引线， 所述金属 引线由钼或含钼合金材料的任意一种构成。 5见有的倒装式 Flip设计中， 将相邻两 行中的 TFT 401沿着数据线 403呈左右分布设置， 这样的设置会造成栅极引脚线 处的上下两行主 TFT的开口朝向不同， 在栅极层 (Gate
Layer)与数据线层 (DataLayer)单方向偏移时候， 相邻两行的耦合电容 Cgd会有 2倍 的差异， 从而隔行之间的亮暗差异明显， 画面不清晰。 图 5所示为本揭示中数据 线两侧 TFT设置示意图。 非倒装式 TFT 501， 栅极引脚线 502， 数据线 403。 本揭 示中， 将 TFT的设置由常用倒装式设计改变为非倒装式设计， 使得数据线上下两 行的 TFT在数据线的同一侧， 如图 5中处于数据线 403同侧的上下两个 TFT 501， 这样， 上下两行的主 TFT的开口朝向就会变成相同， 也不会出现相邻两行的耦合 电容 Cgd之间的差异， 隔行显示就会变正常。
[0040] 通过不同实施例中提供的揭示， 从产生上下两行像素亮暗不同的主要原因出发 ， 减小或降低各部件对耦合电容的影响， 以此改变相邻两行像素亮暗的差异情 况， 或者采用非倒装式 Flip设计， 解决现有技术中存在的问题， 达到解决提高画 面清晰度的目的。
[0041] 以上对本揭示实施例所提供的提高显示清晰度的面板进行了详细介绍， 本文中 应用了具体个例对本揭示的原理及实施方式进行了阐述， 以上实施例的说明只 是用于帮助理解本揭示的技术方案及其核心思想； 本领域的普通技术人员应当 理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部 分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质 脱离本揭示各实施例的技术方案的范围。

Claims

权利要求书
[权利要求 1] 一种提高显示清晰度的面板， 其中， 包括：
数个提供数据信号的数据线、 与所述数据线交叉设置的数个提供扫描 信号的栅极线、 所述数据线与所述栅极线相交围成的数个区域、 设置 于所述区域内的氧化铟锡电极以及脱壳金属，
数个提供数据信号的数据线以及通过栅极引线连接在所述数据线上的 薄膜晶体管 (Thin Film Transistor, TFT) 所述的薄膜晶体管 TFT中的多 层结构， 各层依次为 Mo/Al层、 G-SiN jl Mo/Al/Mo层、 P-SiNM 其中， 相邻上下两行的所述薄膜晶体管 TFT连接在所述数据线的同一 侧， 相邻上下两行的所述薄膜晶体管 TFT的开口朝向相同； 所述薄膜晶体管 TFT中的多层结构还包括保护层， 所述保护层设置在
G-SiN J1与 Mo/Al/Mo层之间；
所述数据线与所述数据线两侧的所述脱壳金属之间的距离为行业内数 据线两侧的所述脱壳金属之间的距离均值倍增。
[权利要求 2] 根据权利要求 1所述的提高显示清晰度的面板， 其中， 所述数据线与 所述数据线两侧的所述脱壳金属之间的距离大于预设距离 2.19 am
[权利要求 3] 根据权利要求 1所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT具有栅极、 源极、 漏极。
[权利要求 4] 根据权利要求 3所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT的所述 G-SiN J1为绝缘层
[权利要求 5] 根据权利要求 3所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT包括有多条金属引线， 所述金属引线由钼或含钼合金材料的任 意一种构成。
[权利要求 6] 根据权利要求 1所述的提高显示清晰度的面板， 其中， 所述保护层为 导电层。
[权利要求 7] 一种提高显示清晰度的面板， 其中， 包括：
数个提供数据信号的数据线、 与所述数据线交叉设置的数个提供扫描 信号的栅极线、 所述数据线与所述栅极线相交围成的数个区域、 设置 于所述区域内的氧化铟锡电极以及脱壳金属，
数个提供数据信号的数据线以及通过栅极引线连接在所述数据线上的 薄膜晶体管 (Thin Film Transistor, TFT) 所述的薄膜晶体管 TFT中的多 层结构， 各层依次为 Mo/Al层、 G-SiN jl， Mo/Al/Mo层、 P-SiNM 其中， 相邻上下两行的所述薄膜晶体管 TFT连接在所述数据线的同一 侧， 相邻上下两行的所述薄膜晶体管 TFT的开口朝向相同； 所述薄膜晶体管 TFT中的多层结构还包括保护层， 所述保护层设置在
G-SiN J1与 Mo/Al/Mo层之间。
[权利要求 8] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述数据线与 所述数据线两侧的所述脱壳金属之间的距离为行业内数据线两侧的所 述脱壳金属之间的距离均值倍增。
[权利要求 9] 根据权利要求 8所述的提高显示清晰度的面板， 其中， 所述数据线与 所述数据线两侧的所述脱壳金属之间的距离大于预设距离 2.19 am
[权利要求 10] 根据权利要求 9所述的提高显示清晰度的面板， 其中， 所述数据线与 所述数据线两侧的所述脱壳金属间的距离为预设距离 2.19 am的倍增 关系。
[权利要求 11] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT具有栅极、 源极、 漏极。
[权利要求 12] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT的所述 G-SiN J1为绝缘层。
[权利要求 13] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述保护层为 导电层。
[权利要求 14] 根据权利要求 12所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT的所述 G-SiNJ1的厚度为大约 3500人。
[权利要求 15] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述 Mo/AL/M o层中， 底 Mo层厚度为 225~325人。
[权利要求 16] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述 Mo/Al/Mo 层中， A1层厚度为 3150~3850人。
[权利要求 17] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述 Mo/AL/M o层中， 顶 Mo层厚度为 450~550入。
[权利要求 18] 根据权利要求 7所述的提高显示清晰度的面板， 其中， 所述薄膜晶体 管 TFT包括有多条金属引线， 所述金属引线由钼或含钼合金材料的任 意一种构成。
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