WO2019100428A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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Publication number
WO2019100428A1
WO2019100428A1 PCT/CN2017/113698 CN2017113698W WO2019100428A1 WO 2019100428 A1 WO2019100428 A1 WO 2019100428A1 CN 2017113698 W CN2017113698 W CN 2017113698W WO 2019100428 A1 WO2019100428 A1 WO 2019100428A1
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Prior art keywords
active layer
region
drain
source
layer
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PCT/CN2017/113698
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English (en)
French (fr)
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徐洪远
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/740,009 priority Critical patent/US10367017B2/en
Publication of WO2019100428A1 publication Critical patent/WO2019100428A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same.
  • Oxide semiconductor It is a class of oxides with semiconductor properties, and is the oxide semiconductor TFT which is the focus of the world's display technicians as the 'basic material for next-generation electronics'. Oxide semiconductor TFT It is one of the best candidates for TFT materials that drive next-generation displays such as ultra-high-definition LCD panels, organic EL panels, and electronic paper.
  • IGZO indium gallium zinc oxide
  • amorphous IGZO The material is a channel layer material used in next-generation thin film transistor technology and is one of the metal oxide (Oxied) panel technologies.
  • IGZO carrier mobility is 20 ⁇ 30 of amorphous silicon Double, can greatly improve the charge and discharge rate of the TFT electrode to achieve faster refresh rate, while the faster response also greatly improves the line scan rate of the pixel, making ultra-high resolution in the TFT-LCD It is possible.
  • IGZO displays have higher energy efficiency levels and are more efficient due to the reduced number of transistors and improved light transmission per pixel.
  • the device structure of IGZO-TFT is generally divided into ESL, BCE, TG, etc., among which ESL and BCE
  • the structure has a large parasitic capacitance due to the large overlap between the Gate electrode and the S/D electrode, and is not suitable for high-resolution OLED panels.
  • the IGZO of the Top-Gate structure can solve the problem of large parasitic capacitance, but the current mainstream TG-IGZO TFT device process is more complicated, generally requires 7 The number of reticles around the track completes the array substrate process.
  • the invention provides an array substrate and a preparation method thereof, which can reduce TG-IGZO TFT
  • the mask process of the device reduces costs.
  • the invention provides a method for fabricating an array substrate, the method comprising the following steps:
  • Step S1 Providing a substrate on which a light shielding layer, a buffer layer, an active layer, a source and a drain, a gate insulating layer and a gate are sequentially prepared; wherein the buffer layer is continuously deposited with an indium gallium zinc oxide layer Forming, with the second metal layer, the indium gallium zinc oxide as an active layer by a halftone mask, and simultaneously forming the second metal layer to form a source and a drain;
  • Step S2 performing a first conducting process for the corresponding regions of the active layer of the source and the drain;
  • Step S3 And performing a second conducting process on a corresponding region of the active layer between the source and the gate and between the drain and the gate.
  • the first conducting process includes performing an annealing process on the array substrate
  • the second conducting process includes performing a laser process on the array substrate.
  • the annealing process has a temperature of 200 to 300 Celsius to achieve conductorization in the active layer for the respective regions of the source and the drain.
  • the wavelength of the laser process is between 300 nm and 315.
  • Excimer laser light in the nanometer range illuminates the surface of the array substrate such that a corresponding region of the active layer between the source and the gate and between the drain and the gate is opposite Achieve conductorization.
  • titanium or aluminum in the source and the drain material is doped in the active layer.
  • the invention also provides an array substrate comprising:
  • the thin film transistor includes an active layer and a source and a drain above both ends of the active layer;
  • a gate electrode is prepared on the gate insulating layer
  • the active layer is an indium gallium zinc oxide material
  • a region of the active layer corresponding to the gate is a non-conductor region, and other regions of the active layer other than the non-conductor region are a conductor region
  • the conductor region corresponding to the source side is a source region
  • the conductor region corresponding to the drain side is a drain region
  • the array substrate includes a carrier for forming a carrier a channel region, the active layer in the non-conducting region is an active layer of the channel region; the active layer extends to the source region and the active layer facing the drain region The corresponding part.
  • the source region and the drain region of the active layer are performed by performing 200 ⁇ 300 on the substrate. Annealing at degrees Celsius and conduction with excimer laser light having a wavelength in the range of 300 nm to 315 nm.
  • the invention also provides an array substrate comprising:
  • the thin film transistor includes an active layer and a source and a drain above both ends of the active layer;
  • a gate electrode is prepared on the gate insulating layer
  • the active layer is an indium gallium zinc oxide material
  • a region of the active layer corresponding to the gate is a non-conductor region, and other regions of the active layer other than the non-conductor region are a conductor region;
  • the conductor region corresponding to the source side is a source region, and the conductor region corresponding to the drain side is a drain region.
  • the source region and the drain region of the active layer are performed by performing 200 ⁇ 300 on the substrate. Annealing at degrees Celsius and conduction with excimer laser light having a wavelength in the range of 300 nm to 315 nm.
  • the beneficial effects of the present invention are: Compared with the manufacturing method of the prior art TG-IGZO TFT device, the present invention Array substrate manufacturing method
  • the indium gallium zinc oxide layer and the second metal layer are continuously deposited on the buffer layer, and the indium gallium zinc oxide layer is formed into an active layer by using the same halftone mask, and the second metal layer is formed into a source and a drain; Annealing the substrate to make the corresponding regions of the indium gallium zinc oxide layer corresponding to the source and the drain below be conductorized; and then irradiating the substrate with the excimer laser to make the gate and the source / Corresponding regions of the corresponding indium gallium zinc oxide layer at the gap between the drains are conductorized.
  • FIG. 1 is a flow chart of a method for preparing an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of different stages in the process of preparing an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the present invention is directed to a method for fabricating a TG-IGZO TFT device of the prior art, which has a complicated process and a high cost technical problem. This embodiment can solve the drawback.
  • a specific embodiment of the present invention provides a method for fabricating an array substrate, and the method includes the following steps:
  • Step S1 Providing a substrate on which a light shielding layer, a buffer layer, an active layer, a source and a drain, a gate insulating layer, and a gate electrode are sequentially prepared;
  • Step S2 performing a first conducting process for the corresponding regions of the active layer of the source and the drain;
  • Step S3 And performing a second conducting process on a corresponding region of the active layer between the source and the gate and between the drain and the gate.
  • the manufacturing method of the array substrate may include the following steps:
  • Step S101 Preparing a first metal layer and a buffer layer on the substrate in sequence, and forming the light shielding layer by passing the first metal layer through the first mask;
  • Step S102 Depositing an indium gallium zinc oxide layer and a second metal layer continuously on the buffer layer, forming the indium gallium zinc oxide layer into an active layer through a second halftone mask, and simultaneously making the second The metal layer forms a source and a drain;
  • Step S103 sequentially preparing a gate insulating layer and a third metal layer, and forming a gate electrode by using the third photomask;
  • Step S104 Conducting a conductor other than the first region corresponding to the gate in the active layer; including: aligning the active layer with respect to the source and the drain Performing a first conducting process for the corresponding region; performing a second conducting process for the corresponding region of the active layer between the source and the gate and between the drain and the gate;
  • Step S105 covering the gate with a layer of the passivation layer, and forming a via hole in the passivation layer with a fourth photomask;
  • Step S106 depositing a pixel electrode layer on the passivation layer, and forming a pixel electrode by using a fifth mask.
  • a substrate 210 is provided first on the substrate 210.
  • a first metal layer is prepared thereon; the first metal layer is patterned by a first mask to form a light shielding layer 211 spaced apart from the substrate 210.
  • a buffer layer 222 is then deposited on the substrate 220, and the buffer layer 222 covers the light shielding layer.
  • 221 continuously depositing indium gallium zinc oxide on the buffer layer 222 (IGZO And the second metal layer, the indium gallium zinc oxide and the second metal layer are simultaneously patterned by a second halftone mask to form the indium gallium zinc oxide to form an indium gallium zinc oxide pattern
  • Active layer 223 The second metal layer forms a source 225 and a drain 224; the source 225 and the drain 224 are respectively located at opposite ends of the active layer 223, and the source 225 and the drain There is a gap between the 224; the source 225 and the drain 224 and the projection of the active layer 223 on the substrate 220 are located on the light shielding layer 221 at the substrate 220 Within the range of the projection.
  • the material of the second metal layer is one or more of titanium or aluminum, and if the second metal layer is a composite material of the titanium and the aluminum, the second metal layer It is a laminated structure of the titanium and the aluminum.
  • Buffer layer The material of 222 is silicon nitride or silicon dioxide.
  • a gate insulating layer 234 is then deposited on the buffer layer 231, and the gate insulating layer 234 Covering the patterned source 236 and the drain 233 and the active layer 232; depositing a third metal layer on the gate insulating layer 234, the third metal layer forming a gate 235 through the third mask .
  • the gate 235 is correspondingly located between the source 236 and the drain 233.
  • a corresponding region corresponding to the gate 235 is a first region 237
  • Corresponding regions corresponding to the source 236 and the drain 233 are a second region 238, and the gate 235 and the source 236/the drain 233
  • the area corresponding to the gap is the third area 239.
  • the material of the gate insulating layer 234 is silicon nitride or silicon dioxide.
  • a first conducting process is performed on the array substrate, and the first conducting process includes an annealing process, specifically, a substrate 241 is annealed at 200 to 300 degrees Celsius for a certain period of time, so that the second region of the active layer 244 under the source 242 and the drain 243 is 2441 Conducting the conductor; in the process, the material 242 and the material in the drain 243 may be uncomfortable to the active layer 244 In the case where the titanium or aluminum element diffusion tends to be uniformly distributed, it is slowly cooled to realize the conductor of the second region 2441.
  • a second conducting process is performed on the array substrate, and the second conducting process includes a laser process, specifically, an active layer.
  • the corresponding area of the corresponding gate 251 in 252 is the first area (as shown in FIG. 2c), and the area corresponding to the gap between the gate 251 and the source 254/drain 253 is the third area.
  • the active layer 252 irradiating the surface of the gate 251 side of the substrate with an excimer laser having a wavelength in the range of 300 nm to 315 nm along the irradiation direction 255, the active layer 252
  • the third region 2521 corresponding to the gate 251 and the source 254 / the drain 253 may be irradiated by laser to achieve conductorization, and the active layer 252 is gated
  • the first region blocked by the 251 is a non-conducting region, and the active layer can be avoided as a channel region.
  • the active layer 252 is formed by the annealing process and the laser process. Achieve self-aligned conductors.
  • a surface of the substrate on which the gate electrode 267 is formed is covered with a passivation layer 265. And forming a second via 264 on the passivation layer 265 with a fourth mask, and forming a first via 263 corresponding to the second via 264 on the gate insulating layer 261 Then depositing a layer of pixel electrodes and forming a pixel electrode 266 with a fifth mask; the pixel electrode 266 is connected to the drain 262 through the second via 264 and the first via 263 . So far, the process flow of the array substrate of the top gate structure is completed by five photomasks.
  • the present invention also provides an array substrate comprising: a substrate; a thin film transistor formed on the substrate; the thin film transistor including an active layer and a source and a drain located above both ends of the active layer; a layer is formed on the surface of the thin film transistor; a gate is formed on the gate insulating layer; wherein the active layer is an indium gallium zinc oxide material, and an area of the active layer corresponding to the gate is a non-conductor region, wherein the active layer is a conductor region other than the non-conductor region; the conductor region corresponding to the source side is a source region corresponding to the drain side The conductorized region is a drain region.
  • the array substrate includes: a substrate 301 a first metal layer formed on a surface of the substrate 301, the first metal layer forming a light shielding layer 302 disposed at intervals; a buffer layer 303 Prepared on the surface of the first metal layer; indium gallium zinc oxide deposited on the surface of the buffer layer 303, the indium gallium zinc oxide is patterned to form an active layer 304 a second metal layer deposited on a surface of the indium gallium zinc oxide, the second metal layer being patterned to form a source 305 and a drain 306; a gate insulating layer 307 Prepared on the surface of the second metal layer; a third metal layer is prepared on the surface of the gate insulating layer 307, and patterned to form a gate 308; a passivation layer 309 And preparing a surface of the third metal layer; a pixel electrode layer is prepared on the surface of the passivation layer 309; and
  • the active layer 304 includes a conductord region and a non-conductor region, and the conductorized region includes a first conductorized region 3042. And the second conductorized region 3041.
  • the indium gallium zinc oxide and the second metal layer are simultaneously patterned by a halftone mask, the active layer 304 corresponding to the source 305
  • the first conductive region 3042 on one side is a source region of the active layer 304
  • the second conductive region 3041 on a side corresponding to the drain 306 is the active layer 304.
  • the source region and the drain region are annealed by 200 to 300 degrees Celsius for the substrate 301, and the wavelength is between 300 nm and 315.
  • the array substrate includes a channel region for forming carriers, and the active layer located in the non-conductor region is an active layer of the channel region; The active layer extends to the source region and a corresponding portion of the active layer 304 opposite the drain region.
  • the gate insulating layer 307 is formed with a first via 3071, and the passivation layer 309 A second via 3091 corresponding to the first via 3071 is formed, and the pixel electrode 310 is connected to the drain through the second via 3091 and the first via 3071 306.
  • the method for fabricating the array substrate of the present invention The indium gallium zinc oxide layer and the second metal layer are continuously deposited on the buffer layer, and the indium gallium zinc oxide layer is formed into an active layer by using the same halftone mask, and the second metal layer is formed into a source and a drain; Annealing the substrate to make the corresponding regions of the indium gallium zinc oxide layer corresponding to the source and the drain below be conductorized; and then irradiating the substrate with the excimer laser to make the gate and the source / Corresponding regions of the corresponding indium gallium zinc oxide layer at the gap between the drains are conductorized. This reduces the two mask processes and completes the fabrication of the display device through five masks, thereby reducing the process and reducing the cost.

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Abstract

提供一种阵列基板及其制备方法。制备方法包括：提供一基板（210），在基板上依次制备遮光层（211）、缓冲层（222）、有源层（223）、源极（225）与漏极（224）、栅绝缘层（234）以及栅极（235）；对正对于源极与漏极的有源层的相应区域（238）进行第一导体化制程；对位于源极与栅极之间以及漏极与栅极之间的所述有源层的相应区域（239）进行第二导体化制程。

Description

一种阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
氧化物半导体（ oxide semiconductor ）是具有半导体特性的一类氧化物，作为'新一代电子的基础材料'而备受全球显示器技术人员关注的就是氧化物半导体 TFT 。因为氧化物半导体 TFT 是驱动超高精细液晶面板、有机 EL 面板以及电子纸等新一代显示器的 TFT 材料最佳候选之一。
IGZO(indium gallium zinc oxide) 为铟镓锌氧化物的缩写，非晶 IGZO 材料是用于新一代薄膜晶体管技术中的沟道层材料 , 是金属氧化物 (Oxied) 面板技术的一种。 IGZO 载流子迁移率是非晶硅的 20~30 倍，可以大大提高 TFT 对像素电极的充放电速率，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在 TFT-LCD 中成为可能。另外，由于晶体管数量减少和提高了每个像素的透光率， IGZO 显示器具有更高的能效水平，而且效率更高。
IGZO-TFT 的器件结构一般分为 ESL 、 BCE 、 TG 等几种类型，其中 ESL 、 BCE 结构因 Gate 电极和 S/D 电极之间存在较大覆盖面积（ overlap ）导致较大的寄生电容，不适合应用于高解析度的 OLED 面板。近几年发展起来的 Top-Gate 结构的 IGZO 可以解决寄生电容较大的问题，但目前主流的 TG-IGZO TFT 器件工艺比较复杂，一般需要 7 道左右的光罩数量来完成阵列基板工艺。
综上所述，现有技术的 TG-IGZO TFT 器件的制作方法，工艺比较复杂，成本较高 。
 技术问题
本发明提供 一种阵列基板及其制备方法， 能够缩减 TG-IGZO TFT 器件的光罩制程，从而降低成本。
技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板的制作方法， 所述方法包括以下步骤：
步骤 S1 、提供一基板，在所述基板上依次制备遮光层、缓冲层、有源层、源极与漏极、栅绝缘层以及栅极；其中，所述缓冲层上连续沉积铟镓锌氧化物层与第二金属层，通过半色调光罩使所述铟镓锌氧化物形成有源层，以及同时使所述第二金属层形成源极与漏极；
步骤 S2 、对正对于所述源极与所述漏极的所述有源层的相应区域进行第一导体化制程；
步骤 S3 、对位于所述源极与所述栅极之间以及所述漏极与所述栅极之间的所述有源层的相应区域进行第二导体化制程。
根据本发明一优选实施例，所述第一导体化制程包括对所述阵列基板进行退火制程，所述第二导体化制程包括对所述阵列基板进行镭射制程。
根据本发明一优选实施例，所述退火制程的温度为 200~300 摄氏度，以使所述有源层中正对于所述源极和所述漏极的相应区域实现导体化。
根据本发明一优选实施例，所述镭射制程中用波长处于 300 纳米 ~315 纳米范围内的准分子镭射光照射所述阵列基板表面，使对位于所述源极与所述栅极之间以及所述漏极与所述栅极之间的所述有源层的相应区域实现导体化。
根据本发明一优选实施例，所述退火制程中，所述源极与所述漏极材料中的钛或铝掺杂于所述有源层中。
本发明还提供一种阵列基板，包括：
基板；
薄膜晶体管，制备于所述基板上；
所述薄膜晶体管包括有源层以及位于所述有源层两端上方的源极与漏极；
栅绝缘层，制备于所述薄膜晶体管表面；
栅极，制备于所述栅绝缘层上；
其中，所述有源层为铟镓锌氧化物材料，所述有源层对应所述栅极的区域为非导体化区域，所述有源层除所述非导体化区域外的其他区域为导体化区域；对应所述源极一侧的所述导体化区域为源区，对应所述漏极一侧的所述导体化区域为漏区；所述阵列基板包括用以形成载流子的 沟道区 ，位于所述非导体化区域的所述有源层为所述 沟道区的主动层； 所述主动层延伸至所述源区以及所述漏区正对的所述有源层的相应部分。
根据本发明一优选实施例，所述有源层的所述源区与所述漏区是通过对所述基板进行 200~300 摄氏度的退火，以及用波长处于 300 纳米 ~315 纳米范围内的准分子镭射光照射来实现导体化的。
本发明还提供一种阵列基板，包括：
基板；
薄膜晶体管，制备于所述基板上；
所述薄膜晶体管包括有源层以及位于所述有源层两端上方的源极与漏极；
栅绝缘层，制备于所述薄膜晶体管表面；
栅极，制备于所述栅绝缘层上；
其中，所述有源层为铟镓锌氧化物材料，所述有源层对应所述栅极的区域为非导体化区域，所述有源层除所述非导体化区域外的其他区域为导体化区域；对应所述源极一侧的所述导体化区域为源区，对应所述漏极一侧的所述导体化区域为漏区。
根据本发明一优选实施例，所述有源层的所述源区与所述漏区是通过对所述基板进行 200~300 摄氏度的退火，以及用波长处于 300 纳米 ~315 纳米范围内的准分子镭射光照射来实现导体化的。
 有益效果
本发明的有益效果为： 相较于 现有技术的 TG-IGZO TFT 器件的制作方法 ，本发明的 阵列基板的制作方法 通过在 缓冲层上连续沉积铟镓锌氧化物层与第二金属层，采用同一道半色调光罩使铟镓锌氧化物层形成有源层，同时使第二金属层形成源极与漏极；通过对基板进行退火，使源极与漏极下方对应的铟镓锌氧化物层的相应区域实现导体化；再通过准分子镭射照射基板使栅极与源极 / 漏极之间的间隙处对应的铟镓锌氧化物层的相应区域实现导体化。如此减少了两道光罩制程，通过五道光罩完成 显示器件的制作，从而缩减了制程，降低了成本 。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图 1 为 本发明实施例提供的阵列基板的制备方法流程图；
图 2 为 本发明实施例提供的阵列基板的制备 过程图中的不同阶段的结构示意图；
图 3 为本发明实施例提供的阵列基板结构示意图 。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如 [ 上 ] 、 [ 下 ] 、 [ 前 ] 、 [ 后 ] 、 [ 左 ] 、 [ 右 ] 、 [ 内 ] 、 [ 外 ] 、 [ 侧面 ] 等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对 现有技术的 TG-IGZO TFT 器件的制作方法，工艺比较复杂，成本较高的技术问题 ，本实施例能够解决该缺陷。
下面结合附图详细介绍本发明具体实施例提供的 阵列基板 的制作方法。
如图 1 所示，本发明具体实施例提供了一种 阵列基板 的制作方法， 所述方法包括以下步骤：
步骤 S1 、提供一基板，在所述基板上依次制备遮光层、缓冲层、有源层、源极与漏极、栅绝缘层以及栅极；
步骤 S2 、对正对于所述源极与所述漏极的所述有源层的相应区域进行第一导体化制程；
步骤 S3 、对位于所述源极与所述栅极之间以及所述漏极与所述栅极之间的所述有源层的相应区域进行第二导体化制程。
具体地，所述阵列基板的制作方法可包括以下步骤：
步骤 S101 、在基板上依次制备第一金属层、缓冲层，将所述第一金属层通过第一道光罩形成遮光层；
步骤 S102 、在所述缓冲层上连续沉积铟镓锌氧化物层与第二金属层，通过第二道半色调光罩使所述铟镓锌氧化物层形成有源层，以及同时使所述第二金属层形成源极与漏极；
步骤 S103 、依次制备栅绝缘层、第三金属层，并用第三道光罩使所述第三金属层形成栅极；
步骤 S104 、对所述有源层中除所述栅极所对应的第一区域之外的其他区域做导体化；其中包括：对正对于所述源极与所述漏极的所述有源层的相应区域进行第一导体化制程；对位于所述源极与所述栅极之间以及所述漏极与所述栅极之间的所述有源层的相应区域进行第二导体化制程；
步骤 S105 、在所述栅极上覆盖一层所述钝化层，并用第四道光罩在所述钝化层中形成过孔；
步骤 S106 、在所述钝化层上沉积像素电极层，并用第五道光罩形成像素电极。
下面结合附图详细介绍本发明具体实施例提供的 阵列基板 的制作过程。
如图 2a 所示，先 提供一基板 210 ，在所述基板 210 上制备一层第一金属层；通过第一道光罩图案化所述第一金属层形成间隔分布于所述基板 210 上的遮光层 211 。
如图 2b 所示，接着在基板 220 上 沉积一层缓冲层 222 ，所述缓冲层 222 覆盖遮光层 221 ，在所述缓冲层 222 上连续沉积铟镓锌氧化物（ IGZO ）与第二金属层，通过第二道半色调光罩使所述铟镓锌氧化物与所述第二金属层同时进行图案化，使所述铟镓锌氧化物形成铟镓锌氧化物图案，即有源层 223 ，所述第二金属层形成源极 225 与漏极 224 ；所述源极 225 与所述漏极 224 分别位于所述有源层 223 的两端，且所述源极 225 与所述漏极 224 之间存在间隙；所述源极 225 与所述漏极 224 以及所述有源层 223 在所述基板 220 上的投影均位于所述遮光层 221 在所述基板 220 上的投影的范围内。
优选的，所述第二金属层的材料为钛或铝中的一种或一种以上，若所述第二金属层为所述钛和所述铝的复合材料，则所述第二金属层为所述钛和所述铝的层叠结构。所述缓冲层 222 的材料为氮化硅或二氧化硅。
如图 2c 所示，接着 在缓冲层 231 上沉积栅绝缘层 234 ，所述栅绝缘层 234 覆盖图案化后的源极 236 与漏极 233 以及有源层 232 ；再在所述栅绝缘层 234 上沉积第三金属层，所述第三金属层通过第三道光罩形成栅极 235 。所述栅极 235 对应位于所述源极 236 与所述漏极 233 之间。在所述有源层 232 中，对应所述栅极 235 的相应区域为第一区域 237 ，对应所述源极 236 与所述漏极 233 的相应区域为第二区域 238 ，与所述栅极 235 与所述源极 236/ 所述漏极 233 之间的间隙对应的区域为第三区域 239 。所述栅绝缘层 234 的材料为氮化硅或二氧化硅。
如图 2d 所示，对所述阵列基板进行第一导体化制程，所述第一导体化制程包括退火制程，具体地， 对基板 241 进行 200~300 摄氏度的退火，维持一定时间，使有源层 244 中位于源极 242 与漏极 243 下方的第二区域 2441 进行导体化；在此过程中，所述源极 242 与所述漏极 243 中的材料钛或铝会惨杂于所述有源层 244 中，待钛或铝元素扩散趋于均匀分布后缓冷，以实现所述第二区域 2441 的导体化。
如图 2e 所示，对所述阵列基板进行第二导体化制程，所述第二导体化制程包括镭射制程，具体地，有源层 252 中对应栅极 251 的相应区域为第一区域（如图 2c 中所示），所述栅极 251 与源极 254/ 漏极 253 之间的间隙对应的区域为第三区域 2521 ，沿着照射方向 255 ，用波长处于 300 纳米 ~315 纳米范围内的准分子镭射照射基板的所述栅极 251 一侧的表面，所述有源层 252 中对应所述栅极 251 与所述源极 254/ 所述漏极 253 之间的所述第三区域 2521 可以被镭射照射而实现导体化，而所述有源层 252 被所述栅极 251 遮挡住的所述第一区域为非导体化区域，可以避免导体化而作为沟道区的主动层，通过上述所述退火制程以及所述镭射制程后，使所述有源层 252 实现自对准式导体化。
如图 2f 所示， 在形成有栅极 267 的基板表面上覆盖一层钝化层 265 ，并用第四道光罩在所述钝化层 265 上形成第二过孔 264 ，以及在所述栅绝缘层 261 上形成对应所述第二过孔 264 的第一过孔 263 ；然后再沉积一层像素电极层，并用第五道光罩形成像素电极 266 ；所述像素电极 266 通过所述第二过孔 264 与所述第一过孔 263 连接到漏极 262 。至此，用五道光罩完成顶栅结构的阵列基板的工艺流程。
本发明还提供一种阵列基板，包括：基板；薄膜晶体管，制备于所述基板上；所述薄膜晶体管包括有源层以及位于所述有源层两端上方的源极与漏极；栅绝缘层，制备于所述薄膜晶体管表面；栅极，制备于所述栅绝缘层上；其中，所述有源层为铟镓锌氧化物材料，所述有源层对应所述栅极的区域为非导体化区域，所述有源层除所述非导体化区域外的其他区域为导体化区域；对应所述源极一侧的所述导体化区域为源区，对应所述漏极一侧的所述导体化区域为漏区。
具体地，如图 3 所示， 为本发明提供的阵列基板结构示意图，所述阵列基板包括：基板 301 ；第一金属层，制备于所述基板 301 表面，所述第一金属层形成间隔设置的遮光层 302 ；缓冲层 303 ，制备于所述第一金属层表面；铟镓锌氧化物，沉积于所述缓冲层 303 的表面，所述铟镓锌氧化物经过图案化后形成有源层 304 ；第二金属层，沉积于所述铟镓锌氧化物的表面，所述第二金属层图案化后形成源极 305 与漏极 306 ；栅绝缘层 307 ，制备于所述第二金属层表面；第三金属层，制备于所述栅绝缘层 307 表面，图案化后形成栅极 308 ；钝化层 309 ，制备于所述第三金属层表面；像素电极层，制备于所述钝化层 309 表面；所述像素电极层图案化后形成像素电极 310 。
其中，所述有源层 304 包括导体化区域与非导体化区域，所述导体化区域包括第一导体化区域 3042 与第二导体化区域 3041 。所述铟镓锌氧化物与所述第二金属层通过一道半色调光罩同时进行图案化，所述有源层 304 对应所述源极 305 一侧的所述第一导体化区域 3042 为所述有源层 304 的源区，对应所述漏极 306 一侧的所述第二导体化区域 3041 为所述有源层 304 的漏区。其中，所述源区与所述漏区是通过对所述基板 301 进行 200~300 摄氏度的退火，以及用波长处于 300 纳米 ~315 纳米范围内的准分子镭射照射来实现导体化的。所述阵列基板包括用以形成载流子的 沟道区 ，位于所述非导体化区域的所述有源层为所述 沟道区的主动层； 所述主动层延伸至所述源区以及所述漏区正对的所述有源层 304 的相应部分。所述栅绝缘层 307 形成有第一过孔 3071 ，所述钝化层 309 形成有对应于所述第一过孔 3071 的第二过孔 3091 ，所述像素电极 310 通过所述第二过孔 3091 以及所述第一过孔 3071 连接到所述漏极 306 。
相较于 现有技术的 TG-IGZO TFT 器件的制作方法 ，本发明的 阵列基板的制作方法 通过在 缓冲层上连续沉积铟镓锌氧化物层与第二金属层，采用同一道半色调光罩使铟镓锌氧化物层形成有源层，同时使第二金属层形成源极与漏极；通过对基板进行退火，使源极与漏极下方对应的铟镓锌氧化物层的相应区域实现导体化；再通过准分子镭射照射基板使栅极与源极 / 漏极之间的间隙处对应的铟镓锌氧化物层的相应区域实现导体化。如此减少了两道光罩制程，通过五道光罩完成 显示器件的制作，从而缩减了制程，降低了成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (9)

  1. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤 S1 、提供一基板，在所述基板上依次制备遮光层、缓冲层、有源层、源极与漏极、栅绝缘层以及栅极；其中，所述缓冲层上连续沉积铟镓锌氧化物层与第二金属层，通过半色调光罩使所述铟镓锌氧化物形成有源层，以及同时使所述第二金属层形成源极与漏极；
    步骤 S2 、对正对于所述源极与所述漏极的所述有源层的相应区域进行第一导体化制程；
    步骤 S3 、对位于所述源极与所述栅极之间以及所述漏极与所述栅极之间的所述有源层的相应区域进行第二导体化制程。
  2. 根据权利要求 1 所述的方法，其中，所述第一导体化制程包括对所述阵列基板进行退火制程，所述第二导体化制程包括对所述阵列基板进行镭射制程。
  3. 根据权利要求 2 所述的方法，其中，所述退火制程的温度为 200~300 摄氏度，以使所述有源层中正对于所述源极和所述漏极的相应区域实现导体化。
  4. 根据权利要求 2 所述的方法，其中，所述镭射制程中用波长处于 300 纳米 ~315 纳米范围内的准分子镭射光照射所述阵列基板表面，使对位于所述源极与所述栅极之间以及所述漏极与所述栅极之间的所述有源层的相应区域实现导体化。
  5. 根据权利要求 3 所述的方法，其中，所述退火制程中，所述源极与所述漏极材料中的钛或铝掺杂于所述有源层中。
  6. 一种阵列基板，其包括：
    基板；
    薄膜晶体管，制备于所述基板上；
    所述薄膜晶体管包括有源层以及位于所述有源层两端上方的源极与漏极；
    栅绝缘层，制备于所述薄膜晶体管表面；
    栅极，制备于所述栅绝缘层上；
    其中，所述有源层为铟镓锌氧化物材料，所述有源层对应所述栅极的区域为非导体化区域，所述有源层除所述非导体化区域外的其他区域为导体化区域；对应所述源极一侧的所述导体化区域为源区，对应所述漏极一侧的所述导体化区域为漏区；所述阵列基板包括用以形成载流子的 沟道区 ，位于所述非导体化区域的所述有源层为所述 沟道区的主动层； 所述主动层延伸至所述源区以及所述漏区正对的所述有源层的相应部分。
  7. 根据权利要求 6 所述的阵列基板，其中，所述有源层的所述源区与所述漏区是通过对所述基板进行 200~300 摄氏度的退火，以及用波长处于 300 纳米 ~315 纳米范围内的准分子镭射光照射来实现导体化的。
  8. 一种阵列基板，其包括：
    基板；
    薄膜晶体管，制备于所述基板上；
    所述薄膜晶体管包括有源层以及位于所述有源层两端上方的源极与漏极；
    栅绝缘层，制备于所述薄膜晶体管表面；
    栅极，制备于所述栅绝缘层上；
    其中，所述有源层为铟镓锌氧化物材料，所述有源层对应所述栅极的区域为非导体化区域，所述有源层除所述非导体化区域外的其他区域为导体化区域；对应所述源极一侧的所述导体化区域为源区，对应所述漏极一侧的所述导体化区域为漏区。
  9. 根据权利要求 8 所述的阵列基板，其中，所述有源层的所述源区与所述漏区是通过对所述基板进行 200~300 摄氏度的退火，以及用波长处于 300 纳米 ~315 纳米范围内的准分子镭射光照射来实现导体化的。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043025A (zh) * 2006-03-22 2007-09-26 群康科技(深圳)有限公司 薄膜晶体管基板的制造方法
CN102280488A (zh) * 2010-06-09 2011-12-14 三星移动显示器株式会社 Tft、包括tft的阵列基板及制造tft和阵列基板的方法
CN106129122A (zh) * 2016-08-31 2016-11-16 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板、显示装置
CN106384714A (zh) * 2016-10-13 2017-02-08 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5567770B2 (ja) * 2007-09-21 2014-08-06 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
CN104900531A (zh) * 2015-06-08 2015-09-09 京东方科技集团股份有限公司 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置
CN106356306A (zh) * 2016-11-14 2017-01-25 深圳市华星光电技术有限公司 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043025A (zh) * 2006-03-22 2007-09-26 群康科技(深圳)有限公司 薄膜晶体管基板的制造方法
CN102280488A (zh) * 2010-06-09 2011-12-14 三星移动显示器株式会社 Tft、包括tft的阵列基板及制造tft和阵列基板的方法
CN106129122A (zh) * 2016-08-31 2016-11-16 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板、显示装置
CN106384714A (zh) * 2016-10-13 2017-02-08 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板

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