WO2019223076A1 - 金属氧化物薄膜晶体管及其制作方法、显示器 - Google Patents

金属氧化物薄膜晶体管及其制作方法、显示器 Download PDF

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WO2019223076A1
WO2019223076A1 PCT/CN2018/095086 CN2018095086W WO2019223076A1 WO 2019223076 A1 WO2019223076 A1 WO 2019223076A1 CN 2018095086 W CN2018095086 W CN 2018095086W WO 2019223076 A1 WO2019223076 A1 WO 2019223076A1
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layer
metal oxide
photoresist
forming
insulating
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PCT/CN2018/095086
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English (en)
French (fr)
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林钦遵
黄贵华
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深圳市华星光电技术有限公司
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Priority to US16/076,276 priority Critical patent/US10950716B2/en
Publication of WO2019223076A1 publication Critical patent/WO2019223076A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the invention belongs to the technical field of thin film transistor manufacturing, and in particular, relates to a metal oxide thin film transistor, a manufacturing method thereof, and a display.
  • a thin film transistor is generally used as a control switch, and the thin film transistor is usually an amorphous silicon (a-Si) thin film transistor.
  • a-Si amorphous silicon
  • amorphous silicon (a-Si) thin film transistors have lower electron mobility.
  • metal oxide thin film transistors have higher mobility and can be applied to transparent display technology, so they have higher research and development value.
  • the photoresist on the top is hardened, which causes difficulty in photoresist peeling in subsequent processes.
  • an object of the present invention is to provide a metal oxide semiconductor thin film transistor that is easy to peel off a photoresist, a manufacturing method thereof, and a display.
  • a manufacturing method of a metal oxide thin film transistor includes the following steps: forming a laminated light-shielding layer, a metal oxide semiconductor layer, a gate electrode, and a first photoresist on a substrate A pattern layer; forming a second photoresist layer on the metal oxide semiconductor layer and the first photoresist pattern layer; performing ashing treatment on the second photoresist layer and the first photoresist pattern layer, And peeling the ashed second photoresist layer and the first photoresist pattern layer; forming a first insulating layer on the metal oxide semiconductor layer and the gate; and insulating the first insulation A source and a drain are formed on the layer through the first insulating layer to contact the metal oxide semiconductor layer, respectively.
  • the method for forming a laminated light-shielding layer, a metal oxide semiconductor layer, a gate, and a first photoresist layer on a substrate includes the following steps: forming a light-shielding layer on the substrate; A second insulating layer is formed on the light shielding layer; a stacked metal oxide semiconductor layer, a gate insulating layer, a gate and a first photoresist pattern layer are formed on the second insulating layer.
  • the method for forming a stacked metal oxide semiconductor layer, a gate insulating layer, a gate, and a first photoresist pattern layer on the second insulating layer includes the following steps: on the second insulating layer Forming a metal oxide layer; forming a third insulating layer on the second insulating layer and the metal oxide layer; forming a stacked first metal layer and a first photoresist layer on the third insulating layer; Patterning the first photoresist layer, the first metal layer, and the third insulating layer to form a gate insulating layer, a gate, and a first photoresist pattern layer; conducting the metal oxide layer To form the metal oxide semiconductor layer.
  • the gate insulating layer includes: a first insulating portion and a second insulating portion respectively located on both sides of the metal oxide layer, and a third insulating portion located on the metal oxide layer; the gate A pole is located on the third insulation portion; the first photoresist pattern layer includes a first photoresist portion on the first insulation portion, a second photoresist portion on the second insulation portion, and A third photoresistor on the grid.
  • the projections of the third insulation portion, the gate electrode, and the third photoresistance portion on the metal oxide layer are all located within the metal oxide layer.
  • the method for forming a light-shielding layer on the substrate includes the following steps: forming a second metal layer on the substrate; and patterning the second metal layer to form the light-shielding layer.
  • the second photoresist layer is located on the first photoresist portion, the second photoresist portion, the third photoresist portion, the metal oxide semiconductor layer, and the second insulating layer. .
  • the method for forming a source electrode and a drain electrode which pass through the first insulating layer to contact the metal oxide semiconductor layer respectively on the first insulating layer includes the following steps: An insulating layer is formed to respectively form a first via hole and a second via hole exposing the metal oxide semiconductor layer; and the first insulating layer is formed to fill the first via hole and the second via hole and be in contact with the first via hole; A third metal layer in contact with the metal oxide semiconductor layer; and patterning the third metal layer to form the source electrode and the drain electrode independently of each other.
  • a metal oxide thin film transistor manufactured by the above manufacturing method is also provided.
  • a display including the above-mentioned metal oxide thin film transistor.
  • the display is a liquid crystal display or an OLED display.
  • Beneficial effect of the present invention In the present invention, by depositing a second photoresist layer on the first photoresist pattern layer hardened after semiconductor processing, the second photoresist layer and the first photoresist pattern layer constitute a level photoresist. Layer, both of which can be easily peeled off after ashing treatment.
  • FIG. 1 is a flowchart of a manufacturing method of a metal oxide thin film transistor according to an embodiment of the present invention
  • FIGS. 2A to 2N are process diagrams of a metal oxide thin film transistor according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a manufacturing method of a metal oxide thin film transistor according to an embodiment of the present invention.
  • 2A to 2N are specific process diagrams of a metal oxide thin film transistor according to an embodiment of the present invention.
  • Step 1 Referring to FIG. 2A, a second metal layer M2 is formed on the substrate 100.
  • the substrate 100 may be, for example, an insulating and transparent glass substrate or a resin substrate.
  • the second metal layer M2 may be, for example, a stacked molybdenum aluminum molybdenum (MoAlMo) structure or a stacked titanium aluminum titan (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure.
  • Step 2 Referring to FIG. 2B, a patterning process is performed on the second metal layer M2 to form a light-shielding layer 200.
  • steps 1 and 2 complete the process of fabricating the light-shielding layer 200 on the substrate 100.
  • step three Referring to FIG. 2C, a second insulating layer 300 is formed on the substrate 100 and the light shielding layer 200.
  • the second insulating layer 300 may be, for example, a stacked SiN x / SiO x structure, or may be a single-layer SiN x structure or a SiO x structure.
  • Step 4 Referring to FIG. 2D, a patterned metal oxide layer 400A is formed on the second insulating layer 300.
  • the material of the metal oxide layer 400A may be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or IGZTO.
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • IGZTO indium gallium zinc oxide
  • Step 5 Referring to FIG. 2E, a third insulating layer IL3 is formed on the second insulating layer 300 and the metal oxide layer 400A.
  • the third insulating layer IL3 may be, for example, a stacked SiN x / SiO x structure, or may be a single-layer SiN x structure or a SiO x structure.
  • Step 6 Referring to FIG. 2F, a stacked first metal layer M1 and a first photoresist layer PR1 are formed on the third insulating layer IL3.
  • the first metal layer M1 may be, for example, a stacked molybdenum aluminum molybdenum (MoAlMo) structure or a stacked titanium aluminum titanium (TiAlTi) structure, or may be a single-layer molybdenum structure or a single-layer aluminum structure.
  • MoAlMo molybdenum aluminum molybdenum
  • TiAlTi titanium aluminum titanium
  • Step 7 Referring to FIG. 2G, the first photoresist layer PR1, the first metal layer M1, and the third insulating layer IL3 are patterned to form a gate insulating layer, a gate 600, and a first photoresist pattern layer.
  • the gate insulating layer includes a first insulating portion 510 and a second insulating portion 520 located on both sides of the metal oxide layer 400A, and a third insulating portion 530 located on the metal oxide layer 400A.
  • the gate 600 is located on the third insulating portion 530.
  • the first photoresist pattern layer includes a first photoresist portion PR11 located on the first insulating portion 510, a second photoresist portion PR12 located on the second insulating portion 520, and a third photoresist portion located on the gate 600. PR13.
  • Step 8 Referring to FIG. 2H, a conductive process is performed on the metal oxide layer 400A to form a metal oxide semiconductor layer 400.
  • the metal oxide layer 400A is subjected to a conductive treatment, the first photoresist pattern layer is hardened, so that the first photoresist pattern layer is difficult to peel off.
  • steps 4 to 8 complete the process of forming a stacked metal oxide semiconductor layer 400, a gate insulating layer, a gate 600, and a first photoresist pattern layer on the second insulating layer 300.
  • steps 1 to 8 complete step S110 shown in FIG. 1.
  • the projections of the third insulating portion 530, the gate electrode 600, and the third photoresistive portion PR13 on the metal oxide semiconductor layer 400 are completely within the metal oxide semiconductor layer 400, so that a part of the metal oxide semiconductor layer 400 can be Exposed. Further, the projections of the third insulating portion 530, the gate electrode 600, and the third photoresistive portion PR13 on the metal oxide semiconductor layer 400 are located in a middle portion of the metal oxide semiconductor layer 400.
  • Step 9 Referring to FIG. 2I, a second photoresist layer PR2 is formed on the metal oxide semiconductor layer 400 and the first photoresist pattern layer.
  • step nine completes step S120 shown in FIG. 1.
  • Step 10 Referring to FIG. 2J, the second photoresist layer PR2 and the first photoresist pattern layer are subjected to ashing treatment, and the ashed second photoresist layer PR2 and the first photoresist pattern layer are peeled off. .
  • step 10 by depositing the second photoresist layer PR2 again in step 10, the second photoresist layer PR2 and the first photoresist pattern layer constitute a level, flat, and integrated photoresist layer. After ashing treatment, Can be easily peeled. In this way, step ten completes step S130 shown in FIG. 1.
  • Step 11 Referring to FIG. 2K, a first insulating layer 700 is formed on the metal oxide semiconductor layer 400, the gate 600, and the second insulating layer 300.
  • the first insulating layer 700 may be, for example, a stacked SiN x / SiO x structure, or may be a single-layer SiN x structure or a SiO x structure. In this way, step 11 completes step S140 shown in FIG. 1.
  • Step twelve Referring to FIG. 2L, a first via hole 710 and a second via hole 720 that expose the metal oxide semiconductor layer 400 are respectively formed in the first insulating layer 700.
  • Step 13 Referring to FIG. 2M, a third metal layer M3 is formed on the first insulating layer 700 to fill the first via hole 710 and the second via hole 720 and to be in contact with the metal oxide semiconductor layer 400.
  • Step 14 Referring to FIG. 2N, the third metal layer M3 is patterned to form a source 800 and a drain 900 that are independent of each other.
  • steps 12 to 14 complete step S150 shown in FIG. 1.
  • a metal oxide thin film transistor manufactured by the above manufacturing method is also provided.
  • a display including the metal oxide thin film transistor is provided.
  • the display may be, for example, a liquid crystal display or an OLED display.
  • the second photoresist layer and the first photoresist pattern layer constitute a level photoresist layer. Both can be easily peeled off after ashing treatment.

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Abstract

本发明公开了一种金属氧化物薄膜晶体管的制作方法。所述制作方法包括以下步骤：在基板上形成层叠的遮光层、金属氧化物半导体层、栅极以及第一光阻图案层；在所述金属氧化物半导体层和所述第一光阻图案层上形成第二光阻层；对所述第二光阻层和所述第一光阻图案层进行灰化处理，并将灰化后的所述第二光阻层和所述第一光阻图案层剥离；在所述金属氧化物半导体层和所述栅极上形成第一绝缘层；在所述第一绝缘层上形成穿过所述第一绝缘层以分别于所述金属氧化物半导体层接触的源极和漏极。本发明通过在半导体化处理后硬化的第一光阻图案层上再次沉积第二光阻层，使得第二光阻层和第一光阻图案层构成流平的光阻层，二者在灰化处理后能够易于被剥离。

Description

金属氧化物薄膜晶体管及其制作方法、显示器 技术领域
本发明属于薄膜晶体管制作技术领域，具体地讲，涉及一种金属氧化物薄膜晶体管及其制作方法、显示器。
背景技术
目前，在现有的显示器(诸如液晶显示器或者OLED显示器)中，通常利用薄膜晶体管(TFT)来作为控制开关，其中，薄膜晶体管通常都采用非晶硅(a-Si)薄膜晶体管。
然而，非晶硅(a-Si)薄膜晶体管的电子迁移率较低。与非晶硅薄膜晶体管相比，金属氧化物薄膜晶体管的迁移率较高，且可应用于透明显示技术，故具有较高的研究开发价值。在顶栅型的金属氧化物薄膜晶体管进行金属氧化物导体化过程中，会将上面的光阻硬化，从而导致后续制程中的光阻剥离出现困难。
发明内容
为了解决上述现有技术的问题，本发明的目的在于提供一种易于剥离光阻的金属氧化物半导体薄膜晶体管及其制作方法、显示器。
根据本发明的一方面，提供了一种金属氧化物薄膜晶体管的制作方法，所述制作方法包括以下步骤：在基板上形成层叠的遮光层、金属氧化物半导体层、栅极以及第一光阻图案层；在所述金属氧化物半导体层和所述第一光阻图案层上形成第二光阻层；对所述第二光阻层和所述第一光阻图案层进行灰化处理，并将灰化后的所述第二光阻层和所述第一光阻图案层剥离；在所述金属氧化物半导体层和所述栅极上形成第一绝缘层；在所述第一绝缘层上形成穿过所述第一绝缘层以分别于所述金属氧化物半导体层接触的源极和漏极。
进一步地，所述在基板上形成层叠的遮光层、金属氧化物半导体层、栅极 以及第一光阻层的方法包括以下步骤：在所述基板上形成遮光层；在所述基板和所述遮光层上形成第二绝缘层；在所述第二绝缘层上形成层叠的金属氧化物半导体层、栅极绝缘层、栅极和第一光阻图案层。
进一步地，所述在所述第二绝缘层上形成层叠的金属氧化物半导体层、栅极绝缘层、栅极和第一光阻图案层的方法包括以下步骤：在所述第二绝缘层上形成金属氧化物层；在所述第二绝缘层和所述金属氧化物层上形成第三绝缘层；在所述第三绝缘层上形成层叠的第一金属层和第一光阻层；对所述第一光阻层、第一金属层和所述第三绝缘层进行图案化处理，以形成栅极绝缘层、栅极和第一光阻图案层；对所述金属氧化物层进行导体化，以形成所述金属氧化物半导体层。
进一步地，所述栅极绝缘层包括：分别位于所述金属氧化物层两侧的第一绝缘部和第二绝缘部，以及位于所述金属氧化物层上的第三绝缘部；所述栅极位于所述第三绝缘部上；所述第一光阻图案层包括位于所述第一绝缘部上的第一光阻部、位于所述第二绝缘部上的第二光阻部以及位于所述栅极上的第三光阻部。
进一步地，所述第三绝缘部、所述栅极和所述第三光阻部分别在所述金属氧化物层上的投影均位于所述金属氧化物层以内。
进一步地，所述在所述基板上形成遮光层的方法包括以下步骤：在所述基板上形成第二金属层；对所述第二金属层进行图案化处理，以形成所述遮光层。
进一步地，所述第二光阻层位于所述第一光阻部、所述第二光阻部、所述第三光阻部、所述金属氧化物半导体层和所述第二绝缘层上。
进一步地，所述在所述第一绝缘层上形成穿过所述第一绝缘层以分别于所述金属氧化物半导体层接触的源极和漏极的方法包括以下步骤：在所述第一绝缘层分别形成暴露所述金属氧化物半导体层的第一过孔和第二过孔；在所述第一绝缘层上形成填充所述第一过孔和所述第二过孔且与所述金属氧化物半导体层接触的第三金属层；对所述第三金属层进行图案化处理，以形成彼此独立的所述源极和所述漏极。
根据本发明的另一方面，还提供了一种由上述的制作方法制作形成的金属氧化物薄膜晶体管。
根据本发明的又一方面，又提供了一种包括上述的金属氧化物薄膜晶体管的显示器。
进一步地，该显示器是液晶显示器或者OLED显示器。
本发明的有益效果：本发明通过在半导体化处理后硬化的第一光阻图案层上再次沉积第二光阻层，使得第二光阻层和第一光阻图案层构成流平的光阻层，二者在灰化处理后能够易于被剥离。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的金属氧化物薄膜晶体管的制作方法的流程图；
图2A至图2N是根据本发明的实施例的金属氧化物薄膜晶体管的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚起见，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1是根据本发明的实施例的金属氧化物薄膜晶体管的制作方法的流程图。图2A至图2N是根据本发明的实施例的金属氧化物薄膜晶体管的具体制程图。
步骤一：参照图2A，在基板100上形成第二金属层M2。
这里，基板100可例如为一绝缘且透明的玻璃基板或树脂基板。第二金属层M2可例如是叠层的钼铝钼(MoAlMo)结构或叠层的钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构。
步骤二：参照图2B，对第二金属层M2进行图案化处理，以形成遮光层200。
如此，步骤一和步骤二完成了在基板100上制作遮光层200的过程。
接着，步骤三：参照图2C，在基板100和遮光层200上形成第二绝缘层300。
这里，第二绝缘层300可例如是叠层的SiN x/SiO x结构，也可以是单层的SiN x结构或SiO x结构。
步骤四：参照图2D，在第二绝缘层300上形成图案化的金属氧化物层400A。
这里，金属氧化物层400A的制作材料可以是铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、IGZTO。
步骤五：参照图2E，在第二绝缘层300和金属氧化物层400A上形成第三绝缘层IL3。
这里，第三绝缘层IL3可例如是叠层的SiN x/SiO x结构，也可以是单层的SiN x结构或SiO x结构。
步骤六：参照图2F，在第三绝缘层IL3上形成叠层的第一金属层M1和第一光阻层PR1。
这里，第一金属层M1可例如是叠层的钼铝钼(MoAlMo)结构或叠层的 钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构。
步骤七：参照图2G，对第一光阻层PR1、第一金属层M1和第三绝缘层IL3进行图案化处理，以形成栅极绝缘层、栅极600和第一光阻图案层。
这里，所述栅极绝缘层包括：位于金属氧化物层400A两侧的第一绝缘部510和第二绝缘部520，以及位于金属氧化物层400A上的第三绝缘部530。栅极600位于第三绝缘部530上。所述第一光阻图案层包括：位于第一绝缘部510的第一光阻部PR11、位于第二绝缘部520上的第二光阻部PR12以及位于栅极600上的第三光阻部PR13。
步骤八：参照图2H，对金属氧化物层400A进行导体化处理，以形成金属氧化物半导体层400。这里，如背景金属中所述，当对金属氧化物层400A进行导体化处理时会将所述第一光阻图案层硬化，从而导致所述第一光阻图案层难以剥离。
如此，步骤四到步骤八完成了在第二绝缘层300上形成叠层的金属氧化物半导体层400、栅极绝缘层、栅极600和第一光阻图案层的过程。此外，步骤一到步骤八完成了图1所示的步骤S110。
进一步地，第三绝缘部530、栅极600和第三光阻部PR13在金属氧化物半导体层400上的投影完全位于金属氧化物半导体层400以内，这样可以将金属氧化物半导体层400的部分暴露。更进一步地，第三绝缘部530、栅极600和第三光阻部PR13在金属氧化物半导体层400上的投影位于金属氧化物半导体层400的中间部分。
步骤九：参照图2I，在金属氧化物半导体层400和所述第一光阻图案层上形成第二光阻层PR2。
进一步地，这里，第二光阻层PR2还设置于第二绝缘层300上。更进一步地，步骤九完成了图1所示的步骤S120。
步骤十：参照图2J，对第二光阻层PR2和所述第一光阻图案层进行灰化处理，并将灰化后的第二光阻层PR2和所述第一光阻图案层剥离。
这样，通过在步骤十中再次沉积第二光阻层PR2，使得第二光阻层PR2和所述第一光阻图案层构成流平的、平整的且一体的光阻层，灰化处理后能够易于被剥离。如此，步骤十完成了图1所示的步骤S130。
步骤十一：参照图2K，在金属氧化物半导体层400、栅极600和第二绝缘层300上形成第一绝缘层700。
这里，第一绝缘层700可例如是叠层的SiN x/SiO x结构，也可以是单层的SiN x结构或SiO x结构。如此，步骤十一完成了图1所示的步骤S140。
步骤十二：参照图2L，在第一绝缘层700中分别形成暴露金属氧化物半导体层400的第一过孔710和第二过孔720。
步骤十三：参照图2M，在第一绝缘层700上形成填充第一过孔710和第二过孔720且与金属氧化物半导体层400接触的第三金属层M3。
步骤十四：参照图2N，对第三金属层M3进行图案化处理，以形成彼此独立的源极800和漏极900。
这里，步骤十二至步骤十四完成了图1所示的步骤S150。
作为本发明的另一实施例，还提供了一种由上述的制作方法制作形成的金属氧化物薄膜晶体管。
作为本发明的又一实施例，又提供了一种包括该金属氧化物薄膜晶体管的显示器。该显示器可例如是液晶显示器或者OLED显示器。
综上所述，本发明通过在半导体化处理后硬化的第一光阻图案层上再次沉积第二光阻层，使得第二光阻层和第一光阻图案层构成流平的光阻层，二者在灰化处理后能够易于被剥离。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种金属氧化物薄膜晶体管的制作方法，其中，所述制作方法包括以下步骤：
    在基板上形成层叠的遮光层、金属氧化物半导体层、栅极以及第一光阻图案层；
    在所述金属氧化物半导体层和所述第一光阻图案层上形成第二光阻层；
    对所述第二光阻层和所述第一光阻图案层进行灰化处理，并将灰化后的所述第二光阻层和所述第一光阻图案层剥离；
    在所述金属氧化物半导体层和所述栅极上形成第一绝缘层；
    在所述第一绝缘层上形成穿过所述第一绝缘层以分别于所述金属氧化物半导体层接触的源极和漏极。
  2. 根据权利要求1所述的制作方法，其中，所述在基板上形成层叠的遮光层、金属氧化物半导体层、栅极以及第一光阻层的方法包括以下步骤：
    在所述基板上形成遮光层；
    在所述基板和所述遮光层上形成第二绝缘层；
    在所述第二绝缘层上形成层叠的金属氧化物半导体层、栅极绝缘层、栅极和第一光阻图案层。
  3. 根据权利要求2所述的制作方法，其中，所述在所述第二绝缘层上形成层叠的金属氧化物半导体层、栅极绝缘层、栅极和第一光阻图案层的方法包括以下步骤：
    在所述第二绝缘层上形成金属氧化物层；
    在所述第二绝缘层和所述金属氧化物层上形成第三绝缘层；
    在所述第三绝缘层上形成层叠的第一金属层和第一光阻层；
    对所述第一光阻层、第一金属层和所述第三绝缘层进行图案化处理，以形成栅极绝缘层、栅极和第一光阻图案层；
    对所述金属氧化物层进行导体化，以形成所述金属氧化物半导体层。
  4. 根据权利要求3所述的制作方法，其中，所述栅极绝缘层包括：分别位于所述金属氧化物层两侧的第一绝缘部和第二绝缘部，以及位于所述金属氧化物层上的第三绝缘部；所述栅极位于所述第三绝缘部上；所述第一光阻图案层包括位于所述第一绝缘部上的第一光阻部、位于所述第二绝缘部上的第二光阻部以及位于所述栅极上的第三光阻部。
  5. 根据权利要求4所述的制作方法，其中，所述第三绝缘部、所述栅极和所述第三光阻部分别在所述金属氧化物层上的投影均位于所述金属氧化物层以内。
  6. 根据权利要求3所述的制作方法，其中，所述在所述基板上形成遮光层的方法包括以下步骤：
    在所述基板上形成第二金属层；
    对所述第二金属层进行图案化处理，以形成所述遮光层。
  7. 根据权利要求4所述的制作方法，其中，所述在所述基板上形成遮光层的方法包括以下步骤：
    在所述基板上形成第二金属层；
    对所述第二金属层进行图案化处理，以形成所述遮光层。
  8. 根据权利要求5所述的制作方法，其中，所述在所述基板上形成遮光层的方法包括以下步骤：
    在所述基板上形成第二金属层；
    对所述第二金属层进行图案化处理，以形成所述遮光层。
  9. 根据权利要求4所述的制作方法，其中，所述第二光阻层位于所述第一光阻部、所述第二光阻部、所述第三光阻部、所述金属氧化物半导体层和所述第二绝缘层上。
  10. 根据权利要求5所述的制作方法，其中，所述第二光阻层位于所述第一光阻部、所述第二光阻部、所述第三光阻部、所述金属氧化物半导体层和所述第二绝缘层上。
  11. 根据权利要求1所述的制作方法，其中，所述在所述第一绝缘层上形成穿过所述第一绝缘层以分别于所述金属氧化物半导体层接触的源极和漏极的方法包括以下步骤：
    在所述第一绝缘层分别形成暴露所述金属氧化物半导体层的第一过孔和第二过孔；
    在所述第一绝缘层上形成填充所述第一过孔和所述第二过孔且与所述金属氧化物半导体层接触的第三金属层；
    对所述第三金属层进行图案化处理，以形成彼此独立的所述源极和所述漏极。
  12. 一种由权利要求1所述的制作方法制作形成的金属氧化物薄膜晶体管。
  13. 一种包括权利要求12所述的金属氧化物薄膜晶体管的显示器。
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