CN106558538B - 阵列基板、显示装置及阵列基板的制备方法 - Google Patents

阵列基板、显示装置及阵列基板的制备方法 Download PDF

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CN106558538B
CN106558538B CN201610364665.XA CN201610364665A CN106558538B CN 106558538 B CN106558538 B CN 106558538B CN 201610364665 A CN201610364665 A CN 201610364665A CN 106558538 B CN106558538 B CN 106558538B
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layer
dielectric layer
film transistor
grid
dielectric
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CN106558538A (zh
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林欣桦
高逸群
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Abstract

本发明提供一种阵列基板，其包括基板、设置于基板上的多个第一薄膜晶体管、多个第二薄膜晶体管以及多个第三薄膜晶体管，第一薄膜晶体管为多晶硅薄膜晶体管，该第一薄膜晶体管包括依次设置于基板上的第一介电层以及第二介电层；第二薄膜晶体管和第三薄膜晶体管为金属氧化物薄膜晶体管；第二薄膜晶体管包括依次设置于基板上的第三介电层；第三薄膜晶体管包括依次设置于基板上的第四介电层，该第一介电层的材质为氮化硅，该第二、第三和第四介电层的材质均为氧化硅。本发明还提供应用该阵列基板的显示装置及该阵列基板的制备方法。第二、第三薄膜晶体管上仅覆盖氧化硅材质的第三介电层和第四介电层，避免氮元素薄膜晶体管的影响。

Description

阵列基板、显示装置及阵列基板的制备方法
技术领域
本发明涉及一种阵列基板，应用该阵列基板的显示装置，及该阵列基板的制备方法。
背景技术
平面显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示装置主要包括液晶显示器(Liquid Crystal Display，LCD)及有机电致发光器件(Organic Electroluminescence Device，OELD)，也称为有机发光二极管(Organic LightEmitting Diode，OLED)。一般而言，显示器的显示阵列基板包括一基板，所述基板上设置有连接像素单元的像素阵列及驱动所述像素阵列的驱动电路。采用低温多晶硅技术(LTPS)制造的多晶硅薄膜晶体管的电子迁移率大于金属氧化物薄膜晶体管的电子迁移率，但多晶硅薄膜晶体管的漏电流高于金属氧化物薄膜晶体管的漏电流。驱动电路上的薄膜晶体管需要电子迁移率较高以提升切换速度，而显示区域内的薄膜晶体管需要较小的漏电流以避免显示器亮度不均匀。
发明内容
有鉴于此，有必要提供一种性能良好的阵列基板。
一种阵列基板，其包括基板、设置于基板上的多个第一薄膜晶体管、多个第二薄膜晶体管以及多个第三薄膜晶体管，第一薄膜晶体管为多晶硅薄膜晶体管，该第一薄膜晶体管包括依次设置于基板上的第一半导体层、第一栅极绝缘层、第一栅极、第一介电层、以及第二介电层；第二薄膜晶体管和第三薄膜晶体管为金属氧化物薄膜晶体管；第二薄膜晶体管包括依次设置于基板上的第二半导体层、第二栅极绝缘层、第二栅极、第三介电层、以及第三半导体层；第三薄膜晶体管包括依次设置于基板上的第三栅极绝缘层、第三栅极、第四介电层以及第四半导体层，该第一介电层的材质为氮化硅，该第二介电层、第三介电层和第四介电层的材质均为氧化硅。
一种阵列基板，其包括基板、设置于基板上的多个第一薄膜晶体管以及多个第三薄膜晶体管，第一薄膜晶体管为多晶硅薄膜晶体管，第三薄膜晶体管为金属氧化物薄膜晶体管；该第一薄膜晶体管包括依次设置于基板上的第一半导体层、第一栅极绝缘层、第一栅极、第一介电层、以及第二介电层，该第一半导体层为掺杂的多晶硅层；该第三薄膜晶体管包括依次设置于基板上的第三栅极绝缘层、第三栅极、第四介电层以及第四半导体层，第一介电层的材质为氮化硅，该第二介电层和第四介电层的材质为氧化硅。
一种应用上述阵列基板的显示装置。
一种阵列基板的制备方法，其包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
对多晶硅层进行掺杂，并图案化多晶硅层以形成第一半导体层和第二半导体层；
对第一半导体层进行掺杂以形成两个间隔设置的第一掺杂区域；
在基板上形成第一栅极绝缘层、第二栅极绝缘层以及第三栅极绝缘层，并在第一栅极绝缘层上形成第一栅极，在第二栅极绝缘层上形成第二栅极，并在第三栅极绝缘层上形成第三栅极；
对第一半导体层进行掺杂以形成两个间隔设置的第二掺杂区域以及非掺杂区域；
仅在第一栅极绝缘层上形成第一介电层，该第一介电层的材质为氮化硅；
在第一介电层、第二栅极绝缘层以及第三栅极绝缘层上形成第二介电层、第三介电层以及第四介电层，该第二介电层、第三介电层以及第四介电层的材质均为氧化硅；
在第三介电层以及第四介电层上分别沉积形成第三半导体层和第四半导体层，该第三半导体层和第四半导体层的材质均为金属氧化物半导体；
在与第一掺杂区域对应处开设第一过孔及第二过孔贯穿第二介电层、第一介电层以及第一栅极绝缘层，在第二半导体层对应的位置处分别开设第三过孔和第四过孔，第三过孔贯穿第三介电层和第二栅极绝缘层，第四过孔贯穿第三介电层；
在在第二介电层上且在第一过孔和第二过孔中分别形成第一源极和第一漏极，在第三介电层上且在第三过孔中形成第二源极和在第三介电层上形成第二漏极，在第四介电层上且在第四过孔中形成第三源极和在第四介电上形成第三漏极。
本发明的阵列基板的第二薄膜晶体管和第三薄膜晶体管上仅覆盖氧化硅材质的第三介电层和第四介电层，避免氮元素对第二薄膜晶体管和第三薄膜晶体管的影响，进而提高第二薄膜晶体管和第三薄膜晶体管的可靠性；同时，为所述第一薄膜晶体管中的通道区域由硅形成，可提高切换速度及驱动强度，且第二薄膜晶体管的通道区域使用氧化半导体材料形成，以降低漏电流并提高均一性，因此本发明的阵列基板的薄膜晶体管的组合能够达到最佳效果。
附图说明
图1为本发明所提供之具有多种类型薄膜晶体管之显示器的平面示意图。
图2为图1中阵列基板的剖图面示意图。
图3至4为本发明所提供之具有多种类型薄膜晶体管之显示器制作流程。
图5至图16为图3、图4中各流程所对应的结构剖视图。
主要元件符号说明
下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参阅图1，本发明提供一种具有多种类型薄膜晶体管之显示器1。在本实施方式中，该显示器1可为一自发光式显示器，如有机电致发光显示器，或一非自发光式显示器，如液晶显示器。
该显示器1包括阵列基板20。该阵列基板20包括多条相互平行设置的资料线11以及多条相互平行且与资料线11正交设置的扫描线12。该多条资料线11与第一驱动电路14电性连接，多条扫描线12与第二驱动电路16电性连接。该多条资料线11与该多条扫描线12垂直绝缘相交，定义多个像素单元18。显示器1定义有一个显示区域130以及围绕显示区域130设置的非显示区域150。所述多条资料线11、多条扫描线12、多个像素单元180设置于显示区域130。第一驱动电路14和第二驱动电路16设置于非显示区域150内。第一驱动电路14设置于显示区域130的上侧，第二驱动电路16设置于显示区域130的至少一侧。在本实施方式中，显示器1包括两个第二驱动电路16。该第二驱动电路16对称设置于阵列基板20的左右两侧。在本实施方式中，第一驱动电路14可包括多任务电路和显示驱动电路。第二驱动电路16为栅极驱动电路。
图2为本实施方式中的阵列基板20的剖面示意图。请同时参阅图1及图2，阵列基板20包括基板21、多个设置于资料线11和扫描线12之间的第一薄膜晶体管23、多个第二薄膜晶体管24以及多个第三薄膜晶体管25。其中，第一薄膜晶体管23、第二薄膜晶体管24以及第三薄膜晶体管25可用于位于非显示区域150内，也可以用于显示区域130内。可以理解，该剖面示意图仅示意出部分该阵列基板20(如该阵列基板的一个像素位置的剖面示意图)，实际上，该阵列基板20可包含多个由图2所示的部分连接于一体的多个单元。第一薄膜晶体管23为多晶硅(poly-silicon)薄膜晶体管，第二薄膜晶体管24和第三薄膜晶体管25均为金属氧化物(Metal Oxide)薄膜晶体管。在本实施方式中，第一薄膜晶体管23位于非显示区域150内，第二薄膜晶体管24和第三薄膜晶体管25位于显示区域130内。在其他实施方式中，第一晶体管23也可设置于显示区域130内，第二薄膜晶体管24也可设置于非显示区域150内。
第一薄膜晶体管23应用于第一驱动电路14或第二驱动电路16中。第一薄膜晶体管23包括设置于基板21上的第一半导体层231、第一栅极绝缘层232、第一栅极234、第一介电层235、第二介电层236、第一源极237以及第一漏极238。第一半导体层231包括两个第一掺杂区域2312、两个第二掺杂区域2314以及非掺杂区域2315。该两个第二掺杂区域2314对称设置于非掺杂区域2315的相对两侧，该两个第一掺杂区域2312对称设置于非掺杂区域2315的相对两侧，且该第二掺杂区域2314夹设于第一掺杂区域2312和非掺杂区域2315之间。其中，第一掺杂区域2312的掺杂浓度大于第二掺杂区域2314的掺杂浓度。
第一栅极绝缘层232形成于基板21上，且覆盖第一半导体层231。第一栅极234形成于第一栅极绝缘层232上，且对应第一半导体层231的位置设置。第一介电层235形成于第一栅极绝缘层232上，且覆盖该第一栅极234。第二介电层236形成于第一介电层235上，且覆盖该第一介电层235。该第一源极237和第一漏极238形成在该第二介电层236上且位于该第一栅极234的相对两侧，且经由穿过第一介电层235、第二介电层236以及第一栅极绝缘层232的第一过孔301和第二过孔302(参图12)与第一半导体层231电性连接。第一半导体层231能够作为像素单元18的存储电容。在本实施方式中，第一介电层235由氮化硅材料制成，第二介电层236由氧化硅材料制成。第一半导体231为多晶硅半导体层，第一掺杂区域2312和第二掺杂区域2314中掺杂有三价元素，例如硼元素。在其他实施方式中，第一掺杂区域2312和第二掺杂区域2314中也可根据需求掺杂其他元素以满足相应需求，例如五价元素。
第二薄膜晶体管24同时与资料线11、扫描线12以及对应的像素单元18电性连接。第二薄膜晶体管24用于驱动发光二极管的阳极。第二薄膜晶体管24包括设置于基板21上的第二半导体层241、第二栅极绝缘层242、第二栅极243、第三介电层245、第三半导体层246、第二源极247以及第二漏极248。第二栅极绝缘层242形成于基板21上，且覆盖第二半导体层241。第二栅极243形成于第二栅极绝缘层242上，且对应第二半导体层241的位置设置。第三介电层245形成于第二栅极绝缘层242上，且覆盖该第二栅极243。第三半导体层246形成于第三介电层245上，且对应第二栅极243的位置设置。第二源极247与第二漏极248形成在245上且对称设置于第三半导体246的相对两侧。该第二源极247经由穿过第三介电层245以及第二栅极绝缘层242的第三过孔304和第四过孔306(参图12)与第二半导体层241电性连接，以使得该第二半导体层241可由半导体转为导体。该第二源极247覆盖部分第三半导体层246。第二漏极248设置于第三介电层245上，且覆盖部分第三半导体层246。该第二半导体层241、第二栅极243以及夹在二者之间的第二栅极绝缘层242共同构成像素单元180的存储电容。在本实施方式中，第三介电层245由氧化硅材料制成。第二半导体层241中掺杂有五价元素，例如磷元素。第三半导体层246由铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)材料制成。在其他可替代的实施方式中，第二半导体层241也可由铟镓锌氧化物材料制成，也可以掺杂有三价元素，例如硼元素。
第三薄膜晶体管25用于驱动像素单元18。第三薄膜晶体管25包括第三栅极绝缘层251、第三栅极252、第四介电层253、第四半导体层254、第三源极255以及第三漏极256。第三栅极绝缘层251形成于基板21上。第三栅极252形成于第三栅极绝缘层251上。第四介电层253形成于第三栅极绝缘层251上，且覆盖该第三栅极252。第四半导体层254形成于第四介电层253上，且对应第三栅极252的位置设置。第三源极255与第三漏极256形成在第四介电层253上且对称设置于第四半导体254相对两侧。该第三源极255穿过第四介电层253与第二栅极243电性连接，且覆盖部分第四半导体层254。第三漏极256设置于第四介电层253上，且覆盖部分第四半导体层254。在本实施方式中，第四介电层253由氧化硅材料制成。第四半导体层254由铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)材料制成。
阵列基板20还包括平坦层26、电极层27、发光定义层28以及至少两个间隔物29。平坦层26覆盖第一薄膜晶体管23、第二薄膜晶体管24以及第三薄膜晶体管25。电极层27形成于平坦层26上，且穿过平坦层26与第二源极247电性连接。发光定义层28形成于平坦层26上，用于界定像素单元的发光区域。发光定义层28的两个端部分别覆盖部分电极层27。间隔物29垂直设置于发光定义层28上。在本实施方式中，电极层27为发光二极管的阳极。间隔物29大致呈等腰梯形。
可以理解，在其他实施例中，所述基板21上可形成一缓冲层(图未示)，所述第一半导体层231、第二半导体层241、第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251可形成于缓冲层上。
上述阵列基板20中，第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251相互连接，且一体成型。第二介电层236、第三介电层245以及第四介电层253相互连接，且一体成型。其中，第二薄膜晶体管24和第三薄膜晶体管25上仅覆盖氧化硅材质的第三介电层245和第四介电层253，避免氮元素对第二薄膜晶体管24和第三薄膜晶体管25的影响，进而提高第二薄膜晶体管24和第三薄膜晶体管25的可靠性。同时，为了增强显示效果，可使用满足一定条件的薄膜晶体管。上述一定条件包括：漏电流、切换速度、驱动强度、均一性等等。在本实施方式中，所述第一驱动电路14的第一薄膜晶体管23中的通道区域可由多晶硅形成，以提高切换速度及驱动强度，且所述像素中的第二薄膜晶体管24和第三薄膜晶体管25中的通道区域可使用氧化半导体材料形成，以降低漏电流并提高均一性，因此本具有多种类型薄膜晶体管的显示器能够达到最佳效果。
在其他实施方式中，当阵列基板20应用于液晶显示器中，可对阵列基板20进行相应的变化，例如去除第二晶体管24以及电极层27，以适应于液晶显示器。应用于液晶显示器中的阵列基板20，第一薄膜晶体管23的第一栅极234被第一介电层235和第二介电层236覆盖，二位于像素单元18对应位置的第三薄膜晶体管25的第三栅极252仅覆盖有第四介电层253。
图3和图4为一种较佳实施方式的具有多种类型薄膜晶体管的显示器1的制造方法流程图。该显示器1制的造方法包括如下步骤：
步骤101，在基板21上形成多晶硅层30。基板21的材质可以选自玻璃、石英、有机聚合物或其他可适用的透明材料。如图5所示，多晶硅层30与基板21的两端对齐，且厚度小于基板21的厚度。
步骤102，对多晶硅层30进行掺杂，并图案化多晶硅层30以形成第一半导体层231和第二半导体层241。如图6A所示，第一半导体层231和第二半导体层241共面设置于基板21上，且间隔一定距离。在本实施方式中，多晶硅层30掺杂有掺杂五价元素，例如元素。在其他实施方式中，多晶硅层30可掺杂有其他元素，例如三价元素，硼。在其他实施方式中，多晶硅层的掺杂也可省略或者与其他掺杂步骤进行调换或调整以满足生产需求。
步骤103，利用第一光罩对第一半导体层231进行掺杂以形成两个间隔设置的第一掺杂区域2312。如图6B所示，具体地，在第一半导体层231的相对两端掺杂三价元素。在本实施方式中，第一掺杂区域2312中掺杂硼元素。在其他实施方式中，第一掺杂区域2312中可掺杂有其他元素，例如五价元素，磷。在其他实施方式中，多晶硅层的掺杂也可省略或者与其他掺杂步骤进行调换或调整以满足生产需求。
步骤104，在基板21上形成第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251，在第一栅极绝缘层232上形成第一栅极234，在第二栅极绝缘层242上形成第二栅极243，并在第三栅极绝缘层251上形成第三栅极252。如图7所示，第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251相互连接，且一体成型。该第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251由同一道工序形成。
步骤105，利用第二光罩对第一半导体层231进行掺杂以形成两个间隔设置的第二掺杂区域2314以及非掺杂区域2315。请参阅图8，该第二掺杂区域2314对称设置于非掺杂区域2315的相对两侧，该第一掺杂区域2312对称设置于非掺杂区域2315的相对两侧，且该第二掺杂区域2314夹设于第一掺杂区域2312和非掺杂区域2315之间。其中，第一掺杂区域2312的掺杂浓度大于第二掺杂区域2314的掺杂浓度。在本实施方式中，第二掺杂区域2314中掺杂有三价元素，例如硼。在其他实施方式中，第二掺杂区域2314中可掺杂有其他元素，例如五价元素，磷。在其他实施方式中，第二掺杂区域2314的掺杂也可与其他掺杂步骤进行调换或调整或者合并以满足生产需求。
步骤106，在第一栅极绝缘层232上形成第一介电层235。具体地，如图9A所示，将第一介电材料覆盖在第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251上；如图9B所示，并利用第三光罩移除位于第二栅极绝缘层242以及第三栅极绝缘层251上的第一介电材料，以形成覆盖第一栅极234的第一介电层235。在本实施方式中，第一介电材料为氮化硅。第三光罩可与第一光罩相同。在其他可替代实施方式中，第三光罩也可与第一光罩不同。
步骤107，在第一介电层235、第二栅极绝缘层242以及第三栅极绝缘层251上形成第二介电层236、第三介电层245以及第四介电层253。具体地，如图10所示，将第二介电材料覆盖在第一介电层235、第二栅极绝缘层242以及第三栅极绝缘层251上以形成第二介电层236、第三介电层245以及第四介电层253。在本实施方式中，第二介电材料为氧化硅。
步骤108，在第三介电层245以及第四介电层253上分别沉积形成第三半导体层246和第四半导体层254。第三半导体层246与第二栅极243相对设置，第四半导体层254与第三栅极252相对设置。具体地，可首先在所述第三介电层245以及第四介电层253上沉积氧化半导材料，再图案化该氧化半导体材料以形成第三半导体层246和第四半导体层254。如图11所示，在本实施方式中，第三半导体层46和第四半导体层均为铟镓锌氧化物(IndiumGalliumZinc Oxide，IGZO)半导体层。
步骤109，在与第一掺杂区域2312对应处开设第一过孔301及第二过孔302，在与第二半导体层241对应的位置处开设第三过孔304和第四过孔306。具体地，如图12所示，第一过孔301和第二过孔302依次贯穿第二介电层236、第一介电层235以及第一栅极绝缘层231，且分别与对应的第一掺杂区域2312相对，以使得第一掺杂区域2312曝露。第三过孔304依次贯穿第三介电层245和第二栅极绝缘层242，以使得第二半导体层241部分曝露，第四过孔310贯穿第三介电层245，以使得第二栅极243部分曝露。
步骤110，在第二介电层236上形成第一源极237和第一漏极238，在第三介电层245上形成第二源极247和第二漏极248，在第四介电层253上形成第三源极255和第三漏极256。具体地，如图13所示，该第一源极237、第一漏极238、第二源极247、第二漏极248、第三源极255和第三漏极256利用在第二介电层236、第三介电层245以及第四介电层253上形成金属层，并图案化金属层以形成第一源极237、第一漏极238、第二源极247、第二漏极248、第三源极255和第三漏极256。可以理解，所述第三过孔304和第四过孔306之间的第三介电层245覆盖在所述第二半导体层241，能够在图案化金属层形成第二源极247和第二漏极248时对第二半导体层241进行保护，从而充当蚀刻阻挡层的作用。上述第一半导体层231、第一栅极绝缘层232、第一栅极234、第一介电层235、第二介电层236、第一源极237以及第一漏极238组成第一薄膜晶体管23。第二半导体层241、第二栅极绝缘层242、第二栅极243、第三介电层245、第三半导体层246、第二源极247以及第二漏极248组成第二薄膜晶体管24。第三栅极绝缘层251、第三栅极252、第四介电层253、第四半导体层254、第三源极255以及第三漏极256组成第三薄膜晶体管25。其中，第一薄膜晶体管23与第一驱动电路14或第二驱动电路16相配合，第二薄膜晶体管24用于驱动发光二极管的阳极，第三薄膜晶体管25用于驱动像素单元18。该第二半导体层241、第二栅极243以及夹在二者之间的第二栅极绝缘层242共同构成像素单元的存储电容。
步骤111，在第二介电层236、第三介电层245、第四介电层253上形成平坦层26。如图14所示，平坦层26覆盖第一源极237、第一漏极238、第二源极247、第二漏极248、第三源极255和第三漏极256。平坦层26的两端与基板21对齐。
步骤112，在平坦层26上形成电极层27。具体地，如图15A所示，在平坦层26与第二源极247对应处开设第五过孔(图未示)，如图15B所示，并在平坦层26上形成电极层27。电极层27穿过第五过孔与第二源极247电性连接。在本实施方式中，电极层27为发光二极管的阳极。间隔物29大致呈等腰梯形。
步骤113，在平坦层26上形成发光定义层28，并在发光定义层28上形成至少两个间隔物29。如图16所示，间隔物29垂直设置于发光定义层28的二端部。
上述显示器1的阵列基板20中，第一栅极绝缘层232、第二栅极绝缘层242以及第三栅极绝缘层251相互连接，且一体成型。第二介电层236、第三介电层245以及第四介电层253相互连接，且一体成型。其中，第二薄膜晶体管24和第三薄膜晶体管25上仅覆盖氧化硅材质的第三介电层245和第四介电层253，避免氮元素对第二薄膜晶体管24和第三薄膜晶体管25的影响，进而提高第二薄膜晶体管24和第三薄膜晶体管25的可靠性。同时，为了增强显示效果，可使用满足一定条件的薄膜晶体管。上述一定条件包括：漏电流、切换速度、驱动强度、均一性等等。在本实施方式中，所述第一驱动电路的薄膜晶体管中的通道区域可由硅形成，以提高切换速度及驱动强度，且所述像素中的薄膜晶体管中的通道区域可使用氧化半导体材料形成，以降低漏电流并提高均一性，因此本薄膜晶体管的组合能够达到最佳效果。
另外，本领域技术人员还可在本发明权利要求公开的范围和精神内做其它形式和细节上的各种修改、添加和替换。当然，这些依据本发明精神所做的各种修改、添加和替换等变化，都应包含在本发明所要求保护的范围之内。

Claims (10)

1.一种阵列基板，其包括基板、设置于基板上的多个第一薄膜晶体管、多个第二薄膜晶体管以及多个第三薄膜晶体管，其特征在于：第一薄膜晶体管为多晶硅薄膜晶体管，该第一薄膜晶体管包括依次设置于基板上的第一半导体层、第一栅极绝缘层、第一栅极、第一介电层、以及第二介电层；第二薄膜晶体管和第三薄膜晶体管为金属氧化物薄膜晶体管；第二薄膜晶体管包括依次设置于基板上的第二半导体层、第二栅极绝缘层、第二栅极、第三介电层、以及第三半导体层；第三薄膜晶体管包括依次设置于基板上的第三栅极绝缘层、第三栅极、第四介电层以及第四半导体层，该第一介电层的材质为氮化硅，该第二介电层、第三介电层和第四介电层的材质均为氧化硅。
2.如权利要求1所述的阵列基板，其特征在于：该第一半导体层为多晶硅层，其包括两个第一掺杂区域、两个第二掺杂区域以及非掺杂区域，该两个第二掺杂区域对称设置于非掺杂区域的相对两侧，该两个第一掺杂区域对称设置于非掺杂区域的相对两侧，第一掺杂区域的掺杂浓度大于第二掺杂区域的掺杂浓度；该第二半导体层为掺杂的多晶硅层，该第三半导体层和第四半导体层的材质均为金属氧化物半导体。
3.如权利要求2所述的阵列基板，其特征在于：该第一薄膜晶体管还包括第一源极和第一漏极，该第一源极和第一漏极形成在第二介电层上且位于该第一栅极的相对两端，且经由穿过第一介电层、第二介电层以及第一栅极绝缘层的过孔与第一半导体层电性连接；该第二薄膜晶体管还包括第二源极以及第二漏极，该第二源极与第二漏极形成在该第三介电层上且对称设置于第三半导体的相对两侧，且该第二源极经由穿过第三介电层以及第二栅极绝缘层的过孔与第二半导体层电性连接；该第三薄膜晶体管还包括第三源极以及第三漏极，第三源极与第三漏极形成在该第四介电层上且对称设置于第二半导体相对两侧。
4.如权利要求2所述的阵列基板，其特征在于：第一栅极绝缘层、第二栅极绝缘层以及第三栅极绝缘层相互连接且一体成型，第二介电层、第三介电层以及第四介电层相互连接且一体成型。
5.如权利要求2所述的阵列基板，其特征在于：所述阵列基板还包括平坦层、电极层、发光定义层以及至少两个间隔物，平坦层覆盖第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；电极层形成于平坦层上且穿过平坦层与第二源极电性连接；发光定义层形成于平坦层上，用于界定像素单元的发光区域；间隔物垂直设置于发光定义层上。
6.一种应用权利要求1-5中任意一项所述阵列基板的显示装置。
7.一种阵列基板的制备方法，其包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
对多晶硅层进行掺杂，并图案化多晶硅层以形成第一半导体层和第二半导体层；
对第一半导体层进行掺杂以形成两个间隔设置的第一掺杂区域；
在基板上形成第一栅极绝缘层、第二栅极绝缘层以及第三栅极绝缘层，并在第一栅极绝缘层上形成第一栅极，在第二栅极绝缘层上形成第二栅极，并在第三栅极绝缘层上形成第三栅极；
对第一半导体层进行掺杂以形成两个间隔设置的第二掺杂区域以及非掺杂区域；
仅在第一栅极绝缘层上形成第一介电层，该第一介电层的材质为氮化硅；
在第一介电层、第二栅极绝缘层以及第三栅极绝缘层上形成第二介电层、第三介电层以及第四介电层，该第二介电层、第三介电层以及第四介电层的材质均为氧化硅；
在第三介电层以及第四介电层上分别沉积形成第三半导体层和第四半导体层，该第三半导体层和第四半导体层的材质均为金属氧化物半导体；
在与第一掺杂区域对应处开设第一过孔及第二过孔贯穿第二介电层、第一介电层以及第一栅极绝缘层，在第二半导体层对应的位置处分别开设第三过孔和第四过孔，第三过孔贯穿第三介电层和第二栅极绝缘层，第四过孔贯穿第三介电层；
在在第二介电层上且在第一过孔和第二过孔中分别形成第一源极和第一漏极，在第三介电层上且在第三过孔中形成第二源极和在第三介电层上形成第二漏极，在第四介电层上且在第四过孔中形成第三源极和在第四介电上形成第三漏极。
8.如权利要求7所述的阵列基板的制备方法，其特征在于：所述方法还包括在第二介电层、第三介电层、第四介电层上形成平坦层的步骤。
9.如权利要求8所述的阵列基板的制备方法，其特征在于：所述方法还包括在平坦层上形成电极层与第二源极电性连接；在平坦层上形成发光定义层，并在发光定义层上形成至少两个间隔物的步骤。
10.如权利要求7所述的阵列基板的制备方法，其特征在于：仅在第一栅极绝缘层上形成该第一介电层的步骤为将氮化硅材料覆盖在第一栅极绝缘层、第二栅极绝缘层以及第三栅极绝缘层上；并利用一光罩移除位于第二栅极绝缘层以及第三栅极绝缘层上的第一介电材料，以形成仅覆盖第一栅极的第一介电层。
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