US20170084641A1 - Array substrate and display device and method for making the array substrate - Google Patents
Array substrate and display device and method for making the array substrate Download PDFInfo
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- US20170084641A1 US20170084641A1 US15/198,116 US201615198116A US2017084641A1 US 20170084641 A1 US20170084641 A1 US 20170084641A1 US 201615198116 A US201615198116 A US 201615198116A US 2017084641 A1 US2017084641 A1 US 2017084641A1
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- gate insulator
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- 239000000758 substrate Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims description 55
- 239000012212 insulator Substances 0.000 claims abstract description 161
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 62
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 359
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- 239000002356 single layer Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- 239000011787 zinc oxide Substances 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 4
- 229910001195 gallium oxide Inorganic materials 0.000 description 4
- 238000005984 hydrogenation reaction Methods 0.000 description 4
- 229910003437 indium oxide Inorganic materials 0.000 description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Definitions
- the subject matter herein generally relates to an array substrate, a display device having the array substrate, and method for making the array substrate, more particularly to an array substrate for an organic light emitting diode (OLED) display device.
- OLED organic light emitting diode
- the OLED display device usually includes a substrate, a pixel array, and a driving circuit formed on the substrate.
- the OLED fabrication process is prone to damage from the high temperature fabrication process which results in degradation in display performance and quality. Furthermore, there is room for improvement in display, operation, and luminance of an OLED device.
- FIG. 1 is a cross-sectional view of a first exemplary embodiment of an array substrate.
- FIG. 2 illustrates a step for manufacturing the array substrate of FIG. 1 at block 301 of FIG. 7 .
- FIG. 3 illustrates a step for manufacturing the array substrate of FIG. 1 at block 303 of FIG. 7 .
- FIG. 4 illustrates a step for manufacturing the array substrate of FIG. 1 at block 305 of FIG. 7 .
- FIG. 5 illustrates a step for manufacturing the array substrate of FIG. 1 at block 309 of FIG. 7 .
- FIG. 6 illustrates a step for manufacturing the array substrate of FIG. 1 at block 311 of FIG. 7 .
- FIG. 7 is a flow chart of a method for making the array substrate of FIG. 1 .
- FIG. 8 is a cross-sectional view of a second exemplary embodiment of an array substrate.
- FIG. 9 is a diagram of an equivalent circuit of a pixel unit in the array substrate of FIG. 8 .
- FIG. 10 illustrates a step for manufacturing the array substrate of FIG. 8 at block 701 of FIG. 15 .
- FIG. 11 illustrates a step for manufacturing the array substrate of FIG. 8 at block 703 of FIG. 15 .
- FIG. 12 illustrates a step for manufacturing the array substrate of FIG. 8 at block 705 of FIG. 15 .
- FIG. 13 illustrates a step for manufacturing the array substrate of FIG. 8 at block 709 of FIG. 15 .
- FIG. 14 illustrates a step for manufacturing the array substrate of FIG. 8 at block 711 of FIG. 15 .
- FIG. 15 is a flow chart of a method for making the array substrate of FIG. 8 .
- Coupled is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections.
- the connection can be such that the objects are permanently connected or releasably connected.
- substantially is defined to be essentially conforming to the particular dimension, shape, or other feature that the term modifies, such that the component need not be exact.
- substantially cylindrical means that the object resembles a cylinder, but can have one or more deviations from a true cylinder.
- comprising when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
- FIG. 1 illustrates a first embodiment of an array substrate (array substrate 10 ) in part and in cross section.
- the array substrate 10 is used in a liquid crystal display device.
- the array substrate 10 comprises at least two kinds of thin film transistors (TFTs), a low-temperature poly silicon TFT and a metal oxide TFT.
- TFTs thin film transistors
- the low-temperature poly silicon TFT has a high electron mobility and a small volume.
- the metal oxide TFT has a low leakage current.
- the array substrate 10 comprises a substrate 101 , a plurality of first TFTs 100 , and a plurality of second TFTs 200 on the substrate 101 .
- a planar layer 19 covers the first TFTs 100 and the second TFTs 200 .
- a common electrode 21 is formed on the planar layer 19 .
- a pixel electrode 23 on the planar layer 19 is coupled to the first TFT 100 .
- FIG. 1 shows only one first TFT 100 and one second TFT 200 .
- each of the first TFTs 100 is a metal oxide TFT
- each of the second TFTs 200 is a low-temperature poly silicon TFT.
- Each first TFT 100 is a bottom-gate type TFT and comprises a buffer layer 103 , a gate electrode 105 , a gate insulator layer 107 , a source electrode 109 , a drain electrode 111 , and a metal oxide semiconductor layer 113 .
- the buffer layer 103 , the gate electrode 105 , and the gate insulator layer 107 are stacked on the substrate 101 in that order.
- a portion of the gate insulator layer 107 corresponding to the gate electrode 105 forms a step.
- the source electrode 109 and the drain electrode 111 are positioned at opposite sides of the step.
- the metal oxide semiconductor layer 113 is formed on the gate insulator layer 107 and partially covers both the source electrode 109 and the drain electrode 111 .
- the metal oxide semiconductor layer 113 is configured to electrically couple the source electrode 109 and the drain electrode 111 .
- the pixel electrode 23 is electrically coupled to the drain electrode 111 .
- the gate insulator layer 107 comprises a first gate insulator layer 1071 formed on the buffer layer 103 and a second gate insulator layer 1072 formed on the first gate insulator layer 1071 .
- the metal oxide semiconductor layer 113 may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. In this embodiment, the metal oxide semiconductor layer 113 is made of IGZO.
- Each second TFT 200 is a top-gate type TFT and comprises a poly-silicon semiconductor layer 201 , a buffer layer 203 , a gate electrode 205 , a gate insulator layer 207 , a source electrode 209 , and a drain electrode 211 .
- the poly-silicon semiconductor layer 201 , the buffer layer 203 , the gate electrode 205 , and the gate insulator layer 207 are stacked on the substrate 101 in that order.
- the gate electrode 205 corresponds to the poly-silicon semiconductor layer 201 .
- Both the source electrode 209 and the drain electrode 211 pass through the buffer layer 203 and the gate insulator layer 207 , and electrically couple to the poly-silicon semiconductor layer 201 .
- the gate insulator layer 207 comprises a first gate insulator layer 2071 formed on the buffer layer 203 and a second gate insulator layer 2072 formed on the first gate insulator layer 2071 .
- the buffer layer 103 and the buffer layer 203 are defined within a single layer and are simultaneously formed in a single process.
- the first gate insulator layer 1071 and the first gate insulator layer 2071 are defined within a single layer and are simultaneously formed in a single process.
- the second gate insulator layer 1072 and the second gate insulator layer 2072 are defined within a single layer and are simultaneously formed in a single process.
- both the buffer layer 103 and the buffer layer 203 are made of an insulator material, such as silicon oxide or silicon nitride. Both the first gate insulator layer 1071 and the first gate insulator layer 2071 are made of silicon oxide. Both the second gate insulator layer 1072 and the second gate insulator layer 2072 are made of silicon oxide.
- FIG. 7 illustrates an example method for making the array substrate 10 shown in FIG. 1 .
- the example method is provided by way of example, as there are a variety of ways to carry out the method.
- Each block shown in FIG. 7 represents one or more processes, methods, or subroutines, carried out in the exemplary method.
- the exemplary method can begin at block 301 .
- a poly-silicon semiconductor layer 201 is formed on a substrate 101 as shown in FIG. 2 .
- the process of forming the poly-silicon semiconductor layer 201 on the substrate 101 may comprise depositing an amorphous silicon layer, laser annealing and ion doping the amorphous silicon layer.
- the substrate 101 can be made of a common material such as glass, quartz, or other material which is flexible.
- a buffer layer 103 and a buffer layer 203 are formed on the substrate 101 .
- a gate 105 is then formed on the buffer layer 103
- a gate 205 is formed on the buffer layer 203 .
- the buffer layer 203 covers the poly-silicon semiconductor layer 201 .
- the buffer layer 103 and the buffer layer 203 are made of an electrical insulator material.
- the process of forming the gate 105 and the gate 205 may comprise depositing a first metal layer on the buffer layer 103 and the buffer layer 203 , and etching and patterning the first metal layer to form the gate 105 and the gate 205 .
- the metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd).
- Mo molybdenum
- Al aluminum
- Cr chromium
- Cu copper
- Nd neodymium
- the etching process can be a photolithography etching process.
- a gate insulator layer 107 and a gate insulator layer 207 are formed, and a first hole 213 and a second hole 215 passing through the gate insulator layer 207 and the buffer layer 203 are defined to expose the poly-silicon semiconductor layer 201 .
- a portion of the gate insulator layer 107 corresponding to the gate electrode 105 forms a step.
- the gate insulator layer 107 comprises a first gate insulator layer 1071 formed on the buffer layer 103 and a second gate insulator layer 1072 formed on the first gate insulator layer 1071 .
- the gate insulator layer 207 comprises a first gate insulator layer 2071 formed on the buffer layer 203 and a second gate insulator layer 2072 formed on the first gate insulator layer 2071 .
- the process of forming the gate insulator layer 107 and the gate insulator layer 207 may comprise depositing a first gate insulator layer to form the first gate insulator layer 1071 and 2071 , and then depositing a second gate insulator layer on the first gate insulator layer to form the second gate insulator layer 1072 and 2072 .
- Both the first gate insulator layer 1071 and the first gate insulator layer 2071 are made of silicon oxide.
- Both the second gate insulator layer 1072 and the second gate insulator layer 2072 are made of silicon nitride.
- the buffer layer 103 , the gate 105 , and the gate insulator layer 107 cooperatively define a region of the first TFT 100 .
- the poly-silicon semiconductor layer 201 , the buffer layer 203 , the gate 205 , and the gate insulator layer 207 cooperatively define a region of the second TFT 200 .
- the region of the second TFT 200 is subjected to a hydrogenation treatment.
- the temperature of the hydrogenation treatment is higher than 400 degrees Celsius.
- a source electrode 109 , a source electrode 209 , a drain electrode 111 , and a drain electrode 211 are formed.
- the process of forming the source electrode 109 , the source electrode 209 , the drain electrode 111 , and the drain electrode 211 may comprise depositing a second metal layer and etching and patterning the second metal layer to form the source electrode 109 , the source electrode 209 , the drain electrode 111 , and the drain electrode 211 .
- the source electrode 209 is formed in the first hole 213 and coupled to the poly-silicon semiconductor layer 201
- the drain electrode 211 is formed in the second through hole 215 and coupled to the poly-silicon semiconductor layer 201 .
- the source electrode 109 and the drain electrode 111 are positioned at a same layer and are positioned at opposite sides of the step.
- a metal oxide semiconductor layer 113 is formed.
- the process of forming the metal oxide semiconductor layer 113 may comprise depositing a metal oxide layer, and patterning the metal oxide layer to form the metal oxide semiconductor layer 113 .
- the metal oxide semiconductor layer 113 is formed on the second gate insulator layer 1072 and corresponds to the gate 105 .
- the metal oxide semiconductor layer 113 partially covers the source electrode 109 and the drain electrode 111 .
- the metal oxide semiconductor layer 413 can be made of IGZO, zinc oxide, indium oxide, or gallium oxide.
- a planar layer 19 is formed to cover the first TFT 100 and a second TFT 200 .
- the method further comprises forming a common electrode layer 21 on the planar layer 19 , and forming a pixel electrode layer 23 , electrically coupled to the drain electrode 111 of the first TFT 100 , on the planar layer 19 .
- the array substrate 10 includes the first TFTs 100 and the second TFTs 200 .
- each first TFT 100 is a metal oxide TFT
- each second TFT 200 is a low-temperature poly silicon TFT.
- the first TFT 100 is a metal oxide TFT, which has a low leakage current and can reduce power consumption.
- the second TFT 200 is a low-temperature poly silicon TFT, which has a high electron mobility and can effectively improve a reaction rate of the driving circuit.
- the low-temperature poly silicon TFT has a small volume and is of benefit for narrowing the non-display region.
- the metal oxide semiconductor layer 113 is formed after the forming of the source electrode 109 and the drain electrode 111 , which protects the metal oxide semiconductor layer 113 from damage during the forming process of the source electrode 109 and the drain electrode 111 .
- FIG. 8 illustrates a second embodiment of the array substrate 40 in part and in cross section.
- the array substrate 40 is used in an organic light emitting diode display device.
- the array substrate 40 comprises at least two kinds of thin film transistors (TFTs), a low-temperature poly silicon TFT and a metal oxide TFT.
- TFTs thin film transistors
- the low-temperature poly silicon TFT has a high electron mobility and a small volume.
- the metal oxide TFT has a low leakage current.
- the array substrate 40 comprises a plurality of pixel units 420 arranged in rows and columns.
- FIG. 9 illustrates one of the pixel units 420 .
- Each pixel unit 420 comprises a light emitting diode 421 , a switch TFT 400 , a driving TFT 500 , and a capacitor C.
- the switch TFT 400 is electrically connected between a gate line and a data line to switch the driving TFT 500 on or off.
- the driving TFT 500 is electrically connected between a power source VDD and the light emitting diode 421 .
- the capacitor C is a storage capacitor and is electrically connected between a gate electrode of the driving TFT 500 and a drain electrode of the driving TFT 500 .
- the capacitor C is configured to control electrical current of the driving TFT 500 , thus the driving TFT 500 can control a luminance of the light emitting diode 421 .
- the array substrate 40 comprises a substrate 401 , and a plurality of switch TFTs 400 , a plurality of driving TFTs 500 , and a plurality of poly silicon TFTs 600 formed on the substrate 401 .
- the array substrate 40 further comprises a planar layer 49 covering the switch TFTs 400 , the driving TFTs 500 , and the poly silicon TFTs 600 , a light-emitting material layer 51 , a plurality of cathodes 53 , a dielectric layer 55 , and a plurality of anodes 57 each electrically coupled to one of the drain electrodes 511 of the driving TFTs 500 .
- FIG. 8 shows only one switch TFT 400 , one driving TFT 500 , and one poly silicon TFT 600 .
- each switch TFT 400 and each driving TFT 500 are metal oxide TFTs
- each poly silicon TFT 600 is a low-temperature poly silicon TFT.
- Each driving TFT 500 is a bottom-gate type TFT and comprises a buffer layer 503 , a gate electrode 505 , a gate insulator layer 507 , a source electrode 509 , a drain electrode 111 , and a metal oxide semiconductor layer 513 .
- the buffer layer 503 , the gate electrode 505 , and the gate insulator layer 507 are stacked on the substrate 401 in that order.
- a portion of the gate insulator layer 507 corresponding to the gate electrode 505 forms a step.
- the source electrode 509 and the drain electrode 511 are positioned at opposite sides of the step.
- the metal oxide semiconductor layer 513 is formed on the gate insulator layer 507 and partially covers the source electrode 509 and the drain electrode 511 .
- the metal oxide semiconductor layer 513 is configured to electrically couple the source electrode 509 and the drain electrode 511 .
- the drain electrode 511 is electrically coupled to the anode 57 .
- the gate insulator layer 507 comprises a first gate insulator layer 5071 formed on the buffer layer 503 and a second gate insulator layer 5072 formed on the first gate insulator layer 5071 .
- the metal oxide semiconductor layer 513 may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. In this embodiment, the metal oxide semiconductor layer 513 is made of IGZO.
- Each switch TFT 400 is substantially the same as the driving TFT 500 , except that the switch TFT 400 is not coupled to an anode.
- Each poly silicon TFT 600 is a top-gate type TFT and comprises a poly-silicon semiconductor layer 601 , a buffer layer 603 , a gate electrode 605 , a gate insulator layer 607 , a source electrode 609 , and a drain electrode 611 .
- the poly-silicon semiconductor layer 601 , the buffer layer 603 , the gate electrode 605 , and the gate insulator layer 607 are stacked on the substrate 401 in that order.
- the gate electrode 605 corresponds to the poly-silicon semiconductor layer 601 .
- Both the source electrode 609 and the drain electrode 611 pass through the buffer layer 603 and the gate insulator layer 607 and electrically couple to the poly-silicon semiconductor layer 601 .
- the gate insulator layer 607 comprises a first gate insulator layer 6071 formed on the buffer layer 603 and a second gate insulator layer 6072 formed on the first gate insulator layer 6071 .
- the first gate insulator layer 5071 of each driving TFT 500 and the first gate insulator layer 6071 of each poly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process.
- the second gate insulator layer 5072 of each driving TFT 500 and the second gate insulator layer 6072 of each poly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process.
- the buffer layer 503 of each driving TFT 500 and the buffer 603 of each poly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process.
- both the first gate insulator layer 5071 and the first gate insulator layer 6071 are made of silicon oxide. Both the second gate insulator layer 5072 and the second gate insulator layer 6072 are made of silicon nitride.
- FIG. 15 illustrates an example method for making the array substrate 40 shown in FIG. 8 .
- the example method is provided by way of example, as there are a variety of ways to carry out the method.
- Each block shown in FIG. 15 represents one or more processes, methods or subroutines, carried out in the exemplary method.
- the method only describes the making of the driving TFT 500 and the poly silicon TFT 600 , the making of the switch TFT 400 is not described.
- the switch TFT 400 is substantially the same as the driving TFT 500
- the method for making TFT 400 on the array substrate 40 resembles the method for making the driving TFT 500 .
- the exemplary method can begin at block 701 .
- a poly-silicon semiconductor layer 601 is formed on a substrate 401 as shown in FIG. 2 .
- the process of forming the poly-silicon semiconductor layer 601 on the substrate 401 may comprise depositing an amorphous silicon layer, and laser annealing and ion doping the amorphous silicon layer.
- the substrate 401 can be made of a common material such as glass or quartz, or other material which is flexible.
- a buffer layer 503 , and a buffer layer 603 are formed on the substrate 401 .
- a gate 505 is then formed on the buffer layer 503 and a gate 605 is formed on the buffer layer 603 .
- the buffer layer 603 covers the poly-silicon semiconductor layer 601 .
- the buffer layer 503 and the buffer layer 603 are made of an insulator material.
- the process of forming the gate 505 and the gate 605 may comprise depositing a first metal layer on the buffer layer 503 and the buffer layer 603 and etching and patterning the first metal layer to form the gate 505 and the gate 605 .
- the metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), neodymium (Nd).
- Mo molybdenum
- Al aluminum
- Cr chromium
- Cu copper
- Nd neodymium
- the etching method can be a photolithography etching method.
- a gate insulator layer 507 and a gate insulator layer 607 are formed, and a first hole 613 and a second hole 615 passing through the gate insulator layer 607 and the buffer layer 603 are defined to expose the poly-silicon semiconductor layer 601 .
- a portion of the gate insulator layer 607 corresponding to the gate electrode 605 forms a step.
- the gate insulator layer 507 comprises a first gate insulator layer 5071 formed on the buffer layer 503 and a second gate insulator layer 5072 formed on the first gate insulator layer 5071 .
- the gate insulator layer 607 comprises a first gate insulator layer 6071 formed on the buffer layer 603 and a second gate insulator layer 6072 formed on the first gate insulator layer 6071 .
- the process of forming the gate insulator layer 507 and the gate insulator layer 607 may comprise depositing a first gate insulator layer to form the first gate insulator layer 5071 and 6071 , and then depositing a second gate insulator layer on the first gate insulator layer to form the second gate insulator layer 5072 and 6072 .
- Both the first gate insulator layer 5071 and the first gate insulator layer 6071 are made of silicon oxide.
- Both the second gate insulator layer 5072 and the second gate insulator layer 6072 are made of silicon nitride.
- the buffer layer 503 , the gate 505 , and the gate insulator layer 507 cooperatively define a region of the driving TFT 500 .
- the poly-silicon semiconductor layer 601 , the buffer layer 603 , the gate 605 , and the gate insulator layer 607 cooperatively define a region of the poly silicon TFT 600 .
- the region of the poly silicon TFT 600 is subjected to a hydrogenation treatment.
- the temperature of the hydrogenation treatment is higher than 400 degrees Celsius.
- a source electrode 509 , a source electrode 609 , a drain electrode 511 , and a drain electrode 611 are formed.
- the process of forming the source electrode 509 , the source electrode 609 , the drain electrode 511 , and the drain electrode 611 may comprise depositing a second metal layer and etching and patterning the second metal layer to form the source electrode 509 , the source electrode 609 , the drain electrode 511 , and the drain electrode 611 .
- the source electrode 609 is formed in the first hole 613 and coupled to the poly-silicon semiconductor layer 601 and the drain electrode 611 is formed in the second through hole 615 and coupled to the poly-silicon semiconductor layer 601 .
- the source electrode 509 and the drain electrode 511 are positioned at opposite sides of the step.
- a metal oxide semiconductor layer 513 is formed.
- the process of forming the metal oxide semiconductor layer 513 may comprise depositing a metal oxide layer and patterning the metal oxide layer to form the metal oxide semiconductor layer 513 .
- the metal oxide semiconductor layer 513 is formed on the second gate insulator layer 5072 and corresponds to the gate 505 .
- the metal oxide semiconductor layer 513 partially covers the source electrode 509 and the drain electrode 511 .
- the metal oxide semiconductor layer 513 can be made of IGZO, zinc oxide, indium oxide, or gallium oxide.
- a planar layer 49 is formed to cover the switch TFT 400 , the driving TFT 500 , and the poly silicon TFT 600 .
- the method further comprises forming an anode 57 on the planar layer 49 which is electrically coupled to the drain electrode 511 of the driving TFT 500 , and forming a cathode 53 , a dielectric layer 55 , and light-emitting material 51 on the planar layer 49 .
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Abstract
An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT includes a buffer layer, a gate, a gate insulator layer, and a metal oxide semiconductor layer stacked on the substrate in that order. A source electrode and a drain electrode are separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT. The metal oxide semiconductor layer partially covers the source electrode and the drain electrode.
Description
- The subject matter herein generally relates to an array substrate, a display device having the array substrate, and method for making the array substrate, more particularly to an array substrate for an organic light emitting diode (OLED) display device.
- Two common kinds of display devices are liquid crystal and OLED. The OLED display device usually includes a substrate, a pixel array, and a driving circuit formed on the substrate. The OLED fabrication process is prone to damage from the high temperature fabrication process which results in degradation in display performance and quality. Furthermore, there is room for improvement in display, operation, and luminance of an OLED device.
- Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.
-
FIG. 1 is a cross-sectional view of a first exemplary embodiment of an array substrate. -
FIG. 2 illustrates a step for manufacturing the array substrate ofFIG. 1 atblock 301 ofFIG. 7 . -
FIG. 3 illustrates a step for manufacturing the array substrate ofFIG. 1 atblock 303 ofFIG. 7 . -
FIG. 4 illustrates a step for manufacturing the array substrate ofFIG. 1 atblock 305 ofFIG. 7 . -
FIG. 5 illustrates a step for manufacturing the array substrate ofFIG. 1 atblock 309 ofFIG. 7 . -
FIG. 6 illustrates a step for manufacturing the array substrate ofFIG. 1 atblock 311 ofFIG. 7 . -
FIG. 7 is a flow chart of a method for making the array substrate ofFIG. 1 . -
FIG. 8 is a cross-sectional view of a second exemplary embodiment of an array substrate. -
FIG. 9 is a diagram of an equivalent circuit of a pixel unit in the array substrate ofFIG. 8 . -
FIG. 10 illustrates a step for manufacturing the array substrate ofFIG. 8 atblock 701 ofFIG. 15 . -
FIG. 11 illustrates a step for manufacturing the array substrate ofFIG. 8 atblock 703 ofFIG. 15 . -
FIG. 12 illustrates a step for manufacturing the array substrate ofFIG. 8 atblock 705 ofFIG. 15 . -
FIG. 13 illustrates a step for manufacturing the array substrate ofFIG. 8 atblock 709 ofFIG. 15 . -
FIG. 14 illustrates a step for manufacturing the array substrate ofFIG. 8 atblock 711 ofFIG. 15 . -
FIG. 15 is a flow chart of a method for making the array substrate ofFIG. 8 . - It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.
- Several definitions that apply throughout this disclosure will now be presented.
- The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “substantially” is defined to be essentially conforming to the particular dimension, shape, or other feature that the term modifies, such that the component need not be exact. For example, “substantially cylindrical” means that the object resembles a cylinder, but can have one or more deviations from a true cylinder. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
-
FIG. 1 illustrates a first embodiment of an array substrate (array substrate 10) in part and in cross section. In this embodiment, thearray substrate 10 is used in a liquid crystal display device. Thearray substrate 10 comprises at least two kinds of thin film transistors (TFTs), a low-temperature poly silicon TFT and a metal oxide TFT. The low-temperature poly silicon TFT has a high electron mobility and a small volume. The metal oxide TFT has a low leakage current. - The
array substrate 10 comprises asubstrate 101, a plurality offirst TFTs 100, and a plurality ofsecond TFTs 200 on thesubstrate 101. Aplanar layer 19 covers thefirst TFTs 100 and thesecond TFTs 200. Acommon electrode 21 is formed on theplanar layer 19. Apixel electrode 23 on theplanar layer 19 is coupled to thefirst TFT 100.FIG. 1 shows only one first TFT 100 and one second TFT 200. In this embodiment, each of thefirst TFTs 100 is a metal oxide TFT, and each of thesecond TFTs 200 is a low-temperature poly silicon TFT. - Each
first TFT 100 is a bottom-gate type TFT and comprises abuffer layer 103, agate electrode 105, agate insulator layer 107, asource electrode 109, adrain electrode 111, and a metaloxide semiconductor layer 113. Thebuffer layer 103, thegate electrode 105, and thegate insulator layer 107 are stacked on thesubstrate 101 in that order. A portion of thegate insulator layer 107 corresponding to thegate electrode 105 forms a step. Thesource electrode 109 and thedrain electrode 111 are positioned at opposite sides of the step. The metaloxide semiconductor layer 113 is formed on thegate insulator layer 107 and partially covers both thesource electrode 109 and thedrain electrode 111. The metaloxide semiconductor layer 113 is configured to electrically couple thesource electrode 109 and thedrain electrode 111. Thepixel electrode 23 is electrically coupled to thedrain electrode 111. Thegate insulator layer 107 comprises a firstgate insulator layer 1071 formed on thebuffer layer 103 and a secondgate insulator layer 1072 formed on the firstgate insulator layer 1071. The metaloxide semiconductor layer 113 may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. In this embodiment, the metaloxide semiconductor layer 113 is made of IGZO. - Each
second TFT 200 is a top-gate type TFT and comprises a poly-silicon semiconductor layer 201, abuffer layer 203, agate electrode 205, agate insulator layer 207, asource electrode 209, and adrain electrode 211. The poly-silicon semiconductor layer 201, thebuffer layer 203, thegate electrode 205, and thegate insulator layer 207 are stacked on thesubstrate 101 in that order. Thegate electrode 205 corresponds to the poly-silicon semiconductor layer 201. Both thesource electrode 209 and thedrain electrode 211 pass through thebuffer layer 203 and thegate insulator layer 207, and electrically couple to the poly-silicon semiconductor layer 201. Thegate insulator layer 207 comprises a firstgate insulator layer 2071 formed on thebuffer layer 203 and a secondgate insulator layer 2072 formed on the firstgate insulator layer 2071. - The
buffer layer 103 and thebuffer layer 203 are defined within a single layer and are simultaneously formed in a single process. The firstgate insulator layer 1071 and the firstgate insulator layer 2071 are defined within a single layer and are simultaneously formed in a single process. The secondgate insulator layer 1072 and the secondgate insulator layer 2072 are defined within a single layer and are simultaneously formed in a single process. - In this embodiment, both the
buffer layer 103 and thebuffer layer 203 are made of an insulator material, such as silicon oxide or silicon nitride. Both the firstgate insulator layer 1071 and the firstgate insulator layer 2071 are made of silicon oxide. Both the secondgate insulator layer 1072 and the secondgate insulator layer 2072 are made of silicon oxide. -
FIG. 7 illustrates an example method for making thearray substrate 10 shown inFIG. 1 . The example method is provided by way of example, as there are a variety of ways to carry out the method. Each block shown inFIG. 7 represents one or more processes, methods, or subroutines, carried out in the exemplary method. The exemplary method can begin atblock 301. - At
block 301, a poly-silicon semiconductor layer 201 is formed on asubstrate 101 as shown inFIG. 2 . The process of forming the poly-silicon semiconductor layer 201 on thesubstrate 101 may comprise depositing an amorphous silicon layer, laser annealing and ion doping the amorphous silicon layer. Thesubstrate 101 can be made of a common material such as glass, quartz, or other material which is flexible. - At
block 303, as shown inFIG. 3 , abuffer layer 103 and abuffer layer 203 are formed on thesubstrate 101. Agate 105 is then formed on thebuffer layer 103, and agate 205 is formed on thebuffer layer 203. Thebuffer layer 203 covers the poly-silicon semiconductor layer 201. Thebuffer layer 103 and thebuffer layer 203 are made of an electrical insulator material. The process of forming thegate 105 and thegate 205 may comprise depositing a first metal layer on thebuffer layer 103 and thebuffer layer 203, and etching and patterning the first metal layer to form thegate 105 and thegate 205. The metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd). The etching process can be a photolithography etching process. - At
block 305, as shown inFIG. 4 , agate insulator layer 107 and agate insulator layer 207 are formed, and afirst hole 213 and asecond hole 215 passing through thegate insulator layer 207 and thebuffer layer 203 are defined to expose the poly-silicon semiconductor layer 201. A portion of thegate insulator layer 107 corresponding to thegate electrode 105 forms a step. Thegate insulator layer 107 comprises a firstgate insulator layer 1071 formed on thebuffer layer 103 and a secondgate insulator layer 1072 formed on the firstgate insulator layer 1071. Thegate insulator layer 207 comprises a firstgate insulator layer 2071 formed on thebuffer layer 203 and a secondgate insulator layer 2072 formed on the firstgate insulator layer 2071. The process of forming thegate insulator layer 107 and thegate insulator layer 207 may comprise depositing a first gate insulator layer to form the firstgate insulator layer gate insulator layer gate insulator layer 1071 and the firstgate insulator layer 2071 are made of silicon oxide. Both the secondgate insulator layer 1072 and the secondgate insulator layer 2072 are made of silicon nitride. - The
buffer layer 103, thegate 105, and thegate insulator layer 107 cooperatively define a region of thefirst TFT 100. The poly-silicon semiconductor layer 201, thebuffer layer 203, thegate 205, and thegate insulator layer 207 cooperatively define a region of thesecond TFT 200. - At
block 307, the region of thesecond TFT 200 is subjected to a hydrogenation treatment. In this embodiment, the temperature of the hydrogenation treatment is higher than 400 degrees Celsius. - At
block 309, as shown inFIG. 5 , asource electrode 109, asource electrode 209, adrain electrode 111, and adrain electrode 211 are formed. The process of forming thesource electrode 109, thesource electrode 209, thedrain electrode 111, and thedrain electrode 211 may comprise depositing a second metal layer and etching and patterning the second metal layer to form thesource electrode 109, thesource electrode 209, thedrain electrode 111, and thedrain electrode 211. Thesource electrode 209 is formed in thefirst hole 213 and coupled to the poly-silicon semiconductor layer 201, and thedrain electrode 211 is formed in the second throughhole 215 and coupled to the poly-silicon semiconductor layer 201. Thesource electrode 109 and thedrain electrode 111 are positioned at a same layer and are positioned at opposite sides of the step. - At
block 311, as shown inFIG. 5 , a metaloxide semiconductor layer 113 is formed. The process of forming the metaloxide semiconductor layer 113 may comprise depositing a metal oxide layer, and patterning the metal oxide layer to form the metaloxide semiconductor layer 113. The metaloxide semiconductor layer 113 is formed on the secondgate insulator layer 1072 and corresponds to thegate 105. The metaloxide semiconductor layer 113 partially covers thesource electrode 109 and thedrain electrode 111. The metal oxide semiconductor layer 413 can be made of IGZO, zinc oxide, indium oxide, or gallium oxide. - At
block 313, as shown inFIG. 1 , aplanar layer 19 is formed to cover thefirst TFT 100 and asecond TFT 200. The method further comprises forming acommon electrode layer 21 on theplanar layer 19, and forming apixel electrode layer 23, electrically coupled to thedrain electrode 111 of thefirst TFT 100, on theplanar layer 19. - The
array substrate 10 includes thefirst TFTs 100 and thesecond TFTs 200. In this embodiment, eachfirst TFT 100 is a metal oxide TFT, and eachsecond TFT 200 is a low-temperature poly silicon TFT. Thefirst TFT 100 is a metal oxide TFT, which has a low leakage current and can reduce power consumption. Thesecond TFT 200 is a low-temperature poly silicon TFT, which has a high electron mobility and can effectively improve a reaction rate of the driving circuit. The low-temperature poly silicon TFT has a small volume and is of benefit for narrowing the non-display region. For eachfirst TFT 100, the metaloxide semiconductor layer 113 is formed after the forming of thesource electrode 109 and thedrain electrode 111, which protects the metaloxide semiconductor layer 113 from damage during the forming process of thesource electrode 109 and thedrain electrode 111. -
FIG. 8 illustrates a second embodiment of thearray substrate 40 in part and in cross section. In this embodiment, thearray substrate 40 is used in an organic light emitting diode display device. Thearray substrate 40 comprises at least two kinds of thin film transistors (TFTs), a low-temperature poly silicon TFT and a metal oxide TFT. The low-temperature poly silicon TFT has a high electron mobility and a small volume. The metal oxide TFT has a low leakage current. - The
array substrate 40 comprises a plurality ofpixel units 420 arranged in rows and columns.FIG. 9 illustrates one of thepixel units 420. Eachpixel unit 420 comprises alight emitting diode 421, aswitch TFT 400, a drivingTFT 500, and a capacitor C. Theswitch TFT 400 is electrically connected between a gate line and a data line to switch the drivingTFT 500 on or off. The drivingTFT 500 is electrically connected between a power source VDD and thelight emitting diode 421. The capacitor C is a storage capacitor and is electrically connected between a gate electrode of the drivingTFT 500 and a drain electrode of the drivingTFT 500. The capacitor C is configured to control electrical current of the drivingTFT 500, thus the drivingTFT 500 can control a luminance of thelight emitting diode 421. - The
array substrate 40 comprises asubstrate 401, and a plurality ofswitch TFTs 400, a plurality of drivingTFTs 500, and a plurality ofpoly silicon TFTs 600 formed on thesubstrate 401. Thearray substrate 40 further comprises aplanar layer 49 covering theswitch TFTs 400, the drivingTFTs 500, and thepoly silicon TFTs 600, a light-emittingmaterial layer 51, a plurality ofcathodes 53, adielectric layer 55, and a plurality ofanodes 57 each electrically coupled to one of thedrain electrodes 511 of the drivingTFTs 500.FIG. 8 shows only oneswitch TFT 400, one drivingTFT 500, and onepoly silicon TFT 600. In this embodiment, eachswitch TFT 400 and each drivingTFT 500 are metal oxide TFTs, eachpoly silicon TFT 600 is a low-temperature poly silicon TFT. - Each driving
TFT 500 is a bottom-gate type TFT and comprises abuffer layer 503, agate electrode 505, agate insulator layer 507, asource electrode 509, adrain electrode 111, and a metaloxide semiconductor layer 513. Thebuffer layer 503, thegate electrode 505, and thegate insulator layer 507 are stacked on thesubstrate 401 in that order. A portion of thegate insulator layer 507 corresponding to thegate electrode 505 forms a step. Thesource electrode 509 and thedrain electrode 511 are positioned at opposite sides of the step. The metaloxide semiconductor layer 513 is formed on thegate insulator layer 507 and partially covers thesource electrode 509 and thedrain electrode 511. The metaloxide semiconductor layer 513 is configured to electrically couple thesource electrode 509 and thedrain electrode 511. Thedrain electrode 511 is electrically coupled to theanode 57. Thegate insulator layer 507 comprises a firstgate insulator layer 5071 formed on thebuffer layer 503 and a secondgate insulator layer 5072 formed on the firstgate insulator layer 5071. The metaloxide semiconductor layer 513 may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. In this embodiment, the metaloxide semiconductor layer 513 is made of IGZO. - Each
switch TFT 400 is substantially the same as the drivingTFT 500, except that theswitch TFT 400 is not coupled to an anode. - Each
poly silicon TFT 600 is a top-gate type TFT and comprises a poly-silicon semiconductor layer 601, abuffer layer 603, agate electrode 605, a gate insulator layer 607, asource electrode 609, and adrain electrode 611. The poly-silicon semiconductor layer 601, thebuffer layer 603, thegate electrode 605, and the gate insulator layer 607 are stacked on thesubstrate 401 in that order. Thegate electrode 605 corresponds to the poly-silicon semiconductor layer 601. Both thesource electrode 609 and thedrain electrode 611 pass through thebuffer layer 603 and the gate insulator layer 607 and electrically couple to the poly-silicon semiconductor layer 601. The gate insulator layer 607 comprises a firstgate insulator layer 6071 formed on thebuffer layer 603 and a second gate insulator layer 6072 formed on the firstgate insulator layer 6071. The firstgate insulator layer 5071 of each drivingTFT 500 and the firstgate insulator layer 6071 of eachpoly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process. The secondgate insulator layer 5072 of each drivingTFT 500 and the second gate insulator layer 6072 of eachpoly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process. Thebuffer layer 503 of each drivingTFT 500 and thebuffer 603 of eachpoly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process. - In this embodiment, both the first
gate insulator layer 5071 and the firstgate insulator layer 6071 are made of silicon oxide. Both the secondgate insulator layer 5072 and the second gate insulator layer 6072 are made of silicon nitride. -
FIG. 15 illustrates an example method for making thearray substrate 40 shown inFIG. 8 . The example method is provided by way of example, as there are a variety of ways to carry out the method. Each block shown inFIG. 15 represents one or more processes, methods or subroutines, carried out in the exemplary method. The method only describes the making of the drivingTFT 500 and thepoly silicon TFT 600, the making of theswitch TFT 400 is not described. As theswitch TFT 400 is substantially the same as the drivingTFT 500, the method for makingTFT 400 on thearray substrate 40 resembles the method for making the drivingTFT 500. The exemplary method can begin atblock 701. - At
block 701, a poly-silicon semiconductor layer 601 is formed on asubstrate 401 as shown inFIG. 2 . The process of forming the poly-silicon semiconductor layer 601 on thesubstrate 401 may comprise depositing an amorphous silicon layer, and laser annealing and ion doping the amorphous silicon layer. Thesubstrate 401 can be made of a common material such as glass or quartz, or other material which is flexible. - At
block 703, as shown inFIG. 11 , abuffer layer 503, and abuffer layer 603 are formed on thesubstrate 401. Agate 505 is then formed on thebuffer layer 503 and agate 605 is formed on thebuffer layer 603. Thebuffer layer 603 covers the poly-silicon semiconductor layer 601. Thebuffer layer 503 and thebuffer layer 603 are made of an insulator material. The process of forming thegate 505 and thegate 605 may comprise depositing a first metal layer on thebuffer layer 503 and thebuffer layer 603 and etching and patterning the first metal layer to form thegate 505 and thegate 605. The metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), neodymium (Nd). The etching method can be a photolithography etching method. - At
block 705, as shown inFIG. 12 , agate insulator layer 507 and a gate insulator layer 607 are formed, and afirst hole 613 and asecond hole 615 passing through the gate insulator layer 607 and thebuffer layer 603 are defined to expose the poly-silicon semiconductor layer 601. A portion of the gate insulator layer 607 corresponding to thegate electrode 605 forms a step. Thegate insulator layer 507 comprises a firstgate insulator layer 5071 formed on thebuffer layer 503 and a secondgate insulator layer 5072 formed on the firstgate insulator layer 5071. The gate insulator layer 607 comprises a firstgate insulator layer 6071 formed on thebuffer layer 603 and a second gate insulator layer 6072 formed on the firstgate insulator layer 6071. The process of forming thegate insulator layer 507 and the gate insulator layer 607 may comprise depositing a first gate insulator layer to form the firstgate insulator layer gate insulator layer 5072 and 6072. Both the firstgate insulator layer 5071 and the firstgate insulator layer 6071 are made of silicon oxide. Both the secondgate insulator layer 5072 and the second gate insulator layer 6072 are made of silicon nitride. - The
buffer layer 503, thegate 505, and thegate insulator layer 507 cooperatively define a region of the drivingTFT 500. The poly-silicon semiconductor layer 601, thebuffer layer 603, thegate 605, and the gate insulator layer 607 cooperatively define a region of thepoly silicon TFT 600. - At
block 707, the region of thepoly silicon TFT 600 is subjected to a hydrogenation treatment. In this embodiment, the temperature of the hydrogenation treatment is higher than 400 degrees Celsius. - At
block 709, as shown inFIG. 13 , asource electrode 509, asource electrode 609, adrain electrode 511, and adrain electrode 611 are formed. The process of forming thesource electrode 509, thesource electrode 609, thedrain electrode 511, and thedrain electrode 611 may comprise depositing a second metal layer and etching and patterning the second metal layer to form thesource electrode 509, thesource electrode 609, thedrain electrode 511, and thedrain electrode 611. Thesource electrode 609 is formed in thefirst hole 613 and coupled to the poly-silicon semiconductor layer 601 and thedrain electrode 611 is formed in the second throughhole 615 and coupled to the poly-silicon semiconductor layer 601. Thesource electrode 509 and thedrain electrode 511 are positioned at opposite sides of the step. - At
block 711, as shown inFIG. 14 , a metaloxide semiconductor layer 513 is formed. The process of forming the metaloxide semiconductor layer 513 may comprise depositing a metal oxide layer and patterning the metal oxide layer to form the metaloxide semiconductor layer 513. The metaloxide semiconductor layer 513 is formed on the secondgate insulator layer 5072 and corresponds to thegate 505. The metaloxide semiconductor layer 513 partially covers thesource electrode 509 and thedrain electrode 511. The metaloxide semiconductor layer 513 can be made of IGZO, zinc oxide, indium oxide, or gallium oxide. - At
block 713, as shown inFIG. 8 , aplanar layer 49 is formed to cover theswitch TFT 400, the drivingTFT 500, and thepoly silicon TFT 600. The method further comprises forming ananode 57 on theplanar layer 49 which is electrically coupled to thedrain electrode 511 of the drivingTFT 500, and forming acathode 53, adielectric layer 55, and light-emittingmaterial 51 on theplanar layer 49. - The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of an image device. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.
Claims (19)
1. An array substrate comprising:
a substrate;
a first TFT on the substrate, the first TFT being a metal oxide TFT; and
a second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;
wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT; the metal oxide semiconductor layer partially covers the source electrode and the drain electrode of the first TFT.
2. The array substrate of claim 1 , wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed; the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.
3. The array substrate of claim 2 , wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the buffer layer of the first TFT and a second gate insulator layer formed on the first gate insulator layer of the first TFT; and the gate insulator layers of the second TFT comprises a first gate insulator layer formed on the buffer layer of the second TFT and a second gate insulator layer formed on the first gate insulator layer of the second TFT.
4. The array substrate of claim 3 , wherein the first gate insulator layers of the first TFT and the second TFT are made of silicon oxide; and the second gate insulator layers of the first TFT and the second TFT are made of silicon nitride.
5. The array substrate of claim 1 , further comprising a planar layer covering the first TFT and the second TFT, a common electrode on the planar layer, and a pixel electrode electrically coupled to the first TFT.
6. An array substrate comprising:
a substrate;
a switch TFT on the substrate, the switch TFT being a metal oxide TFT;
a driving TFT on the substrate, the driving TFT being a metal oxide TFT; and
a poly silicon TFT on the substrate, the poly silicon TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT,
wherein the switch TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the switch TFT; the metal oxide semiconductor layer of the switch TFT covers the source electrode and the drain electrode of the switch TFT; and
wherein the driving TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the driving TFT; the metal oxide semiconductor layer of the driving TFT covers the source electrode and the drain electrode of the driving TFT.
7. The array substrate of claim 6 , wherein the buffer layers of the poly silicon TFT, the switch TFT, and the driving TFT are defined by a single layer and are simultaneously formed; and
the gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are defined by a single layer and are simultaneously formed.
8. The array substrate of claim 6 , wherein the gate insulator layer of the poly silicon TFT comprises a first gate insulator layer formed on the buffer layer of the poly silicon TFT and a second gate insulator layer formed on the first gate insulator layer; the gate insulator layer of the switch TFT comprises a first gate insulator layer formed on the buffer layer of the switch TFT and a second gate insulator layer formed on the first gate insulator layer; and the gate insulator layer of the driving TFT comprises a first gate insulator layer formed on the buffer layer of the driving TFT and a second gate insulator layer formed on the first gate insulator layer.
9. The array substrate of claim 8 , wherein the first gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are made of the silicon oxide; and the second gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are made of silicon nitride.
10. The array substrate of claim 6 , wherein the array substrate further comprises a planar layer covering the switch TFT, the driving TFT, and the poly silicon TFT, a lighting emitting material layer on the planar layer, a cathode on the planar layer, a dielectric layer on the planar layer, and an anode on the planar layer and electrically coupled to the driving TFT.
11. A display device comprising:
an array substrate comprising:
a substrate;
a first TFT on the substrate, the first TFT being a metal oxide TFT; and
a second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;
wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT; the metal oxide semiconductor layer partially covers the source electrode and the drain electrode.
12. The display device of claim 11 , wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed; the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.
13. The display device of claim 12 , wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the buffer layer of the first TFT and a second gate insulator layer formed on the first gate insulator layer of the first TFT; and the gate insulator layers of the second TFT comprises a first gate insulator layer formed on the buffer layer of the second TFT and a second gate insulator layer formed on the first gate insulator layer of the second TFT.
14. The display device of claim 13 , wherein the first gate insulator layers of the first TFT and the second TFT are made of the silicon oxide; and the second gate insulator layers of the first TFT and the second TFT are made of silicon nitride.
15. The display device of claim 11 , wherein the array substrate further comprises a planar layer covering the first TFT and the second TFT, a common electrode on the planar layer, and a pixel electrode electrically coupled to the first TFT.
16. A method for making an array substrate comprising:
forming a poly-silicon semiconductor layer on a substrate;
forming a buffer layer on the poly-silicon semiconductor layer and the substrate;
depositing a first metal layer and patterning the first metal layer to form a first gate electrode and a second gate electrode, the first gate electrode corresponding to the poly-silicon semiconductor layer;
forming a gate insulator layer covering the first gate electrode and the second gate electrode;
defining a first hole and a second hole passing through the buffer layer and the gate insulator layer to expose the poly-silicon semiconductor layer;
depositing a second metal layer on the gate insulator layer and patterning the second metal layer to form a first source electrode in the first hole and a first drain electrode in the second through hole, a second source electrode and a second drain electrode on the gate insulator layer; and
depositing a metal oxide layer on the gate insulator layer and patterning the metal oxide layer to form a metal oxide semiconductor layer coupled to the second source electrode and the second drain electrode.
17. The method of claim 16 , wherein the method further comprises forming a planar layer to cover the gate insulator layer, the metal oxide semiconductor layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.
18. The method of claim 17 , wherein the method further comprises forming an anode on the planar layer which is electrically coupled to the second drain electrode, forming a dielectric layer on the planar layer, forming an emitting material on the planar layer, and forming a cathode on the planar layer.
19. The method of claim 17 , wherein the method further comprises forming a common electrode layer on the planar layer, and forming a pixel electrode layer on the planar layer which is electrically coupled to the second drain electrode.
Priority Applications (1)
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US15/198,116 US20170084641A1 (en) | 2015-09-18 | 2016-06-30 | Array substrate and display device and method for making the array substrate |
Applications Claiming Priority (5)
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US201562220257P | 2015-09-18 | 2015-09-18 | |
US201562220259P | 2015-09-18 | 2015-09-18 | |
US201562220258P | 2015-09-18 | 2015-09-18 | |
US201562220261P | 2015-09-18 | 2015-09-18 | |
US15/198,116 US20170084641A1 (en) | 2015-09-18 | 2016-06-30 | Array substrate and display device and method for making the array substrate |
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US20170084641A1 true US20170084641A1 (en) | 2017-03-23 |
Family
ID=58283227
Family Applications (7)
Application Number | Title | Priority Date | Filing Date |
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US15/194,772 Active US9768204B2 (en) | 2015-09-18 | 2016-06-28 | Array substrate and display device and method for making the array substrate |
US15/198,116 Abandoned US20170084641A1 (en) | 2015-09-18 | 2016-06-30 | Array substrate and display device and method for making the array substrate |
US15/252,900 Active US10319752B2 (en) | 2015-09-18 | 2016-08-31 | Array substrate and method for making same |
US15/252,883 Active US10192897B2 (en) | 2015-09-18 | 2016-08-31 | Array substrate and display device and method for making the array substrate |
US15/681,254 Active US10276606B2 (en) | 2015-09-18 | 2017-08-18 | Array substrate and display device and method for making the array substrate |
US16/197,392 Active US10978498B2 (en) | 2015-09-18 | 2018-11-21 | Array substrate and display device and method for making the array substrate |
US16/393,314 Active 2036-09-05 US11289518B2 (en) | 2015-09-18 | 2019-04-24 | Array substrate and method for making same |
Family Applications Before (1)
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US15/194,772 Active US9768204B2 (en) | 2015-09-18 | 2016-06-28 | Array substrate and display device and method for making the array substrate |
Family Applications After (5)
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US15/252,900 Active US10319752B2 (en) | 2015-09-18 | 2016-08-31 | Array substrate and method for making same |
US15/252,883 Active US10192897B2 (en) | 2015-09-18 | 2016-08-31 | Array substrate and display device and method for making the array substrate |
US15/681,254 Active US10276606B2 (en) | 2015-09-18 | 2017-08-18 | Array substrate and display device and method for making the array substrate |
US16/197,392 Active US10978498B2 (en) | 2015-09-18 | 2018-11-21 | Array substrate and display device and method for making the array substrate |
US16/393,314 Active 2036-09-05 US11289518B2 (en) | 2015-09-18 | 2019-04-24 | Array substrate and method for making same |
Country Status (3)
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US (7) | US9768204B2 (en) |
CN (4) | CN106558593B (en) |
TW (4) | TWI619152B (en) |
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US20170084642A1 (en) * | 2015-09-18 | 2017-03-23 | Hon Hai Precision Industry Co., Ltd. | Array substrate and display device and method for making the array substrate |
CN107731858A (en) * | 2017-10-27 | 2018-02-23 | 京东方科技集团股份有限公司 | A kind of array base palte, its preparation method and display panel |
US20180122835A1 (en) * | 2016-11-02 | 2018-05-03 | Japan Display Inc. | Display device |
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Also Published As
Publication number | Publication date |
---|---|
US10319752B2 (en) | 2019-06-11 |
CN106558594A (en) | 2017-04-05 |
US20190109160A1 (en) | 2019-04-11 |
US20170084639A1 (en) | 2017-03-23 |
US10192897B2 (en) | 2019-01-29 |
CN106558538A (en) | 2017-04-05 |
TWI618123B (en) | 2018-03-11 |
CN106558538B (en) | 2019-09-13 |
TWI619152B (en) | 2018-03-21 |
CN106558594B (en) | 2019-09-13 |
US9768204B2 (en) | 2017-09-19 |
US20170084636A1 (en) | 2017-03-23 |
TW201714008A (en) | 2017-04-16 |
US10978498B2 (en) | 2021-04-13 |
TWI606289B (en) | 2017-11-21 |
CN106558592B (en) | 2019-06-18 |
TW201714296A (en) | 2017-04-16 |
TW201721720A (en) | 2017-06-16 |
TWI606581B (en) | 2017-11-21 |
US20190252418A1 (en) | 2019-08-15 |
TW201721721A (en) | 2017-06-16 |
CN106558592A (en) | 2017-04-05 |
CN106558593B (en) | 2019-12-17 |
US10276606B2 (en) | 2019-04-30 |
US20180006065A1 (en) | 2018-01-04 |
CN106558593A (en) | 2017-04-05 |
US20170084642A1 (en) | 2017-03-23 |
US11289518B2 (en) | 2022-03-29 |
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