TWI675460B - Memory structure and manufacturing method thereof - Google Patents

Abstract

A memory structure includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor includes a first recessed gate, a first doped region, a second doped region, and a first metal silicide layer. The first metal silicide layer is disposed on the first doped region. There is no metal silicide layer disposed directly on the second doped region. The second transistor includes a second recessed gate, a third doped region, a fourth doped region, and a second metal silicide layer. The second metal silicide layer is disposed on the fourth doped region. There is no metal silicide layer directly disposed on the third doped region. The second doped region and the third doped region are located between the first recessed gate and the second recessed gate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is directly connected to the second doped region and the third doped region.

Description

Memory structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a memory structure and a manufacturing method thereof.

Currently, a memory structure is developed, which includes a transistor and a capacitor coupled to each other. In such a memory structure, a capacitor is used as a storage component. However, how to improve the electrical performance of such memory devices is the goal of continuous efforts in the industry.

The invention provides a memory structure and a manufacturing method thereof, which can improve the electrical performance of a memory element.

The invention provides a memory structure including a substrate, a first transistor, a second transistor, and a capacitor. The first transistor includes a first recess gate, a first doped region, a second doped region, and a first metal silicide layer. A first recessed gate is disposed in the substrate. The first recessed gate is insulated from the substrate. The first doped region and the second doped region are located in a substrate on both sides of the first recessed gate. The first metal silicide layer is disposed on the first doped region. There is no metal silicide layer disposed directly on the second doped region. The second transistor is located on one side of the first transistor. The second transistor includes a second recessed gate, a third doped region, a fourth doped region, and a second metal silicide layer. A second recessed gate is disposed in the substrate. The second recessed gate is insulated from the substrate. The third doped region and the fourth doped region are located in a substrate on both sides of the second recessed gate. The second metal silicide layer is disposed on the fourth doped region. There is no metal silicide layer directly disposed on the third doped region. The second doped region and the third doped region are located between the first recessed gate and the second recessed gate. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is directly connected to the second doped region and the third doped region. The second electrode is disposed on the first electrode. An insulating layer is provided between the first electrode and the second electrode.

According to an embodiment of the present invention, in the above memory structure, the first transistor and the second transistor may be one of an N-type metal-oxide semiconductor transistor and a P-type metal-oxide semiconductor transistor, respectively, and the other One.

According to an embodiment of the present invention, in the memory structure, part of the first recessed gate and part of the second recessed gate may protrude from the base.

According to an embodiment of the present invention, in the above memory structure, the first transistor may further include a first dielectric layer. The first dielectric layer is disposed between the first recessed gate and the substrate. The second transistor may further include a second dielectric layer. The second dielectric layer is disposed between the second recessed gate and the substrate.

According to an embodiment of the present invention, in the above memory structure, the first transistor may further include a third metal silicide layer. The third metal silicide layer is disposed on the first recessed gate. The second transistor may further include a fourth metal silicide layer. A fourth metal silicide layer is disposed on the second recessed gate.

The invention provides a method for manufacturing a memory structure, which includes the following steps. Provide a substrate. A first transistor is formed. The first transistor includes a first recessed gate, a first doped region, a second doped region, and a first metal silicide layer. A first recessed gate is disposed in the substrate. The first recessed gate is insulated from the substrate. The first doped region and the second doped region are located in a substrate on both sides of the first recessed gate. The first metal silicide layer is disposed on the first doped region. There is no metal silicide layer disposed directly on the second doped region. A second transistor is formed on one side of the first transistor. The second transistor includes a second recessed gate, a third doped region, a fourth doped region, and a second metal silicide layer. A second recessed gate is disposed in the substrate. The second recessed gate is insulated from the substrate. The third doped region and the fourth doped region are located in a substrate on both sides of the second recessed gate. The second metal silicide layer is disposed on the fourth doped region. There is no metal silicide layer directly disposed on the third doped region. The second doped region and the third doped region are located between the first recessed gate and the second recessed gate. A capacitor is formed between the first transistor and the second transistor. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is directly connected to the second doped region and the third doped region. The second electrode is disposed on the first electrode. An insulating layer is provided between the first electrode and the second electrode.

According to an embodiment of the present invention, in the method for manufacturing a memory structure, the method for forming the first recessed gate and the second recessed gate may include the following steps. A first groove and a second groove are formed in the substrate. A gate material layer is formed to fill the first groove and the second groove. A patterning process is performed on the gate material layer, and a first recessed gate and a second recessed gate are formed in the first groove and the second groove, respectively.

According to an embodiment of the present invention, in the method for manufacturing a memory structure, the method for forming the first recessed gate and the second recessed gate further includes the following steps. A first dielectric layer is formed between the first recessed gate and the substrate. A second dielectric layer is formed between the second recessed gate and the substrate.

According to an embodiment of the present invention, in the method for manufacturing a memory structure, the method for forming the first metal silicide layer and the second metal silicide layer may include the following steps. A self-aligned metal silicide barrier layer is formed on the substrate. The self-aligned metal silicide blocking layer exposes the first and fourth doped regions and covers the second and third doped regions. A self-aligned metal silicide process is used to form a first metal silicide layer and a second metal silicide layer on the first doped region and the fourth doped region, respectively.

According to an embodiment of the present invention, in the method for manufacturing a memory structure, a self-aligned metal silicide process can further form a first recessed gate and a second recessed gate, respectively. The three metal silicide layer and the fourth metal silicide layer.

Based on the above, in the manufacturing method of the memory structure proposed by the present invention, since the first electrode of the capacitor is directly connected to the second doped region and the third doped region, a Schottky contact can be formed. Further, the leakage current of the capacitor can be reduced. In addition, since the first recessed gate and the second recessed gate are disposed in the substrate, the channel length of the first transistor and the second transistor can be effectively increased. In this way, the gate lengths of the first recessed gate and the second recessed gate can be further shortened, thereby reducing the size of the memory element. In addition, since the first metal silicide layer and the second metal silicide layer are respectively disposed on the first doped region and the second doped region, the contact resistance can be effectively reduced.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 100 may have a first conductivity type. Hereinafter, the first conductivity type and the second conductivity type described may be one of the P-type conductivity type and the N-type conductivity type and the other. In this embodiment, the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type, but the present invention is not limited thereto.

Then, a well region 102 may be formed in the substrate 100. The well region 102 may have a second conductivity type (eg, N-type). A method for forming the well region 102 is, for example, an ion implantation method.

Then, a groove 104 and a groove 106 may be formed in the substrate 100. The grooves 104 and the grooves 106 are formed by, for example, patterning the substrate 100 by a lithography process and an etching process.

Next, a dielectric layer 108 may be formed on the substrate 100. The material of the dielectric layer 108 is, for example, silicon oxide. A method of forming the dielectric layer 108 is, for example, a thermal oxidation method.

Furthermore, a gate material layer 110 may be formed on the dielectric layer 108 and filled with the grooves 104 and 106. The material of the gate material layer 110 is, for example, a conductive material, such as doped polycrystalline silicon. A method for forming the gate material layer 110 is, for example, a chemical vapor deposition method.

Referring to FIG. 1B, a patterning process is performed on the gate material layer 110, and a recessed gate 110a and a recessed gate 110b are formed in the grooves 104 and 106, respectively. Thereby, the recessed gate 110a and the recessed gate 110b can be formed in the substrate 100. Since the recessed gate 110a and the recessed gate 110b are disposed in the substrate 100, a recessed channel can be formed in the substrate 100, and the channel length of the transistor formed later can be effectively increased. In addition, the partially recessed gate 110 a and the partially recessed gate 110 b may protrude from the substrate 100. The patterning process of the gate material layer 110 includes a lithography process and an etching process.

Then, a portion of the dielectric layer 108 not covered by the recessed gate 110a and the recessed gate 110b may be removed, and a dielectric layer 108a is formed between the recessed gate 110a and the substrate 100, A dielectric layer 108b is formed between the recessed gate 110b and the substrate 100. A method of removing a portion of the dielectric layer 108 includes a dry etching method. The recessed gate 110a can be insulated from the substrate 100 by a dielectric layer 108a. The recessed gate 110b may be insulated from the substrate 100 by a dielectric layer 108b.

Referring to FIG. 1C, a gap wall 112 and a gap wall 114 can be formed on the sidewall of the recessed gate 110a and the sidewall of the recessed gate 110b, respectively. The partition wall 112 and the partition wall 114 may be a single-layer structure or a multi-layer structure. The material of the partition wall 112 and the partition wall 114 is, for example, silicon oxide, silicon nitride, or a combination thereof. The formation method of the spacer wall 112 and the spacer wall 114 is, for example, first forming a spacer material layer (not shown) on the sidewall of the recessed gate 110a and the recessed gate 110b, and then performing etch-back Process.

Next, a doped region 116 and a doped region 118 may be formed in the substrate 100 on both sides of the recessed gate 110a. The doped regions 116 and 118 may have a second conductivity type (eg, N-type). The method of forming the doped region 116 and the doped region 118 is, for example, an ion implantation method.

In addition, a doped region 120 and a doped region 122 may be formed in the substrate 100 on both sides of the recessed gate 110b. The doped region 120 and the doped region 122 may have a first conductivity type (for example, a P type). The doped region 120 and the doped region 122 may be located in the well region 102. The method of forming the doped region 120 and the doped region 122 is, for example, an ion implantation method.

In addition, those skilled in the art can determine the order of forming the doped region 116, the doped region 118, the doped region 120, and the doped region 122 according to the process requirements.

Next, a self-aligned metal silicide block (SAB) 124 may be formed on the substrate 100. The self-aligned metal silicide blocking layer 124 exposes the doped region 116 and the doped region 122 and covers the doped region 118 and the doped region 120. In addition, the self-aligned metal silicide blocking layer 124 can further expose the recessed gate 110a and the recessed gate 110b. The material of the self-aligned metal silicide barrier layer 124 is, for example, silicon oxide. The method for forming the self-aligned metal silicide barrier layer 124 is, for example, a combination of a deposition process, a lithography process, and an etching process.

Referring to FIG. 1D, a metal silicide layer 126 and a metal silicide layer 128 are formed on the doped region 116 and the doped region 122 respectively by a self-aligned metal silicide process, thereby effectively reducing contact resistance. In addition, through the aforementioned self-aligned metal silicide process, a metal silicide layer 130 and a metal silicide layer 132 can be formed on the recessed gate 110a and the recessed gate 110b, respectively, thereby effectively reducing contact. resistance. The material of the metal silicide layer 126, the metal silicide layer 128, the metal silicide layer 130, and the metal silicide layer 132 is, for example, cobalt silicide or nickel silicide.

In this way, the transistor 134 can be formed, and the transistor 136 can be formed on one side of the transistor 134. Although the method of forming the transistor 134 and the transistor 134 is described by taking the above method as an example, the present invention is not limited thereto.

The transistor 134 may have a second conductivity type, and the transistor 136 may have a first conductivity type. The transistor 134 and the transistor 136 may be one of the N-type metal-oxide semiconductor transistor and the P-type metal-oxide semiconductor transistor, respectively. In this embodiment, the transistor 134 is an N-type metal-oxide-semiconductor transistor, and the transistor 136 is a P-type metal-oxide semiconductor transistor. However, the present invention is not limited thereto.

The transistor 134 includes a recessed gate 110 a, a doped region 116, a doped region 118, and a metal silicide layer 126. The recessed gate 110 a is disposed in the substrate 100. The recessed gate 110 a is insulated from the substrate 100. The doped regions 116 and 118 are located in the substrate 100 on both sides of the recessed gate 110 a. A metal silicide layer 126 is disposed on the doped region 116. There is no metal silicide layer disposed directly on the doped region 118.

In addition, the transistor 134 may further include at least one of a dielectric layer 108a, a spacer 112, and a metal silicide layer 130. A dielectric layer 108 a is disposed between the recessed gate 110 a and the substrate 100. The partition wall 112 is disposed on a side wall of the recessed gate electrode 110a. The metal silicide layer 130 is disposed on the recessed gate 110a.

The transistor 136 includes a recessed gate 110b, a doped region 120, a doped region 122, and a metal silicide layer 128. The recessed gate electrode 110 b is disposed in the substrate 100. The recessed gate electrode 110 b is insulated from the substrate 100. The doped region 120 and the doped region 122 are located in the substrate 100 on both sides of the recessed gate 110b. A metal silicide layer 128 is disposed on the doped region 122. There is no metal silicide layer directly disposed on the doped region 120. In addition, the doped region 118 and the doped region 120 are located between the recessed gate 110a and the recessed gate 110b.

In addition, the transistor 136 may further include at least one of the well region 102, the dielectric layer 108b, the spacer 114, and the metal silicide layer 132. The well region 102 is located in the substrate 100, and the doped region 120 and the doped region 122 may be located in the well region 102. The dielectric layer 108 b is disposed between the recessed gate 110 b and the substrate 100. The partition wall 114 is disposed on a side wall of the recessed gate electrode 110b. The metal silicide layer 132 is disposed on the recessed gate 110b.

In this embodiment, the structures of the transistor 134 and the transistor 136 are merely examples, but the present invention is not limited thereto. Those skilled in the art can adjust the structures of the transistor 134 and the transistor 136 according to product requirements. For example, the transistor 134 and the transistor 136 may further include a lightly doped drain (LDD) (not shown), etc., which will not be described herein.

Referring to FIG. 1E, a dielectric layer 138 may be formed to cover the transistor 134 and the transistor 136. The dielectric layer 138 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 138 is, for example, silicon oxide, silicon nitride, or a combination thereof. The method for forming the dielectric layer 138 is, for example, a chemical vapor deposition method.

Next, a capacitor 140 is formed between the transistor 134 and the transistor 136. The capacitor 140 may be located in the dielectric layer 138, and a portion of the capacitor 140 may be located on the dielectric layer 138. The capacitor 140 includes an electrode 142, an electrode 144, and an insulating layer 146. The electrode 142 is directly connected to the doped region 118 and the doped region 120. The electrode 142 can be used as a lower electrode of the capacitor 140. The electrode 144 is provided on the electrode 142. The electrode 142 can be used as an upper electrode of the capacitor 140. The materials of the electrodes 142 and 144 are, for example, Ti, TiN, Ta, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y, or a combination thereof. An insulating layer 146 is provided between the electrode 142 and the electrode 144. The material of the insulating layer 146 is, for example, a high-k material, silicon oxide, silicon nitride, silicon oxide / silicon nitride / silicon oxide (ONO), or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), zirconia (ZrO ₂ ), or a combination thereof. In the capacitor 140, a metal-insulator-metal (MIM) capacitor can be formed because the insulating layer 146 is disposed between the electrode 142 and the electrode 144.

During the formation of the capacitor 140, a part of the self-aligned metal silicide blocking layer 124 is removed to expose the doped region 118 and the doped region 120. Accordingly, the electrode 142 of the capacitor 140 can be directly connected to the doped region 118 and the doped region 120. In this way, since the electrode 142 of the capacitor 140 is directly connected to the doped region 118 and the doped region 120, a Schottky contact can be formed, and the leakage current of the capacitor 140 can be reduced. The method for forming the capacitor 140 may be a method well known to those having ordinary knowledge in the technical field, and will not be described here.

Then, a dielectric layer 148 may be formed on the dielectric layer 138 to cover the capacitor 140. The material of the dielectric layer 148 is, for example, silicon oxide. A method of forming the dielectric layer 148 is, for example, a chemical vapor deposition method.

Referring to FIG. 1F, a contact window 150 and a contact window 152 may be formed in the dielectric layer 148 and the dielectric layer 138. The contact window 150 and the contact window 152 may be coupled to the doped region 116 and the doped region 122 through the metal silicide layer 126 and the metal silicide layer 128, respectively. The material of the contact window 150 and the contact window 152 is, for example, tungsten. A method of forming the contact window 150 and the contact window 152 is, for example, a damascene method.

Next, a dielectric layer 154 may be formed on the dielectric layer 148. The material of the dielectric layer 154 is, for example, silicon oxide. A method of forming the dielectric layer 154 is, for example, a chemical vapor deposition method.

Then, a conductive layer 156, a conductive layer 158, and a conductive layer 160 may be formed in the dielectric layer 154. The conductive layer 156, the conductive layer 158, and the conductive layer 160 may be coupled to the contact window 150, the contact window 152, and the electrode 144, respectively. The material of the conductive layer 156, the conductive layer 158, and the conductive layer 160 is, for example, copper. A method of forming the conductive layer 156, the conductive layer 158, and the conductive layer 160 is, for example, a damascene method.

Hereinafter, the memory structure 10 of this embodiment will be described with reference to FIG. 1F. In this embodiment, in addition, although the method for forming the memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1F, the memory structure 10 includes a substrate 100, a transistor 134, a transistor 136, and a capacitor 140. The memory structure 10 is, for example, a two-transistor static random access memory (2T SRAM), but the invention is not limited thereto. The transistor 134 includes a recessed gate 110a, a doped region 116, a doped region 118, and a metal silicide layer 126, and further includes at least one of a dielectric layer 108a, a spacer 112, and a metal silicide layer 130 . The transistor 136 is located on one side of the transistor 134. The transistor 136 includes a recessed gate 110b, a doped region 120, a doped region 122, and a metal silicide layer 128, and further includes a well region 102, a dielectric layer 108b, a spacer 114, and a metal silicide layer 132 At least one of them. The capacitor 140 is coupled between the transistor 134 and the transistor 136. The capacitor 140 includes an electrode 142, an electrode 144, and an insulating layer 146. In addition, the materials, installation methods, conductive types, formation methods, and functions of the components in the memory structure 10 have been described in detail in the above embodiments, and are not repeated here.

Based on the above embodiments, it can be known that in the above-mentioned memory structure 10 and the manufacturing method thereof, since the electrode 142 of the capacitor 140 is directly connected to the doped region 118 and the doped region 120, a Schottky contact can be formed, thereby reducing the capacitor 140 Leakage current. In addition, since the recessed gate 110a and the recessed gate 110b are disposed in the substrate 100, the channel length of the transistor 134 and the transistor 136 can be effectively increased. In this way, the gate lengths of the recessed gate 110a and the recessed gate 110b can be further shortened, thereby reducing the size of the memory element. In addition, since the metal silicide layer 126 and the metal silicide layer 128 are respectively disposed on the doped region 116 and the doped region 122, the contact resistance can be effectively reduced.

In summary, with the above memory structure and manufacturing method thereof, the leakage current of the capacitor can be reduced, the size of the memory element can be reduced, and the contact resistance can be reduced, so the electrical performance of the memory element can be improved.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Memory structure

100‧‧‧ substrate

102‧‧‧well area

104, 106‧‧‧ groove

108, 108a, 108b, 138, 148, 154‧‧‧ dielectric layers

110‧‧‧Gate material layer

110a, 110b ‧‧‧ recessed gate

112, 114‧‧‧ wall

116, 118, 120, 122‧‧‧ doped regions

124‧‧‧Self-aligned metal silicide barrier

126, 128, 130, 132‧‧‧ metal silicide layers

134, 136‧‧‧ Transistors

140‧‧‧Capacitor

142, 144‧‧‧ electrodes

146‧‧‧Insulation

150, 152‧‧‧ contact windows

156, 158, 160‧‧‧ conductor layer

1A to 1F are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the present invention.

Claims (10)

A memory structure includes: a substrate; a first transistor including: a first recess gate disposed in the substrate and insulated from the substrate; a first doped region and a second A doped region is located in the substrate on both sides of the first recessed gate; and a first metal silicide layer is disposed on the first doped region, wherein none is directly disposed on the first doped region A metal silicide layer on a second doped region; a second transistor, located on one side of the first transistor, and including: a second recessed gate, disposed in the substrate and insulated from The substrate; a third doped region and a fourth doped region located in the substrate on both sides of the second recessed gate; and a second metal silicide layer provided in the fourth On the doped region, there is no metal silicide layer directly disposed on the third doped region, and the second doped region and the third doped region are located on the first recessed gate And the second recessed gate; and a capacitor coupled between the first transistor and the second transistor And comprising: a first electrode directly connected to the second doped region and the third doped region; a second electrode provided on the first electrode; and an insulating layer provided on the first Between the electrode and the second electrode. The memory structure according to item 1 of the scope of patent application, wherein the first transistor and the second transistor are one of an N-type metal-oxide semiconductor transistor and a P-type metal-oxide semiconductor transistor, respectively. The other. The memory structure according to item 1 of the scope of the patent application, wherein part of the first recessed gate and part of the second recessed gate protrude from the base. The memory structure according to item 1 of the patent application scope, wherein the first transistor further includes a first dielectric layer, and the first dielectric layer is disposed between the first recessed gate and the first recessed gate. Between the substrates, and the second transistor further includes a second dielectric layer, wherein the second dielectric layer is disposed between the second recessed gate and the substrate. The memory structure according to item 1 of the patent application scope, wherein the first transistor further includes a third metal silicide layer, and the third metal silicide layer is disposed on the first recessed gate. The second transistor further includes a fourth metal silicide layer, wherein the fourth metal silicide layer is disposed on the second recessed gate. A method for manufacturing a memory structure includes: providing a substrate; forming a first transistor, wherein the first transistor includes: a first recess gate disposed in the substrate and insulated from the substrate; The substrate; a first doped region and a second doped region located in the substrate on both sides of the first recessed gate; and a first metal silicide layer disposed in the first On the doped region, there is no metal silicide layer directly disposed on the second doped region; a second transistor is formed on one side of the first transistor, and the second transistor includes: Two recessed gates, which are arranged in the substrate and are insulated from the substrate; a third doped region and a fourth doped region, which are located on both sides of the second recessed gate A substrate; and a second metal silicide layer disposed on the fourth doped region, wherein there is no metal silicide layer directly disposed on the third doped region, and the second doped region and The third doped region is located between the first recessed gate and the second recessed gate; And forming a capacitor coupled between the first transistor and the second transistor, wherein the capacitor includes: a first electrode directly connected to the second doped region and the third doped A region; a second electrode disposed on the first electrode; and an insulating layer disposed between the first electrode and the second electrode. The method for manufacturing a memory structure according to item 6 of the scope of patent application, wherein the method of forming the first recessed gate and the second recessed gate includes: forming a first in the substrate; A groove and a second groove; forming a gate material layer filled in the first groove and the second groove; and performing a patterning process on the gate material layer, respectively, in the first groove The first recessed gate and the second recessed gate are formed in the groove and the second groove. The method for manufacturing a memory structure according to item 7 of the scope of patent application, wherein the method of forming the first recessed gate and the second recessed gate further includes: Forming a first dielectric layer between the gate and the substrate; and forming a second dielectric layer between the second recessed gate and the substrate. The method for manufacturing a memory structure according to item 6 of the patent application, wherein the method for forming the first metal silicide layer and the second metal silicide layer includes: forming a self-aligned metal on the substrate The silicide blocking layer, wherein the self-aligned metal silicide blocking layer exposes the first doped region and the fourth doped region, and covers the second doped region and the third doped region. Region; and forming the first metal silicide layer and the second metal silicide layer on the first doped region and the fourth doped region by a self-aligned metal silicide process, respectively. The method for manufacturing a memory structure according to item 9 of the scope of the patent application, further comprising separately applying the self-aligned metal silicide process to the first recessed gate and the second recessed gate. A third metal silicide layer and a fourth metal silicide layer are formed on the electrode.