TWI725769B - Capacitor and method for manufacturing the same - Google Patents

Abstract

A capacitor and a method for manufacturing the same are provided. The capacitor includes an oxide layer pattern, a first electrode, a dielectric, and a second electrode. The oxide layer pattern is disposed on the substrate and has a capacitor opening, wherein the sidewall profile of the capacitor opening is in a wave shape. The first electrode is disposed on a sidewall and a bottom surface of the capacitor opening conformally. The dielectric is disposed in the first electrode conformally. The second electrode covers the dielectric.

Description

Capacitor manufacturing method

The present invention relates to a semiconductor element and its manufacturing method, and more particularly to a capacitor and its manufacturing method.

With the advancement of science and technology, semiconductor components are constantly developing towards a "light, thin, short, and small" type. However, as the size of semiconductor components becomes smaller and smaller, the effective surface area of the capacitor becomes smaller and smaller, resulting in a decrease in capacitance. Therefore, how to maintain a sufficiently large capacitance even when the size of the semiconductor device is reduced has become one of the problems that R&D personnel urgently want to solve.

The present invention provides a capacitor and a manufacturing method thereof, which can provide a good capacitance when the size of a semiconductor element is reduced.

The present invention provides a method for manufacturing a capacitor, which includes the following steps. A barrier layer is formed on the substrate. A photoresist pattern is formed on the barrier layer, wherein the sidewall profile of the photoresist pattern is wavy. An oxide layer is formed on the sidewall and the top surface of the photoresist pattern. The oxide layer on the top surface of the photoresist pattern is removed to form an oxide layer pattern exposing the top surface of the photoresist pattern. The photoresist pattern and the barrier layer underneath are sequentially removed to form a capacitor opening exposing the substrate, wherein the capacitor opening has a part of the sidewall profile opposite to the sidewall profile of the photoresist pattern. A first electrode, a dielectric substance and a second electrode are sequentially formed on the bottom surface and the sidewall of the capacitor opening.

In an embodiment of the present invention, the above-mentioned first electrode and the dielectric are conformally formed on the bottom surface and sidewalls of the opening of the capacitor, and the second electrode covers the dielectric.

In an embodiment of the present invention, the above-mentioned photoresist pattern is formed by a standing wave effect (standing wave effect) generated during an exposure process to form a wavy sidewall profile.

In an embodiment of the present invention, the thickness t of the aforementioned photoresist pattern satisfies the following equation 1: [Equation 1] t=n×λ, where λ is the wavelength of the exposure light used in the exposure process, and n Is a positive integer.

In an embodiment of the present invention, in the step of forming the above-mentioned photoresist pattern, after the exposure process, the photoresist pattern is not subjected to a baking process.

In an embodiment of the present invention, the above-mentioned oxide layer is formed at room temperature.

In an embodiment of the present invention, the step of forming the opening of the capacitor includes the following steps. After removing the photoresist pattern and remove the barrier layer under the photoresist pattern Previously, a dielectric layer was covered on the barrier layer, and the dielectric layer was filled in the opening defined by the oxide layer pattern and the barrier layer. A mask pattern is formed on the dielectric layer, and the mask pattern has an opening pattern exposing the dielectric layer in the opening. Remove the dielectric layer in the opening. The mask pattern and the barrier layer in the opening are sequentially removed to form the capacitor opening.

In an embodiment of the present invention, the etching selection ratio of the above-mentioned dielectric layer and oxide layer pattern is greater than 10.

In an embodiment of the present invention, the above-mentioned oxide layer pattern is undoped silicon oxide, and the dielectric layer is silicon oxide with dopants, wherein the concentration of the dopants is 1×10 ²³ /cm ³ to 1×10 ²⁷ /cm ³ .

In an embodiment of the present invention, the size of the above-mentioned opening pattern is smaller than the size of the opening defined by the oxide layer pattern and the barrier layer.

The present invention provides a capacitor including an oxide layer pattern, a first electrode, a dielectric substance, and a second electrode. The oxide layer pattern is disposed on the substrate and has a capacitor opening, wherein the sidewall profile of the capacitor opening is wavy. The first electrode is conformally arranged on the side wall and the bottom surface of the capacitor opening. The dielectric is conformally arranged on the first electrode. The second electrode covers the dielectric substance.

In an embodiment of the present invention, the above-mentioned oxide layer pattern is a ring pattern with an inner wall and an outer wall, the inner wall and the upper surface of the substrate form a capacitor opening, and the contour of the outer wall is different from the contour of the inner wall.

In an embodiment of the present invention, the aforementioned capacitor further includes a dielectric layer pattern disposed on the substrate and surrounding the oxide layer pattern.

In an embodiment of the present invention, the above-mentioned oxide layer pattern is undoped silicon oxide, and the dielectric layer pattern is silicon oxide with dopants, wherein the concentration of the dopants is 1×10 ²³ /cm ³ To 1×10 ²⁷ /cm ³ .

In an embodiment of the present invention, the aforementioned capacitor further includes a barrier layer disposed between the oxide layer pattern and the substrate.

The present invention also provides a capacitor including a barrier layer pattern, an oxide layer pattern, a first electrode, a dielectric substance, and a second electrode. The barrier layer pattern is disposed on the substrate and has a first opening. The oxide layer pattern is disposed on the barrier layer pattern and has a second opening, wherein the sidewall profile of the second opening is wavy, and the first opening and the second opening constitute a capacitor opening. The first electrode is arranged on the side wall and the bottom surface of the capacitor opening. The dielectric substance is arranged on the first electrode. The second electrode covers the dielectric substance. The sidewall profile of the second opening is different from the sidewall profile of the first opening.

Based on the foregoing, in the capacitor and its manufacturing method of the present invention, since the sidewall profile of the photoresist pattern is wavy, the capacitor opening formed in the subsequent manufacturing process has a sidewall profile opposite to the sidewall profile of the photoresist pattern. In this way, the capacitance density can be increased by increasing the capacitance surface area of the capacitance structure formed therein, so that the semiconductor device can still provide a good capacitance even when the size is reduced.

100: base

200: barrier layer

202, 222: barrier layer pattern

204: first opening

300: photoresist pattern

400: oxide layer

402, 422: oxide layer pattern

404: opening, second opening

406: Capacitor opening

500: Dielectric layer

502, 522: Dielectric pattern

600: mask pattern

602: Opening Pattern

700: first electrode

702: Dielectric

704: second electrode

1000, 2000: capacitor

110, 120: Well area

112, 122: Source

114, 124: Drain

116, 126: Gate

T1, T2: Transistor

M: memory

t: thickness

1A to 1G are schematic cross-sectional views of a method of manufacturing a capacitor according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a memory according to an embodiment of the invention.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may also be present. If an element is said to be "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" can refer to physical and/or electrical connection, and "electrical connection" or "coupling" can mean that there are other elements between two elements. "Electrical connection" as used herein may include physical connection (for example, wired connection) and physical disconnection (for example, wireless connection).

As used herein, "about", "approximately" or "substantially" includes the mentioned value and the average value within the acceptable deviation range of the specific value that can be determined by a person with ordinary knowledge in the technical field. The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximate" or "substantially" used herein can select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and not one standard deviation can be applied to all properties .

The terminology used in this article is only used to describe exemplary embodiments, not Limit this disclosure. In this case, unless otherwise explained in the context, the singular form includes the majority form.

1A to 1G are schematic cross-sectional views of a method of manufacturing a capacitor according to an embodiment of the present invention.

First, referring to FIG. 1A, a barrier layer 200 is formed on the substrate 100. In some embodiments, the substrate 100 may include a semiconductor substrate. The semiconductor substrate can be, for example, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate. The doped silicon substrate can be P-type doped, N-type doped, or a combination thereof. In some embodiments, the substrate 100 may include active devices (such as PMOS, NMOS, or CMOS), inner dielectric layers and/or contact windows, intermetal dielectric layers (IMD), conductor layers of multiple metal interconnections, and / Or interlayer window. However, in order to more clearly describe the manufacturing method of the capacitor of the present invention, these components are not shown in FIGS. 1A to 1G. In this embodiment, the barrier layer 200 may be an anti-reflection layer. For example, the material of the barrier layer 200 may be silicon nitride (SiN).

Next, a photoresist pattern 300 with a wavy sidewall profile is formed on the barrier layer 200. In this embodiment, the photoresist pattern 300 forms a wavy sidewall profile by the standing wave effect generated during the exposure process. For example, the photoresist pattern 300 is formed by the following steps. First, a photoresist material (not shown) is coated on the barrier layer 200. Then, a photomask is used to define the area to be exposed and an exposure process is performed on it. After that, a development process is performed on the exposed photoresist material to form a photoresist pattern 300. It should be noted that, in order to make the photoresist pattern 300 formed after the development process have a wavy sidewall profile, the exposed photoresist material will not be processed before the development process. An additional baking process (temperature, for example, 200° C.) is used to prevent the sidewall of the photoresist pattern 300 formed after the development process from becoming a smooth surface. In this embodiment, the thickness t of the photoresist pattern 300 satisfies the following equation 1: [Equation 1] t=n×λ, where λ is the exposure light used in the exposure process (such as I-line light source) Wavelength, and n is a positive integer. In other words, the number of waves of the wavy sidewall profile of the photoresist pattern 300 is related to the thickness t of the photoresist pattern 300 and the wavelength of the exposure light used in the exposure process. In other words, the influence of the standing wave effect can be adjusted by adjusting the thickness of the photoresist material layer. For example, the thickness of the photoresist material layer can be adjusted so that the constructive interference is greater than the destructive interference, so as to increase the wave amplitude of the sidewall profile of the formed photoresist pattern 300.

After that, referring to FIG. 1B, an oxide layer 400 is formed on the sidewall and top surface of the photoresist pattern 300. In this embodiment, the oxide layer 400 may be formed on the top surface of the barrier layer 200 and the side and top surfaces of the photoresist pattern 300. In this embodiment, the oxide layer 400 can be formed at room temperature. For example, the oxide layer 400 may be silicon dioxide (SiO ₂ ) formed at room temperature.

Then, referring to FIGS. 1B and 1C at the same time, the oxide layer 400 on the top surface of the photoresist pattern 300 is removed to form an oxide layer pattern 402 exposing the top surface of the photoresist pattern 300. In this embodiment, the contour of the outer wall of the oxide layer pattern 402 may be different from the contour of the inner wall of the oxide layer pattern 402. For example, the inner sidewall profile of the oxide layer pattern 402 may be opposite to the sidewall profile of the photoresist pattern 300, and the sidewall profile of the oxide layer pattern 402 The contour of the outer side wall can be a smooth surface. In this embodiment, the oxide layer pattern 402 may be formed on the sidewall of the photoresist pattern 300 and surround the photoresist pattern 300. That is, the oxide layer pattern 402 may be a ring pattern having an inner ring and an outer ring. In this embodiment, an etch back method can be used to remove the oxide layer 400 on the top surface of the photoresist pattern 300 to expose the top surface of the photoresist pattern 300. In this embodiment, in addition to removing the oxide layer 400 on the top surface of the photoresist pattern 300, the oxide layer 400 formed on the top surface of the barrier layer 200 can also be removed during this process.

Then, referring to FIGS. 1C to 1F at the same time, the photoresist pattern 300 and the barrier layer 200 underneath are sequentially removed to form a capacitor opening 406 exposing the substrate 100, wherein the capacitor opening 406 has the same size as the photoresist pattern 300 The part of the sidewall profile opposite the sidewall profile. In this way, the capacitance density can be increased by increasing the capacitance surface area of the capacitance structure (that is, the first electrode, the dielectric substance, and the second electrode) subsequently formed in the capacitor opening 406, so that the size of the semiconductor device can be reduced. , Can still provide good capacitance. On the other hand, since the photoresist pattern 300 is formed with a wavy sidewall profile by omitting an additional baking process, there is no need to add an additional process to form a wavy sidewall profile, and the general exposure and development process can be omitted. Baking steps.

In this embodiment, the capacitor opening 406 can be formed by the following steps. First, referring to FIGS. 1C to 1E at the same time, after removing the photoresist pattern 300 and before removing the barrier layer 200 under the photoresist pattern 300, the barrier layer 200 may be covered with a dielectric layer 500, wherein the dielectric The layer 500 may be filled in the opening 404 defined by the oxide layer pattern 402 and the barrier layer 200. Then, as shown in Figure 1E, in the dielectric A mask pattern 600 is formed on the layer 500, wherein the mask pattern 600 has an opening pattern 602 exposing the dielectric layer 500 in the opening 404. After that, as shown in FIG. 1F, the dielectric layer 500 in the opening 404 is removed to form a dielectric pattern 502. Then, the mask pattern 600 on the dielectric pattern 502 and the barrier layer 200 in the opening 404 are sequentially removed to form the capacitor opening 406.

In this embodiment, the etching selection ratio of the dielectric layer 500 and the oxide pattern 402 may be greater than 10. In this way, even after the step of removing the dielectric layer 500 in the opening 404, the oxide layer pattern 402 can still maintain a good pattern profile. In this embodiment, the oxide layer pattern 402 may be undoped silicon oxide, and the dielectric layer 500 may be silicon oxide with dopants, and the concentration of the dopants is 1×10 ²³ /cm ³ to 1×10 ²⁷ /cm ³ . In this embodiment, since the hydrogen fluoride gas (Vapor HF) has a good etching selection ratio to the highly doped silicon oxide, the hydrogen fluoride gas can be used to remove the dielectric layer 500 in the opening 404. In this embodiment, the size of the opening pattern 602 may be smaller than the size of the opening 404 defined by the oxide layer pattern 402 and the barrier layer 200. The material of the dielectric layer 500 may be, for example, borophosphosilicate glass (BPSG), but the invention is not limited thereto.

After that, referring to FIGS. 1F and 1G at the same time, a first electrode 700, a dielectric 702, and a second electrode 704 are sequentially formed on the bottom surface and sidewalls of the capacitor opening 406 to form the capacitor 1000. In this embodiment, the capacitor 1000 may be a metal-insulator-metal (MIM) capacitor. In this embodiment, the first electrode 700 and the dielectric 702 may be conformally formed on the bottom surface and sidewalls of the capacitor opening 406, and the second electrode 704 may cover the dielectric 702.

The material of the first electrode 700 may be a conductive material. The conductive material can be, for example, a metal, a metal alloy, a metal nitride, a metal silicide, or a combination thereof. In some exemplary embodiments, the metal and metal alloy may be Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof, for example. The metal nitride can be, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten silicon nitride, or a combination thereof. The metal silicide is, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide or a combination thereof. The formation method of the first electrode 700 may be, for example, ALD, CVD, PVD, or a combination thereof.

The material of the dielectric 702 may be, for example, an oxide, a nitride, an oxynitride, or a high-k material. In some exemplary embodiments, the material of the dielectric 702 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxide-silicon nitride-silicon oxide (ONO), with a dielectric constant greater than 4, greater than 7, or even High dielectric constant material greater than 10 or a combination thereof. The high dielectric constant material is, for example, a metal oxide. For example, the metal oxide may be a rare earth metal oxide, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON). ), alumina (aluminum oxide, Al ₂ O ₃ ), yttrium oxide (yttrium oxide, Y ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum alumina (lanthanum aluminum oxide, LaAlO), oxide Tantalum (tantalum oxide, Ta ₂ O ₅ ), zirconium oxide (zirconium oxide, ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO), strontium bismuth tantalum oxide (Strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT) or a combination thereof. The formation method of the dielectric 702 is, for example, ALD, CVD, or a combination thereof.

The material of the second electrode 704 may be, for example, a conductive material. The conductive material can be, for example, a metal, a metal alloy, a metal nitride, a metal silicide, or a combination thereof. In some exemplary embodiments, the metal and metal alloy may be Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof, for example. The metal nitride can be, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten silicon nitride, or a combination thereof. The metal silicide can be, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof. The formation method of the second electrode 704 may be, for example, ALD, CVD, PVD, or a combination thereof. In some embodiments, the second electrode 704 may have a multilayer structure. For example, from bottom to top (that is, from a direction close to the dielectric 702 to away from the dielectric 702), the second electrode 704 may sequentially include a titanium layer and a tungsten layer covering the dielectric 702, but The present invention is not limited to this.

Based on the above, since the sidewall profile of the photoresist pattern is wavy, the capacitor opening formed in the subsequent manufacturing process has a sidewall profile opposite to the sidewall profile of the photoresist pattern. In this way, the capacitance density can be increased by increasing the capacitance surface area of the capacitance structure formed therein, so that the semiconductor device can still provide a good capacitance even when the size is reduced.

Hereinafter, the capacitor of this embodiment will be described with reference to FIG. 1G. In addition, although the manufacturing method of the capacitor of this embodiment is described by taking the above steps as an example, the manufacturing method of the capacitor of the present invention is not limited to this.

1G, in this embodiment, the capacitor 1000 may include an oxide layer pattern 402, a first electrode 700, a dielectric 702, and a second electrode 704. Oxide layer The pattern 402 can be disposed on the substrate 100 and has a capacitor opening 406, wherein the sidewall profile of the capacitor opening 406 is wavy. The first electrode 700 may be conformally disposed on the sidewall and the bottom surface of the capacitor opening 406. The dielectric 702 may be conformally disposed on the first electrode 700. The second electrode 704 may cover the dielectric 702. In this embodiment, the oxide layer pattern 402 may be a ring pattern having an inner wall and an outer wall, wherein the inner wall and the upper surface of the substrate constitute the capacitor opening 406, and the contour of the outer wall is different from the contour of the inner wall. In this embodiment, the capacitor 1000 may further include a dielectric layer pattern 502 disposed on the substrate 100 and surrounding the oxide layer pattern 402. In this embodiment, the capacitor 1000 may further include a barrier layer pattern 202, which may be disposed between the oxide layer pattern 402 and the substrate 100 and between the dielectric layer pattern 502 and the substrate 100. That is, the capacitor 1000 may include a barrier layer pattern 202, an oxide layer pattern 402, a first electrode 700, a dielectric 702, and a second electrode 704. The barrier layer pattern 202 can be disposed on the substrate 100 and has a first opening 204. The oxide layer pattern 402 can be disposed on the barrier layer pattern 202 and has a second opening 404, wherein the sidewall profile of the second opening 404 is wavy, and the first opening 204 and the second opening 404 constitute a capacitor opening 406. The first electrode 700 may be disposed on the sidewall and the bottom surface of the capacitor opening 406. The dielectric 702 can be disposed on the first electrode 700. The second electrode 704 may cover the dielectric 702. The sidewall profile of the second opening 404 may be different from the sidewall profile of the first opening 204.

FIG. 2 is a schematic cross-sectional view of a memory according to an embodiment of the invention.

Hereinafter, the memory including the capacitor of this embodiment will be described with reference to FIG. 2. The capacitor 2000 of the memory M shown in FIG. 2 is similar to the capacitor 1000 shown in FIG. 1, the difference is only that FIG. 2 also shows the transistors T1, T2 and the conductive layer 130, so the barrier layer pattern 222, oxide layer pattern 422, and dielectric layer pattern 522 shown in FIG. 2 and the barrier layer pattern 202, oxide layer pattern 402, and dielectric layer pattern 502 shown in FIG. There are some differences, but the manufacturing process and the materials used are similar to those of the barrier layer pattern 202, oxide layer pattern 402, and dielectric layer pattern 502 shown in FIG. The material will be further elaborated.

Please refer to FIG. 2, in this embodiment, the memory M may include a capacitor 2000, transistors T1, T2, and a conductive layer 130. The transistor T1 and the transistor T2 can be formed on opposite sides of the capacitor structure formed by the first electrode 700, the dielectric 702, and the second electrode 704, respectively. The transistors T1 and T2 may include well regions 110 and 120, source electrodes 112 and 122, drain electrodes 114 and 124, and gate electrodes 116 and 126, wherein the source electrodes 112 and 122 may be electrically connected to the first electrode 700. In this embodiment, the barrier layer pattern 222 may cover the top surfaces and sidewalls of the gate electrodes 116 and 126 and part of the top surfaces of the source electrodes 112 and 122 and the drain electrodes 114 and 124. The oxide layer pattern 422 may include a first portion 402 used to define the opening of the capacitor and a second portion 403 on the sidewalls of the gate electrodes 116 and 126. The conductive layer 130 may be disposed between the transistor T1 and the transistor T2 and electrically connected to the first electrode 700. The material of the conductive layer 130 may be metal.

In this embodiment, the transistor T1 and the transistor T2 may be transistors of the same conductivity type or transistors of different conductivity types, and the present invention is not limited thereto. If the memory M is a 2T SRAM, the transistor T1 and the transistor T2 can be PMOS and NMOS, respectively, but the invention is not limited to this. The memory M can also be a DRAM, and the transistor T1 and the transistor T2 can be transistors of the same conductivity type, such as PMOS or NMOS. In the case of this embodiment, since the transistor T1 and the transistor T2 are The transistors of the same conductivity type, therefore, the source electrodes 112 and 122 can be formed together to become a common source electrode. In this way, the formation of the conductive layer 130 can be selectively omitted, but the present invention is not limited to this.

In summary, in the capacitor and its manufacturing method of the above embodiment, since the sidewall profile of the photoresist pattern is wavy, the capacitor opening formed in the subsequent manufacturing process has a sidewall profile opposite to the sidewall profile of the photoresist pattern . In this way, the capacitance density can be increased by increasing the capacitance surface area of the capacitance structure formed therein, so that the semiconductor device can still provide a good capacitance even when the size is reduced.

100: base

202: Barrier layer pattern

204: first opening

402: oxide layer pattern

404: opening

406: Capacitor opening

502: Dielectric pattern

700: first electrode

702: Dielectric

704: second electrode

1000: capacitor

Claims (10)

A method for manufacturing a capacitor includes: forming a barrier layer on a substrate; forming a photoresist pattern on the barrier layer, the sidewall profile of the photoresist pattern is wavy; on the sidewall and top surface of the photoresist pattern Forming an oxide layer; removing the oxide layer on the top surface of the photoresist pattern to form an oxide layer pattern exposing the top surface of the photoresist pattern; sequentially removing the light The barrier pattern and the barrier layer under the photoresist pattern to form a capacitor opening exposing the substrate, the capacitor opening having a portion of the sidewall profile opposite to the sidewall profile of the photoresist pattern; A first electrode, a dielectric substance, and a second electrode are sequentially formed on the bottom surface and the sidewall of the capacitor opening. The method of manufacturing a capacitor according to claim 1, wherein the first electrode and the dielectric are conformally formed on the bottom surface and the sidewall of the capacitor opening, and the second electrode covers The dielectric substance. The method for manufacturing a capacitor according to claim 1, wherein the photoresist pattern is formed by a standing wave effect generated in an exposure process to form a wavy sidewall profile. The method of manufacturing a capacitor according to claim 3, wherein the thickness t of the photoresist pattern satisfies the following equation 1: [Equation 1] t=n×λ, where λ is the wavelength of the exposure light used in the exposure process, and n is a positive integer. The method for manufacturing a capacitor according to claim 3, wherein in the step of forming the photoresist pattern, after the exposure process, the photoresist pattern is not subjected to a baking process. The method of manufacturing a capacitor according to claim 1, wherein the oxide layer is formed at room temperature. The method for manufacturing a capacitor according to claim 1, wherein the step of forming the capacitor opening includes: after removing the photoresist pattern and before removing the barrier layer under the photoresist pattern, in the step The barrier layer is covered with a dielectric layer, wherein the dielectric layer is filled in the opening defined by the oxide layer pattern and the barrier layer; a mask pattern is formed on the dielectric layer, the The mask pattern has an opening pattern exposing the dielectric layer in the opening; removing the dielectric layer in the opening; and sequentially removing the mask pattern and all in the opening The barrier layer to form the capacitor opening. The method for manufacturing a capacitor according to claim 7, wherein the etching selection ratio of the dielectric layer and the oxide layer pattern is greater than 10. The method for manufacturing a capacitor according to claim 8, wherein the oxide layer pattern is undoped silicon oxide, the dielectric layer is silicon oxide with dopants, and the concentration of the dopants is 1× 10 ²³ /cm ³ to 1×10 ²⁷ /cm ³ . The method for manufacturing a capacitor according to claim 8, wherein the size of the opening pattern is smaller than the size of the opening defined by the oxide layer pattern and the barrier layer.

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