TWI691051B - Memory structure - Google Patents

Abstract

A memory structure including a substrate, a first transistor, a second transistor, and a capacitor is provided. The substrate includes active areas. One of two adjacent active areas extends in a first direction, and the other of the two adjacent active areas extends in a second direction. The first direction intersects the second direction. The first transistor and the second transistor are respectively located in one and the other of the two adjacent active areas. The capacitor is electrically connected between the first transistor and the second transistor. The capacitor is located above a portion of the two adjacent active areas. A portion of the capacitor extends in the first direction, and another portion of the capacitor extends in the second direction.

Description

Memory structure

The invention relates to a semiconductor structure, and in particular to a memory structure.

Currently, a memory structure has been developed, which includes a transistor and a capacitor coupled to each other. In this memory structure, capacitors are used as storage components. However, how to improve the electrical performance of such memory devices is currently the goal of continuous efforts in the industry.

The present invention provides a memory structure that can improve the electrical performance of memory elements.

The invention provides a memory structure, which includes a substrate, a first transistor, a second transistor and a capacitor. The substrate includes multiple active regions. One of the two adjacent active areas extends in the first direction, and the other of the two adjacent active areas extends in the second direction. The first direction intersects the second direction. The first transistor and the second transistor are respectively located in one of the two adjacent active regions and the other. The capacitor is electrically connected between the first transistor and the second transistor. The capacitor is located above a part of two adjacent active regions. A part of the capacitor extends in the first direction, and another part of the capacitor extends in the second direction.

According to an embodiment of the invention, in the above memory structure, the top-view shape formed by the two adjacent active areas is, for example, a V-shape.

According to an embodiment of the invention, in the above memory structure, the top-view shape of each active area is, for example, a parallelogram.

According to an embodiment of the invention, in the above memory structure, the top-view shape of the capacitor is, for example, a V-shape.

According to an embodiment of the invention, in the above memory structure, the first transistor and the second transistor may be one of P-type metal oxide semiconductor transistors and N-type metal oxide semiconductor transistors and the other One.

According to an embodiment of the invention, in the above memory structure, the first transistor includes a first gate, a first doped region and a second doped region. The first gate electrode is disposed on the substrate and insulated from the substrate. The first doped region and the second doped region are located in the substrate on both sides of the first gate. The second transistor includes a second gate, a third doped region and a fourth doped region. The second gate is disposed on the substrate and is insulated from the substrate. The third doped region and the fourth doped region are located in the substrate on both sides of the second gate. The second doped region and the third doped region are located between the first gate and the second gate. The capacitor includes a first electrode, a second electrode and an insulating layer. The first electrode is electrically connected to the second doped region and the third doped region. The second electrode is provided on the first electrode. The insulating layer is provided between the first electrode and the second electrode.

According to an embodiment of the invention, in the above memory structure, the first gate and the second gate may extend in the third direction. The third direction and the first direction may be non-orthogonal, and the third direction and the second direction may be non-orthogonal.

According to an embodiment of the invention, in the above memory structure, the capacitor may extend above at least one of the first gate and the second gate.

According to an embodiment of the invention, the memory structure may further include a termination layer. The termination layer is disposed between the first electrode and the first gate and between the first electrode and the second gate.

According to an embodiment of the invention, in the above memory structure, the top of the second electrode may be higher than the top of the first electrode.

Based on the above, in the memory structure proposed by the present invention, the capacitor is located above a part of two adjacent active regions, a part of the capacitor extends in the first direction, and another part of the capacitor extends in the second direction. In this way, the capacitor can have a larger circumference, thereby increasing the area of the capacitor, which in turn can increase the capacitance of the capacitor. Therefore, the memory structure can have better data storage capacity, which can further improve the electrical performance of the memory device.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

FIG. 1 is a top view of a memory structure according to an embodiment of the invention. FIG. 2 is a cross-sectional view of the memory structure taken along the line I-I' in FIG. 1. FIG. In FIG. 1, some components in FIG. 2 are omitted to clearly explain the positional relationship between the components in FIG. 1.

1 and 2, the memory structure 100 includes a substrate 102, a transistor 104, a transistor 106 and a capacitor 108, and may further include an isolation structure 110. The memory structure 100 is, for example, a two-transistor static random access memory (two-transistor static random access memory, 2T SRAM), but the invention is not limited thereto.

The substrate 102 may be a semiconductor substrate, such as a silicon substrate. The isolation structure 110 is located in the substrate 102 and can be used to define the active area AA. The isolation structure 110 is, for example, a shallow trench isolation (STI). The material of the isolation structure 110 is, for example, silicon oxide.

The substrate 102 includes a plurality of active areas AA. One of the two adjacent active areas AA extends in the first direction D1, and the other of the two adjacent active areas AA extends in the second direction D2. The first direction D1 intersects the second direction D2. The top-view shape formed by two adjacent active areas AA is, for example, a V shape. The top-view shape of each active area AA is, for example, a parallelogram.

Hereinafter, the first conductivity type and the second conductivity type described may be one of the P-type conductivity type and the N-type conductivity type and the other. In this embodiment, the first conductivity type is the P-type conductivity type, and the second conductivity type is the N-type conductivity type, but the invention is not limited thereto. In another embodiment, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

The transistor 104 and the transistor 106 are respectively located in one of the two adjacent active areas AA and the other. The transistor 104 and the transistor 106 may be one or the other of a P-type metal oxide semiconductor transistor and an N-type metal oxide semiconductor transistor, respectively. In this embodiment, the transistor 104 may have a first conductivity type (P type), and the transistor 106 may have a second conductivity type (N type). That is, the transistor 104 is exemplified by a P-type metal oxide semiconductor transistor, and the transistor 106 is exemplified by an N-type metal oxide semiconductor transistor, but the invention is not limited thereto.

The transistor 104 includes a gate 112, a doped region 114 and a doped region 116. The gate 112 is disposed on the substrate 102 and insulated from the substrate 102. The material of the gate 112 is, for example, doped polysilicon. The doped region 114 and the doped region 116 are located in the substrate 102 on both sides of the gate 112. The doped region 114 and the doped region 116 can be used as a source or a drain, respectively. The doped region 114 and the doped region 116 may have a first conductivity type (eg, P type).

In addition, the transistor 104 may further include a well region 118, a dielectric layer 120, a spacer 122, a lightly doped drain (LDD) 124, a lightly doped drain 126, a metal silicide layer 128, and a metal silicide At least one of the object layer 130 and the metal silicide layer 132. The well area 118 is located in the substrate 102. The well region 118 may have a second conductivity type (eg, N type). In addition, the doped region 114 and the doped region 116 may be located in the well region 118. The dielectric layer 120 is disposed between the gate 112 and the substrate 102, whereby the gate 112 and the substrate 102 can be insulated from each other. The material of the dielectric layer 120 is, for example, silicon oxide. The spacer 122 is provided on the side wall of the gate 112. The spacer 122 may be a single-layer structure or a multi-layer structure. The material of the spacer 122 is, for example, silicon oxide, silicon nitride, or a combination thereof.

The lightly doped drain 124 is located in the substrate 102 between the gate 112 and the doped region 114. The lightly doped drain 126 is located in the substrate 102 between the gate 112 and the doped region 116. In addition, the lightly doped drain 124 and the lightly doped drain 126 may be located in the well region 118. The lightly doped drain 124 and the lightly doped drain 126 may have a first conductivity type (eg, P type). In some embodiments, "lightly doped drain (LDD)" may also be referred to as "source/drain extension (SDE)").

The metal silicide layer 128 is provided on the gate 112. The metal silicide layer 130 is disposed on the doped region 114. The metal silicide layer 132 is disposed on the doped region 116. The materials of the metal silicide layer 128, the metal silicide layer 130 and the metal silicide layer 132 are, for example, nickel silicide or cobalt silicide.

The transistor 106 includes a gate 134, a doped region 136 and a doped region 138. The gate electrode 134 is disposed on the substrate 102 and is insulated from the substrate 102. The material of the gate electrode 134 is, for example, doped polysilicon. The doped regions 136 and the doped regions 138 are located in the substrate 102 on both sides of the gate 134. The doped region 136 and the doped region 138 may serve as a source or a drain, respectively. The doped region 136 and the doped region 138 may have a second conductivity type (eg, N type). In addition, the doped region 116 and the doped region 136 are located between the gate 112 and the gate 134.

In addition, the transistor 106 may further include a well region 140, a dielectric layer 142, a spacer 144, a lightly doped drain (LDD) 146, a lightly doped drain 148, a metal silicide layer 150, and a metal silicide At least one of the object layer 152 and the metal silicide layer 154. The well area 140 is located in the substrate 102. The well region 140 may have a first conductivity type (eg, P type). In addition, the doped region 136 and the doped region 138 may be located in the well region 140. The dielectric layer 142 is disposed between the gate 134 and the substrate 102, whereby the gate 134 and the substrate 102 can be insulated from each other. The material of the dielectric layer 142 is, for example, silicon oxide. The spacer 144 is provided on the side wall of the gate electrode 134. The spacer 144 may be a single-layer structure or a multi-layer structure. The material of the spacer 144 is, for example, silicon oxide, silicon nitride, or a combination thereof.

The lightly doped drain 146 is located in the substrate 102 between the gate 134 and the doped region 136. The lightly doped drain 148 is located in the substrate 102 between the gate 134 and the doped region 138. In addition, the lightly doped drain 146 and the lightly doped drain 148 may be located in the well region 140. The lightly doped drain 146 and the lightly doped drain 148 may have a second conductivity type (eg, N type).

The metal silicide layer 150 is provided on the gate 134. The metal silicide layer 152 is disposed on the doped region 136. The metal silicide layer 154 is disposed on the doped region 138. The materials of the metal silicide layer 150, the metal silicide layer 152 and the metal silicide layer 154 are, for example, nickel silicide or cobalt silicide.

In addition, the gate electrode 112 and the gate electrode 134 may extend in the third direction D3. The third direction D3 and the first direction D1 may be non-orthogonal, and the third direction D3 and the second direction D2 may be non-orthogonal. In this way, the channel length L1 under the gate 112 of the transistor 104 and the channel length L2 under the gate 134 of the transistor 106 can be increased (FIG. 1), thus preventing the short channel effect (short channel effect) and Reduce the leakage current. In this embodiment, the portion where the active area AA overlaps the gate 112 may be a parallelogram, and the portion where the active area AA overlaps the gate 134 may be a parallelogram, but the invention is not limited thereto.

The capacitor 108 is electrically connected between the transistor 104 and the transistor 106. The capacitor 108 is located above a part of the two adjacent active areas AA. A part of the capacitor 108 extends in the first direction D1, and another part of the capacitor 108 extends in the second direction D2. In this way, the capacitor 108 may have a larger circumference, thereby increasing the area of the capacitor 108, and thereby increasing the capacitance of the capacitor 108. The top-view shape of the capacitor 108 is, for example, V-shaped.

The capacitor 108 includes an electrode 156, an electrode 158 and an insulating layer 160. The electrode 156 is electrically connected to the doped region 116 and the doped region 136. In this embodiment, the electrode 156 may be electrically connected to the doped region 116 and the doped region 136 via the metal silicide layer 132 and the metal silicide layer 152, but the invention is not limited thereto. The electrode 158 is provided on the electrode 156. The top of electrode 158 may be higher than the top of electrode 156. The materials of the electrode 156 and the electrode 158 are, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y, W, Pt, or a combination thereof. The insulating layer 160 is provided between the electrode 156 and the electrode 158. The material of the insulating layer 160 is, for example, a high-k material, silicon oxide, silicon nitride, silicon oxide/silicon nitride/oxide (ONO), or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), or a combination thereof. In the capacitor 108, since the insulating layer 160 is provided between the electrode 156 and the electrode 158, a metal-insulator-metal (MIM) capacitor can be formed.

In addition, the memory structure 100 may further include a termination layer 162, a conductor layer 164, a dielectric layer 166, a contact window 168, a barrier layer 170, a contact window 172, a barrier layer 174, a conductor layer 176, a barrier layer 178, a conductor At least one of layer 180, barrier layer 182, conductor layer 184, and barrier layer 186.

The termination layer 162 is provided between the electrode 156 and the gate 112 and between the electrode 156 and the gate 134. The stop layer 162 can be used as an etch stop layer. In this embodiment, the termination layer 162 may be disposed on the metal silicide layer 128, the spacer 122, the metal silicide layer 150, the spacer 144, part of the metal silicide layer 130 and part of the metal silicide layer 132, part of the metal silicide The layer 152 and a portion of the metal silicide layer 154, but the invention is not limited thereto. The material of the termination layer 162 is, for example, silicon nitride.

The conductor layer 164 is electrically connected to the electrode 158. The material of the conductor layer 164 is, for example, tungsten. The dielectric layer 166 is disposed on the termination layer 162. The dielectric layer 166 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 166 is, for example, silicon oxide, silicon nitride, or a combination thereof.

The contact window 168 is electrically connected to the doped region 114. The barrier layer 170 may be disposed between the contact window 168 and the metal silicide layer 130. The contact window 172 is electrically connected to the doped region 138. The barrier layer 174 may be disposed between the contact window 172 and the metal silicide layer 154. The material of the contact window 168 and the contact window 172 is, for example, tungsten. The materials of the barrier layer 170 and the barrier layer 174 are, for example, Ti, TiN, Ta, TaN, or a combination thereof.

The conductor layer 176 is electrically connected to the contact window 168. The barrier layer 178 is disposed between the conductor layer 176 and the contact window 168. The conductor layer 180 is electrically connected to the contact window 172. The barrier layer 182 is disposed between the conductor layer 180 and the contact window 172. The conductor layer 184 is electrically connected to the conductor layer 164. The barrier layer 186 is provided between the conductor layer 184 and the conductor layer 164. The materials of the conductor layer 176, the conductor layer 180, and the conductor layer 184 are, for example, copper, aluminum, tungsten, or a combination thereof. The materials of the barrier layer 178, the barrier layer 182, and the barrier layer 186 are, for example, Ti, TiN, Ta, TaN, or a combination thereof.

Based on the above embodiment, it can be seen that in the memory structure 100, the capacitor 108 is located above a portion of the two adjacent active areas AA, a portion of the capacitor 108 extends in the first direction D1, and another portion of the capacitor 108 in the second direction D2 extends. In this way, the capacitor 108 may have a larger circumference, thereby increasing the area of the capacitor 108, and thereby increasing the capacitance of the capacitor 108. Therefore, the memory structure 100 can have better data storage capability, and thus can improve the electrical performance of the memory device.

3 is a top view of a memory structure according to another embodiment of the invention. 4 is a cross-sectional view of the memory structure taken along the line II-II' in FIG. 3. Some components in FIG. 4 are omitted in FIG. 3 to clearly explain the positional relationship between the components in FIG. 3.

Please refer to FIGS. 1 to 4, the differences between the memory structure 200 in FIGS. 3 and 4 and the memory structure 100 in FIGS. 1 and 2 are as follows. In the memory structure 200, the capacitor 208 may extend above at least one of the gate 112 and the gate 134 to increase the size of the capacitor 208, thereby further increasing the capacitance of the capacitor 208. For example, the electrode 256 of the capacitor 208 may extend above at least one of the gate 112 and the gate 134. In this embodiment, the example in which the capacitor 208 extends simultaneously above the gate 112 and the gate 134 is used as an example for description, but the invention is not limited thereto. As long as at least one of the electrode 256, the electrode 258, and the insulating layer 260 in the capacitor 208 extends above at least one of the gate 112 and the gate 134, it falls within the scope of the present invention.

In addition, the termination layer 162 may be disposed between the electrode 256 and the gate 112 and between the electrode 256 and the gate 134, thereby suppressing the coupling phenomenon between the electrode 256 and the gate 112 and between the electrode 256 and the gate 134 Coupling phenomenon.

In addition, in the memory structure 200 and the memory structure 100, the same or similar components are denoted by the same or similar symbols and their descriptions are omitted.

Based on the above embodiment, it can be seen that in the memory structure 200, since the capacitor 208 can extend above at least one of the gate 112 and the gate 134, the size of the capacitor 208 can be increased to further increase the capacity of the capacitor 208 capacitance. In this way, the data storage capability and electrical performance of the memory structure 200 can be further improved.

In summary, in the memory structure of the above embodiment, the capacitor is located above a part of the two adjacent active regions, a part of the capacitor extends in the first direction, and another part of the capacitor extends in the second direction. In this way, the capacitor can have a larger circumference, thereby increasing the area of the capacitor, which in turn can increase the capacitance of the capacitor. Therefore, the memory structure can have better data storage capacity, which can further improve the electrical performance of the memory device.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 200: memory structure

102: base

104, 106: transistor

108, 208: capacitor

110: isolation structure

112, 134: Gate

114, 116, 136, 138: doped regions

118, 140: Well area

120, 142, 166: dielectric layer

122, 144: gap wall

124, 126, 146, 148: lightly doped drain

128, 130, 132, 150, 152, 154: metal silicide layer

156, 158, 256, 258: electrode

160, 260: insulating layer

162: Termination layer

164, 176, 180, 184: conductor layer

168, 172: contact window

170, 174, 178, 182, 186: barrier layer

D1: First direction

D2: Second direction

D3: Third direction

FIG. 1 is a top view of a memory structure according to an embodiment of the invention. FIG. 2 is a cross-sectional view of the memory structure taken along the line I-I' in FIG. 1. FIG. 3 is a top view of a memory structure according to another embodiment of the invention. 4 is a cross-sectional view of the memory structure taken along the line II-II' in FIG. 3.

100: memory structure

102: base

104, 106: transistor

108: capacitor

110: isolation structure

112, 134: Gate

D1: First direction

D2: Second direction

D3: Third direction

Claims (8)

A memory structure includes: a base, including a plurality of active regions, wherein one of two adjacent active regions extends in a first direction, and the other of the two adjacent active regions is in a second direction Extending upward, and the first direction intersects the second direction, and the top-view shape formed by the two adjacent active regions includes a V-shape; the first transistor and the second transistor are respectively located in the One of the two adjacent active regions and the other; and a capacitor electrically connected between the first transistor and the second transistor, wherein the capacitor is located in the two adjacent regions Above a part of each active region, a part of the capacitor extends in the first direction and another part of the capacitor extends in the second direction, and the top-view shape of the capacitor includes a V-shape. The memory structure as described in item 1 of the patent application scope, wherein the top-view shape of each active area includes a parallelogram. The memory structure as described in item 1 of the patent application range, wherein the first transistor and the second transistor are one of a P-type metal oxide semiconductor transistor and an N-type metal oxide semiconductor transistor, respectively. The other. The memory structure according to item 1 of the patent application scope, wherein the first transistor includes: a first gate electrode, which is disposed on the substrate and is insulated from the substrate; and The first doped region and the second doped region are located in the substrate on both sides of the first gate, and the second transistor includes: a second gate, which is disposed on the substrate, And insulated from the substrate; and a third doped region and a fourth doped region, located in the substrate on both sides of the second gate, wherein the second doped region and the third The doped region is located between the first gate and the second gate, and the capacitor includes: a first electrode electrically connected to the second doped region and the third doped region The second electrode is provided on the first electrode; and the insulating layer is provided between the first electrode and the second electrode. The memory structure as described in item 4 of the patent application range, wherein the first gate and the second gate extend in a third direction, and the third direction is non-orthogonal to the first direction, and The third direction is non-orthogonal to the second direction. The memory structure as recited in item 4 of the patent application range, wherein the capacitor extends above at least one of the first gate and the second gate. The memory structure as described in item 4 of the patent application scope further includes: a termination layer disposed between the first electrode and the first gate and between the first electrode and the second gate between. The memory structure according to item 4 of the patent application scope, wherein the top of the second electrode is higher than the top of the first electrode.

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