TWI703735B - Semiconductor substrate, array substrate, inverter circuit, and switch circuit - Google Patents

Abstract

The present disclosure provides a semiconductor substrate including a substrate, a first thin film transistor and a second thin film transistor disposed on the substrate. The first thin film transistor is a metal oxide thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor; the first thin film transistor includes a first source and a first drain, and the second thin film transistor includes a second source and a second drain. One of the first source or the first drain is electrically connected to one of the second source or the second drain. The semiconductor substrate of the present disclosure includes a metal oxide thin film transistor, and the metal oxide thin film transistor share a same source/drain with the low temperature polycrystalline silicon thin film transistor, which can reduce the volume and leakage current of the electronic component using the semiconductor substrate.

Description

Semiconductor substrate, array substrate, inverter circuit and switching circuit

The invention relates to a semiconductor substrate, an array substrate, an inverter circuit and a switch circuit.

Flat display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used. The conventional flat display device mainly includes a liquid crystal display (LCD) and an organic electroluminescence device (OELD), also known as an organic light emitting diode (OLED). Generally speaking, the array substrate of a display includes a substrate on which a pixel array including a plurality of pixel units and a driving circuit for driving the pixel array are arranged. The driving circuit needs to be applied to a thin film transistor. In addition, the peripheral circuits of display devices are also applied to thin film transistors. The electron mobility of polysilicon thin film transistors manufactured by low temperature polysilicon technology (LTPS) is greater than that of metal oxide thin film transistors. However, the leakage current of polysilicon thin film transistors is higher than that of metal oxide thin film transistors. Affect the performance of the array substrate or peripheral circuits.

In view of this, it is necessary to provide a semiconductor substrate with good performance.

A semiconductor substrate includes a substrate, a first thin film transistor and a second thin film transistor disposed on the substrate, the first thin film transistor is a bottom gate type metal oxide thin film transistor, The second thin film transistor is a top gate type low-temperature polysilicon thin film transistor; the first thin film transistor includes a first gate provided on the substrate, a metal oxide semiconductor layer, and a metal oxide semiconductor layer connected to the metal oxide semiconductor layer. A first source and a first drain are spaced apart from each other; the second thin film transistor includes a polysilicon semiconductor layer, a second gate, and a second source connected to the polysilicon semiconductor layer and spaced apart from each other, which are sequentially arranged on the substrate And the second drain; one of the first source or the first drain is electrically connected to one of the second source or the second drain.

The present invention also provides an array substrate, an inverter circuit and a switch circuit, which include the above-mentioned semiconductor substrate.

Compared with the prior art, the semiconductor substrate of the present invention includes a metal oxide thin film transistor, and the metal oxide thin film transistor and the low temperature polysilicon thin film transistor share the source/drain, which can reduce the volume of electronic components using the semiconductor substrate And leakage current.

10: Semiconductor substrate

101: substrate

T1: The first thin film transistor

T2: The second thin film transistor

103: buffer layer

105: first gate

205: second gate

107: Gate insulation layer

1071: first gate insulating layer

1072: second gate insulating layer

109: First Source

111: The first drain

113: metal oxide semiconductor layer

201: polysilicon semiconductor layer

209: second source

211: The second drain

115: first via

215: second via

100: Array substrate

11: Substrate

12: The first drive circuit

13: The second drive circuit

14: Pixel unit

15: Pixel drive circuit

16: Flattening layer

17: third via

18: anode

19: Pixel limit layer

30: Inverter circuit

40: switch circuit

FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor substrate according to a first embodiment of the present invention.

2 is a schematic diagram of a cross-sectional structure of a semiconductor substrate according to a second embodiment of the present invention.

3 is a schematic diagram of a cross-sectional structure of a semiconductor substrate according to a third embodiment of the present invention.

4 is a schematic plan view of an array substrate to which an embodiment of the invention is applied.

FIG. 5 is an equivalent circuit diagram of a pixel driving circuit in a pixel unit according to an embodiment of the present invention.

6 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.

Fig. 7 is an equivalent circuit diagram of an inverter circuit according to an embodiment of the present invention.

Fig. 8 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.

Fig. 9 is an equivalent circuit diagram of a switch circuit according to an embodiment of the present invention.

Please refer to FIG. 1, which is a schematic cross-sectional structure diagram of a semiconductor substrate 10 according to a first embodiment of the present invention. The semiconductor substrate 10 includes a composite transistor structure of at least two different types of thin film transistors (Thin Film Transistor, TFT). In this embodiment, the two different types of thin film transistors are low temperature polysilicon (Low Temperature Poly Silicon). , LTPS) thin film transistors and metal oxide (Metal Oxide) thin film transistors. The low-temperature polysilicon thin film transistor has the characteristics of high electron mobility, and the metal oxide (Metal Oxide) thin film transistor has the characteristics of low leakage current and small volume.

As shown in FIG. 1, in this embodiment, the semiconductor substrate 10 includes a substrate 101 and a first thin film transistor T1 and a second thin film transistor T2 formed on the substrate 101. In this embodiment, the first thin film transistor T1 is a metal oxide thin film transistor, and the second thin film transistor T2 is a low temperature polysilicon thin film transistor.

The first thin film transistor T1 is a bottom-gate type thin film transistor, which includes a buffer layer 103, a first gate electrode 105, a gate insulating layer 107, a first source electrode 109, and a first drain electrode 111 And the metal oxide semiconductor layer 113. The buffer layer 103, the first gate 105, and the gate insulating layer 107 are sequentially disposed on the substrate 101. The gate insulating layer 107 is affected by the thickness of the first gate 105, so as to correspond to the first gate 105 to have a convex shape. The first source electrode 109 and the first drain electrode 111 are separately arranged in the same layer, and are respectively arranged on two opposite sides of the boss of the gate insulating layer 107. The metal oxide semiconductor layer 113 is disposed on the gate insulating layer 107 between the first source electrode 109 and the first drain electrode 111 corresponding to the first gate electrode 105, and partially covers the first source electrode 109 and the first drain electrode 111, respectively. The first drain 111. The metal oxide semiconductor layer 113 is electrically connected to the first source 109 and the first drain 111. In this embodiment, the metal oxide semiconductor layer 113 is Indium Gallium Zinc Oxide (IGZO). In other embodiments, the metal oxide semiconductor layer 113 may be a metal oxide material containing at least one of zinc, indium, and gallium.

The second thin film transistor T2 is located beside the first thin film transistor T1. It is a top-gate type thin film transistor, which includes a poly-silicon (Poly-silicon) semiconductor layer 201 and the buffer The punching layer 103, the second gate 205, the gate insulating layer 107, the second source 209 and the second drain 211. The polysilicon semiconductor layer 201, the buffer layer 103, the second gate 205, and the gate insulating layer 107 are sequentially stacked on the substrate 101 from bottom to top, and the second gate 205 corresponds to the polysilicon semiconductor layer 201 Set up. The second source 209 is electrically connected to the polysilicon semiconductor layer 201 through a second via 215 that penetrates the buffer layer 103 and the gate insulating layer 107, and the second drain 211 penetrates the buffer layer 103 and the gate insulating layer The second via 215 of 107 is electrically connected to the polysilicon semiconductor layer 201.

In this embodiment, the material of the buffer layers 103 and 103 is an insulating material, such as silicon oxide and silicon nitride. The gate insulating layer 107 includes a first gate insulating layer 1071 and a second gate insulating layer 1072 stacked in a direction away from the substrate 101, that is, the first gate insulating layer 1071 is relatively closer to the substrate 101. The material of the first gate insulating layer 1071, 1071 is silicon oxide, and the material of the second gate insulating layer 1072, 1072 is silicon nitride.

One of the first source 109 or the first drain 111 is electrically connected to one of the second source 209 or the second drain 211. As shown in FIG. 1, in this embodiment, the first drain electrode 111 and the second source electrode 209 are arranged in the same layer and directly connected. In this embodiment, the first source 109, the first drain 111, the second source 209, and the second drain 211 are formed by patterning the same conductive layer, and the first drain 111 and the second drain 111 The two source electrodes 209 are a continuous conductive layer.

In this embodiment, the metal oxide semiconductor layer 113 of the first thin film transistor T1 is formed after the first source 109 and the first drain 111 are formed, so as to avoid the high temperature hydrogenation of the second thin film transistor T2 Damage to the metal oxide semiconductor 113 during the manufacturing process, and the metal oxide semiconductor layer 113 is formed after the first source 109 and the first drain 111 are formed, which can avoid etching the first source 109 and the first drain. The metal layer where the electrode 111 is located damages the metal oxide semiconductor layer 113.

In this embodiment, the first gate 105 and the second gate 205 are located on the same layer, and the first gate 105 and the second gate 205 can be formed from the same conductive layer in the same manufacturing process.

For ease of description, in the following embodiments, elements with the same structure and function as the first embodiment will not be repeated here, and the component symbols in the first embodiment will be used.

Please refer to FIG. 2, which is a schematic cross-sectional structure diagram of a semiconductor substrate 10 according to a second embodiment of the present invention. The structure of the semiconductor substrate 10 of this embodiment is similar to the structure of the semiconductor substrate 10 of the first embodiment. The difference is that: in this embodiment, the second gate insulating layer 1072 of the first thin film transistor T1 corresponds to The metal oxide semiconductor layer 113 is provided with a first via hole 115 passing through the thickness direction thereof to expose the first gate insulating layer 1071. The metal oxide semiconductor layer 113 directly contacts the first gate insulating layer 1071 through the first via 115 and partially covers the first source 109 and the first drain 111.

In this embodiment, since the second gate insulating layer 1072 is provided with a first via 115 passing through its thickness direction, the gate between the first source 109, the first drain 111 and the first gate 105 The thickness of the electrode insulating layer 107 is reduced, which reduces the capacitance between the first source electrode 109, the first drain electrode 111 and the first gate electrode 105.

Please refer to FIG. 3, which is a schematic cross-sectional structure diagram of a semiconductor substrate 10 according to a third embodiment of the present invention. For the sake of brevity, in this embodiment, elements with the same structure and function as the first embodiment will not be repeated here.

In this embodiment, the gate insulating layer 107 includes a first gate insulating layer 1071 and a second gate insulating layer 1072 that are vertically stacked in a direction away from the substrate 101. The buffer layer 103, the second gate 205, the first gate insulation layer 1071, the first gate 105, and the second gate insulation layer 1072 are sequentially disposed on the substrate 101. The second gate electrode 205 is located on the side of the first gate insulating layer 1071 away from the second gate insulating layer 1072, and the first gate electrode 105 is located on the first gate insulating layer 1071 and the second gate insulating layer 1072 between.

In this embodiment, the material of the first gate insulating layer 1071, 1071 is silicon nitride, and the material of the second gate insulating layer 1072, 1072 is silicon oxide.

In this embodiment, the first gate electrode 105 is separated from the first source electrode 109 and the first drain electrode 111 by a second gate insulating layer 1072, and the first gate electrode 105 is separated from the first source electrode 109 There is no first gate insulating layer 1071 between the first drain electrode 111, so that the thickness of the gate insulating layer 107 between the first source electrode 109, the first drain electrode 111 and the first gate electrode 105 is reduced It is small, reducing the capacitance between the first source 109, the first drain 111 and the first gate 105.

In this embodiment, the first gate 105 and the second gate 205 are located on different layers, and the first gate 105 and the second gate 205 are formed of different conductive layers.

The semiconductor substrate 10 of the first to third embodiments described above can be applied to a pixel drive circuit in a pixel unit of an array substrate in an electronic device, and can also be applied to an inverter circuit or a switch circuit in a peripheral circuit of an electronic device. Hereinafter, only the application of the semiconductor substrate 10 of the third embodiment is used for description. It is understandable that the semiconductor substrate 10 of the third embodiment applied in the following embodiments can also be replaced with the semiconductor substrate 10 of the first embodiment or the second embodiment. The semiconductor substrate 10 of the embodiment.

Please refer to FIG. 4, which is a schematic plan view of an array substrate 100 to which an embodiment of the present invention is applied. The array substrate 100 of an embodiment of the present invention is an organic electroluminescence (OLED) display panel. The array substrate 100 includes a substrate 11 on which a plurality of scan lines S1-Sn and a plurality of scan lines S1-Sn arranged in parallel are arranged. The data lines D1-Dn are arranged parallel to each other and cross the scan lines S1-Sn. The scan lines S1-Sn are electrically connected to the first driving circuit 12, and the data lines D1-Dn are electrically connected to the second driving circuit 13 respectively. The plurality of scan lines S1-Sn and the plurality of data lines D1-Dn intersect vertically and in an insulated manner, defining a plurality of pixel units 14. Each pixel unit 14 has a corresponding pixel driving circuit 15 (as shown in FIG. 5). In this embodiment, the first driving circuit 12 may include a multiplexing circuit and a gate driving circuit. The second driving circuit 13 is a data driving circuit.

Please refer to FIG. 5, which is an equivalent circuit diagram of the pixel driving circuit 15 in the pixel unit 14 according to an embodiment of the present invention. Including power line VDD, initial terminal Vini, first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, first node A, second node B, Organic light emitting diode OLED, storage capacitor Cs, parasitic capacitor COLED and ground terminal Vss. In this embodiment, the first thin film transistor T1 is a low temperature polysilicon thin film transistor, the second thin film transistor T2 is a metal oxide thin film transistor, and the third thin film transistor T3 and the fourth thin film transistor T4 can be Any of low-temperature polysilicon thin film transistors, amorphous silicon thin film transistors or organic thin film transistors. In this embodiment, the third thin film transistor T3 and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors.

The gate of the third thin film transistor T3 is electrically connected to the first scan line S1, the drain is electrically connected to the data line D1, and the source is electrically connected to the first node A and the first thin film transistor T1. The gate electrode is electrically connected. The drain of the first thin film transistor T1 is electrically connected to the source of the second thin film transistor T2, and the source of the first thin film transistor T1 is connected to the organic light emitting diode OLED through the second node B The anode (Anode) is electrically connected. The gate of the second thin film transistor T2 is electrically connected to the third scan line S3, and the drain of the second thin film transistor T2 is electrically connected to the power line VDD. The gate of the fourth thin film transistor T4 is electrically connected to the second scan line S2, and the drain of the fourth thin film transistor T4 is electrically connected to the second node B. The anode of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode is electrically connected to the ground terminal Vss. The storage capacitor Cs is electrically connected between the gate and the source of the first thin film transistor T1. The parasitic capacitor COLED is electrically connected between the cathode and the anode of the organic light emitting diode OLED.

It can be understood that the pixel unit 14 is not limited to the structure shown in FIG. 5, and may also be a 5T1C pixel structure (including 5 Thin Film Transistors (TFT) and a capacitor C) (not shown in the figure) ) And so on, as long as it is applicable to one of the first source 109 or the first drain 111 of the first thin film transistor T1 and the second source 209 or the second drain 211 of the second thin film transistor T2 One is the structure of electrical connection.

Please refer to FIG. 6, which is a schematic cross-sectional view of an array substrate 100 according to an embodiment of the present invention. For the convenience of description, the first thin film transistor T1 and the second thin film transistor T2 are shown in FIG. 6, and the first thin film transistor is omitted. Three thin film transistors T3, fourth thin film transistors T4 and other components. The array substrate 100 in this embodiment uses the semiconductor substrate 10 of the aforementioned third embodiment. For the sake of brevity, the structure of the first thin film transistor T1 and the second thin film transistor T2 will not be repeated.

As shown in FIG. 6, the array substrate 100 further includes a planarization layer 16 covering the first thin film transistor T1 and the second thin film transistor T2. The planarization layer 16 is provided with a third via hole 17 passing through it in a direction perpendicular to the thickness of the substrate 101, the third via hole 17 is filled with an anode 18 of an organic light emitting diode OLED, and the planarization layer 16 is provided There is a pixel defining layer 19 (PDL). One end of the anode 18 is connected to the first source electrode 109, and the other end is connected to the pixel defining layer 19.

In the array substrate 100 of this embodiment, the second thin film transistor T2 is a metal oxide thin film transistor, which is a second thin film of a metal oxide thin film transistor compared to an array substrate using only low temperature polysilicon thin film transistors. The transistor T2 has a smaller volume, a simpler manufacturing process, and has a low leakage current, which can reduce power consumption and improve the performance of the array substrate 100.

In this embodiment, the first drain electrode 111 and the second source electrode 209 are arranged in the same layer. The first drain electrode 111 and the third source/drain electrode are a continuous conductive layer, which can reduce the arrangement space occupied by the first thin film transistor T2 and the second thin film transistor T2. In addition, the second thin film transistor T2 can realize the electrical connection between the metal oxide semiconductor layer 113 and the first source 109 and the first drain 111 without opening through holes, and can also reduce the area occupied by the second thin film transistor T2.

Please refer to FIG. 7 and FIG. 8. FIG. 7 is an equivalent circuit diagram of the inverter circuit 30 according to an embodiment of the present invention. FIG. 8 is a schematic plan view of the inverter circuit 30 according to an embodiment of the present invention. In this embodiment, the inverter circuit 30 applies the semiconductor substrate 10 of the third embodiment of the present invention. For ease of description, the gate insulating layer and other elements are omitted in FIG. 8.

As shown in FIG. 8, the first gate 105 of the first thin film transistor T1 of the inverter circuit 30 and the second gate 205 of the second thin film transistor T2 are electrically connected. As shown in FIG. 7, in this embodiment, when the input terminal IN inputs a high level, the first thin film transistor T1 is turned on, and the second thin film transistor T2 is turned off. The first thin film transistor T1 outputs a low level. When the input terminal IN inputs a low level, the second thin film transistor T2 is turned on, the first thin film transistor T1 is turned off, and the second thin film transistor T2 outputs a high level.

Please refer to FIG. 9, which is an equivalent circuit diagram of the switch circuit 40 according to an embodiment of the present invention. In this embodiment, the switch circuit 40 applies the semiconductor substrate 10 of the third embodiment of the present invention. In this embodiment, the input terminal IN of the switch circuit 40 inputs a signal, the first gate 105 of the first thin film transistor T1 controls the switching of the first thin film transistor T1, and the second thin film transistor T2 The second gate 205 controls the switching of the second thin film transistor T2. When the first thin film transistor T1 is turned on, the signal input from the input terminal IN is output through the first thin film transistor T1; when the second thin film transistor T2 is turned on, the signal input from the input terminal IN goes through the second thin film transistor. Transistor T2 output.

The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred implementations, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced. Without departing from the spirit and scope of the technical solution of the present invention.

10: Semiconductor substrate

101: substrate

T1: The first thin film transistor

T2: The second thin film transistor

103: buffer layer

105: first gate

205: second gate

107: Gate insulation layer

1071: first gate insulating layer

1072: second gate insulating layer

109: First Source

111: The first drain

113: metal oxide semiconductor layer

201: polysilicon semiconductor layer

209: second source

211: The second drain

215: second via

Claims (8)

A semiconductor substrate includes a substrate, a first thin film transistor and a second thin film transistor arranged on the substrate. The improvement lies in that the first thin film transistor is a bottom gate type metal oxide thin film transistor, and the second thin film transistor is The thin film transistor is a top-gate type low-temperature polysilicon thin film transistor; the first thin film transistor includes a first gate provided on the substrate, a metal oxide semiconductor layer, and a metal oxide semiconductor layer connected to and spaced apart from each other A first source electrode and a first drain electrode; the second thin film transistor includes a polysilicon semiconductor layer, a second gate electrode, a second source electrode and a second electrode connected to the polysilicon semiconductor layer and spaced apart from each other, which are sequentially arranged on the substrate And one of the first source or the first drain is shared with one of the second source or the second drain; the semiconductor substrate further includes a substrate formed on the substrate and covering the first A gate and a gate insulating layer of the second gate; the gate insulating layer includes a first gate insulating layer and a second gate insulating layer sequentially stacked in a direction away from the substrate; and the second gate The insulating layer is provided with at least one via hole penetrating the thickness direction thereof, and the first source and the first drain are in direct contact with the first gate insulating layer through the at least one via. The semiconductor substrate according to claim 1, wherein: one of the first source or the first drain and one of the second source or the second drain are provided in the same layer and directly connected. The semiconductor substrate according to claim 2, wherein: the first source, the first drain, the second source, and the second drain are formed by patterning the same conductive layer. The semiconductor substrate according to claim 1, wherein: the metal oxide semiconductor layer is located on a side of the first source and the first drain away from the substrate. The semiconductor substrate according to claim 4, wherein: the first gate and the second gate are formed by patterning the same conductive layer. An array substrate comprising the semiconductor substrate according to any one of claims 1-5. An inverter circuit comprising the semiconductor substrate according to any one of claims 1-5. A switch circuit comprising the semiconductor substrate according to any one of claims 1-5.

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