TW202002305A - Semiconductor substrate, array substrate, inverter circuit, and switch circuit - Google Patents

Abstract

The present disclosure provides a semiconductor substrate including a substrate, a first thin film transistor and a second thin film transistor disposed on the substrate. The first thin film transistor is a metal oxide thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor; the first thin film transistor includes a first source and a first drain, and the second thin film transistor includes a second source and a second drain. One of the first source or the first drain is electrically connected to one of the second source or the second drain. The semiconductor substrate of the present disclosure includes a metal oxide thin film transistor, and the metal oxide thin film transistor share a same source/drain with the low temperature polycrystalline silicon thin film transistor, which can reduce the volume and leakage current of the electronic component using the semiconductor substrate.

Description

Semiconductor substrate, array substrate, inverter circuit and switch circuit

The invention relates to a semiconductor substrate, an array substrate, an inverter circuit and a switching circuit.

The flat display device has many advantages such as a thin body, power saving, no radiation, etc., and is widely used. Conventional flat display devices mainly include liquid crystal displays (Liquid Crystal Display, LCD) and organic electroluminescence devices (Organic Electroluminescence Device, OELD), also known as organic light emitting diodes (Organic Light Emitting Diode, OLED). Generally speaking, an array substrate of a display includes a substrate on which a pixel array including a plurality of pixel units and a driving circuit for driving the pixel array are provided. The driving circuit needs to be applied to a thin film transistor. In addition, the peripheral circuits of the display device are also applied to thin film transistors. The electron mobility of polycrystalline silicon thin film transistors manufactured using low temperature polysilicon technology (LTPS) is greater than that of metal oxide thin film transistors. However, the leakage current of polycrystalline silicon thin film transistors is higher than that of metal oxide thin film transistors. Affects the performance of the array substrate or peripheral circuits.

In view of this, it is necessary to provide a semiconductor substrate with good performance.

A semiconductor substrate includes a substrate, a first thin film transistor and a second thin film transistor provided on the substrate, the first thin film transistor is a top gate type metal oxide thin film transistor, and the second thin film transistor is Bottom gate type low-temperature polysilicon thin film transistor; the first thin film transistor includes a first gate electrode, a metal oxide semiconductor layer and a first source electrode connected to the metal oxide semiconductor layer and spaced apart from each other And the first drain electrode; the second thin film transistor includes a polysilicon semiconductor layer, a second gate electrode, a second source electrode and a second drain electrode connected to the polysilicon semiconductor layer and spaced apart from each other; One of the first source or the first drain is electrically connected to the second source or the second drain.

The invention also provides an array substrate, an inverter circuit and a switching circuit, which include the above-mentioned semiconductor substrate.

Compared with the conventional technology, the semiconductor substrate of the present invention includes a metal oxide thin film transistor, and the metal oxide thin film transistor and the low-temperature polysilicon thin film transistor share a source/drain, which can reduce the volume of electronic components using the semiconductor substrate And leakage current.

Please refer to FIG. 1, which is a schematic cross-sectional structural diagram of a semiconductor substrate 10 according to a first embodiment of the present invention. The semiconductor substrate 10 includes a composite transistor structure of at least two different types of thin film transistors (Thin Film Transistor, TFT). In this embodiment, the two different types of thin film transistors are Low Temperature Poly Silicon , LTPS) thin film transistor and metal oxide (Metal Oxide) thin film transistor. The low-temperature polycrystalline silicon thin film transistor has the characteristics of high electron mobility, and the metal oxide (Metal Oxide) thin film transistor has the characteristics of low leakage current and small volume.

As shown in FIG. 1, in this embodiment, the semiconductor substrate 10 includes a substrate 101 and first and second thin film transistors T1 and T2 formed on the substrate 101. In this embodiment, the first thin film transistor T1 is a metal oxide thin film transistor, and the second thin film transistor T2 is a low temperature polycrystalline silicon thin film transistor.

The first thin-film transistor T1 is a bottom-gate thin-film transistor, which includes a buffer layer 103, a first gate 105, a gate insulating layer 107, a first source 109, a first drain 111 And metal oxide semiconductor layer 113. The buffer layer 103, the first gate 105, and the gate insulating layer 107 are sequentially disposed on the substrate 101. The gate insulating layer 107 is affected by the thickness of the first gate electrode 105, so that the first gate electrode 105 corresponds to a convex shape. The first source electrode 109 and the first drain electrode 111 are separately disposed on the same layer, and are respectively disposed on two opposite sides of the boss of the gate insulating layer 107. The metal oxide semiconductor layer 113 is disposed on the gate insulating layer 107 between the first source electrode 109 and the first drain electrode 111 corresponding to the first gate electrode 105, and partially covers the first source electrode 109 and the The first drain 111. The metal oxide semiconductor layer 113 is electrically connected to the first source electrode 109 and the first drain electrode 111. In this embodiment, the metal oxide semiconductor layer 113 is Indium Gallium Zinc Oxide (IGZO). In other embodiments, the metal oxide semiconductor layer 113 may be a metal oxide material containing at least one of zinc, indium, and gallium.

The second thin film transistor T2 is located beside the first thin film transistor T1, which is a top-gate thin film transistor, which includes a poly-silicon semiconductor layer 201 and the buffer layer 103 , The second gate 205, the gate insulating layer 107, the second source 209 and the second drain 211. The polysilicon semiconductor layer 201, the buffer layer 103, the second gate 205, and the gate insulating layer 107 are sequentially stacked on the substrate 101 from bottom to top, and the second gate 205 corresponds to the polysilicon semiconductor layer 201 Settings. The second source electrode 209 is electrically connected to the polysilicon semiconductor layer 201 via a second via 215 penetrating the buffer layer 103 and the gate insulating layer 107, and the second drain electrode 211 is penetrating the buffer layer 103 and the gate insulating layer The second via 215 of 107 is electrically connected to the polysilicon semiconductor layer 201.

In this embodiment, the buffer layers 103 and 103 are made of insulating materials, such as silicon oxide and silicon nitride. The gate insulating layer 107 includes a first gate insulating layer 1071 and a second gate insulating layer 1072 that are sequentially stacked in a direction away from the substrate 101, that is, the first gate insulating layer 1071 is relatively closer to the substrate 101. The material of the first gate insulating layers 1071 and 1071 is silicon oxide, and the material of the second gate insulating layers 1072 and 1072 is silicon nitride.

One of the first source 109 or the first drain 111 is electrically connected to one of the second source 209 or the second drain 211. As shown in FIG. 1, in this embodiment, the first drain 111 and the second source 209 are provided in the same layer and are directly connected. In this embodiment, the first source electrode 109, the first drain electrode 111, the second source electrode 209 and the second drain electrode 211 are formed by patterning the same conductive layer, the first drain electrode 111 and the first The two source electrodes 209 are a continuous conductive layer.

In this embodiment, the metal oxide semiconductor layer 113 of the first thin film transistor T1 is formed after the first source electrode 109 and the first drain electrode 111 are formed, thereby avoiding the high temperature hydrogenation of the second thin film transistor T2 Damage to the metal oxide semiconductor 113 during the manufacturing process, and the metal oxide semiconductor layer 113 is formed after forming the first source electrode 109 and the first drain electrode 111 to avoid etching the first source electrode 109 and the first drain electrode The metal layer where the electrode 111 is located damages the metal oxide semiconductor layer 113.

In this embodiment, the first gate 105 and the second gate 205 are located in the same layer. The first gate 105 and the second gate 205 may be formed by the same conductive layer in the same manufacturing process.

For the convenience of description, in the following embodiments, the elements having the same structure and function as those in the first embodiment will not be repeated here, and the element symbols in the first embodiment will be used.

Please refer to FIG. 2, which is a schematic cross-sectional structural diagram of a semiconductor substrate 10 according to a second embodiment of the present invention. The structure of the semiconductor substrate 10 of this embodiment is similar to the structure of the semiconductor substrate 10 of the first embodiment, except that in this embodiment, the second gate insulating layer 1072 of the first thin film transistor T1 corresponds to The metal oxide semiconductor layer 113 is provided with a first via 115 penetrating through its thickness direction, so that the first gate insulating layer 1071 is exposed. The metal oxide semiconductor layer 113 directly contacts the first gate insulating layer 1071 through the first via 115 and partially covers the first source electrode 109 and the first drain electrode 111.

In this embodiment, since the second gate insulating layer 1072 is provided with a first via 115 extending through its thickness direction, the gate between the first source electrode 109, the first drain electrode 111 and the first gate electrode 105 The thickness of the electrode insulating layer 107 is reduced, which reduces the capacitance between the first source electrode 109, the first drain electrode 111, and the first gate electrode 105.

Please refer to FIG. 3, which is a schematic cross-sectional view of a semiconductor substrate 10 according to a third embodiment of the present invention. For the sake of brevity, in this embodiment, the elements having the same structure and function as those of the first embodiment will not be repeated here.

In the present embodiment, the gate insulating layer 107 includes a first gate insulating layer 1071 and a second gate insulating layer 1072 which are stacked vertically and away from the substrate 101 in this order. The buffer layer 103, the second gate 205, the first gate insulating layer 1071, the first gate 105, and the second gate insulating layer 1072 are sequentially disposed on the substrate 101. The second gate 205 is located on a side of the first gate insulating layer 1071 away from the second gate insulating layer 1072, and the first gate 105 is located on the first gate insulating layer 1071 and the second gate insulating layer 1072 between.

In this embodiment, the material of the first gate insulating layers 1071 and 1071 is silicon nitride, and the material of the second gate insulating layers 1072 and 1072 is silicon oxide.

In this embodiment, the first gate 105 is separated from the first source 109 and the first drain 111 by a second gate insulating layer 1072, the first gate 105 and the first source 109 1. There is no first gate insulating layer 1071 between the first drain 111, so that the thickness of the gate insulating layer 107 between the first source 109, the first drain 111 and the first gate 105 is reduced Small, reducing the capacitance between the first source 109, the first drain 111 and the first gate 105.

In this embodiment, the first gate 105 and the second gate 205 are located in different layers, and the first gate 105 and the second gate 205 are formed of different conductive layers.

The semiconductor substrate 10 of the first to third embodiments described above can be applied to a pixel drive circuit in a pixel unit of an array substrate in an electronic device, and can also be applied to an inverter circuit or a switching circuit in a peripheral circuit in an electronic device. The following uses only the application of the semiconductor substrate 10 of the third embodiment as an explanation. It can be understood that the semiconductor substrate 10 of the third embodiment applied in the following embodiments can also be replaced with the semiconductor substrate 10 of the first embodiment or the second实施例的Smart substrate 10.

Please refer to FIG. 4, which is a schematic plan view of an array substrate 100 to which an embodiment of the present invention is applied. An array substrate 100 according to an embodiment of the present invention is an organic electroluminescence (OLED) display panel. The array substrate 100 includes a substrate 11 on which a plurality of scan lines S1-Sn and a plurality of scan lines parallel to each other are provided. The data lines D1-Dn are parallel to each other and cross the scan lines S1-Sn. The plurality of scanning lines S1-Sn are electrically connected to the first driving circuit 12 respectively, and the plurality of data lines D1-Dn are electrically connected to the second driving circuit 13 respectively. The plurality of scan lines S1-Sn and the plurality of data lines D1-Dn are vertically insulated to intersect, and a plurality of pixel units 14 are defined. Each pixel unit 14 has a corresponding pixel drive circuit 15 (as shown in FIG. 5). In this embodiment, the first driving circuit 12 may include a multiplexing circuit and a gate driving circuit. The second driving circuit 13 is a data driving circuit.

Please refer to FIG. 5, which is an equivalent circuit diagram of the pixel driving circuit 15 in the pixel unit 14 according to an embodiment of the invention. Including power line VDD, initial terminal Vini, first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, first node A, second node B, organic The light emitting diode OLED, the storage capacitor Cs, the parasitic capacitor COLED, and the ground terminal Vss. In this embodiment, the first thin film transistor T1 is a low temperature polysilicon thin film transistor, the second thin film transistor T2 is a metal oxide thin film transistor, the third thin film transistor T3 and the fourth thin film transistor T4 may be Any one of low temperature polycrystalline silicon thin film transistor, amorphous silicon thin film transistor or organic thin film transistor. In this embodiment, the third thin film transistor T3 and the fourth thin film transistor T4 are low-temperature polysilicon thin film transistors.

The gate electrode of the third thin film transistor T3 is electrically connected to the first scan line S1, the drain electrode is electrically connected to the data line D1, and the source electrode is connected to the first thin film transistor T1 through the first node A The gate is electrically connected. The drain electrode of the first thin film transistor T1 is electrically connected to the source electrode of the second thin film transistor T2. The source electrode of the first thin film transistor T1 is connected to the organic light emitting diode OLED through the second node B The anode (Anode) is electrically connected. The gate electrode of the second thin film transistor T2 is electrically connected to the third scan line S3, and the drain electrode of the second thin film transistor T2 is electrically connected to the power supply line VDD. The gate electrode of the fourth thin film transistor T4 is electrically connected to the second scan line S2, and the drain electrode of the fourth thin film transistor T4 is electrically connected to the second node B. The anode of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode is electrically connected to the ground terminal Vss. The storage capacitor Cs is electrically connected between the gate and the source of the first thin film transistor T1. The parasitic capacitance COLED is electrically connected between the cathode and the anode of the organic light emitting diode OLED.

It can be understood that the pixel unit 14 is not limited to the structure shown in FIG. 5, but may also be a 5T1C pixel structure (including 5 thin film transistors (TFT) and a capacitor C) (not shown) ) Etc., as long as it applies to one of the first source 109 or the first drain 111 of the first thin film transistor T1 and the second source 209 or the second drain 211 of the second thin film transistor T2 One is electrically connected structure.

Please refer to FIG. 6, which is a schematic cross-sectional view of an array substrate 100 according to an embodiment of the invention. For convenience of description, the first thin film transistor T1 and the second thin film transistor T2 are shown in FIG. 6, and other components such as the third thin film transistor T3 and the fourth thin film transistor T4 are omitted. The array substrate 100 in this embodiment uses the semiconductor substrate 10 of the foregoing third embodiment. For simplicity, the structures of the first thin film transistor T1 and the second thin film transistor T2 will not be described in detail.

As shown in FIG. 6, the array substrate 100 further includes a planarization layer 16 covering the first thin film transistor T1 and the second thin film transistor T2. The planarization layer 16 is provided with a third via 17 extending through the thickness direction perpendicular to the substrate 101, the third via 17 is filled with an anode 18 of an organic light emitting diode OLED, and the planarization layer 16 is provided There is a pixel definition layer 19 (Pixel Defining Layer, PDL). One end of the anode 18 is connected to the first source electrode 109 and the other end is connected to the pixel definition layer 19.

In the array substrate 100 of this embodiment, the second thin film transistor T2 is a metal oxide thin film transistor, which is the second film of the metal oxide thin film transistor compared to an array substrate using only low-temperature polysilicon thin film transistors The transistor T2 has a smaller volume, a simpler manufacturing process, and a low leakage current can reduce power consumption and improve the performance of the array substrate 100.

In this embodiment, the first drain electrode 111 and the second source electrode 209 are disposed in the same layer. A continuous conductive layer between the first drain electrode 111 and the third source/drain electrode can reduce the layout space occupied by the first thin film transistor T2 and the second thin film transistor T2. In addition, the second thin film transistor T2 can realize the electrical connection between the metal oxide semiconductor layer 113 and the first source electrode 109 and the first drain electrode 111 without opening a through hole, and can also reduce the area occupied by the second thin film transistor T2.

Please refer to FIGS. 7 and 8. FIG. 7 is an equivalent circuit diagram of the inverter circuit 30 according to an embodiment of the present invention. 8 is a schematic plan view of an inverter circuit 30 according to an embodiment of the invention. In this embodiment, the inverter circuit 30 applies the semiconductor substrate 10 of the third embodiment of the present invention. For the convenience of description, elements such as the gate insulating layer are omitted in FIG. 8.

As shown in FIG. 8, the first gate electrode 105 of the first thin film transistor T1 and the second gate electrode 205 of the second thin film transistor T2 of the inverter circuit 30 are electrically connected. As shown in FIG. 7, in this embodiment, when the input terminal IN inputs a high level, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, and the first thin film transistor T1 outputs a low power level. When the input terminal IN inputs a low level, the second thin film transistor T2 is turned on, the first thin film transistor T1 is turned off, and the second thin film transistor T2 outputs a high level.

Please refer to FIG. 9, which is an equivalent circuit diagram of the switch circuit 40 according to an embodiment of the present invention. In this embodiment, the switching circuit 40 is applied to the semiconductor substrate 10 of the third embodiment of the present invention. In this embodiment, the input terminal IN of the switch circuit 40 inputs a signal, the first gate 105 of the first thin film transistor T1 controls the switching of the first thin film transistor T1, and the second thin film transistor T2 The second gate 205 controls the switching of the second thin film transistor T2. When the first thin film transistor T1 is turned on, the signal input from the input terminal IN is output through the first thin film transistor T1; when the second thin film transistor T2 is turned on, the signal input from the input terminal IN is passed through the second film Transistor T2 output.

The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced, and Without departing from the spirit and scope of the technical solution of the present invention.

10‧‧‧Semiconductor substrate 101‧‧‧ substrate T1‧‧‧The first thin film transistor T2‧‧‧Second Thin Film Transistor 103‧‧‧buffer layer 105‧‧‧ First gate 205‧‧‧second gate 107‧‧‧Gate insulation 1071‧‧‧The first gate insulating layer 1072‧‧‧The second gate insulating layer 109‧‧‧First source 111‧‧‧The first drain 113‧‧‧Metal oxide semiconductor layer 201‧‧‧polysilicon semiconductor layer 209‧‧‧Second source 211‧‧‧Second drain 115‧‧‧First via 215‧‧‧Second via 100‧‧‧Array substrate 11‧‧‧ Base material 12‧‧‧ First drive circuit 13‧‧‧ Second drive circuit 14‧‧‧Pixel unit 15‧‧‧ pixel drive circuit 16‧‧‧Planning layer 17‧‧‧third via 18‧‧‧Anode 19‧‧‧ pixel limited layer 30‧‧‧Inverter circuit 40‧‧‧Switch circuit

FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor substrate according to a first embodiment of the invention.

2 is a schematic cross-sectional structure diagram of a semiconductor substrate according to a second embodiment of the invention.

3 is a schematic cross-sectional structure diagram of a semiconductor substrate according to a third embodiment of the invention.

4 is a schematic plan view of an array substrate to which an embodiment of the present invention is applied.

5 is an equivalent circuit diagram of a pixel driving circuit in a pixel unit according to an embodiment of the invention.

6 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.

7 is an equivalent circuit diagram of an inverter circuit according to an embodiment of the invention.

8 is a schematic plan view of an inverter circuit according to an embodiment of the invention.

9 is an equivalent circuit diagram of a switch circuit according to an embodiment of the invention.

10‧‧‧Semiconductor substrate

101‧‧‧ substrate

T1‧‧‧The first thin film transistor

T2‧‧‧Second Thin Film Transistor

103‧‧‧buffer layer

105‧‧‧ First gate

205‧‧‧second gate

107‧‧‧Gate insulation

1071‧‧‧The first gate insulating layer

1072‧‧‧The second gate insulating layer

109‧‧‧First source

111‧‧‧The first drain

113‧‧‧Metal oxide semiconductor layer

201‧‧‧polysilicon semiconductor layer

209‧‧‧Second source

211‧‧‧Second drain

215‧‧‧Second via

Claims (10)

A semiconductor substrate includes a substrate, a first thin film transistor and a second thin film transistor provided on the substrate, the improvement is that the first thin film transistor is a top gate type metal oxide thin film transistor, the second The thin film transistor is a low-temperature polysilicon thin film transistor of the bottom gate type; the first thin film transistor includes a first gate electrode provided on the substrate, a metal oxide semiconductor layer, and a metal oxide semiconductor layer connected to the metal oxide semiconductor layer and spaced apart from each other A first source electrode and a first drain electrode; a second thin film transistor includes a polysilicon semiconductor layer, a second gate electrode, a second source electrode and a second electrode connected to the polysilicon semiconductor layer and spaced apart from each other in sequence A drain; and one of the first source or the first drain is electrically connected to one of the second source or the second drain. The semiconductor substrate according to claim 1, wherein one of the first source or the first drain and the second source or the second drain are provided in the same layer and are directly connected. The semiconductor substrate according to claim 2, wherein the first source, the first drain, the second source, and the second drain are patterned by the same conductive layer. The semiconductor substrate according to claim 1, wherein the metal oxide semiconductor layer is located on a side of the first source and the first drain away from the substrate. The semiconductor substrate according to claim 1, wherein: the semiconductor substrate further includes a gate insulating layer formed on the substrate and covering the first gate and the second gate; the gate insulating layer includes A first gate insulating layer and a second gate insulating layer stacked in this order away from the substrate; and the second gate insulating layer is provided with at least one via penetrating through its thickness direction, the first source electrode and the first The drain is in direct contact with the first gate insulating layer through the at least one via. The semiconductor substrate according to claim 4, wherein the first gate electrode and the second gate electrode are formed by patterning the same conductive layer. The semiconductor substrate according to claim 1, wherein the semiconductor substrate includes a first gate insulating layer and a second gate insulating layer sequentially stacked on the substrate, the second gate is located on the first gate insulating The layer is away from the side of the second gate insulating layer, the first gate is located between the first gate insulating layer and the second gate insulating layer. An array substrate comprising the semiconductor substrate according to any one of claims 1-7. An inverter circuit includes the semiconductor substrate according to any one of claims 1-7. A switching circuit includes the semiconductor substrate according to any one of claims 1-7.

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