WO2011135920A1 - Circuit board, display device, and method for producing circuit board - Google Patents

Circuit board, display device, and method for producing circuit board Download PDF

Info

Publication number
WO2011135920A1
WO2011135920A1 PCT/JP2011/054796 JP2011054796W WO2011135920A1 WO 2011135920 A1 WO2011135920 A1 WO 2011135920A1 JP 2011054796 W JP2011054796 W JP 2011054796W WO 2011135920 A1 WO2011135920 A1 WO 2011135920A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
transistor element
film transistor
circuit
circuit board
Prior art date
Application number
PCT/JP2011/054796
Other languages
French (fr)
Japanese (ja)
Inventor
北川　英樹
田中　信也
今井　元
村井　淳人
光則 今出
菊池　哲郎
一典 森本
純也 嶋田
西村　淳
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to US13/643,652 priority Critical patent/US9111810B2/en
Publication of WO2011135920A1 publication Critical patent/WO2011135920A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14678—Contact-type imagers

Definitions

  • the present invention relates to a circuit board on which a thin film transistor is mounted, a display device including the circuit board, and a method for manufacturing the circuit board.
  • TFTs Thin film transistors
  • LCD liquid crystal display device
  • LCD drivers circuit elements that constitute LCD drivers.
  • high performance and high reliability are increasingly required for TFTs in order to achieve performance improvements such as large screen, high definition, and high frame rate required for LCDs.
  • Patent Document 1 discloses a configuration of a bottom gate type (reverse stagger type) TFT.
  • FIG. 14 is a cross-sectional view showing the structure of a conventional bottom gate type (inverted stagger type) TFT.
  • a gate electrode 302 is provided over a substrate 301, a first insulating film 303, an oxide semiconductor layer 304 as a channel layer, a second insulating film 305 functioning as an etching stop layer, and a source electrode 306. And a drain electrode 307.
  • Patent Document 1 a display device having an image sensing function as well as an image sensing function has been developed by providing an optical sensor circuit at a location corresponding to a pixel.
  • Patent Document 2 discloses a one-transistor photosensor circuit.
  • FIG. 15 is a circuit diagram showing a configuration of an image display apparatus provided with a conventional photosensor circuit.
  • the image display device 110 includes a display unit 112 and a sensor unit 113 which are partitioned by signal lines S101, S102, S103, S104... And gate lines G101, G102,. Are arranged in a matrix.
  • the display unit 112 is provided with a TFT 114 for driving each pixel.
  • the sensor unit 113 includes a diode 115 and a Tr 116 that is an amplifier circuit for output of the diode 115.
  • the display unit 112 and the sensor unit 113 are provided with three types of transistors having different functions.
  • the gate electrode 115G and the source electrode 115S of the diode 115 are connected to the photodiode reset wiring RST, and the drain electrode 115D of the diode 115 intersects the source wirings S102 and S103 and the output bus line Vout, and the gate electrode 116G of the Tr 116 Connected with.
  • the source electrode 116S of the Tr 116 is connected to the power supply bus line Vs, and the drain electrode 116D of the Tr 116 is connected to the output bus line Vout arranged in parallel with the signal line S101.
  • one terminal portion 141a of the boosting capacitor is connected to the drain electrode 115D and the gate electrode 116G. Further, one terminal portion 141b of the boosting capacitor is connected to the photosensor row selection wiring RW.
  • FIG. 16 is a plan view showing a state of a circuit board in which each transistor of the image display device 110 is configured as a bottom gate type.
  • the TFT 114, the photodiode 115, and the Tr 116 are all configured as a bottom gate type.
  • the main wiring RST and the auxiliary capacitance wiring Cs intersect at the lower layer.
  • the gate electrode 115G of the diode 115 is provided so as to extend from the photodiode reset wiring RST, and is connected to the source electrode 115S through the contact hole 117.
  • the drain electrode 115D of the photodiode 115 is formed in the same layer as the source electrode 115S, and the extended portion of one terminal portion 141a of the boosting capacitor and the contact hole 118 formed in the same layer as the gate electrode 115G. Connected through.
  • the terminal portion 141a intersects at the lower layer of the signal lines S102 and S103 and the output bus line Vout and is connected to the gate electrode 116G of the Tr116.
  • the other terminal portion 141b of the boosting capacitor is formed in the same layer as the source electrode 115S and the drain electrode 115D, and is connected to the extending portion of the photosensor row selection wiring RW via the contact hole 119. Has been.
  • JP 2008-166716 A (published July 17, 2008)”
  • Japanese Patent Publication “International Publication WO 2007-145347 (published on Dec. 21, 2007)”
  • Japanese Patent Publication “International Publication WO2009-025120 (published on Feb. 26, 2009)”
  • the oxide TFT disclosed in Patent Document 1 has a higher mobility than, for example, an amorphous silicon TFT, an output voltage with a sufficiently high S / N ratio can be obtained even if the TFT size is small. It has the disadvantage that its sensitivity to light is extremely low.
  • Patent Document 2 includes a TFT that plays a role of sensor output and a diode-type TFT that plays a role of a photosensor element. For this reason, if all these TFTs are oxide TFTs, there is no problem in the TFT that plays the role of sensor output, while the TFT that plays the role of the photosensor element has a very low sensitivity to light. As a circuit, the performance becomes insufficient.
  • amorphous silicon TFTs have the advantage of high sensitivity to light, they have a lower mobility than oxide TFTs, so the TFT size is increased to obtain an output voltage with a sufficiently high S / N ratio.
  • the size of the TFT serving as the sensor output must be increased. Therefore, for example, in the case of a display device incorporating a photosensor circuit, there arises a problem that the aperture ratio of the pixel becomes small.
  • the sensor unit 113 requires a plurality of transistors and capacitors.
  • the plurality of transistors provided in the sensor unit 113 are configured by bottom-gate transistors as in Patent Document 1, a large number of contact holes are connected to connect the plurality of transistors provided in the sensor unit 113 and the capacitor. It is necessary to provide.
  • the sensor portion 113 is formed with three contact holes 117, 118, and 119.
  • the present invention has been made in view of the above problems, and its purpose is to improve the performance of a circuit board on which TFTs having different roles in circuit are mounted, and to reduce the area required for mounting TFTs. It is in providing the structure which can be reduced, and its manufacturing method.
  • a circuit board of the present invention is a circuit board having a plurality of transistor elements on the same insulating substrate, and at least one of the plurality of transistor elements is relatively ,
  • a first thin film transistor element including, as a channel layer, a semiconductor having high mobility and low sensitivity to light, and at least another one of the plurality of transistor elements is circuit-like with the first thin film transistor element
  • a second thin film transistor element having a channel layer of a semiconductor having a different role and relatively low mobility and high sensitivity to light, wherein the first thin film transistor element is a top-gate transistor.
  • the second thin film transistor element is a bottom-gate transistor.
  • the first thin film transistor element provided with a semiconductor having a relatively high mobility as a channel layer can obtain a high output voltage without increasing the size, so that a decrease in the aperture ratio of the pixel can be suppressed.
  • the thin film transistor element having the first characteristic and the thin film transistor element having the second characteristic can play different roles in terms of circuit. Therefore, according to said structure, the circuit board with the sufficient performance which mounted the electric circuit using each of the said different role can be obtained.
  • the first thin film transistor element is a top gate type transistor
  • the second thin film transistor element is a bottom gate type transistor. Therefore, the drain electrode and the source electrode of the second thin film transistor element and the gate electrode of the first thin film transistor can be formed in the same layer.
  • an electric circuit in which the output electrode of the second thin film transistor element and the gate electrode of the first thin film transistor are connected can be configured without providing a contact hole.
  • an electric circuit that controls the driving of the first thin film transistor in accordance with the output of the second thin film transistor electrode can be configured without providing a contact hole.
  • the first thin film transistor element and the second thin film transistor element having different circuit roles are arranged on the same insulating substrate due to different types of semiconductors forming the channel layer.
  • a method for manufacturing a circuit board wherein an insulating film is formed on a channel layer of the first thin film transistor element and a gate electrode of the second semiconductor transistor element patterned on the insulating substrate. And forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second semiconductor transistor by patterning the same conductive layer on the insulating film. It is a feature.
  • the substrate can be manufactured at a low cost.
  • the circuit board of the present invention is a circuit board provided with a plurality of transistor elements on the same insulating substrate, and at least one of the plurality of transistor elements has a relatively high mobility and resistance to light.
  • a first thin film transistor element including a semiconductor having a low sensitivity as a channel layer, wherein at least another one of the plurality of transistor elements has a circuit role different from that of the first thin film transistor element, and a relative
  • the second thin film transistor element includes, as a channel layer, a semiconductor having low mobility and high sensitivity to light, the first thin film transistor element is a top-gate transistor, and the second thin film transistor element Is a bottom-gate transistor.
  • the first thin film transistor element and the second thin film transistor element having different circuit roles are arranged on the same insulating substrate due to different types of semiconductors forming the channel layer.
  • a method for manufacturing a circuit board wherein an insulating film is formed on a channel layer of the first thin film transistor element and a gate electrode of the second semiconductor transistor element patterned on the insulating substrate. Forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second semiconductor transistor by patterning the same conductive layer on the insulating film.
  • FIG. 1 is a cross-sectional view schematically showing a basic configuration of a circuit board according to an embodiment of the present invention. It is a figure showing the modification of the circuit board of FIG. It is a circuit diagram showing a circuit configuration of a liquid crystal display device in which a plurality of pixels and a photosensor circuit are formed on an active matrix substrate. It is a top view showing the structure of the active matrix substrate of a liquid crystal display device. It is process drawing which shows the manufacturing process of a circuit board in order. It is a schematic block diagram which shows the structure of a liquid crystal display device.
  • FIG. 7 is a circuit diagram illustrating a configuration of a protection circuit and a pixel circuit formed in a region Sb illustrated in FIG. 6.
  • FIG. 11 is a schematic cross-sectional view of the protection circuit along the line A-A ′ shown in FIG. 10.
  • It is a circuit diagram showing the structure of the liquid crystal display device provided with the optical sensor circuit.
  • It is a figure showing the other modification of the circuit board of FIG.
  • It is sectional drawing which shows the structure of the conventional bottom gate type (reverse stagger type) TFT.
  • It is a circuit diagram showing the structure of the image display apparatus provided with the conventional photosensor circuit. It is a top view showing a mode that each transistor of the image display apparatus was comprised by the bottom gate type.
  • FIG. 1 is a cross-sectional view schematically showing a basic configuration of the circuit board 1.
  • the circuit board 1 includes a plurality of transistor elements provided on the same insulating substrate 2 corresponding to the pixels (see FIG. 3) arranged in a matrix.
  • At least one of the plurality of transistor elements is a first thin film transistor element
  • the first thin film transistor element includes a semiconductor having a relatively high mobility and low sensitivity to light as a channel layer (also referred to as an active layer). 11).
  • the channel layer 11 included in the first thin film transistor element is made of an oxide semiconductor.
  • the first thin film transistor element is referred to as an oxide TFT 10.
  • the oxide semiconductor an amorphous oxide (IGZO) material typified by In—Ga—Zn—O is suitable, and a polycrystalline material typified by zinc oxide (ZnO) can also be used.
  • IGZO amorphous oxide
  • ZnO zinc oxide
  • At least another of the plurality of transistor elements is a second thin film transistor element, and the second thin film transistor element includes a semiconductor having a relatively high sensitivity to light as the channel layer 21, and the oxide layer The role of the circuit is different from that of the TFT 10.
  • the channel layer 21 included in the second thin film transistor element is made of a hydrogenated amorphous silicon semiconductor (a-Si: H).
  • a-Si TFT 20 The second thin film transistor element is hereinafter referred to as a-Si TFT 20.
  • the constituent material of the channel layer 21 is not limited to an amorphous silicon semiconductor, but a microcrystalline silicon semiconductor (microcrystalline silicon semiconductor, that is, ⁇ c-Si), or a stacked semiconductor in which a-Si: H and ⁇ c-Si are stacked. Can be adopted. Since the laminated semiconductor can cover a wavelength band that cannot be received by one layer, a highly sensitive photosensor element can be formed for a wide wavelength band.
  • the oxide TFT 10 can obtain a high output voltage without increasing its size (mobility is about 20 times that of the a-Si TFT), so that it can suppress a decrease in the aperture ratio of the pixel, but light (
  • the a-Si TFT 20 has a second characteristic that the output voltage is low because the mobility is low, while the sensitivity to light is high.
  • the oxide TFT 10 having the first characteristic and the a-Si TFT 20 having the second characteristic can play different roles in terms of circuit. Therefore, according to said structure, the circuit board 1 with the sufficient performance which mounted the electric circuit using each of the said different role can be obtained.
  • the diode portion is composed of a bottom gate type oxide TFT 10 and is used for an output amplifier (Tr portion).
  • This transistor is composed of a top gate type a-Si TFT 20.
  • the switching element for driving each pixel is also composed of the bottom gate type oxide TFT 10.
  • the oxide TFT 10 used in the Tr portion is referred to as an oxide TFT 10a
  • the oxide TFT 10 used in a switching element for driving each pixel provided in the display portion is referred to as an oxide TFT 10b. There is a case.
  • the oxide TFT 10 (10a / 10b) is formed on the insulating substrate 2 with the channel layer 11 (11a / 11b), the source electrode 15 (15a / 15b), and the drain electrode 16 (16a / 16b) arranged in parallel. ing.
  • the channel layer 11 is formed so as to cover part of the side surfaces of the source electrode 15 and the drain electrode 16.
  • a gate insulating film 3 mainly composed of SiO 2 is formed on the insulating substrate 2 so as to cover the channel layer 11, the source electrode 15 and the drain electrode 16.
  • gate electrodes 12 (12a and 12b) are formed on the gate insulating film 3.
  • the a-Si TFT 20 has a gate electrode 22 formed on the insulating substrate 2.
  • a gate insulating film 3 is formed on the insulating substrate 2 so as to cover the gate electrode 22.
  • a channel layer 21, a source electrode 25, and a drain electrode 26 are formed side by side. Each of the source electrode 25 and the drain electrode 26 is formed so as to cover a part of the side surface of the channel layer 21.
  • the oxide TFT 10 and the a-Si TFT 20 are covered and protected by a passivation film 4 containing SiN X as a main component.
  • the oxide TFT 10 is configured as a top gate type
  • the a-Si TFT 20 is configured as a bottom gate type, whereby the source electrode 25 and the drain electrode 26 of the a-Si TFT 20 and the gate electrode 12 of the oxide TFT 10 are formed. It can be formed in the same layer.
  • the drain 26 of the a-Si TFT 20 and the gate electrode 12 of the oxide TFT 10 can be connected without providing a contact hole.
  • an electric circuit such as an optical sensor circuit that controls the driving of the oxide TFT 10 according to the output of the a-Si TFT 20 can be configured without providing a contact hole.
  • the oxide TFT 10 has a lower sensitivity to light than the a-Si TFT 20, it can be suitably used as a switching element for driving the display portion of each pixel. This prevents the semiconductor layer of the switching element that drives the display unit from being deteriorated by the light emitted from the backlight as compared with the case where the a-Si TFT 20 is used as the switching element that drives the display unit. it can. In addition, since it is not necessary to provide a light shielding layer in the lowermost layer of the switching element that drives the display portion, it is possible to obtain material cost and an effect of reducing the manufacturing process.
  • the a-Si TFT 20 is a bottom gate type, for example, when the circuit board 1 is mounted on a display device that includes a backlight and modulates the emitted light intensity of the backlight by pixels, the emitted light from the backlight is gated.
  • the electrode 22 can shield light. As a result, it is possible to prevent the deterioration of the characteristics of the channel layer 21 without providing a light shielding film separately.
  • the source electrode 15, the drain electrode 16, and the gate electrode 22 are formed of the same conductive layer, and the gate electrode 12, the source electrode 25, and the drain electrode are formed. 26 is formed of the same conductive layer.
  • the circuit board 1 when the circuit board 1 is mounted on a display device having a backlight, the excellent advantages of suppressing the decrease in aperture ratio of the pixel, high sensitivity, and fast response speed are not deteriorated.
  • the manufacturing process can be simplified, and a remarkable effect that costs can be reduced can be obtained.
  • FIG. 2 is a cross-sectional view illustrating a modification of the circuit board.
  • a second gate insulating film (second insulating layer) 23 containing SiN X as a main component may be further provided below the channel layer 21.
  • the channel layer 11 of the oxide TFT 10 is sandwiched between the insulating substrate 2 and the gate insulating film 3 (first insulating film) containing oxide-based SiO 2 as a main component.
  • the gate insulating film of the a-Si TFT 20a has a two-layer structure of SiN X / SiO 2 (gate insulating film 3 and gate insulating film 23).
  • the channel layer 21 of the a-Si TFT 20a has a nitride-based SiN X Is sandwiched between a gate insulating film 23 containing SiN X as a main component and a passivation film 4 containing SiN X as a main component.
  • the gate insulating film 3 is formed as the same layer common to the oxide TFT 10 and the a-Si TFT 20.
  • the oxide semiconductor constituting the channel layer 11 and the amorphous silicon semiconductor constituting the channel layer 21 can be in contact with a gate insulating film or a passivation film suitable for each.
  • the gate insulating film 3 (oxide) is in contact with the channel layer 11 (oxide semiconductor). It is possible to prevent the characteristics from deteriorating.
  • the gate insulating film 23 and the passivation film 4 are formed on the channel layer 11 (amorphous silicon semiconductor). Therefore, it is possible to prevent the characteristics from deteriorating.
  • a conductive layer 24 separated on the source side and the drain side is stacked on the channel layer 21.
  • n + a-Si or n + ⁇ c-Si doped with a relatively high concentration of n-type impurities can be used.
  • the insulating film included in the a-Si TFT 20a has a two-layer structure including the first gate insulating film 3 and the second gate insulating film 23.
  • the insulating film included in the oxide TFT 10 may have a two-layer structure, contrary to the configuration of FIG.
  • FIG. 13 is a cross-sectional view schematically showing a modification of the basic configuration of the circuit board shown in FIGS.
  • symbol is attached
  • a circuit board 1b shown in FIG. 13 includes an oxide TFT 10 (10c and 10d) configured as a top gate type transistor and an a-Si TFT 20b configured as a bottom gate type transistor.
  • the oxide TFTs 10c and 10d include a gate electrode 12 as a top gate on a first gate insulating film (first insulating film) 3B mainly composed of SiN X , A second gate insulating film (second insulating layer) mainly composed of SiO 2 formed so as to cover the channel layer 11 between the gate insulating film (first insulating film) 3B and the channel layer 11. ) 23B.
  • the a-Si TFT 20b includes a gate electrode 22 as a bottom gate below the first gate insulating film (first insulating film) 3B formed in common with the oxide TFT 10 (10c and 10d).
  • a channel layer 21 is formed directly on the first gate insulating film 3B.
  • the oxide TFTs 10c and 10d are the same as the oxide TFTs 10a and 10b except that a second gate insulating film 23B is added to the oxide TFTs 10a and 10b in FIG.
  • the a-Si TFT 20b is the same as the a-Si TFT 20a except that the second gate insulating film 23 is removed from the a-Si TFT 20a in FIG.
  • the oxide TFTs 10c and 10d and the a-Si TFT 20b are also covered and protected by the passivation film 4 mainly composed of SiN X , which is the same as the configuration of FIG.
  • FIG. 3 shows an equivalent circuit of the liquid crystal display device 50 provided with the photosensor circuit.
  • FIG. 3 is a circuit diagram showing a circuit configuration of a liquid crystal display device 50 in which a plurality of pixels 30 and a photosensor circuit 40 are formed on an active matrix substrate. This active matrix substrate corresponds to the circuit substrate 1.
  • FIG. 3 shows a circuit configuration built in the region Sa shown in the display panel 51 provided in the liquid crystal display device 50 described later with reference to FIG.
  • the display panel 51 includes a display unit 31 in which the pixels 30 are arranged and a sensor unit 32 in which an optical sensor circuit (electric circuit) 40 is arranged in a matrix.
  • the optical sensor circuit 40 includes an oxide TFT 10a, an a-Si TFT 20, and a boosting capacitor 41.
  • the oxide TFT 10a serves as a sensor output (Tr: output amplifier) of the photosensor circuit 40
  • the a-Si TFT 20 serves as a photosensor element (diode) of the photosensor circuit 40.
  • the optical sensor circuit 40 is configured as a 1T (abbreviation of transistor) type circuit using only one transistor that plays a role of sensor output.
  • the oxide TFT 10a functions as a source follower transistor (voltage follower transistor).
  • the source electrode (input electrode) 15a of the oxide TFT 10a is connected to the AMP power supply bus line Vs, and the drain electrode (output electrode) 16a is connected to the photosensor output bus line Vout.
  • the AMP power supply bus line Vs and the optical sensor output bus line Vout are connected to a sensor read circuit 55 shown in FIG. 4 (described later), and the power supply voltage VDD is applied to the AMP power supply bus line Vs from the sensor read circuit 55.
  • a drain electrode (output electrode) 26 of the a-Si TFT 20 functioning as a photodiode is connected to the gate (base) electrode 12a of the oxide TFT 10a, and a terminal portion which is one terminal portion of the boosting capacitor 41. 41a is connected.
  • Both the source electrode (input electrode) 25 and the gate electrode (base) 22 of the a-Si TFT 20 are short-circuited by being connected to the photodiode reset wiring RST. That is, the a-Si TFT 20 has a diode connection configuration, and functions as a photodiode having the source electrode 25 as an anode and the drain electrode 26 as a cathode.
  • the source electrode 25 of the a-Si TFT 20 is connected to a photodiode reset wiring RST to which a reset signal RST is sent from the sensor scanning signal line drive circuit 54 shown in FIG.
  • the terminal portion 41b is connected to an optical sensor row selection wiring RW to which an optical sensor row selection signal RWS is sent.
  • the photosensor row selection signal RW has a role of selecting a specific row of photosensor circuits arranged in a matrix and outputting a detection signal from the photosensor circuit 40 in the specific row.
  • the oxide TFT 10a has the first characteristic that it can suppress a decrease in the aperture ratio of the pixel but has low sensitivity to light because a high output voltage can be obtained without increasing the size. Therefore, it is suitable for the role of the sensor output of the optical sensor circuit 40.
  • the a-Si TFT 20 is suitable for the role of the photosensor element of the photosensor circuit 40 because it has the second characteristic that the output voltage is low because of its low mobility but high sensitivity to light.
  • the optical sensor element is required to have sensitivity to any wavelength band of the ultraviolet light region, the visible light region, and the infrared light region.
  • a-Si: H has a good sensitivity over almost the entire visible light region so as to have a sensitivity peak in the vicinity of 600 to 700 nm.
  • the oxide TFT 10a and the a-Si TFT 20 can constitute the optical sensor circuit 40 having excellent advantages of suppressing the decrease in aperture ratio of the pixel, high sensitivity, and high response speed.
  • ⁇ c-Si or a laminated semiconductor in which a-Si: H and ⁇ c-Si are laminated is used for the channel layer 21 of the a-Si TFT 20.
  • an excellent advantage of such a photosensor circuit 40 is that, for example, by mounting a plurality of photosensor circuits 40 in an active matrix substrate in which pixels using liquid crystals are arranged in a matrix, a touch panel function or an image can be obtained. This is extremely advantageous when a liquid crystal display device having a scanner function or the like is configured.
  • the active matrix substrate of the liquid crystal display device 50 provided with the photosensor circuit 40 is further provided with gate wirings M2-1 (M2-n), M2-2 ((M2-n + 1).
  • n is a natural number indicating the pixel row number
  • the active matrix substrate of the liquid crystal display device 50 is disposed so as to face the counter substrate through the liquid crystal layer.
  • common wiring lines COM1, COM2,... are formed in parallel with the gate wiring lines M2-1,.
  • the switching element that drives the pixel 30 is composed of an oxide TFT 10b.
  • the source electrode 15b of the oxide TFT 10b is connected to the source wiring M1-1, and the drain electrode 16b is connected to the common wiring COM1 of the counter substrate through a liquid crystal layer forming a capacitor.
  • the drain electrode 16b is also connected to an auxiliary capacitor.
  • the gate electrode 12b of the oxide TFT 10b is connected to the gate wiring M2-1.
  • the same number of photosensor circuits 40 as that of all the pixels 30 may be provided, or a predetermined number of groups of pixels 30 may be provided.
  • the number of photosensor circuits 40 may be determined according to the balance with the resolution required for photodetection.
  • one photosensor circuit 40 is provided for three pixels 30.
  • three pixels of R (red), G (green), and B (blue) corresponding to full color display can be assigned.
  • the source wiring M1-1 may also serve as the AMP power supply bus line Vs, and the source wiring M1-2 adjacent to the source wiring M1-1 may also serve as the photosensor output bus line Vout.
  • FIG. 4 is a plan view showing the configuration of the active matrix substrate of the liquid crystal display device.
  • Source wirings M1-1, M1-2, M1-3, M1-4,... AMP power supply bus line Vs, the optical sensor output bus line Vout are gate wirings M2-1, M2-2,. , The photosensor row selection signal RW and the photodiode reset wiring RST are crossed under each other.
  • the source electrode 25 of the a-Si TFT 20 is an extending portion of the photodiode reset wiring RST provided so as to extend from the photodiode reset wiring RST toward the photosensor row selection signal RW.
  • the source electrode 25 is connected to the gate electrode 22 through the contact hole 27.
  • the drain electrode 26 formed in the same layer as the source electrode 25 is connected to the gate electrode 12a of the oxide TFT 10a through one terminal portion (wiring) 41a of the boosting capacitor 41.
  • the gate electrode 12a of the oxide TFT 10a and the drain electrode (output electrode) 26 of the a-Si TFT 20 are formed of the same conductive layer and are connected via the terminal portion (wiring) 41a. Has been.
  • the gate insulating film 3 is provided in the lower layer of one terminal portion 41a, and the other terminal portion 41b of the boost capacitor 41 is formed in the lower layer.
  • the other terminal portion 41 b of the boosting capacitor 41 is connected to an extended portion formed extending from the photosensor row selection signal RW toward the photodiode reset wiring RST via a contact hole 42.
  • the drain electrode 16a of the oxide TFT 10a also serves as the AMP power supply bus line Vs, and the source electrode 15a also serves as the optical sensor output bus line Vout.
  • the a-Si TFT 20 is configured as a bottom gate type
  • the oxide TFT 10a is configured as a top gate type, thereby straddling a plurality of source lines (in the example of FIG. 3, the source lines M1-2, M1-3) )
  • the drain electrode 26 of the a-Si TFT 20 and the gate electrode 12a of the oxide TFT 10a can be made of the same material in the same layer via wiring such as the terminal portion 41a.
  • the gate electrode 12a of the oxide TFT 10a and the drain electrode 26 of the a-Si TFT 20 can be connected without providing a contact hole. For this reason, the area of a region necessary for forming the contact hole of the sensor unit 32 can be reduced.
  • the area of the display part 31 can be enlarged and the aperture ratio reduction of a pixel can be suppressed.
  • an oxide TFT 10b is arranged in the pixel 30, an oxide TFT 10b is arranged.
  • the source electrode 15b is configured as an extended portion of the source wiring M1-1.
  • a wiring extends from the drain electrode 16b in the direction of the auxiliary capacitance wiring Cs, and the wiring and the auxiliary capacitance wiring Cs are connected via a contact hole.
  • FIG. 5 is a process chart showing the manufacturing process of the circuit board 1 in order.
  • the method of manufacturing a circuit board according to the present invention is different in that the oxide TFT 10 and the a-Si TFT 20 have different circuit roles due to different types of semiconductors forming the channel layers 11 and 21. Is a manufacturing method for forming on the same insulating substrate 2.
  • the source electrode 15 and the drain electrode 16 of the oxide TFT 10 and the gate electrode 22 of the a-Si TFT 20 are simultaneously formed by patterning the same conductive layer formed on the insulating substrate 2 (see FIG. 5A). That is, it is formed (in the same manufacturing process) (process A).
  • an oxide semiconductor film is formed and patterned on the insulating substrate 2 so as to cover the source electrode 15, the drain electrode 16, and the gate electrode 22, and the oxide TFT 10
  • the channel layer 11 is formed (step B).
  • SiO 2 is mainly contained on the channel layer 11 of the oxide TFT 10 and the gate electrode 22 of the a-Si TFT 20 patterned on the insulating substrate 2.
  • a gate insulating film 3 is formed (step C).
  • a-Si is deposited on the gate insulating film 3 and patterned to form a channel layer 21 for the a-Si TFT 20 (step D).
  • the channel layer 21 is formed on the gate insulating film 23. Patterning may be performed.
  • the gate electrode 12 of the oxide TFT 10 and the source electrode 25 and the drain electrode 26 of the a-Si TFT 20 are simultaneously formed (that is, in the same manufacturing process) on the gate insulating film 3 by patterning the same conductive layer. (Process F). Thereby, the source electrode 25 and the gate electrode 22 are connected via the contact hole 27.
  • step G the entire surface is covered with the passivation film 4 (step G), and the circuit board 1 is completed.
  • the gate insulating film 3 is formed simultaneously (that is, in the same manufacturing process) as the same layer shared by the oxide TFT 10 and the a-Si TFT 20. Therefore, the manufacturing process is not complicated, can be simplified, and cost can be reduced.
  • the source electrode 15 and the drain electrode 16 of the oxide TFT 10 and the gate electrode 22 of the a-Si TFT 20 are formed by the same conductive layer, and the gate electrode 12 of the oxide TFT 10, the source electrode 25 and the drain electrode 26 of the a-Si TFT 20 are also formed. Further, they are formed by the same conductive layer. Thereby, the manufacturing process can be further simplified and the cost can be reduced.
  • FIG. 6 is a schematic block diagram showing the configuration of the liquid crystal display device 50.
  • the liquid crystal display device 50 includes a display panel 51, a display scanning signal line driving circuit 52, a display video signal line driving circuit 53, a sensor scanning signal line driving circuit 54, a sensor readout circuit 55, a sensing image.
  • a processing unit 56 and a power supply circuit 57 are provided.
  • the display panel 51 includes an active matrix substrate (circuit substrate 1) and a counter substrate which are sealed with a liquid crystal layer interposed therebetween. That is, the display panel 51 includes a circuit substrate 1 configured as an active matrix substrate, a liquid crystal layer, and a counter substrate disposed to face the active matrix substrate via the liquid crystal layer.
  • the insulating substrate 2 shown in FIG. 1 is a base member of an active matrix substrate, for example, a glass substrate. All circuit elements constituting the display scanning signal line driving circuit 52, the display video signal line driving circuit 53, the sensor scanning signal line driving circuit 54, and the sensor readout circuit 55 are formed monolithically on the insulating substrate 2. Yes.
  • “Monolithically formed” means that a circuit element is formed directly on the insulating substrate 2 by at least one of a physical process and a chemical process, and the semiconductor circuit is mounted on the glass substrate as a module. Does not include that.
  • the liquid crystal display device 50 When the liquid crystal display device 50 is a VA (Vertical Alignment) mode liquid crystal display device, a common electrode and R (red), G (green), and B (blue) color filters are provided on the counter substrate. . Since the present invention is not limited by the liquid crystal mode, it can also be applied to a TN (Twisted Nematic) mode, and further, an IPS (In-Plane Switching) also called a lateral electric field application method in which a common electrode is provided on an active matrix substrate. ) Mode.
  • VA Vertical Alignment
  • a common electrode and R (red), G (green), and B (blue) color filters are provided on the counter substrate.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • the display scanning signal line drive circuit 52 uses the gate wiring M2-n to generate a scanning signal for selectively scanning the pixels 30 row by row.
  • the display video signal line drive circuit 53 supplies a video signal to each pixel 30 using the source wiring M1-m.
  • the sensor scanning signal line drive circuit 54 selects and drives the optical sensor circuit 40 row by row, and the sensor readout circuit 55 supplies the optical sensor circuit 40 with a constant power supply voltage VDD using the AMP power supply bus line Vsm. And a photodetection signal is read out from the photosensor circuit 40 using the photosensor output bus line Vout.
  • the sensing image processing unit 56 includes an LSI (Large Scale Integrated Circuit), a PC (Programmable Controller), and the like, and scans an original from a photodetection signal output from the photosensor circuit 40 according to a stored image processing program, Alternatively, information such as the position of a finger or a pointing pen with respect to the display panel 51 is generated.
  • LSI Large Scale Integrated Circuit
  • PC Computer Controller
  • the power supply circuit 57 supplies necessary power supply voltages to the circuits 52 to 56, respectively.
  • the configuration of the liquid crystal display device 50 is not limited to the above-described configuration, and the sensor scanning signal line drive circuit 54 or the sensor readout circuit 55 is another circuit, specifically, a display scanning signal line drive circuit. 52 or the display video signal line drive circuit 53 or the like may be included as a function, and the sensor readout circuit 55 may be included in the function of the sensing image processing unit 56.
  • FIG. 7 is a circuit diagram showing the configuration of the protection circuit 60 and the pixel circuit formed in the region Sb shown in FIG.
  • the circuit board 1 has wiring for connecting the display panel 51 to each circuit (display scanning signal line driving circuit 52, display video signal line driving circuit 53, sensor scanning signal line driving circuit 54, sensor reading circuit 55).
  • a protection circuit may be provided.
  • the optical sensor circuit 40 is not shown.
  • the circuit board 1 is a protection circuit 60 that protects the oxide TFTs 10 (10a and 10b) (first transistor elements) which are part of a plurality of transistor elements provided on the same insulating substrate in a circuit manner.
  • a protection circuit 60 including a diode 61 (second transistor element) that becomes a part of the plurality of transistor elements is included.
  • the diode 61 is made of an a-Si TFT.
  • an a-Si TFT is used for an element that requires high resistance (for example, a protection element), and an oxide semiconductor is used for an element that preferably has low resistance (high mobility) (for example, a switching element).
  • the protection circuit 60 is a bidirectional diode configured by connecting diodes 61 whose forward directions are opposite to each other in parallel, and all the gate wirings M2-n are connected to each other. One by one. Such a protection circuit 60 is also called a diode short ring. One end of the protection circuit 60 is connected to the gate line Gn (corresponding to the gate line M2-n described above), and the other end is connected to, for example, a ground line.
  • the bidirectional diode can cope with an excessive voltage of both positive and negative polarities.
  • the protection circuit 60 may be provided so as to connect the gate wiring M2-n and the gate wiring M2-n + 1 adjacent to each other.
  • a pixel circuit formed in the pixel 30 such as the oxide TFT 10a is arranged. Can be protected.
  • the TFT functioning as the diode 61 of the protection circuit 60 is an a-Si TFT. This is effective for reducing the area occupied by the protection circuit 60 and reducing the frame size of the display panel 51.
  • the oxide TFT has a characteristic that the on-resistance is one digit smaller than that of the a-Si TFT. Therefore, the threshold voltage at which the oxide TFT is turned on is lower than the threshold voltage of the a-Si TFT. Therefore, when the oxide TFT is used in the protection circuit 60 of FIG. 7, the gate wiring M2-n is grounded. There is a risk of current leakage between the lines, and when an oxide TFT is used for the protection circuit 60 in FIG. 8, current leakage may occur between adjacent gate wirings.
  • the channel length (L length) of the oxide TFT is increased as shown in FIG. It is necessary to increase the on-resistance. For this reason, the size of the oxide TFT must be increased, which hinders the narrowing of the frame of the display panel 51.
  • the protective circuit 60 is not provided in preference to narrowing the frame of the display panel 51, dielectric breakdown or the like occurs in the pixel circuit provided in the pixel 30, and the manufacturing yield of the display panel 51 decreases. .
  • thin film transistors that play different roles on the same insulating substrate
  • thin film transistors having optimum characteristics are adopted according to their roles, so that the performance of the circuit board can be maximized. it can.
  • the transistor elements constituting the protection circuit 60 are a-Si TFTs, the display panel 51 can be narrowed, which contributes to downsizing of the display device.
  • protection circuit 60 can be provided in the source wiring M1-m as disclosed in the above-mentioned Patent Document 3, and is not limited to the forms shown in FIGS.
  • FIG. 9 is a circuit diagram showing bidirectional diodes constituting the protection circuit 60 using circuit symbols of TFTs.
  • the gate of the TFT 60a is connected to the gate wiring Gn (corresponding to the gate wiring M2-n described above), and the gate of the TFT 60b is connected. It is connected to the adjacent gate wiring Gn + 1 (corresponding to the above-mentioned gate wiring M2-n + 1), and each drain is connected to the other gate.
  • FIG. 10 is a schematic plan view of the protection circuit 60 and the TFT.
  • the gate electrode 62a extends from the gate line Gn to the gate line Gn + 1, and the source electrode is formed on the channel layer 63a of the a-Si semiconductor provided above the gate electrode 62a.
  • 64a and the drain electrode 65a are opposed to each other with a gap therebetween.
  • the source electrode 64a is connected to the gate electrode 62a through the contact hole 66a.
  • the drain electrode 65a is connected to the gate electrode 62b of the TFT 60b through the contact hole 66b.
  • the gate electrode 62b extends from the gate wiring Gn + 1 to the gate wiring Gn, and the source electrode 64b and the drain electrode are formed on the channel layer 63b of the a-Si semiconductor provided above the gate electrode 62b. 65b is opposed to each other with a gap.
  • the source electrode 64b is connected to the gate electrode 62b through the contact hole 67b.
  • the drain electrode 65b is connected to the gate electrode 62a of the TFT 60a through the contact hole 67a.
  • both the channel layer 63a and the channel layer 63b are formed of an a-Si semiconductor, the channel length (L length) is changed to an oxide without changing the channel width (W length) shown in FIG.
  • the required on-resistance can be obtained by making it shorter than the TFT.
  • FIG. 11 is a schematic cross-sectional view of the protection circuit 60 taken along the line AA ′ shown in FIG. As shown in FIG. 11, the TFTs 60 a and 60 b are formed on the same insulating substrate 2, and are covered and protected by the passivation film 4.
  • gate electrodes 62a and 62b are formed on the insulating substrate 2, and the first gate insulating film 3 covers the gate electrodes 62a and 62b.
  • Second gate insulating films 23a and 23b corresponding to the second gate insulating film 23 are stacked on the first gate insulating film 3 at positions above the gate electrodes 62a and 62b, respectively.
  • channel layers 63a and 63b of an a-Si semiconductor are stacked on the second gate insulating films 23a and 23b, respectively.
  • Conductive layers 68a and 68b with gaps are stacked on the channel layers 63a and 63b, and a source electrode 64a and a drain electrode 65a facing each other with a gap are formed on the conductive layer 68a.
  • a source electrode 64b and a drain electrode 65b facing each other with a gap are formed.
  • the drain electrode 65a extends on the gate electrode 62b of the TFT 60b and is connected to the gate electrode 62b through the contact hole 66b.
  • the source electrode 64a is connected to its own gate electrode 62a through a contact hole 66a.
  • the drain electrode 65b extends on the gate electrode 62a of the TFT 60a and is connected to the gate electrode 62a through the contact hole 66b.
  • the source electrode 64b is connected to its own gate electrode 62b through the contact hole 66a.
  • FIG. 12 is a circuit diagram showing a configuration of a liquid crystal display device 58 provided with an optical sensor circuit.
  • the liquid crystal display device 58 is different in that the scanning direction of the optical sensor circuit 40 provided in the liquid crystal display device 50 is different.
  • the optical sensor row selection wiring RW and the photodiode reset wiring RST of the liquid crystal display device 50 are arranged in parallel to the gate wiring M2-n, and the AMP power supply bus line Vs and the optical sensor output bus line Vout are the source wiring M1. -It was arranged parallel to m.
  • the AMP power supply bus line Vs and the optical sensor output bus line Vout are arranged in parallel to the gate wiring M2-n, and the optical sensor row selection wiring RW and the photodiode reset wiring RST. Are arranged in parallel to the source wiring M1-m.
  • the scanning direction of the display of the pixels 30 is from the top to the bottom in FIG.
  • the scanning direction of the optical sensor circuit 40 of the liquid crystal display device 58 is from the left to the right in FIG. 12, and the scanning direction of display by each pixel 30 is different from the scanning direction of sensing by the optical sensor circuit 40. .
  • liquid crystal display device 58 that can obtain the same effect as the liquid crystal display device 50 can be configured.
  • the circuit board of the present invention is a circuit board having a plurality of transistor elements on the same insulating substrate, and at least one of the plurality of transistor elements has a relatively high mobility.
  • the first thin film transistor element provided with a semiconductor having a relatively high mobility as a channel layer can obtain a high output voltage without increasing the size, so that a decrease in the aperture ratio of the pixel can be suppressed.
  • the thin film transistor element having the first characteristic and the thin film transistor element having the second characteristic can play different roles in terms of circuit. Therefore, according to said structure, the circuit board with the sufficient performance which mounted the electric circuit using each of the said different role can be obtained.
  • the first thin film transistor element is a top gate type transistor
  • the second thin film transistor element is a bottom gate type transistor. Therefore, the drain electrode and the source electrode of the second thin film transistor element and the gate electrode of the first thin film transistor can be formed in the same layer.
  • an electric circuit in which the output electrode of the second thin film transistor element and the gate electrode of the first thin film transistor are connected can be configured without providing a contact hole.
  • an electric circuit that controls the driving of the first thin film transistor in accordance with the output of the second thin film transistor electrode can be configured without providing a contact hole.
  • the first thin film transistor element and the second thin film transistor element constitute an optical sensor circuit, and the first thin film transistor element serves as a sensor output of the optical sensor circuit, It is preferable that the second thin film transistor element plays a role of an optical sensor element of the optical sensor circuit.
  • the first thin film transistor element including a relatively high mobility semiconductor as a channel layer can obtain a high output voltage while suppressing a decrease in the aperture ratio of the pixel, but has low sensitivity to light. Therefore, it is suitable for the role of the sensor output of the optical sensor circuit.
  • the second thin film transistor element including a semiconductor having a relatively high sensitivity to light as a channel layer has the second characteristic that the output voltage is low because the sensitivity to light is high but the mobility is low. Therefore, it is suitable for the role of the optical sensor element of the optical sensor circuit.
  • the first thin film transistor element and the second thin film transistor element can constitute an optical sensor circuit having excellent advantages of suppressing the decrease in aperture ratio of the pixel, high sensitivity, and high response speed.
  • an excellent advantage of such a photosensor circuit is that, for example, a plurality of photosensor circuits are mounted on an active matrix substrate in which pixels using liquid crystals are arranged in a matrix, thereby enabling a touch panel function or an image scanner function. This is extremely advantageous when a liquid crystal display device including the above is configured.
  • the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element are formed by the same conductive layer.
  • the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element can be connected without providing a contact hole.
  • the area of a region necessary for forming the contact hole can be reduced, and a decrease in the aperture ratio of the pixel can be suppressed.
  • the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element are preferably connected by wiring.
  • the first thin film transistor element can be operated based on the output from the drain electrode of the second thin film transistor.
  • the channel layer provided in the first thin film transistor element is made of an oxide semiconductor
  • the channel layer provided in the second thin film transistor element is made of an amorphous silicon semiconductor. It is preferable.
  • the first thin film transistor element having the first characteristic and the second thin film transistor element having the second characteristic can be configured.
  • a gate insulating film mainly composed of SiO 2 is sandwiched between the channel layer and the gate electrode of the first thin film transistor element, and the channel layer of the second thin film transistor element Between the gate layer and the gate electrode, a gate insulating film mainly composed of SiN X and a gate insulating film mainly composed of SiO 2 are sequentially stacked and sandwiched from the channel layer side, and are common to both gate insulating films
  • the SiO 2 layers to be formed are formed as the same layer.
  • the oxide semiconductor which comprises the channel layer of a 1st thin-film transistor element, and the amorphous silicon semiconductor which comprises the channel layer of a 2nd thin-film transistor element are in contact with the gate insulating film suitable for each, Can do.
  • the manufacturing process can be simplified and the cost can be reduced.
  • a protection circuit that protects the first transistor element that is a part of the plurality of transistor elements in a circuit, the protection circuit including a second transistor element that is a part of the plurality of transistor elements;
  • the first transistor element is composed of the first thin film transistor element
  • the second transistor element is composed of the second thin film transistor element.
  • the second transistor element constituting the protection circuit is a second thin film transistor element including an amorphous silicon semiconductor as a channel layer, whereby the second transistor element is a channel of the oxide semiconductor.
  • the occupation area of the protection circuit can be reduced.
  • the first transistor element that is protected in terms of the circuit is the first thin film transistor element, for example, the switching element of each pixel of the liquid crystal display device or a monolithic on the same insulating substrate as the switching element.
  • the transistor elements included in the driving circuit formed in the above the responsiveness or driving capability of the transistor elements that perform the main operation can be increased.
  • the display panel according to the present invention includes any one of the circuit boards described above. According to said structure, the display panel provided with each advantage of each circuit board already demonstrated can be provided.
  • a display device includes any one of the circuit boards described above. According to said structure, the display apparatus provided with each advantage of each circuit board already demonstrated can be provided.
  • the first thin film transistor element and the second thin film transistor element having different circuit roles are arranged on the same insulating substrate due to different types of semiconductors forming the channel layer.
  • a method for manufacturing a circuit board wherein an insulating film is formed on a channel layer of the first thin film transistor element and a gate electrode of the second semiconductor transistor element patterned on the insulating substrate. And forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second semiconductor transistor by patterning the same conductive layer on the insulating film. It is a feature.
  • the substrate can be manufactured at a low cost.
  • the present invention can be applied to a signal distribution device that supplies an output signal from a front-stage circuit to a subsequent-stage circuit through a plurality of distribution lines, and a display device using such a signal distribution device It can be applied to electronic devices such as.

Abstract

The disclosed circuit board (1) is provided with a plurality of transistor elements on the same insulating substrate (2); at least one of the abovementioned plurality of transistor elements is an oxide TFT (10) provided with an oxide semiconductor as a channel layer (11); at least one other of the abovementioned plurality of transistor elements is an a-SiTFT (20) that is provided with an amorphous silicon semiconductor as a channel layer (21) and that has a different purpose in the circuit from the oxide TFT (10); the oxide TFT (10) is a top-gate transistor; and the a-SiTFT (20) is a bottom-gate transistor. As a result, provided are: a structure that can increase the performance of the circuit board to which TFTs having different roles in the circuit are mounted and can reduce the area needed for mounting the TFTs; and a method for producing same.

Description

回路基板、表示装置および回路基板の製造方法Circuit board, display device, and circuit board manufacturing method
　本発明は、薄膜トランジスタを搭載した回路基板と、その回路基板を備えた表示装置と、その回路基板の製造方法とに関するものである。 The present invention relates to a circuit board on which a thin film transistor is mounted, a display device including the circuit board, and a method for manufacturing the circuit board.
　薄膜トランジスタ（ＴＦＴ）は、例えば液晶表示装置（ＬＣＤ）の画素のスイッチングを司る回路素子、あるいはＬＣＤのドライバを構成する回路素子などの用途に広く用いられてきた。近年では、ＬＣＤに要求される大画面、高精細および高フレームレートなどの性能向上を達成するために、ＴＦＴに対しても、高性能および高信頼性が益々求められている。 Thin film transistors (TFTs) have been widely used for applications such as circuit elements that control switching of pixels of a liquid crystal display device (LCD) or circuit elements that constitute LCD drivers. In recent years, high performance and high reliability are increasingly required for TFTs in order to achieve performance improvements such as large screen, high definition, and high frame rate required for LCDs.
　特許文献１には、ボトムゲート型（逆スタガ型）のＴＦＴの構成が開示されている。 Patent Document 1 discloses a configuration of a bottom gate type (reverse stagger type) TFT.
　図１４は、従来のボトムゲート型（逆スタガ型）ＴＦＴの構造を示す断面図である。当該ＴＦＴは、基板３０１上にゲート電極３０２を設け、その上に第１の絶縁膜３０３、チャネル層としての酸化物半導体層３０４、エッチングストップ層として機能する第２の絶縁膜３０５、ソース電極３０６およびドレイン電極３０７を設けることにより構成される。 FIG. 14 is a cross-sectional view showing the structure of a conventional bottom gate type (inverted stagger type) TFT. In the TFT, a gate electrode 302 is provided over a substrate 301, a first insulating film 303, an oxide semiconductor layer 304 as a channel layer, a second insulating film 305 functioning as an etching stop layer, and a source electrode 306. And a drain electrode 307.
　また、近年、例えば特許文献１に記載されているように、画素に対応した箇所に光センサ回路を備えることで、画像表示機能と共に、画像センシング機能を有する表示装置が開発されている。 In recent years, as described in Patent Document 1, for example, a display device having an image sensing function as well as an image sensing function has been developed by providing an optical sensor circuit at a location corresponding to a pixel.
　特許文献２には、１トランジスタ型光センサ回路が開示されている。 Patent Document 2 discloses a one-transistor photosensor circuit.
　図１５は、従来の光センサ回路を備えた画像表示装置の構成を表す回路図である。 FIG. 15 is a circuit diagram showing a configuration of an image display apparatus provided with a conventional photosensor circuit.
　図１５に示すように、画像表示装置１１０は、信号線Ｓ１０１、Ｓ１０２、Ｓ１０３、Ｓ１０４…と、ゲート線Ｇ１０１、Ｇ１０２、…とが互いに交差することで区画された表示部１１２及びセンサ部１１３とがマトリクス状に配されている。 As shown in FIG. 15, the image display device 110 includes a display unit 112 and a sensor unit 113 which are partitioned by signal lines S101, S102, S103, S104... And gate lines G101, G102,. Are arranged in a matrix.
　表示部１１２には、各画素の駆動用のＴＦＴ１１４が配されている。また、センサ部１１３には、ダイオード１１５と、ダイオード１１５の出力用アンプ回路であるＴｒ１１６とが配されている。このように、表示部１１２及びセンサ部１１３には、３種類の機能が異なるトランジスタが配されている。 The display unit 112 is provided with a TFT 114 for driving each pixel. The sensor unit 113 includes a diode 115 and a Tr 116 that is an amplifier circuit for output of the diode 115. Thus, the display unit 112 and the sensor unit 113 are provided with three types of transistors having different functions.
　ダイオード１１５のゲート電極１１５Ｇ及びソース電極１１５Ｓは、フォトダイオードリセット用配線ＲＳＴと接続され、ダイオード１１５のドレイン電極１１５Ｄは、ソース配線Ｓ１０２、Ｓ１０３及び出力バスラインＶｏｕｔと交差して、Ｔｒ１１６のゲート電極１１６Ｇと接続されている。そして、Ｔｒ１１６のソース電極１１６Ｓは、電源供給バスラインＶｓと接続され、Ｔｒ１１６のドレイン電極１１６Ｄは、信号線Ｓ１０１と並列に配されている出力バスラインＶｏｕｔと接続されている。 The gate electrode 115G and the source electrode 115S of the diode 115 are connected to the photodiode reset wiring RST, and the drain electrode 115D of the diode 115 intersects the source wirings S102 and S103 and the output bus line Vout, and the gate electrode 116G of the Tr 116 Connected with. The source electrode 116S of the Tr 116 is connected to the power supply bus line Vs, and the drain electrode 116D of the Tr 116 is connected to the output bus line Vout arranged in parallel with the signal line S101.
　また、昇圧用コンデンサの一方の端子部１４１ａは、ドレイン電極１１５Ｄ及びゲート電極１１６Ｇに接続されている。また、昇圧用コンデンサの一方の端子部１４１ｂは、光センサ行選択用配線ＲＷと接続されている。 Further, one terminal portion 141a of the boosting capacitor is connected to the drain electrode 115D and the gate electrode 116G. Further, one terminal portion 141b of the boosting capacitor is connected to the photosensor row selection wiring RW.
　図１６は、画像表示装置１１０の各トランジスタをボトムゲート型で構成した回路基板の様子を表す平面図である。 FIG. 16 is a plan view showing a state of a circuit board in which each transistor of the image display device 110 is configured as a bottom gate type.
　ＴＦＴ１１４、フォトダイオード１１５、Ｔｒ１１６は何れもボトムゲート型で構成されている。 The TFT 114, the photodiode 115, and the Tr 116 are all configured as a bottom gate type.
　画像表示装置１１０では、信号線Ｓ１０１、Ｓ１０２、Ｓ１０３、Ｓ１０４、及び電源供給バスラインＶｓ、出力バスラインＶｏｕｔに対して、ゲート線Ｇ１０１、Ｇ１０２、…、光センサ行選択用配線ＲＷ、フォトダイオードリセット用配線ＲＳＴ、補助容量配線Ｃｓは、下層で交差している。 In the image display device 110, the gate lines G101, G102,..., The photosensor row selection wiring RW, the photodiode reset, with respect to the signal lines S101, S102, S103, S104, the power supply bus line Vs, and the output bus line Vout. The main wiring RST and the auxiliary capacitance wiring Cs intersect at the lower layer.
　ダイオード１１５のゲート電極１１５Ｇは、フォトダイオードリセット用配線ＲＳＴから延びて設けられており、コンタクトホール１１７を介して、ソース電極１１５Ｓと接続している。また、フォトダイオード１１５のドレイン電極１１５Ｄは、ソース電極１１５Ｓと同層に形成されており、ゲート電極１１５Ｇと同層に形成された昇圧用コンデンサの一方の端子部１４１ａの延設部とコンタクトホール１１８を介して接続されている。端子部１４１ａは、信号線Ｓ１０２、Ｓ１０３、出力バスラインＶｏｕｔの下層で交差し、Ｔｒ１１６のゲート電極１１６Ｇと接続している。 The gate electrode 115G of the diode 115 is provided so as to extend from the photodiode reset wiring RST, and is connected to the source electrode 115S through the contact hole 117. In addition, the drain electrode 115D of the photodiode 115 is formed in the same layer as the source electrode 115S, and the extended portion of one terminal portion 141a of the boosting capacitor and the contact hole 118 formed in the same layer as the gate electrode 115G. Connected through. The terminal portion 141a intersects at the lower layer of the signal lines S102 and S103 and the output bus line Vout and is connected to the gate electrode 116G of the Tr116.
　また、昇圧用コンデンサの他方の端子部１４１ｂは、ソース電極１１５Ｓ及びドレイン電極１１５Ｄと同層に形成されたものであり、コンタクトホール１１９を介して光センサ行選択用配線ＲＷの延設部と接続されている。 The other terminal portion 141b of the boosting capacitor is formed in the same layer as the source electrode 115S and the drain electrode 115D, and is connected to the extending portion of the photosensor row selection wiring RW via the contact hole 119. Has been.
日本国公開特許公報「特開２００８-１６６７１６号公報（２００８年７月１７日公開）」Japanese Patent Publication “JP 2008-166716 A (published July 17, 2008)” 日本国公開特許公報「国際公開ＷＯ２００７－１４５３４７号（２００７年１２月２１日公開）」Japanese Patent Publication “International Publication WO 2007-145347 (published on Dec. 21, 2007)” 日本国公開特許公報「国際公開ＷＯ２００９－０２５１２０号（２００９年２月２６日公開）」Japanese Patent Publication “International Publication WO2009-025120 (published on Feb. 26, 2009)”
　特許文献１に開示された酸化物ＴＦＴは、例えば非晶質シリコンＴＦＴと比べると、移動度が大きいため、ＴＦＴサイズが小さくても、十分なＳＮ比の高い出力電圧を得ることができる反面、光に対する感度が極めて低いという欠点を持っている。 Since the oxide TFT disclosed in Patent Document 1 has a higher mobility than, for example, an amorphous silicon TFT, an output voltage with a sufficiently high S / N ratio can be obtained even if the TFT size is small. It has the disadvantage that its sensitivity to light is extremely low.
　特許文献２の開示を引くまでもなく、光を検出する光センサ回路には、センサ出力の役割を担うＴＦＴと、光センサ素子の役割を担うダイオード型のＴＦＴとが備えられている。このため、これら全てのＴＦＴを酸化物ＴＦＴとすると、センサ出力の役割を担うＴＦＴには問題が無い一方で、光センサ素子の役割を担うＴＦＴは、光に対する感度が極めて低くなるため、光センサ回路としては性能が不十分になるという問題を招いてしまう。 Needless to say, the disclosure of Patent Document 2 includes a TFT that plays a role of sensor output and a diode-type TFT that plays a role of a photosensor element. For this reason, if all these TFTs are oxide TFTs, there is no problem in the TFT that plays the role of sensor output, while the TFT that plays the role of the photosensor element has a very low sensitivity to light. As a circuit, the performance becomes insufficient.
　その一方で、非晶質シリコンＴＦＴは、光に対する感度が高いという長所を持っているものの、酸化物ＴＦＴより移動度が低いので、十分なＳＮ比の高い出力電圧を得るにはＴＦＴサイズを大きくする必要がある。このため、光センサ回路の全てのＴＦＴを非晶質シリコンＴＦＴとすると、光センサ素子の役割を担うＴＦＴには問題が無い一方で、センサ出力の役割を担うＴＦＴのサイズを大きくしなければならないため、例えば光センサ回路を内蔵した表示装置の場合、画素の開口率が小さくなるという問題を招いてしまう。 On the other hand, although amorphous silicon TFTs have the advantage of high sensitivity to light, they have a lower mobility than oxide TFTs, so the TFT size is increased to obtain an output voltage with a sufficiently high S / N ratio. There is a need to. For this reason, if all TFTs of the photosensor circuit are amorphous silicon TFTs, there is no problem with the TFT serving as the photosensor element, but the size of the TFT serving as the sensor output must be increased. Therefore, for example, in the case of a display device incorporating a photosensor circuit, there arises a problem that the aperture ratio of the pixel becomes small.
　また、センサ部１１３には、複数のトランジスタとコンデンサとが必要である。センサ部１１３に設けられた複数のトランジスタを、特許文献１のようなボトムゲート型のトランジスタで構成すると、センサ部１１３に設けられた複数のトランジスタとコンデンサとを接続するために、多数のコンタクトホールを設ける必要がある。 The sensor unit 113 requires a plurality of transistors and capacitors. When the plurality of transistors provided in the sensor unit 113 are configured by bottom-gate transistors as in Patent Document 1, a large number of contact holes are connected to connect the plurality of transistors provided in the sensor unit 113 and the capacitor. It is necessary to provide.
　例えば、図１６に示した例では、センサ部１１３には、コンタクトホール１１７、１１８、１１９の３個のコンタクトホールが形成されている。 For example, in the example shown in FIG. 16, the sensor portion 113 is formed with three contact holes 117, 118, and 119.
　このように、コンタクトホールを形成するには、コンタクトホールを形成する配線や電極にある程度の面積を確保する必要があり、センサ部１１３の面積を低減することができないという課題が生じる。このように、センサ部の面積が増加すると、開口率が低下してしまうことになる。 As described above, in order to form the contact hole, it is necessary to secure a certain area for the wiring and the electrode for forming the contact hole, which causes a problem that the area of the sensor unit 113 cannot be reduced. Thus, when the area of a sensor part increases, an aperture ratio will fall.
　本発明は、上記の問題に鑑みてなされたものであり、その目的は、回路的に役割の異なるＴＦＴが搭載された回路基板の性能を向上させると共に、ＴＦＴを搭載するために必要な面積を低減することができる構成と、その製造方法とを提供することにある。 The present invention has been made in view of the above problems, and its purpose is to improve the performance of a circuit board on which TFTs having different roles in circuit are mounted, and to reduce the area required for mounting TFTs. It is in providing the structure which can be reduced, and its manufacturing method.
　上記の課題を解決するために、本発明の回路基板は、同一の絶縁性基板上に複数のトランジスタ素子を備えた回路基板であって、上記複数のトランジスタ素子の少なくとも１つは、相対的に、移動度が大きく、かつ光に対する感度が低い半導体をチャネル層として備えた第１の薄膜トランジスタ素子であり、上記複数のトランジスタ素子の少なくとも他の１つは、上記第１の薄膜トランジスタ素子と回路的な役割が異なっており、かつ、相対的に、移動度が小さく、かつ光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子であり、上記第１の薄膜トランジスタ素子がトップゲート型のトランジスタであり、上記第２の薄膜トランジスタ素子がボトムゲート型のトランジスタであることを特徴としている。 In order to solve the above problems, a circuit board of the present invention is a circuit board having a plurality of transistor elements on the same insulating substrate, and at least one of the plurality of transistor elements is relatively , A first thin film transistor element including, as a channel layer, a semiconductor having high mobility and low sensitivity to light, and at least another one of the plurality of transistor elements is circuit-like with the first thin film transistor element A second thin film transistor element having a channel layer of a semiconductor having a different role and relatively low mobility and high sensitivity to light, wherein the first thin film transistor element is a top-gate transistor. The second thin film transistor element is a bottom-gate transistor.
　上記の構成において、相対的に、移動度が大きい半導体をチャネル層として備えた第１の薄膜トランジスタ素子は、サイズを大きくせずに高い出力電圧が得られるので、画素の開口率の低下を抑制できる反面、光に対する感度が低いという第１の特性を備えており、相対的に、光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子は、光に対する感度が高い反面、移動度が低いため出力電圧が低いという第２の特性を備えている。 In the above structure, the first thin film transistor element provided with a semiconductor having a relatively high mobility as a channel layer can obtain a high output voltage without increasing the size, so that a decrease in the aperture ratio of the pixel can be suppressed. On the other hand, the second thin film transistor element having the first characteristic that the sensitivity to light is low and the semiconductor layer having a relatively high sensitivity to light as the channel layer is high in sensitivity to light, but has high mobility. Since it is low, it has the second characteristic that the output voltage is low.
　つまり、上記第１の特性を備えた薄膜トランジスタ素子と、第２の特性を備えた薄膜トランジスタ素子とは、回路的に異なる役割を果たすことができる。したがって、上記の構成によれば、上記異なる役割のそれぞれを活かした電気回路を実装した性能の良い回路基板を得ることができる。 That is, the thin film transistor element having the first characteristic and the thin film transistor element having the second characteristic can play different roles in terms of circuit. Therefore, according to said structure, the circuit board with the sufficient performance which mounted the electric circuit using each of the said different role can be obtained.
　上記構成によると、第１の薄膜トランジスタ素子がトップゲート型のトランジスタであり、上記第２の薄膜トランジスタ素子がボトムゲート型のトランジスタである。このため、第２の薄膜トランジスタ素子のドレイン電極及びソース電極と、第１の薄膜トランジスタのゲート電極とを同層に形成することができる。 According to the above configuration, the first thin film transistor element is a top gate type transistor, and the second thin film transistor element is a bottom gate type transistor. Therefore, the drain electrode and the source electrode of the second thin film transistor element and the gate electrode of the first thin film transistor can be formed in the same layer.
　これにより、コンタクトホールを設けることなく第２の薄膜トランジスタ素子の出力電極と、第１の薄膜トランジスタのゲート電極とを接続した電気回路を構成することができる。このため、例えば上記電気回路として、第２の薄膜トランジスタ電極の出力に応じて、第１の薄膜トランジスタの駆動を制御するような電気回路を、コンタクトホールを設けることなく構成することができる。 Thus, an electric circuit in which the output electrode of the second thin film transistor element and the gate electrode of the first thin film transistor are connected can be configured without providing a contact hole. For this reason, for example, an electric circuit that controls the driving of the first thin film transistor in accordance with the output of the second thin film transistor electrode can be configured without providing a contact hole.
　従って、そのような電気回路の製造工程を簡略化できる。さらに、コンタクトホールを形成するために必要な領域の面積を低減することができるので、電気回路を搭載するために必要な領域の面積を低減することができ、さらなる画素の開口率低下の抑制効果を得ることができる。 Therefore, the manufacturing process of such an electric circuit can be simplified. Further, since the area of the region necessary for forming the contact hole can be reduced, the area of the region necessary for mounting the electric circuit can be reduced, and the effect of further reducing the aperture ratio of the pixel can be reduced. Can be obtained.
　本発明の回路基板の製造方法は、チャネル層を形成する半導体の種類が異なることにより、回路的な役割が互いに異なる第１の薄膜トランジスタ素子と第２の薄膜トランジスタ素子とを同一の絶縁性基板上に形成する回路基板の製造方法であって、上記絶縁性基板上にパターニングされた、上記第１の薄膜トランジスタ素子のチャネル層、及び、上記第２の半導体トランジスタ素子のゲート電極上に絶縁膜を形成する工程と、上記絶縁膜上に、同一の導電層のパターニングによって、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の半導体トランジスタのソース電極及びドレイン電極とを形成する工程とを含むことを特徴としている。 According to the method for manufacturing a circuit board of the present invention, the first thin film transistor element and the second thin film transistor element having different circuit roles are arranged on the same insulating substrate due to different types of semiconductors forming the channel layer. A method for manufacturing a circuit board, wherein an insulating film is formed on a channel layer of the first thin film transistor element and a gate electrode of the second semiconductor transistor element patterned on the insulating substrate. And forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second semiconductor transistor by patterning the same conductive layer on the insulating film. It is a feature.
　上記の構成によれば、回路基板の発明について既に説明したように、電気回路を設置するために必要な領域の面積を低減することができ、画素の開口率低下を抑制して高性能の回路基板を安価に製造することができる。 According to the above configuration, as already described in the invention of the circuit board, it is possible to reduce the area of the region necessary for installing the electric circuit, and to suppress a decrease in the aperture ratio of the pixel, thereby achieving a high-performance circuit. The substrate can be manufactured at a low cost.
　本発明の回路基板は、同一の絶縁性基板上に複数のトランジスタ素子を備えた回路基板であって、上記複数のトランジスタ素子の少なくとも１つは、相対的に、移動度が大きく、かつ光に対する感度が低い半導体をチャネル層として備えた第１の薄膜トランジスタ素子であり、上記複数のトランジスタ素子の少なくとも他の１つは、上記第１の薄膜トランジスタ素子と回路的な役割が異なっており、かつ、相対的に、移動度が小さく、かつ光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子であり、上記第１の薄膜トランジスタ素子がトップゲート型のトランジスタであり、上記第２の薄膜トランジスタ素子がボトムゲート型のトランジスタである。 The circuit board of the present invention is a circuit board provided with a plurality of transistor elements on the same insulating substrate, and at least one of the plurality of transistor elements has a relatively high mobility and resistance to light. A first thin film transistor element including a semiconductor having a low sensitivity as a channel layer, wherein at least another one of the plurality of transistor elements has a circuit role different from that of the first thin film transistor element, and a relative In particular, the second thin film transistor element includes, as a channel layer, a semiconductor having low mobility and high sensitivity to light, the first thin film transistor element is a top-gate transistor, and the second thin film transistor element Is a bottom-gate transistor.
　それゆえ、異なる役割のそれぞれを活かした電気回路を実装した性能の良い回路基板を得ることができると共に、電気回路の電気回路を搭載するために必要な領域の面積を低減することができるという効果を奏する。 Therefore, it is possible to obtain a high-performance circuit board on which an electric circuit utilizing each of the different roles is mounted, and to reduce the area required for mounting the electric circuit of the electric circuit. Play.
　本発明の回路基板の製造方法は、チャネル層を形成する半導体の種類が異なることにより、回路的な役割が互いに異なる第１の薄膜トランジスタ素子と第２の薄膜トランジスタ素子とを同一の絶縁性基板上に形成する回路基板の製造方法であって、上記絶縁性基板上にパターニングされた、上記第１の薄膜トランジスタ素子のチャネル層、及び、上記第２の半導体トランジスタ素子のゲート電極上に絶縁膜を形成する工程と、上記絶縁膜上に、同一の導電層のパターニングによって、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の半導体トランジスタのソース電極及びドレイン電極とを形成する工程とを含む。 According to the method for manufacturing a circuit board of the present invention, the first thin film transistor element and the second thin film transistor element having different circuit roles are arranged on the same insulating substrate due to different types of semiconductors forming the channel layer. A method for manufacturing a circuit board, wherein an insulating film is formed on a channel layer of the first thin film transistor element and a gate electrode of the second semiconductor transistor element patterned on the insulating substrate. Forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second semiconductor transistor by patterning the same conductive layer on the insulating film.
　それゆえ、高性能の回路基板を安価に製造することができるという効果を奏する。 Therefore, there is an effect that a high-performance circuit board can be manufactured at low cost.
本発明の実施の形態に係る回路基板の基本的な構成を概略的に示す断面図である。1 is a cross-sectional view schematically showing a basic configuration of a circuit board according to an embodiment of the present invention. 図１の回路基板の変形例を表す図である。It is a figure showing the modification of the circuit board of FIG. アクティブマトリクス基板上に複数の画素および光センサ回路が形成された液晶表示装置の回路構成を示す回路図である。It is a circuit diagram showing a circuit configuration of a liquid crystal display device in which a plurality of pixels and a photosensor circuit are formed on an active matrix substrate. 液晶表示装置のアクティブマトリクス基板の構成を表す平面図である。It is a top view showing the structure of the active matrix substrate of a liquid crystal display device. 回路基板の製造工程を順番に示す工程図である。It is process drawing which shows the manufacturing process of a circuit board in order. 液晶表示装置の構成を示す概略ブロック図である。It is a schematic block diagram which shows the structure of a liquid crystal display device. 図６に図示した領域Ｓｂ内に作り込まれた保護回路および画素の回路の構成を示す回路図である。FIG. 7 is a circuit diagram illustrating a configuration of a protection circuit and a pixel circuit formed in a region Sb illustrated in FIG. 6. 上記保護回路の他の回路構成を示す回路図である。It is a circuit diagram which shows the other circuit structure of the said protection circuit. 保護回路を構成する双方向ダイオードをＴＦＴの回路記号を用いて示す回路図である。It is a circuit diagram which shows the bidirectional | two-way diode which comprises a protection circuit using the circuit symbol of TFT. 保護回路およびＴＦＴの模式的な平面図である。It is a typical top view of a protection circuit and TFT. 図１０に示すＡ－Ａ’線に沿う、保護回路の模式的な断面図である。FIG. 11 is a schematic cross-sectional view of the protection circuit along the line A-A ′ shown in FIG. 10. 光センサ回路を備えた液晶表示装置の構成を表す回路図である。It is a circuit diagram showing the structure of the liquid crystal display device provided with the optical sensor circuit. 図１の回路基板の他の変形例を表す図である。It is a figure showing the other modification of the circuit board of FIG. 従来のボトムゲート型（逆スタガ型）ＴＦＴの構造を示す断面図である。It is sectional drawing which shows the structure of the conventional bottom gate type (reverse stagger type) TFT. 従来の光センサ回路を備えた画像表示装置の構成を表す回路図である。It is a circuit diagram showing the structure of the image display apparatus provided with the conventional photosensor circuit. 画像表示装置の各トランジスタをボトムゲート型で構成した様子を表す平面図である。It is a top view showing a mode that each transistor of the image display apparatus was comprised by the bottom gate type.
　〔実施の形態１〕
　本発明の第１の実施の形態について図面に基づいて説明すれば、以下のとおりである。但し、この実施の形態に記載されている構成部品の寸法、材質、形状、その相対配置などは、特に特定的な記載がない限り、この発明の範囲をそれのみに限定する趣旨ではなく、単なる説明例に過ぎない。 [Embodiment 1]
The following describes the first embodiment of the present invention with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only to those unless otherwise specified. This is just an example.
　（回路基板の基本構成）
　初めに、図１を参照しながら本発明の回路基板１の基本的な構成について説明する。図１は、回路基板１の基本的な構成を概略的に示す断面図である。 (Basic configuration of circuit board)
First, a basic configuration of the circuit board 1 of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a basic configuration of the circuit board 1.
　図１に示すように、回路基板１は、マトリクス状に配列された画素（図３参照）に対応して、同一の絶縁性基板２上に設けられた複数のトランジスタ素子を備えている。 As shown in FIG. 1, the circuit board 1 includes a plurality of transistor elements provided on the same insulating substrate 2 corresponding to the pixels (see FIG. 3) arranged in a matrix.
　その複数のトランジスタ素子の少なくとも１つは、第１の薄膜トランジスタ素子であり、上記第１の薄膜トランジスタ素子は、相対的に、移動度が大きく、かつ光に対する感度が低い半導体をチャネル層（活性層ともいう）１１として備えている。本実施の形態では、上記第１の薄膜トランジスタ素子が備えているチャネル層１１は、酸化物半導体からなるものとする。なお、上記第１の薄膜トランジスタ素子を、以降、酸化物ＴＦＴ１０と呼ぶ。酸化物半導体としては、Ｉｎ－Ｇａ－Ｚｎ－Ｏに代表されるアモルファス酸化物（ＩＧＺＯ）材料が適しており、酸化亜鉛（ＺｎＯ）に代表される多結晶材料を用いることもできる。 At least one of the plurality of transistor elements is a first thin film transistor element, and the first thin film transistor element includes a semiconductor having a relatively high mobility and low sensitivity to light as a channel layer (also referred to as an active layer). 11). In this embodiment mode, the channel layer 11 included in the first thin film transistor element is made of an oxide semiconductor. Hereinafter, the first thin film transistor element is referred to as an oxide TFT 10. As the oxide semiconductor, an amorphous oxide (IGZO) material typified by In—Ga—Zn—O is suitable, and a polycrystalline material typified by zinc oxide (ZnO) can also be used.
　また、上記複数のトランジスタ素子の少なくとも他の１つは、第２の薄膜トランジスタ素子であり、第２の薄膜トランジスタ素子は、相対的に、光に対する感度が高い半導体をチャネル層２１として備え、上記酸化物ＴＦＴ１０とは回路的な役割が異なっている。本実施の形態では、上記第２の薄膜トランジスタ素子が備えているチャネル層２１は、水素化アモルファスシリコン半導体（ａ－Ｓｉ：Ｈ）からなるものとする。なお、上記第２の薄膜トランジスタ素子を、以降、ａ－ＳｉＴＦＴ２０と呼ぶ。 At least another of the plurality of transistor elements is a second thin film transistor element, and the second thin film transistor element includes a semiconductor having a relatively high sensitivity to light as the channel layer 21, and the oxide layer The role of the circuit is different from that of the TFT 10. In the present embodiment, the channel layer 21 included in the second thin film transistor element is made of a hydrogenated amorphous silicon semiconductor (a-Si: H). The second thin film transistor element is hereinafter referred to as a-Si TFT 20.
　上記チャネル層２１の構成材料としては、アモルファスシリコン半導体に限られず、微結晶シリコン半導体（マイクロクリスタルシリコン半導体、すなわちμｃ－Ｓｉ）、またはａ－Ｓｉ：Ｈとμｃ－Ｓｉとを積層した積層半導体を採用することができる。積層半導体は、１層では受光し切れない波長帯域をカバーすることができるため、広い波長帯域に対して高感度の光センサ素子を形成することができる。 The constituent material of the channel layer 21 is not limited to an amorphous silicon semiconductor, but a microcrystalline silicon semiconductor (microcrystalline silicon semiconductor, that is, μc-Si), or a stacked semiconductor in which a-Si: H and μc-Si are stacked. Can be adopted. Since the laminated semiconductor can cover a wavelength band that cannot be received by one layer, a highly sensitive photosensor element can be formed for a wide wavelength band.
　また、酸化物ＴＦＴ１０およびａ－ＳｉＴＦＴ２０の細部の構成については、後述する。 The detailed configuration of the oxide TFT 10 and the a-Si TFT 20 will be described later.
　上記の構成において、酸化物ＴＦＴ１０は、サイズを大きくせずに高い出力電圧が得られる（移動度が、ａ－ＳｉＴＦＴの約２０倍）ので、画素の開口率の低下を抑制できる反面、光（特に可視光）に対する感度が低いという第１の特性を備えており、ａ－ＳｉＴＦＴ２０は、光に対する感度が高い反面、移動度が低いため出力電圧が低いという第２の特性を備えている。 In the above configuration, the oxide TFT 10 can obtain a high output voltage without increasing its size (mobility is about 20 times that of the a-Si TFT), so that it can suppress a decrease in the aperture ratio of the pixel, but light ( In particular, the a-Si TFT 20 has a second characteristic that the output voltage is low because the mobility is low, while the sensitivity to light is high.
　つまり、上記第１の特性を備えた酸化物ＴＦＴ１０と、第２の特性を備えたａ－ＳｉＴＦＴ２０とは、回路的に異なる役割を果たすことができる。したがって、上記の構成によれば、上記異なる役割のそれぞれを活かした電気回路を実装した性能の良い回路基板１を得ることができる。 That is, the oxide TFT 10 having the first characteristic and the a-Si TFT 20 having the second characteristic can play different roles in terms of circuit. Therefore, according to said structure, the circuit board 1 with the sufficient performance which mounted the electric circuit using each of the said different role can be obtained.
　さらに、詳細は後述するが、回路基板１を、光センサ回路を備えた表示装置の回路に適用する場合、ダイオード部は、ボトムゲート型の酸化物ＴＦＴ１０で構成し、出力アンプ（Ｔｒ部）用のトランジスタをトップゲート型のａ－ＳｉＴＦＴ２０で構成する。さらに、各画素を駆動するスイッチング素子もボトムゲート型の酸化物ＴＦＴ１０で構成する。 Further, as will be described in detail later, when the circuit board 1 is applied to a circuit of a display device including an optical sensor circuit, the diode portion is composed of a bottom gate type oxide TFT 10 and is used for an output amplifier (Tr portion). This transistor is composed of a top gate type a-Si TFT 20. Further, the switching element for driving each pixel is also composed of the bottom gate type oxide TFT 10.
　以下、酸化物ＴＦＴ１０のうち、Ｔｒ部に用いられる酸化物ＴＦＴ１０を酸化物ＴＦＴ１０ａと称し、表示部に設けられる各画素を駆動するスイッチング素子に用いられる酸化物ＴＦＴ１０を酸化物ＴＦＴ１０ｂと称して区別する場合がある。 Hereinafter, among the oxide TFTs 10, the oxide TFT 10 used in the Tr portion is referred to as an oxide TFT 10a, and the oxide TFT 10 used in a switching element for driving each pixel provided in the display portion is referred to as an oxide TFT 10b. There is a case.
　酸化物ＴＦＴ１０（１０ａ・１０ｂ）は、絶縁性基板２上にチャネル層１１（１１ａ・１１ｂ）、ソース電極１５（１５ａ・１５ｂ）、及びドレイン電極１６（１６ａ・１６ｂ）が並置されて成膜されている。チャネル層１１は、ソース電極１５及びドレイン電極１６それぞれの一部の側面を覆って形成されている。 The oxide TFT 10 (10a / 10b) is formed on the insulating substrate 2 with the channel layer 11 (11a / 11b), the source electrode 15 (15a / 15b), and the drain electrode 16 (16a / 16b) arranged in parallel. ing. The channel layer 11 is formed so as to cover part of the side surfaces of the source electrode 15 and the drain electrode 16.
　そして、絶縁性基板２上に、チャネル層１１、ソース電極１５、及びドレイン電極１６を覆って、ＳｉＯ２を主成分とするゲート絶縁膜３が成膜されている。ゲート絶縁膜３上に、ゲート電極１２（１２ａ・１２ｂ）が成膜されている。 A gate insulating film 3 mainly composed of SiO 2 is formed on the insulating substrate 2 so as to cover the channel layer 11, the source electrode 15 and the drain electrode 16. On the gate insulating film 3, gate electrodes 12 (12a and 12b) are formed.
　ａ－ＳｉＴＦＴ２０は、絶縁性基板２上にゲート電極２２が成膜されている。そして、ゲート電極２２を覆って、絶縁性基板２上にゲート絶縁膜３が成膜されている。ゲート絶縁膜３上には、チャネル層２１、ソース電極２５、及びドレイン電極２６が並置されて成膜されている。ソース電極２５及びドレイン電極２６それぞれは、チャネル層２１の一部の側面を覆って形成されている。 The a-Si TFT 20 has a gate electrode 22 formed on the insulating substrate 2. A gate insulating film 3 is formed on the insulating substrate 2 so as to cover the gate electrode 22. On the gate insulating film 3, a channel layer 21, a source electrode 25, and a drain electrode 26 are formed side by side. Each of the source electrode 25 and the drain electrode 26 is formed so as to cover a part of the side surface of the channel layer 21.
　そして、酸化物ＴＦＴ１０およびａ－ＳｉＴＦＴ２０は、ＳｉＮＸを主成分とするパッシベーション膜４によって被覆され保護されている。 The oxide TFT 10 and the a-Si TFT 20 are covered and protected by a passivation film 4 containing SiN X as a main component.
　このように、酸化物ＴＦＴ１０をトップゲート型で構成し、ａ－ＳｉＴＦＴ２０をボトムゲート型で構成することで、ａ－ＳｉＴＦＴ２０のソース電極２５及びドレイン電極２６と、酸化物ＴＦＴ１０のゲート電極１２とを同層に形成することができる。 Thus, the oxide TFT 10 is configured as a top gate type, and the a-Si TFT 20 is configured as a bottom gate type, whereby the source electrode 25 and the drain electrode 26 of the a-Si TFT 20 and the gate electrode 12 of the oxide TFT 10 are formed. It can be formed in the same layer.
　このため、コンタクトホールを設けることなくａ－ＳｉＴＦＴ２０のドレイン２６と、酸化物ＴＦＴ１０のゲート電極１２とを接続することができる。このため、例えば上記電気回路として、ａ－ＳｉＴＦＴ２０の出力に応じて、酸化物ＴＦＴ１０の駆動を制御するような光センサ回路などの電気回路を、コンタクトホールを設けることなく構成することができる。 Therefore, the drain 26 of the a-Si TFT 20 and the gate electrode 12 of the oxide TFT 10 can be connected without providing a contact hole. For this reason, for example, an electric circuit such as an optical sensor circuit that controls the driving of the oxide TFT 10 according to the output of the a-Si TFT 20 can be configured without providing a contact hole.
　従って、そのような電気回路の製造工程を簡略化でき、さらに、コンタクトホールを形成するために必要な領域の面積を低減することができるので、さらなる画素の開口率低下の抑制効果を得ることができる。 Therefore, the manufacturing process of such an electric circuit can be simplified, and further, the area of the region necessary for forming the contact hole can be reduced, so that the effect of further reducing the aperture ratio of the pixel can be obtained. it can.
　さらに、酸化物ＴＦＴ１０は、ａ－ＳｉＴＦＴ２０と比べて光に対する感度が低いので、各画素の表示部を駆動させるスイッチング素子としても好適に用いることができる。これにより、表示部を駆動させるスイッチング素子として、ａ－ＳｉＴＦＴ２０を用いた場合と比較して、バックライトから発光された光により、表示部を駆動させるスイッチング素子の半導体層の劣化を防止することができる。また、表示部を駆動させるスイッチング素子の最下層に、遮光層を設ける必要がないので、材料費や、製造工程の削減効果を得ることができる。 Furthermore, since the oxide TFT 10 has a lower sensitivity to light than the a-Si TFT 20, it can be suitably used as a switching element for driving the display portion of each pixel. This prevents the semiconductor layer of the switching element that drives the display unit from being deteriorated by the light emitted from the backlight as compared with the case where the a-Si TFT 20 is used as the switching element that drives the display unit. it can. In addition, since it is not necessary to provide a light shielding layer in the lowermost layer of the switching element that drives the display portion, it is possible to obtain material cost and an effect of reducing the manufacturing process.
　また、ａ－ＳｉＴＦＴ２０がボトムゲート型であることにより、例えば、バックライトを備え、バックライトの出射光強度を画素によって変調する表示装置に回路基板１を搭載した場合、バックライトの出射光をゲート電極２２が遮光することができる。これにより、チャネル層２１の特性劣化を、遮光膜を別途設けなくても防止できるという効果が得られる。 In addition, since the a-Si TFT 20 is a bottom gate type, for example, when the circuit board 1 is mounted on a display device that includes a backlight and modulates the emitted light intensity of the backlight by pixels, the emitted light from the backlight is gated. The electrode 22 can shield light. As a result, it is possible to prevent the deterioration of the characteristics of the channel layer 21 without providing a light shielding film separately.
　また、後で回路基板１の製造工程を詳述するが、ソース電極１５、ドレイン電極１６、及びゲート電極２２が同一の導電層によって形成されており、ゲート電極１２、ソース電極２５、及びドレイン電極２６が、同一の導電層によって形成されている。 Although the manufacturing process of the circuit board 1 will be described in detail later, the source electrode 15, the drain electrode 16, and the gate electrode 22 are formed of the same conductive layer, and the gate electrode 12, the source electrode 25, and the drain electrode are formed. 26 is formed of the same conductive layer.
　これにより、既に説明したように、バックライトを備えた表示装置に回路基板１を搭載した場合に、画素の開口率の低下抑制、高感度、応答速度が速いという優れた利点を劣化させることなく、製造工程を簡素化でき、コストを軽減できるという格段の効果を得ることができる。 Thus, as described above, when the circuit board 1 is mounted on a display device having a backlight, the excellent advantages of suppressing the decrease in aperture ratio of the pixel, high sensitivity, and fast response speed are not deteriorated. The manufacturing process can be simplified, and a remarkable effect that costs can be reduced can be obtained.
　（ＴＦＴの変形例）
　図２は、回路基板の変形例を表す断面図である。 (TFT variants)
FIG. 2 is a cross-sectional view illustrating a modification of the circuit board.
　図２のａ－ＳｉＴＦＴ２０ａに示すように、チャネル層２１の下層に、さらにＳｉＮＸを主成分とする第２のゲート絶縁膜（第２の絶縁層）２３を設けてもよい。 As shown in the a-Si TFT 20a in FIG. 2, a second gate insulating film (second insulating layer) 23 containing SiN X as a main component may be further provided below the channel layer 21.
　回路基板１ａでは、酸化物ＴＦＴ１０のチャネル層１１は、絶縁性基板２と、酸化物系のＳｉＯ２を主成分とするゲート絶縁膜３（第１の絶縁膜）とによって挟まれている。 In the circuit substrate 1a, the channel layer 11 of the oxide TFT 10 is sandwiched between the insulating substrate 2 and the gate insulating film 3 (first insulating film) containing oxide-based SiO 2 as a main component.
　一方、ａ－ＳｉＴＦＴ２０ａのゲート絶縁膜を、ＳｉＮＸ／ＳｉＯ２の２層構造（ゲート絶縁膜３及びゲート絶縁膜２３）とする結果、ａ－ＳｉＴＦＴ２０ａのチャネル層２１は、窒化物系のＳｉＮＸを主成分とするゲート絶縁膜２３と、ＳｉＮＸを主成分とするパッシベーション膜４とによって挟まれている。 On the other hand, the gate insulating film of the a-Si TFT 20a has a two-layer structure of SiN X / SiO 2 (gate insulating film 3 and gate insulating film 23). As a result, the channel layer 21 of the a-Si TFT 20a has a nitride-based SiN X Is sandwiched between a gate insulating film 23 containing SiN X as a main component and a passivation film 4 containing SiN X as a main component.
　さらに、ゲート絶縁膜３は、酸化物ＴＦＴ１０およびａ－ＳｉＴＦＴ２０に共通する同一の層として形成されている。 Furthermore, the gate insulating film 3 is formed as the same layer common to the oxide TFT 10 and the a-Si TFT 20.
　これにより、チャネル層１１を構成する酸化物半導体と、チャネル層２１を構成するアモルファスシリコン半導体とが、それぞれに適したゲート絶縁膜あるいはパッシベーション膜と接することができる。 Thereby, the oxide semiconductor constituting the channel layer 11 and the amorphous silicon semiconductor constituting the channel layer 21 can be in contact with a gate insulating film or a passivation film suitable for each.
　つまり、酸化物半導体に還元性材料が接すると、還元され、その特性が劣化するが、上記の構成では、チャネル層１１（酸化物半導体）にゲート絶縁膜３（酸化物）が接するため、その特性が劣化するのを防止できる。 That is, when the reducing material is in contact with the oxide semiconductor, it is reduced and its characteristics are deteriorated. However, in the above structure, the gate insulating film 3 (oxide) is in contact with the channel layer 11 (oxide semiconductor). It is possible to prevent the characteristics from deteriorating.
　また、アモルファスシリコン半導体に酸化物が接すると、酸化され、その特性が劣化するが、上記の構成では、チャネル層１１（アモルファスシリコン半導体）にゲート絶縁膜２３及びパッシベーション膜４（還元性材料）が接するため、その特性が劣化するのを防止できる。 In addition, when an oxide comes into contact with an amorphous silicon semiconductor, it is oxidized and its characteristics deteriorate. However, in the above configuration, the gate insulating film 23 and the passivation film 4 (reducing material) are formed on the channel layer 11 (amorphous silicon semiconductor). Therefore, it is possible to prevent the characteristics from deteriorating.
　また、チャネル層２１上に、ソース側とドレイン側とに分離された導電層２４が積層されている。導電層２４には、ｎ型不純物が比較的高濃度にドープされたｎ＋ａ－Ｓｉまたはｎ＋μｃ－Ｓｉを用いることができる。 Further, a conductive layer 24 separated on the source side and the drain side is stacked on the channel layer 21. For the conductive layer 24, n + a-Si or n + μc-Si doped with a relatively high concentration of n-type impurities can be used.
　（ＴＦＴの変形例２）
　上述のように、回路基板１ａでは、ａ－ＳｉＴＦＴ２０ａが備える絶縁膜を、上記第１のゲート絶縁膜３と第２のゲート絶縁膜２３との２層構造とした。 (TFT Modification 2)
As described above, in the circuit substrate 1a, the insulating film included in the a-Si TFT 20a has a two-layer structure including the first gate insulating film 3 and the second gate insulating film 23.
　しかし、第１のゲート絶縁膜３の主成分をＳｉＯ２からＳｉＮＸに置き換えることによって、図２の構成とは逆に、酸化物ＴＦＴ１０が備える絶縁膜を２層構造としてもよい。 However, by replacing the main component of the first gate insulating film 3 from SiO 2 to SiN X , the insulating film included in the oxide TFT 10 may have a two-layer structure, contrary to the configuration of FIG.
　その具体的な構成を図１３に示す。図１３は、図１、２に示す回路基板の基本的な構成の変形例を概略的に示す断面図である。なお、図１、２に示す部材と同じ部材には、同じ符号を付して、その詳細な説明を省略する。 The specific configuration is shown in FIG. FIG. 13 is a cross-sectional view schematically showing a modification of the basic configuration of the circuit board shown in FIGS. In addition, the same code | symbol is attached | subjected to the same member as the member shown in FIG.
　図１３に示す回路基板１ｂは、トップゲート型のトランジスタとして構成された酸化物ＴＦＴ１０（１０ｃ・１０ｄ）と、ボトムゲート型のトランジスタとして構成されたａ－ＳｉＴＦＴ２０ｂを備えている。 A circuit board 1b shown in FIG. 13 includes an oxide TFT 10 (10c and 10d) configured as a top gate type transistor and an a-Si TFT 20b configured as a bottom gate type transistor.
　より具体的には、酸化物ＴＦＴ１０ｃ・１０ｄは、ＳｉＮＸを主成分とする第１のゲート絶縁膜（第１の絶縁膜）３Ｂ上に、トップゲートとしてのゲート電極１２を備え、第１のゲート絶縁膜（第１の絶縁膜）３Ｂと、チャネル層１１との間に、チャネル層１１を覆って成膜されたＳｉＯ２を主成分とする第２のゲート絶縁膜（第２の絶縁層）２３Ｂを備えている。 More specifically, the oxide TFTs 10c and 10d include a gate electrode 12 as a top gate on a first gate insulating film (first insulating film) 3B mainly composed of SiN X , A second gate insulating film (second insulating layer) mainly composed of SiO 2 formed so as to cover the channel layer 11 between the gate insulating film (first insulating film) 3B and the channel layer 11. ) 23B.
　ａ－ＳｉＴＦＴ２０ｂは、酸化物ＴＦＴ１０（１０ｃ・１０ｄ）と共通して成膜されている第１のゲート絶縁膜（第１の絶縁膜）３Ｂの下層に、ボトムゲートとしてのゲート電極２２を備え、第１のゲート絶縁膜３Ｂ上に、直接、チャネル層２１が成膜されている。 The a-Si TFT 20b includes a gate electrode 22 as a bottom gate below the first gate insulating film (first insulating film) 3B formed in common with the oxide TFT 10 (10c and 10d). A channel layer 21 is formed directly on the first gate insulating film 3B.
　酸化物ＴＦＴ１０ｃ・１０ｄは、図２の酸化物ＴＦＴ１０ａ・１０ｂに第２のゲート絶縁膜２３Ｂを加えた以外の構成は、酸化物ＴＦＴ１０ａ・１０ｂと同じである。また、ａ－ＳｉＴＦＴ２０ｂは、図２のａ－ＳｉＴＦＴ２０ａから第２のゲート絶縁膜２３を取り除いた以外の構成は、ａ－ＳｉＴＦＴ２０ａと同じである。 The oxide TFTs 10c and 10d are the same as the oxide TFTs 10a and 10b except that a second gate insulating film 23B is added to the oxide TFTs 10a and 10b in FIG. The a-Si TFT 20b is the same as the a-Si TFT 20a except that the second gate insulating film 23 is removed from the a-Si TFT 20a in FIG.
　さらに、酸化物ＴＦＴ１０ｃ・１０ｄおよびａ－ＳｉＴＦＴ２０ｂが、ＳｉＮＸを主成分とするパッシベーション膜４によって被覆され保護されている点も、図２の構成と同じである。 Further, the oxide TFTs 10c and 10d and the a-Si TFT 20b are also covered and protected by the passivation film 4 mainly composed of SiN X , which is the same as the configuration of FIG.
　（回路の構成例－光センサ回路）
　光センサ回路を備えた液晶表示装置５０の等価回路を図３に示す。 (Circuit configuration example-optical sensor circuit)
FIG. 3 shows an equivalent circuit of the liquid crystal display device 50 provided with the photosensor circuit.
　図３は、アクティブマトリクス基板上に複数の画素３０および光センサ回路４０が形成された液晶表示装置５０の回路構成を示す回路図である。このアクティブマトリクス基板が、回路基板１に相当する。 FIG. 3 is a circuit diagram showing a circuit configuration of a liquid crystal display device 50 in which a plurality of pixels 30 and a photosensor circuit 40 are formed on an active matrix substrate. This active matrix substrate corresponds to the circuit substrate 1.
　なお、図３は、後で図６に基づいて説明する液晶表示装置５０に備えられた表示パネル５１に図示した領域Ｓａ内に作りこまれた回路構成を示している。 Note that FIG. 3 shows a circuit configuration built in the region Sa shown in the display panel 51 provided in the liquid crystal display device 50 described later with reference to FIG.
　表示パネル５１は、画素３０が配されている表示部３１と、光センサ回路（電気回路）４０が配されているセンサ部３２とがマトリクス状に配されている。 The display panel 51 includes a display unit 31 in which the pixels 30 are arranged and a sensor unit 32 in which an optical sensor circuit (electric circuit) 40 is arranged in a matrix.
　図３に示すように、光センサ回路４０は、酸化物ＴＦＴ１０ａと、ａ－ＳｉＴＦＴ２０と、昇圧用コンデンサ４１とを備えている。酸化物ＴＦＴ１０ａは、光センサ回路４０のセンサ出力（Ｔｒ：出力アンプ）の役割を担い、ａ－ＳｉＴＦＴ２０は、光センサ回路４０の光センサ素子（diode;ダイオード）の役割を担っている。 As shown in FIG. 3, the optical sensor circuit 40 includes an oxide TFT 10a, an a-Si TFT 20, and a boosting capacitor 41. The oxide TFT 10a serves as a sensor output (Tr: output amplifier) of the photosensor circuit 40, and the a-Si TFT 20 serves as a photosensor element (diode) of the photosensor circuit 40.
　より具体的には、光センサ回路４０は、センサ出力の役割を担うトランジスタを１つだけ用いた１Ｔ（トランジスタの略）方式の回路として構成されている。酸化物ＴＦＴ１０ａは、ソースフォロワトランジスタ（電圧フォロワトランジスタ）として機能する。 More specifically, the optical sensor circuit 40 is configured as a 1T (abbreviation of transistor) type circuit using only one transistor that plays a role of sensor output. The oxide TFT 10a functions as a source follower transistor (voltage follower transistor).
　酸化物ＴＦＴ１０ａのソース電極(入力電極)１５ａはＡＭＰ電源供給バスラインＶｓに接続され、ドレイン電極（出力電極）１６ａは光センサ出力バスラインＶoutに接続されている。ＡＭＰ電源供給バスラインＶｓおよび光センサ出力バスラインＶoutは、図４（後述する）に示すセンサ読出し回路５５に接続され、ＡＭＰ電源供給バスラインＶｓにはセンサ読出し回路５５から電源電圧ＶＤＤが印加される。 The source electrode (input electrode) 15a of the oxide TFT 10a is connected to the AMP power supply bus line Vs, and the drain electrode (output electrode) 16a is connected to the photosensor output bus line Vout. The AMP power supply bus line Vs and the optical sensor output bus line Vout are connected to a sensor read circuit 55 shown in FIG. 4 (described later), and the power supply voltage VDD is applied to the AMP power supply bus line Vs from the sensor read circuit 55. The
　また、酸化物ＴＦＴ１０ａのゲート（ベース）電極１２ａには、フォトダイオードとして機能するａ－ＳｉＴＦＴ２０のドレイン電極（出力電極）２６が接続されるとともに、昇圧用コンデンサ４１の一方の端子部である端子部４１ａが接続されている。 In addition, a drain electrode (output electrode) 26 of the a-Si TFT 20 functioning as a photodiode is connected to the gate (base) electrode 12a of the oxide TFT 10a, and a terminal portion which is one terminal portion of the boosting capacitor 41. 41a is connected.
　ａ－ＳｉＴＦＴ２０のソース電極（入力電極）２５及びゲート電極（ベース）２２は共に、フォトダイオードリセット用配線ＲＳＴに接続されることで短絡されている。すなわち、ａ－ＳｉＴＦＴ２０はダイオード接続の構成を有しており、ソース電極２５をアノード、ドレイン電極２６をカソードとするフォトダイオードとして機能する。 Both the source electrode (input electrode) 25 and the gate electrode (base) 22 of the a-Si TFT 20 are short-circuited by being connected to the photodiode reset wiring RST. That is, the a-Si TFT 20 has a diode connection configuration, and functions as a photodiode having the source electrode 25 as an anode and the drain electrode 26 as a cathode.
　さらに、ａ－ＳｉＴＦＴ２０のソース電極２５は、後述するように、図６に示すセンサ走査信号線駆動回路５４からリセット信号ＲＳＴが送られるフォトダイオードリセット用配線ＲＳＴに接続され、昇圧用コンデンサ４１の他方の端子部４１ｂは、光センサ行選択信号ＲＷＳが送られる光センサ行選択用配線ＲＷに接続されている。なお、光センサ行選択信号ＲＷは、マトリクス状に並んでいる光センサ回路の特定行を選択し、その特定行にある光センサ回路４０から検出信号を出力させる役割を持っている。 Further, the source electrode 25 of the a-Si TFT 20 is connected to a photodiode reset wiring RST to which a reset signal RST is sent from the sensor scanning signal line drive circuit 54 shown in FIG. The terminal portion 41b is connected to an optical sensor row selection wiring RW to which an optical sensor row selection signal RWS is sent. The photosensor row selection signal RW has a role of selecting a specific row of photosensor circuits arranged in a matrix and outputting a detection signal from the photosensor circuit 40 in the specific row.
　上記の構成において、酸化物ＴＦＴ１０ａは、サイズを大きくせずに高い出力電圧が得られるので、画素の開口率の低下を抑制できる反面、光に対する感度が低いという前記第１の特性を備えているから、光センサ回路４０のセンサ出力の役割に適している。 In the above-described configuration, the oxide TFT 10a has the first characteristic that it can suppress a decrease in the aperture ratio of the pixel but has low sensitivity to light because a high output voltage can be obtained without increasing the size. Therefore, it is suitable for the role of the sensor output of the optical sensor circuit 40.
　一方、ａ－ＳｉＴＦＴ２０は、光に対する感度が高い反面、移動度が低いため出力電圧が低いという前記第２の特性を備えているから、光センサ回路４０の光センサ素子の役割に適している。なお、光センサ素子には、紫外光領域、可視光領域および赤外光領域のいずれかの波長帯に対する感度を有していることが求められる。ａ－Ｓｉ：Ｈは、６００～７００ｎｍ付近に感度のピークを持つように、ほぼ可視光領域全体にわたる良好な感度を有している。 On the other hand, the a-Si TFT 20 is suitable for the role of the photosensor element of the photosensor circuit 40 because it has the second characteristic that the output voltage is low because of its low mobility but high sensitivity to light. The optical sensor element is required to have sensitivity to any wavelength band of the ultraviolet light region, the visible light region, and the infrared light region. a-Si: H has a good sensitivity over almost the entire visible light region so as to have a sensitivity peak in the vicinity of 600 to 700 nm.
　これにより、酸化物ＴＦＴ１０ａおよびａ－ＳｉＴＦＴ２０は、画素の開口率の低下抑制、高感度、応答速度が速いという優れた利点を備えた光センサ回路４０を構成することができる。ａ－ＳｉＴＦＴ２０のチャネル層２１に、μｃ－Ｓｉ、またはａ－Ｓｉ：Ｈとμｃ－Ｓｉとを積層した積層半導体を採用した場合でも同様である。 Thereby, the oxide TFT 10a and the a-Si TFT 20 can constitute the optical sensor circuit 40 having excellent advantages of suppressing the decrease in aperture ratio of the pixel, high sensitivity, and high response speed. The same applies when μc-Si or a laminated semiconductor in which a-Si: H and μc-Si are laminated is used for the channel layer 21 of the a-Si TFT 20.
　また、そのような光センサ回路４０の優れた利点は、例えば液晶を用いた画素がマトリクス状に配列されたアクティブマトリクス基板内に、複数の光センサ回路４０を実装することにより、タッチパネル機能または画像スキャナ機能などを備えた液晶表示装置を構成する場合に、極めて有利となる。 In addition, an excellent advantage of such a photosensor circuit 40 is that, for example, by mounting a plurality of photosensor circuits 40 in an active matrix substrate in which pixels using liquid crystals are arranged in a matrix, a touch panel function or an image can be obtained. This is extremely advantageous when a liquid crystal display device having a scanner function or the like is configured.
　（画素の回路図）
　図３に示すように、光センサ回路４０が設けられた液晶表示装置５０のアクティブマトリクス基板には、さらに、ゲート配線Ｍ２‐１（Ｍ２‐ｎ）、Ｍ２‐２（（Ｍ２‐ｎ＋１）…（ｎは画素の行番号を示す自然数）およびソース配線Ｍ１‐１（Ｍ１‐ｍ）、Ｍ１‐２（Ｍ１‐ｍ＋１）、Ｍ１‐３（Ｍ１‐ｍ＋３）、…（ｍは画素の列番号を示す自然数）がマトリクス状に形成され、両線の交差位置に対応して、上記画素３０を駆動するスイッチング素子が形成されている。 (Pixel circuit diagram)
As shown in FIG. 3, the active matrix substrate of the liquid crystal display device 50 provided with the photosensor circuit 40 is further provided with gate wirings M2-1 (M2-n), M2-2 ((M2-n + 1). n is a natural number indicating the pixel row number) and source lines M1-1 (M1-m), M1-2 (M1-m + 1), M1-3 (M1-m + 3),... (m indicates the column number of the pixel) Natural numbers) are formed in a matrix, and switching elements for driving the pixels 30 are formed corresponding to the intersection positions of the two lines.
　また、液晶表示装置５０のアクティブマトリクス基板は、液晶層を介して対向基板と対向して配置されている。対向基板には、画素３０に対応して、ゲート配線Ｍ２‐１、…、２‐ｎと平行に共通配線ＣＯＭ１、ＣＯＭ２、…が形成されている。 Further, the active matrix substrate of the liquid crystal display device 50 is disposed so as to face the counter substrate through the liquid crystal layer. On the counter substrate, common wiring lines COM1, COM2,... Are formed in parallel with the gate wiring lines M2-1,.
　画素３０を駆動するスイッチング素子は、酸化物ＴＦＴ１０ｂで構成されている。酸化物ＴＦＴ１０ｂのソース電極１５ｂはソース配線Ｍ１‐１に接続され、ドレイン電極１６ｂは容量を形成する液晶層を介して対向基板の共通配線ＣＯＭ１と接続されている。またドレイン電極１６ｂは補助容量とも接続されている。酸化物ＴＦＴ１０ｂのゲート電極１２ｂは、ゲート配線Ｍ２‐１と接続されている。 The switching element that drives the pixel 30 is composed of an oxide TFT 10b. The source electrode 15b of the oxide TFT 10b is connected to the source wiring M1-1, and the drain electrode 16b is connected to the common wiring COM1 of the counter substrate through a liquid crystal layer forming a capacitor. The drain electrode 16b is also connected to an auxiliary capacitor. The gate electrode 12b of the oxide TFT 10b is connected to the gate wiring M2-1.
　光センサ回路４０は全ての画素３０と同数設けてもよいし、画素３０の所定数の一群に対応して設けてもよい。光センサ回路４０の数は、光検出のために求められる解像度との兼ね合いにより、決めればよい。 The same number of photosensor circuits 40 as that of all the pixels 30 may be provided, or a predetermined number of groups of pixels 30 may be provided. The number of photosensor circuits 40 may be determined according to the balance with the resolution required for photodetection.
　図３に示す例では、３つの画素３０に１つの光センサ回路４０を設けている。３つの画素３０として、フルカラー表示に対応したＲ（赤），Ｇ（緑），Ｂ（青）の３つの画素を割り当てることができる。 In the example shown in FIG. 3, one photosensor circuit 40 is provided for three pixels 30. As the three pixels 30, three pixels of R (red), G (green), and B (blue) corresponding to full color display can be assigned.
　なお、ソース配線Ｍ１‐１、…は、前記ＡＭＰ電源供給バスラインＶｓを兼ね、ソース配線Ｍ１‐１に隣り合うソース配線Ｍ１‐２は、前記光センサ出力バスラインＶｏｕｔを兼ねてもよい。 The source wiring M1-1,... May also serve as the AMP power supply bus line Vs, and the source wiring M1-2 adjacent to the source wiring M1-1 may also serve as the photosensor output bus line Vout.
　（回路基板の平面図の構成）
　次に、図４を用いて、回路基板１を、液晶表示装置５０のアクティブマトリクス基板に用いた場合の構成例について説明する。 (Configuration of plan view of circuit board)
Next, a configuration example when the circuit board 1 is used as an active matrix substrate of the liquid crystal display device 50 will be described with reference to FIG.
　図４は、液晶表示装置のアクティブマトリクス基板の構成を表す平面図である。 FIG. 4 is a plan view showing the configuration of the active matrix substrate of the liquid crystal display device.
　ソース配線Ｍ１‐１、Ｍ１‐２、Ｍ１‐３、Ｍ１‐４…、ＡＭＰ電源供給バスラインＶｓ、前記光センサ出力バスラインＶｏｕｔは、ゲート配線Ｍ２‐１、Ｍ２‐２…、補助容量配線Ｃｓ、光センサ行選択信号ＲＷ、フォトダイオードリセット用配線ＲＳＴの下層で交差している。 Source wirings M1-1, M1-2, M1-3, M1-4,... AMP power supply bus line Vs, the optical sensor output bus line Vout are gate wirings M2-1, M2-2,. , The photosensor row selection signal RW and the photodiode reset wiring RST are crossed under each other.
　ａ－ＳｉＴＦＴ２０のソース電極２５は、フォトダイオードリセット用配線ＲＳＴから光センサ行選択信号ＲＷの方へ延びて設けられたフォトダイオードリセット用配線ＲＳＴの延設部である。ソース電極２５は、コンタクトホール２７を介してゲート電極２２と接続されている。ソース電極２５と同層に形成されたドレイン電極２６は、昇圧用コンデンサ４１の一方の端子部（配線）４１ａを介して、酸化物ＴＦＴ１０ａのゲート電極１２ａと接続している。 The source electrode 25 of the a-Si TFT 20 is an extending portion of the photodiode reset wiring RST provided so as to extend from the photodiode reset wiring RST toward the photosensor row selection signal RW. The source electrode 25 is connected to the gate electrode 22 through the contact hole 27. The drain electrode 26 formed in the same layer as the source electrode 25 is connected to the gate electrode 12a of the oxide TFT 10a through one terminal portion (wiring) 41a of the boosting capacitor 41.
　すなわち、回路基板１は、酸化物ＴＦＴ１０ａのゲート電極１２ａと、ａ－ＳｉＴＦＴ２０のドレイン電極（出力電極）２６とが、同一の導電層によって形成されており、端子部（配線）４１ａを介して接続されている。 That is, in the circuit board 1, the gate electrode 12a of the oxide TFT 10a and the drain electrode (output electrode) 26 of the a-Si TFT 20 are formed of the same conductive layer and are connected via the terminal portion (wiring) 41a. Has been.
　昇圧用コンデンサ４１は、一方の端子部４１ａの下層にゲート絶縁膜３が設けられ、さらにその下層に、昇圧用コンデンサ４１の他方の端子部４１ｂが形成されている。昇圧用コンデンサ４１の他方の端子部４１ｂは、光センサ行選択信号ＲＷからフォトダイオードリセット用配線ＲＳＴの方へ延びて形成されている延設部分と、コンタクトホール４２を介して接続されている。 In the boost capacitor 41, the gate insulating film 3 is provided in the lower layer of one terminal portion 41a, and the other terminal portion 41b of the boost capacitor 41 is formed in the lower layer. The other terminal portion 41 b of the boosting capacitor 41 is connected to an extended portion formed extending from the photosensor row selection signal RW toward the photodiode reset wiring RST via a contact hole 42.
　酸化物ＴＦＴ１０ａのドレイン電極１６ａは、ＡＭＰ電源供給バスラインＶｓを兼ねており、ソース電極１５ａは、光センサ出力バスラインＶoutを兼ねている。 The drain electrode 16a of the oxide TFT 10a also serves as the AMP power supply bus line Vs, and the source electrode 15a also serves as the optical sensor output bus line Vout.
　このように、ａ－ＳｉＴＦＴ２０をボトムゲート型で構成し、酸化物ＴＦＴ１０ａをトップゲート型で構成することにより、複数のソース配線を跨いで（図３の例ではソース配線Ｍ１‐２、Ｍ１‐３）ａ－ＳｉＴＦＴ２０のドレイン電極２６と、酸化物ＴＦＴ１０ａのゲート電極１２ａとを、端子部４１ａ等の配線を介して、同層であって、同一の材料から構成することができる。 In this way, the a-Si TFT 20 is configured as a bottom gate type, and the oxide TFT 10a is configured as a top gate type, thereby straddling a plurality of source lines (in the example of FIG. 3, the source lines M1-2, M1-3) ) The drain electrode 26 of the a-Si TFT 20 and the gate electrode 12a of the oxide TFT 10a can be made of the same material in the same layer via wiring such as the terminal portion 41a.
　これにより、酸化物ＴＦＴ１０ａのゲート電極１２ａと、ａ－ＳｉＴＦＴ２０のドレイン電極２６とをコンタクトホールを設けることなく接続することができる。このため、センサ部３２のコンタクトホールを形成するために必要な領域の面積を低減することができる。 Thereby, the gate electrode 12a of the oxide TFT 10a and the drain electrode 26 of the a-Si TFT 20 can be connected without providing a contact hole. For this reason, the area of a region necessary for forming the contact hole of the sensor unit 32 can be reduced.
　このため、表示部３１の面積を大きくすることができ、画素の開口率低下を抑制することができる。 For this reason, the area of the display part 31 can be enlarged and the aperture ratio reduction of a pixel can be suppressed.
　また、画素３０では、酸化物ＴＦＴ１０ｂが配されている。ソース電極１５ｂは、ソース配線Ｍ１‐１の延設部として構成されている。ドレイン電極１６ｂから、補助容量配線Ｃｓの方向へ配線が延びており、当該配線と、補助容量配線Ｃｓとはコンタクトホールを介して接続されている。 Further, in the pixel 30, an oxide TFT 10b is arranged. The source electrode 15b is configured as an extended portion of the source wiring M1-1. A wiring extends from the drain electrode 16b in the direction of the auxiliary capacitance wiring Cs, and the wiring and the auxiliary capacitance wiring Cs are connected via a contact hole.
　（回路基板の製造方法）
　回路基板１の製造方法について、簡素化のためのポイントを中心に据えて、以下に説明する。図５は、回路基板１の製造工程を順番に示す工程図である。 (Circuit board manufacturing method)
A method of manufacturing the circuit board 1 will be described below with a focus on the points for simplification. FIG. 5 is a process chart showing the manufacturing process of the circuit board 1 in order.
　本発明の回路基板の製造方法は、図１に基づいて説明したように、チャネル層１１、２１を形成する半導体の種類が異なることにより、回路的な役割が互いに異なる酸化物ＴＦＴ１０およびａ－ＳｉＴＦＴ２０を同一の絶縁性基板２上に形成するための製造方法である。 As described with reference to FIG. 1, the method of manufacturing a circuit board according to the present invention is different in that the oxide TFT 10 and the a-Si TFT 20 have different circuit roles due to different types of semiconductors forming the channel layers 11 and 21. Is a manufacturing method for forming on the same insulating substrate 2.
　図５の（ａ）に示すように、絶縁性基板２上に形成した同一の導電層のパターニングによって、酸化物ＴＦＴ１０のソース電極１５、ドレイン電極１６、及びａ－ＳｉＴＦＴ２０のゲート電極２２を同時に（すなわち同一の製造工程で）形成する（工程Ａ）。 As shown in FIG. 5A, the source electrode 15 and the drain electrode 16 of the oxide TFT 10 and the gate electrode 22 of the a-Si TFT 20 are simultaneously formed by patterning the same conductive layer formed on the insulating substrate 2 (see FIG. 5A). That is, it is formed (in the same manufacturing process) (process A).
　次に、図５の（ｂ）に示すように、ソース電極１５、ドレイン電極１６、及びゲート電極２２を覆って、絶縁性基板２上に酸化物半導体を成膜してパターニングし、酸化物ＴＦＴ１０のチャネル層１１を形成する（工程Ｂ）。 Next, as shown in FIG. 5B, an oxide semiconductor film is formed and patterned on the insulating substrate 2 so as to cover the source electrode 15, the drain electrode 16, and the gate electrode 22, and the oxide TFT 10 The channel layer 11 is formed (step B).
　続いて、図５の（ｃ）に示すように、絶縁性基板２上にパターニングされた、酸化物ＴＦＴ１０のチャネル層１１、及び、ａ－ＳｉＴＦＴ２０のゲート電極２２上に、ＳｉＯ２を主成分とするゲート絶縁膜３を形成する（工程Ｃ）。 Subsequently, as shown in FIG. 5C, SiO 2 is mainly contained on the channel layer 11 of the oxide TFT 10 and the gate electrode 22 of the a-Si TFT 20 patterned on the insulating substrate 2. A gate insulating film 3 is formed (step C).
　次に、図５の（ｄ）に示すように、ゲート絶縁膜３の上に、ａ－Ｓｉを成膜してパターニングし、ａ－ＳｉＴＦＴ２０のためのチャネル層２１を形成する（工程Ｄ）。なお、図２のａ－Ｓｉ膜２１ａに示したように、ゲート絶縁膜３上にＳｉＮＸを主成分とするゲート絶縁膜２３をパターニングしてから、そのゲート絶縁膜２３上にチャネル層２１をパターニングしてもよい。 Next, as shown in FIG. 5 (d), a-Si is deposited on the gate insulating film 3 and patterned to form a channel layer 21 for the a-Si TFT 20 (step D). As shown in the a-Si film 21a in FIG. 2, after patterning the gate insulating film 23 mainly composed of SiN X on the gate insulating film 3, the channel layer 21 is formed on the gate insulating film 23. Patterning may be performed.
　次に、図５の（ｅ）に示すように、ａ－ＳｉＴＦＴ２０にダイオード接続を設けるために、第１のゲート絶縁膜３にコンタクトホール２７を形成し、ゲート電極２２を局部的に露出させる（工程Ｅ）。 Next, as shown in FIG. 5E, in order to provide a diode connection to the a-Si TFT 20, a contact hole 27 is formed in the first gate insulating film 3, and the gate electrode 22 is locally exposed (see FIG. 5E). Step E).
　その後、ゲート絶縁膜３上に、同一の導電層のパターニングによって、酸化物ＴＦＴ１０のゲート電極１２と、ａ－ＳｉＴＦＴ２０のソース電極２５及びドレイン電極２６とを同時に（すなわち同一の製造工程で）形成する（工程Ｆ）。これにより、コンタクトホール２７を介して、ソース電極２５と、ゲート電極２２とが接続される。 Thereafter, the gate electrode 12 of the oxide TFT 10 and the source electrode 25 and the drain electrode 26 of the a-Si TFT 20 are simultaneously formed (that is, in the same manufacturing process) on the gate insulating film 3 by patterning the same conductive layer. (Process F). Thereby, the source electrode 25 and the gate electrode 22 are connected via the contact hole 27.
　最後に、図５の（ｆ）に示すように、全面をパッシベーション膜４によって被覆して（工程Ｇ）、回路基板１が完成する。 Finally, as shown in FIG. 5 (f), the entire surface is covered with the passivation film 4 (step G), and the circuit board 1 is completed.
　以上のように、本発明の回路基板の製造方法によれば、ゲート絶縁膜３を、酸化物ＴＦＴ１０およびａ－ＳｉＴＦＴ２０に共有された同一の層として同時に（すなわち同一の製造工程で）形成しているので、製造工程が煩雑にならず、簡素化でき、コストダウンを図ることができる。 As described above, according to the method for manufacturing a circuit board of the present invention, the gate insulating film 3 is formed simultaneously (that is, in the same manufacturing process) as the same layer shared by the oxide TFT 10 and the a-Si TFT 20. Therefore, the manufacturing process is not complicated, can be simplified, and cost can be reduced.
　さらに、酸化物ＴＦＴ１０のソース電極１５、ドレイン電極１６、ａ－ＳｉＴＦＴ２０のゲート電極２２を同一の導電層によって形成し、酸化物ＴＦＴ１０のゲート電極１２、ａ－ＳｉＴＦＴ２０のソース電極２５、ドレイン電極２６もまた、同一の導電層によって形成している。これにより、製造工程のさらなる簡素化とコストダウンとを図ることができる。 Further, the source electrode 15 and the drain electrode 16 of the oxide TFT 10 and the gate electrode 22 of the a-Si TFT 20 are formed by the same conductive layer, and the gate electrode 12 of the oxide TFT 10, the source electrode 25 and the drain electrode 26 of the a-Si TFT 20 are also formed. Further, they are formed by the same conductive layer. Thereby, the manufacturing process can be further simplified and the cost can be reduced.
　（表示装置の構成）
　回路基板１が搭載される表示装置の一例として、液晶表示装置５０の概要的な構成を説明する。 (Configuration of display device)
As an example of a display device on which the circuit board 1 is mounted, a schematic configuration of a liquid crystal display device 50 will be described.
　図６は、液晶表示装置５０の構成を示す概略ブロック図である。図６に示すように、液晶表示装置５０は、表示パネル５１、表示用走査信号線駆動回路５２、表示用映像信号線駆動回路５３、センサ走査信号線駆動回路５４、センサ読出し回路５５、センシング画像処理部５６、および電源回路５７を備えている。 FIG. 6 is a schematic block diagram showing the configuration of the liquid crystal display device 50. As shown in FIG. 6, the liquid crystal display device 50 includes a display panel 51, a display scanning signal line driving circuit 52, a display video signal line driving circuit 53, a sensor scanning signal line driving circuit 54, a sensor readout circuit 55, a sensing image. A processing unit 56 and a power supply circuit 57 are provided.
　表示パネル５１は、液晶層を挟持して封止したアクティブマトリクス基板（回路基板１）および対向基板を備えている。すなわち、表示パネル５１は、アクティブマトリクス基板として構成された回路基板１と、液晶層と、液晶層を介して上記アクティブマトリクス基板と対向配置されている対向基板とを備えている。 The display panel 51 includes an active matrix substrate (circuit substrate 1) and a counter substrate which are sealed with a liquid crystal layer interposed therebetween. That is, the display panel 51 includes a circuit substrate 1 configured as an active matrix substrate, a liquid crystal layer, and a counter substrate disposed to face the active matrix substrate via the liquid crystal layer.
　図１に示した前記絶縁性基板２は、アクティブマトリクス基板のベース部材であり、例えばガラス基板である。表示用走査信号線駆動回路５２、表示用映像信号線駆動回路５３、センサ走査信号線駆動回路５４およびセンサ読出し回路５５を構成する全ての回路素子は、絶縁性基板２上にモノリシックに形成されている。 The insulating substrate 2 shown in FIG. 1 is a base member of an active matrix substrate, for example, a glass substrate. All circuit elements constituting the display scanning signal line driving circuit 52, the display video signal line driving circuit 53, the sensor scanning signal line driving circuit 54, and the sensor readout circuit 55 are formed monolithically on the insulating substrate 2. Yes.
　「モノリシックに形成」とは、物理的プロセスおよび化学的プロセスの少なくとも一方により、絶縁性基板２上に直接に回路素子が形成されることを意味し、半導体回路がモジュールとしてガラス基板に実装されることを含まない。 “Monolithically formed” means that a circuit element is formed directly on the insulating substrate 2 by at least one of a physical process and a chemical process, and the semiconductor circuit is mounted on the glass substrate as a module. Does not include that.
　液晶表示装置５０が、ＶＡ（Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モードの液晶表示装置である場合、対向基板には、共通電極およびＲ（赤），Ｇ（緑），Ｂ（青）のカラーフィルタが設けられている。なお、本発明は、液晶モードの制約を受けないため、ＴＮ（Ｔｗｉｓｔｅｄ　Ｎｅｍａｔｉｃ）モードにも適用でき、さらに、共通電極がアクティブマトリクス基板に設けられた横電界印加方式とも呼ばれるＩＰＳ（Ｉｎ－Ｐｌａｎｅ　Ｓｗｉｔｃｈｉｎｇ）モードにも適用できる。 When the liquid crystal display device 50 is a VA (Vertical Alignment) mode liquid crystal display device, a common electrode and R (red), G (green), and B (blue) color filters are provided on the counter substrate. . Since the present invention is not limited by the liquid crystal mode, it can also be applied to a TN (Twisted Nematic) mode, and further, an IPS (In-Plane Switching) also called a lateral electric field application method in which a common electrode is provided on an active matrix substrate. ) Mode.
　表示用走査信号線駆動回路５２は、上記ゲート配線Ｍ２‐ｎを用いて、画素３０を１行ずつ選択的に走査する走査信号を生成する。表示用映像信号線駆動回路５３は、上記ソース配線Ｍ１‐ｍを用いて、各画素３０に映像信号を供給する。 The display scanning signal line drive circuit 52 uses the gate wiring M2-n to generate a scanning signal for selectively scanning the pixels 30 row by row. The display video signal line drive circuit 53 supplies a video signal to each pixel 30 using the source wiring M1-m.
　センサ走査信号線駆動回路５４は、光センサ回路４０を１行ずつ選択して駆動し、センサ読出し回路５５は、ＡＭＰ電源供給バスラインＶｓmを用いて、光センサ回路４０に一定電位の電源電圧ＶＤＤを供給するとともに、光センサ出力バスラインＶoutを用いて、光検出信号を光センサ回路４０から読み出す。 The sensor scanning signal line drive circuit 54 selects and drives the optical sensor circuit 40 row by row, and the sensor readout circuit 55 supplies the optical sensor circuit 40 with a constant power supply voltage VDD using the AMP power supply bus line Vsm. And a photodetection signal is read out from the photosensor circuit 40 using the photosensor output bus line Vout.
　センシング画像処理部５６は、ＬＳＩ（Ｌａｒｇｅ　Ｓｃａｌｅ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）およびＰＣ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｃｏｎｔｒｏｌｅｒ）などによって構成され、メモリされた画像処理プログラムに従って、光センサ回路４０が出力した光検出信号から、原稿のスキャン画像、あるいは表示パネル５１に対する指またはポインティングペンの位置などの情報を生成する。 The sensing image processing unit 56 includes an LSI (Large Scale Integrated Circuit), a PC (Programmable Controller), and the like, and scans an original from a photodetection signal output from the photosensor circuit 40 according to a stored image processing program, Alternatively, information such as the position of a finger or a pointing pen with respect to the display panel 51 is generated.
　電源回路５７は、各回路５２～５６へ、それぞれ必要な電源電圧を供給する。 The power supply circuit 57 supplies necessary power supply voltages to the circuits 52 to 56, respectively.
　なお、液晶表示装置５０の構成は、上述した構成に限定されることはなく、センサ走査信号線駆動回路５４またはセンサ読出し回路５５は、他の回路、具体的には表示用走査信号線駆動回路５２または表示用映像信号線駆動回路５３等に、機能として含まれていてもよく、センサ読出し回路５５が、センシング画像処理部５６の機能に含まれていても構わない。 The configuration of the liquid crystal display device 50 is not limited to the above-described configuration, and the sensor scanning signal line drive circuit 54 or the sensor readout circuit 55 is another circuit, specifically, a display scanning signal line drive circuit. 52 or the display video signal line drive circuit 53 or the like may be included as a function, and the sensor readout circuit 55 may be included in the function of the sensing image processing unit 56.
　（保護回路および画素回路）
　図７は、図６に図示した領域Ｓｂ内に作り込まれた保護回路６０および画素の回路の構成を示す回路図である。 (Protection circuit and pixel circuit)
FIG. 7 is a circuit diagram showing the configuration of the protection circuit 60 and the pixel circuit formed in the region Sb shown in FIG.
　回路基板１は、表示パネル５１を各回路（表示用走査信号線駆動回路５２、表示用映像信号線駆動回路５３、センサ走査信号線駆動回路５４、センサ読出し回路５５）と接続するための配線に、保護回路を備えていてもよい。 The circuit board 1 has wiring for connecting the display panel 51 to each circuit (display scanning signal line driving circuit 52, display video signal line driving circuit 53, sensor scanning signal line driving circuit 54, sensor reading circuit 55). A protection circuit may be provided.
　なお、図７では、光センサ回路４０の図示は省略している。 In FIG. 7, the optical sensor circuit 40 is not shown.
　回路基板１は、同一の絶縁性基板上に設けられた複数のトランジスタ素子の一部となる酸化物ＴＦＴ１０（１０ａ・１０ｂ）（第１のトランジスタ素子）を回路的に保護する保護回路６０であって、上記複数のトランジスタ素子の一部となるダイオード６１（第２のトランジスタ素子）を備えた保護回路６０を含む。ダイオード６１は、ａ－ＳｉＴＦＴからなっている。 The circuit board 1 is a protection circuit 60 that protects the oxide TFTs 10 (10a and 10b) (first transistor elements) which are part of a plurality of transistor elements provided on the same insulating substrate in a circuit manner. In addition, a protection circuit 60 including a diode 61 (second transistor element) that becomes a part of the plurality of transistor elements is included. The diode 61 is made of an a-Si TFT.
　すなわち、高抵抗が必要な素子（例：保護素子）にはａ－ＳｉＴＦＴを用い、低抵抗（高移動度）が好ましい素子（例：スイッチング素子）には酸化物半導体を用いている。 That is, an a-Si TFT is used for an element that requires high resistance (for example, a protection element), and an oxide semiconductor is used for an element that preferably has low resistance (high mobility) (for example, a switching element).
　より具体的には、図７に示すように、保護回路６０は、順方向が互いに逆向きのダイオード６１を並列に接続して構成した双方向ダイオードであり、全てのゲート配線Ｍ２‐ｎに対し１つずつ設けられている。このような保護回路６０は、ダイオードショートリングとも呼ばれている。保護回路６０の一端は、ゲート配線Ｇｎ（上述したゲート配線Ｍ２‐ｎに対応する）に接続され、他端は、例えば接地線に接続されている。 More specifically, as shown in FIG. 7, the protection circuit 60 is a bidirectional diode configured by connecting diodes 61 whose forward directions are opposite to each other in parallel, and all the gate wirings M2-n are connected to each other. One by one. Such a protection circuit 60 is also called a diode short ring. One end of the protection circuit 60 is connected to the gate line Gn (corresponding to the gate line M2-n described above), and the other end is connected to, for example, a ground line.
　これにより、静電気等による過大な電圧がゲート配線Ｍ２‐ｎに印加されたとしても、ゲート配線Ｍ２‐ｎと接地線との間に、速やかに放電パスを形成することができるので、画素回路を構成する薄膜トランジスタなどを過大な電圧から保護することができる。しかも、双方向ダイオードは、正負両極性の過大な電圧に対応することができる。 As a result, even if an excessive voltage due to static electricity or the like is applied to the gate wiring M2-n, a discharge path can be quickly formed between the gate wiring M2-n and the ground line. A thin film transistor to be formed can be protected from an excessive voltage. Moreover, the bidirectional diode can cope with an excessive voltage of both positive and negative polarities.
　また、図８に示すように、保護回路６０を、互いに隣り合うゲート配線Ｍ２‐ｎとゲート配線Ｍ２‐ｎ＋１とを接続するように設けることもできる。この場合には、１つのゲート配線Ｍ２‐ｎに印加された過大な電圧を、他のゲート配線に分散させることができるので、同様に、酸化物ＴＦＴ１０ａ等、画素３０に形成された画素回路を保護することができる。 Further, as shown in FIG. 8, the protection circuit 60 may be provided so as to connect the gate wiring M2-n and the gate wiring M2-n + 1 adjacent to each other. In this case, since an excessive voltage applied to one gate wiring M2-n can be distributed to other gate wirings, similarly, a pixel circuit formed in the pixel 30 such as the oxide TFT 10a is arranged. Can be protected.
　（保護回路のＴＦＴをａ－ＳｉＴＦＴとする意義）
　上述のように、保護回路６０のダイオード６１として機能するＴＦＴをａ－ＳｉＴＦＴとしている。これは、保護回路６０の占有面積を小さくし、表示パネル５１の額縁サイズを小さくするのに有効である。 (Significance of making the protection circuit TFT an a-Si TFT)
As described above, the TFT functioning as the diode 61 of the protection circuit 60 is an a-Si TFT. This is effective for reducing the area occupied by the protection circuit 60 and reducing the frame size of the display panel 51.
　酸化物ＴＦＴは、ａ－ＳｉＴＦＴに比べてオン抵抗が１桁小さいという特性を持っている。このため、酸化物ＴＦＴがオンになるしきい電圧は、ａ－ＳｉＴＦＴのしきい電圧より低いため、図７の保護回路６０に酸化物ＴＦＴを用いた場合には、ゲート配線Ｍ２‐ｎから接地線間で、電流のリークが発生するおそれがあり、図８の保護回路６０に酸化物ＴＦＴを用いた場合には、隣り合うゲート配線間で、電流のリークが発生するおそれがある。 The oxide TFT has a characteristic that the on-resistance is one digit smaller than that of the a-Si TFT. Therefore, the threshold voltage at which the oxide TFT is turned on is lower than the threshold voltage of the a-Si TFT. Therefore, when the oxide TFT is used in the protection circuit 60 of FIG. 7, the gate wiring M2-n is grounded. There is a risk of current leakage between the lines, and when an oxide TFT is used for the protection circuit 60 in FIG. 8, current leakage may occur between adjacent gate wirings.
　したがって、保護回路６０のダイオード６１として酸化物ＴＦＴを用いようとすると、図１０（後述する）に示すように、酸化物ＴＦＴのチャネル長（Ｌ長）を大きくし、それによって酸化物ＴＦＴの上記オン抵抗を大きくすることが必要になる。このため、酸化物ＴＦＴのサイズが大きくならざるを得ないので、表示パネル５１の狭額縁化に支障を来たす。 Therefore, when an oxide TFT is used as the diode 61 of the protection circuit 60, the channel length (L length) of the oxide TFT is increased as shown in FIG. It is necessary to increase the on-resistance. For this reason, the size of the oxide TFT must be increased, which hinders the narrowing of the frame of the display panel 51.
　なお、表示パネル５１の狭額縁化を優先して、保護回路６０を設けないようにすると、画素３０に設けられた画素回路で絶縁破壊などが発生し、表示パネル５１の製造の歩留まりが低下する。 Note that if the protective circuit 60 is not provided in preference to narrowing the frame of the display panel 51, dielectric breakdown or the like occurs in the pixel circuit provided in the pixel 30, and the manufacturing yield of the display panel 51 decreases. .
　このように、同一の絶縁性基板上で回路的に異なる役割を果たす薄膜トランジスタについて、その役割に応じて、最適な特性を持つ薄膜トランジスタを採用したので、回路基板の性能を最大限に向上させることができる。 As described above, for thin film transistors that play different roles on the same insulating substrate, thin film transistors having optimum characteristics are adopted according to their roles, so that the performance of the circuit board can be maximized. it can.
　すなわち、本実施形態では、液晶表示装置の各画素のスイッチング素子や、あるいは、このスイッチング素子と同一の絶縁性基板上にモノリシックに形成された表示用走査信号線駆動回路５２、表示用映像信号線駆動回路５３に含まれるトランジスタ素子のように、主たる動作を行うトランジスタ素子を、酸化物ＴＦＴとしたので、応答性または駆動能力を高くすることができる。 That is, in the present embodiment, the switching element of each pixel of the liquid crystal display device, or the display scanning signal line drive circuit 52 monolithically formed on the same insulating substrate as the switching element, the display video signal line Since the transistor element that performs the main operation, such as the transistor element included in the drive circuit 53, is an oxide TFT, responsiveness or drive capability can be increased.
　また、保護回路６０を構成するトランジスタ素子をａ－ＳｉＴＦＴとしたので、表示パネル５１の狭額縁化を図ることができ、表示装置の小型化に寄与する。 In addition, since the transistor elements constituting the protection circuit 60 are a-Si TFTs, the display panel 51 can be narrowed, which contributes to downsizing of the display device.
　これにより、小型で高性能の電気回路を搭載した回路基板および表示装置を提供することができる。 Thereby, it is possible to provide a circuit board and a display device on which a small and high-performance electric circuit is mounted.
　なお、保護回路６０は、前掲の特許文献３に開示されているように、ソース配線Ｍ１-ｍに設けることもでき、図７および図８の形態に限定されない。 Note that the protection circuit 60 can be provided in the source wiring M1-m as disclosed in the above-mentioned Patent Document 3, and is not limited to the forms shown in FIGS.
　（双方向ダイオードの平面構造）
　図９は、保護回路６０を構成する双方向ダイオードをＴＦＴの回路記号を用いて示す回路図である。図９に示すように、ドレインとゲートとを短絡させた２つのＴＦＴ６０ａ，６０ｂのうち、ＴＦＴ６０ａのゲートをゲート配線Ｇn（上述したゲート配線Ｍ２-ｎに対応する）に接続し、ＴＦＴ６０ｂのゲートを隣りのゲート配線Ｇｎ+1（上述したゲート配線Ｍ２-ｎ＋１に対応する）に接続し、さらに、各々のドレインを相手のゲートに接続している。 (Planar structure of bidirectional diode)
FIG. 9 is a circuit diagram showing bidirectional diodes constituting the protection circuit 60 using circuit symbols of TFTs. As shown in FIG. 9, of the two TFTs 60a and 60b whose drain and gate are short-circuited, the gate of the TFT 60a is connected to the gate wiring Gn (corresponding to the gate wiring M2-n described above), and the gate of the TFT 60b is connected. It is connected to the adjacent gate wiring Gn + 1 (corresponding to the above-mentioned gate wiring M2-n + 1), and each drain is connected to the other gate.
　図１０は、保護回路６０およびＴＦＴの模式的な平面図である。図１０に示すように、ＴＦＴ６０ａにおいて、ゲート配線Ｇnからゲート配線Ｇn+1の方へゲート電極６２ａが張り出し、ゲート電極６２ａの上方に設けられたａ－Ｓｉ半導体のチャネル層６３ａ上で、ソース電極６４ａとドレイン電極６５ａとが、間隔を空けて対向している。 FIG. 10 is a schematic plan view of the protection circuit 60 and the TFT. As shown in FIG. 10, in the TFT 60a, the gate electrode 62a extends from the gate line Gn to the gate line Gn + 1, and the source electrode is formed on the channel layer 63a of the a-Si semiconductor provided above the gate electrode 62a. 64a and the drain electrode 65a are opposed to each other with a gap therebetween.
　ソース電極６４ａは、コンタクトホール６６ａを介して、ゲート電極６２ａに接続されている。ドレイン電極６５ａは、コンタクトホール６６ｂを介して、ＴＦＴ６０ｂのゲート電極６２ｂに接続されている。 The source electrode 64a is connected to the gate electrode 62a through the contact hole 66a. The drain electrode 65a is connected to the gate electrode 62b of the TFT 60b through the contact hole 66b.
　ＴＦＴ６０ｂにおいても同様に、ゲート配線Ｇn+1からゲート配線Ｇnの方へゲート電極６２ｂが張り出し、ゲート電極６２ｂの上方に設けられたａ－Ｓｉ半導体のチャネル層６３ｂ上で、ソース電極６４ｂとドレイン電極６５ｂとが、間隔を空けて対向している。 Similarly, in the TFT 60b, the gate electrode 62b extends from the gate wiring Gn + 1 to the gate wiring Gn, and the source electrode 64b and the drain electrode are formed on the channel layer 63b of the a-Si semiconductor provided above the gate electrode 62b. 65b is opposed to each other with a gap.
　ソース電極６４ｂは、コンタクトホール６７ｂを介して、ゲート電極６２ｂに接続されている。ドレイン電極６５ｂは、コンタクトホール６７ａを介して、ＴＦＴ６０ａのゲート電極６２ａに接続されている。 The source electrode 64b is connected to the gate electrode 62b through the contact hole 67b. The drain electrode 65b is connected to the gate electrode 62a of the TFT 60a through the contact hole 67a.
　チャネル層６３ａおよびチャネル層６３ｂを、いずれもａ－Ｓｉ半導体によって形成しているので、図１０に示すチャネル幅（Ｗ長）を酸化物ＴＦＴと変えずに、チャネル長（Ｌ長）を酸化物ＴＦＴより短くして、必要なオン抵抗を得ることができる。 Since both the channel layer 63a and the channel layer 63b are formed of an a-Si semiconductor, the channel length (L length) is changed to an oxide without changing the channel width (W length) shown in FIG. The required on-resistance can be obtained by making it shorter than the TFT.
　（双方向ダイオードの断面構造）
　図１１は、図１０に示すＡ－Ａ’線に沿う、保護回路６０の模式的な断面図である。図１１に示すように、ＴＦＴ６０ａおよび６０ｂは、同一の絶縁性基板２上に形成され、パッシベーション膜４によって被覆され保護されている。 (Cross-sectional structure of bidirectional diode)
FIG. 11 is a schematic cross-sectional view of the protection circuit 60 taken along the line AA ′ shown in FIG. As shown in FIG. 11, the TFTs 60 a and 60 b are formed on the same insulating substrate 2, and are covered and protected by the passivation film 4.
　ＴＦＴ６０ａおよび６０ｂにおいて、絶縁性基板２上にゲート電極６２ａおよび６２ｂが形成され、ゲート電極６２ａおよび６２ｂを前記第１のゲート絶縁膜３が被覆している。ゲート電極６２ａおよび６２ｂのそれぞれの上方位置において、第１のゲート絶縁膜３上に、前記第２のゲート絶縁膜２３に相当する第２のゲート絶縁膜２３ａおよび２３ｂが積層されている。 In the TFTs 60a and 60b, gate electrodes 62a and 62b are formed on the insulating substrate 2, and the first gate insulating film 3 covers the gate electrodes 62a and 62b. Second gate insulating films 23a and 23b corresponding to the second gate insulating film 23 are stacked on the first gate insulating film 3 at positions above the gate electrodes 62a and 62b, respectively.
　さらに、第２のゲート絶縁膜２３ａおよび２３ｂのそれぞれの上に、ａ－Ｓｉ半導体のチャネル層６３ａおよび６３ｂが積層されている。チャネル層６３ａおよび６３ｂの上には、ギャップを設けた導電層６８ａおよび６８ｂが積層され、導電層６８ａ上には、間隔を空けて対向したソース電極６４ａおよびドレイン電極６５ａが形成され、導電層６８ｂ上には、間隔を空けて対向したソース電極６４ｂおよびドレイン電極６５ｂが形成されている。 Further, channel layers 63a and 63b of an a-Si semiconductor are stacked on the second gate insulating films 23a and 23b, respectively. Conductive layers 68a and 68b with gaps are stacked on the channel layers 63a and 63b, and a source electrode 64a and a drain electrode 65a facing each other with a gap are formed on the conductive layer 68a. On the top, a source electrode 64b and a drain electrode 65b facing each other with a gap are formed.
　ドレイン電極６５ａは、ＴＦＴ６０ｂのゲート電極６２ｂ上に延び出し、コンタクトホール６６ｂを介してゲート電極６２ｂに接続されている。 The drain electrode 65a extends on the gate electrode 62b of the TFT 60b and is connected to the gate electrode 62b through the contact hole 66b.
　ソース電極６４ａは、コンタクトホール６６ａを介して、自らのゲート電極６２ａに接続されている。 The source electrode 64a is connected to its own gate electrode 62a through a contact hole 66a.
　一方、ドレイン電極６５ｂは、ＴＦＴ６０ａのゲート電極６２ａ上に延び出し、コンタクトホール６６ｂを介してゲート電極６２ａに接続されている。 On the other hand, the drain electrode 65b extends on the gate electrode 62a of the TFT 60a and is connected to the gate electrode 62a through the contact hole 66b.
　ソース電極６４ｂは、コンタクトホール６６ａを介して、自らのゲート電極６２ｂに接続されている。 The source electrode 64b is connected to its own gate electrode 62b through the contact hole 66a.
　〔実施の形態２〕
　次に、図１２を用いて、本発明の第２の実施の形態について説明する。 [Embodiment 2]
Next, a second embodiment of the present invention will be described with reference to FIG.
　図１２は、光センサ回路を備えた液晶表示装置５８の構成を表す回路図である。 FIG. 12 is a circuit diagram showing a configuration of a liquid crystal display device 58 provided with an optical sensor circuit.
　液晶表示装置５８は、液晶表示装置５０が備える光センサ回路４０のスキャン方向が異なる点で相違する。 The liquid crystal display device 58 is different in that the scanning direction of the optical sensor circuit 40 provided in the liquid crystal display device 50 is different.
　液晶表示装置５０の光センサ行選択用配線ＲＷ及びフォトダイオードリセット用配線ＲＳＴは、ゲート配線Ｍ２‐ｎに平行に配され、ＡＭＰ電源供給バスラインＶｓ及び光センサ出力バスラインＶoutは、ソース配線Ｍ１‐ｍに平行に配されていた。 The optical sensor row selection wiring RW and the photodiode reset wiring RST of the liquid crystal display device 50 are arranged in parallel to the gate wiring M2-n, and the AMP power supply bus line Vs and the optical sensor output bus line Vout are the source wiring M1. -It was arranged parallel to m.
　一方、液晶表示装置５８では、ＡＭＰ電源供給バスラインＶｓ及び光センサ出力バスラインＶoutは、ゲート配線Ｍ２‐ｎに平行に配されており、光センサ行選択用配線ＲＷ及びフォトダイオードリセット用配線ＲＳＴは、ソース配線Ｍ１‐ｍに平行に配されている。 On the other hand, in the liquid crystal display device 58, the AMP power supply bus line Vs and the optical sensor output bus line Vout are arranged in parallel to the gate wiring M2-n, and the optical sensor row selection wiring RW and the photodiode reset wiring RST. Are arranged in parallel to the source wiring M1-m.
　液晶表示装置５８では、画素３０の表示のスキャン方向は、図１２の紙面上から下方向となる。一方、液晶表示装置５８の光センサ回路４０のスキャン方向は、図１２の紙面左から右方向となり、各画素３０による表示のスキャン方向と、光センサ回路４０によるセンシングのスキャン方向とが異なっている。 In the liquid crystal display device 58, the scanning direction of the display of the pixels 30 is from the top to the bottom in FIG. On the other hand, the scanning direction of the optical sensor circuit 40 of the liquid crystal display device 58 is from the left to the right in FIG. 12, and the scanning direction of display by each pixel 30 is different from the scanning direction of sensing by the optical sensor circuit 40. .
　このようにして、液晶表示装置５０と同様の効果が得られる液晶表示装置５８を構成することもできる。 In this way, the liquid crystal display device 58 that can obtain the same effect as the liquid crystal display device 50 can be configured.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
　以上のように、本発明の回路基板は、同一の絶縁性基板上に複数のトランジスタ素子を備えた回路基板であって、上記複数のトランジスタ素子の少なくとも１つは、相対的に、移動度が大きく、かつ光に対する感度が低い半導体をチャネル層として備えた第１の薄膜トランジスタ素子であり、上記複数のトランジスタ素子の少なくとも他の１つは、上記第１の薄膜トランジスタ素子と回路的な役割が異なっており、かつ、相対的に、移動度が小さく、かつ光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子であり、上記第１の薄膜トランジスタ素子がトップゲート型のトランジスタであり、上記第２の薄膜トランジスタ素子がボトムゲート型のトランジスタであることを特徴としている。 As described above, the circuit board of the present invention is a circuit board having a plurality of transistor elements on the same insulating substrate, and at least one of the plurality of transistor elements has a relatively high mobility. A first thin film transistor element including a semiconductor that is large and has low sensitivity to light as a channel layer, and at least another one of the plurality of transistor elements has a circuit role different from that of the first thin film transistor element. And a second thin film transistor element provided with a semiconductor having a relatively low mobility and high sensitivity to light as a channel layer, wherein the first thin film transistor element is a top-gate transistor, The second thin film transistor element is a bottom-gate transistor.
　上記の構成において、相対的に、移動度が大きい半導体をチャネル層として備えた第１の薄膜トランジスタ素子は、サイズを大きくせずに高い出力電圧が得られるので、画素の開口率の低下を抑制できる反面、光に対する感度が低いという第１の特性を備えており、相対的に、光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子は、光に対する感度が高い反面、移動度が低いため出力電圧が低いという第２の特性を備えている。 In the above structure, the first thin film transistor element provided with a semiconductor having a relatively high mobility as a channel layer can obtain a high output voltage without increasing the size, so that a decrease in the aperture ratio of the pixel can be suppressed. On the other hand, the second thin film transistor element having the first characteristic that the sensitivity to light is low and the semiconductor layer having a relatively high sensitivity to light as the channel layer is high in sensitivity to light, but has high mobility. Since it is low, it has the second characteristic that the output voltage is low.
　つまり、上記第１の特性を備えた薄膜トランジスタ素子と、第２の特性を備えた薄膜トランジスタ素子とは、回路的に異なる役割を果たすことができる。したがって、上記の構成によれば、上記異なる役割のそれぞれを活かした電気回路を実装した性能の良い回路基板を得ることができる。 That is, the thin film transistor element having the first characteristic and the thin film transistor element having the second characteristic can play different roles in terms of circuit. Therefore, according to said structure, the circuit board with the sufficient performance which mounted the electric circuit using each of the said different role can be obtained.
　上記構成によると、第１の薄膜トランジスタ素子がトップゲート型のトランジスタであり、上記第２の薄膜トランジスタ素子がボトムゲート型のトランジスタである。このため、第２の薄膜トランジスタ素子のドレイン電極及びソース電極と、第１の薄膜トランジスタのゲート電極とを同層に形成することができる。 According to the above configuration, the first thin film transistor element is a top gate type transistor, and the second thin film transistor element is a bottom gate type transistor. Therefore, the drain electrode and the source electrode of the second thin film transistor element and the gate electrode of the first thin film transistor can be formed in the same layer.
　これにより、コンタクトホールを設けることなく第２の薄膜トランジスタ素子の出力電極と、第１の薄膜トランジスタのゲート電極とを接続した電気回路を構成することができる。このため、例えば上記電気回路として、第２の薄膜トランジスタ電極の出力に応じて、第１の薄膜トランジスタの駆動を制御するような電気回路を、コンタクトホールを設けることなく構成することができる。 Thus, an electric circuit in which the output electrode of the second thin film transistor element and the gate electrode of the first thin film transistor are connected can be configured without providing a contact hole. For this reason, for example, an electric circuit that controls the driving of the first thin film transistor in accordance with the output of the second thin film transistor electrode can be configured without providing a contact hole.
　従って、そのような電気回路の製造工程を簡略化できる。さらに、コンタクトホールを形成するために必要な領域の面積を低減することができるので、電気回路を搭載するために必要な領域の面積を低減することができ、さらなる画素の開口率低下の抑制効果を得ることができる。 Therefore, the manufacturing process of such an electric circuit can be simplified. Further, since the area of the region necessary for forming the contact hole can be reduced, the area of the region necessary for mounting the electric circuit can be reduced, and the effect of further reducing the aperture ratio of the pixel can be reduced. Can be obtained.
　本発明の回路基板では、上記第１の薄膜トランジスタ素子および第２の薄膜トランジスタ素子は、光センサ回路を構成しており、上記第１の薄膜トランジスタ素子は、上記光センサ回路のセンサ出力の役割を担い、上記第２の薄膜トランジスタ素子は、上記光センサ回路の光センサ素子の役割を担っていることが好ましい。 In the circuit board of the present invention, the first thin film transistor element and the second thin film transistor element constitute an optical sensor circuit, and the first thin film transistor element serves as a sensor output of the optical sensor circuit, It is preferable that the second thin film transistor element plays a role of an optical sensor element of the optical sensor circuit.
　上記の構成において、相対的に、移動度が大きい半導体をチャネル層として備えた第１の薄膜トランジスタ素子は、画素の開口率の低下を抑制しつつ高い出力電圧が得られる反面、光に対する感度が低いという前記第１の特性を備えているから、光センサ回路のセンサ出力の役割に適している。 In the above configuration, the first thin film transistor element including a relatively high mobility semiconductor as a channel layer can obtain a high output voltage while suppressing a decrease in the aperture ratio of the pixel, but has low sensitivity to light. Therefore, it is suitable for the role of the sensor output of the optical sensor circuit.
　一方、相対的に、光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子は、光に対する感度が高い反面、移動度が低いため出力電圧が低いという前記第２の特性を備えているから、光センサ回路の光センサ素子の役割に適している。 On the other hand, the second thin film transistor element including a semiconductor having a relatively high sensitivity to light as a channel layer has the second characteristic that the output voltage is low because the sensitivity to light is high but the mobility is low. Therefore, it is suitable for the role of the optical sensor element of the optical sensor circuit.
　これにより、第１の薄膜トランジスタ素子および第２の薄膜トランジスタ素子は、画素の開口率の低下抑制、高感度、応答速度が速いという優れた利点を備えた光センサ回路を構成することができる。 Thereby, the first thin film transistor element and the second thin film transistor element can constitute an optical sensor circuit having excellent advantages of suppressing the decrease in aperture ratio of the pixel, high sensitivity, and high response speed.
　また、そのような光センサ回路の優れた利点は、例えば液晶を用いた画素がマトリクス状に配列されたアクティブマトリクス基板内に、複数の光センサ回路を実装することにより、タッチパネル機能または画像スキャナ機能などを備えた液晶表示装置を構成する場合に、極めて有利となる。 In addition, an excellent advantage of such a photosensor circuit is that, for example, a plurality of photosensor circuits are mounted on an active matrix substrate in which pixels using liquid crystals are arranged in a matrix, thereby enabling a touch panel function or an image scanner function. This is extremely advantageous when a liquid crystal display device including the above is configured.
　本発明の回路基板は、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の薄膜トランジスタ素子のドレイン電極とが、同一の導電層によって形成されていることが好ましい。 In the circuit board of the present invention, it is preferable that the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element are formed by the same conductive layer.
　上記構成により、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の薄膜トランジスタ素子のドレイン電極とをコンタクトホールを設けることなく接続することができる。これによりコンタクトホールを形成するために必要な領域の面積を低減することができ、画素の開口率低下を抑制することができる。 With the above configuration, the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element can be connected without providing a contact hole. As a result, the area of a region necessary for forming the contact hole can be reduced, and a decrease in the aperture ratio of the pixel can be suppressed.
　本発明の回路基板は、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の薄膜トランジスタ素子のドレイン電極とが配線で接続されていることが好ましい。 In the circuit board of the present invention, the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element are preferably connected by wiring.
　上記構成によると、上記第２の薄膜トランジスタのドレイン電極からの出力に基づいて、上記第１の薄膜トランジスタ素子を動作させることができる。 According to the above configuration, the first thin film transistor element can be operated based on the output from the drain electrode of the second thin film transistor.
　本発明の回路基板は、上記第１の薄膜トランジスタ素子が備えている上記チャネル層は、酸化物半導体からなり、上記第２の薄膜トランジスタ素子が備えている上記チャネル層は、アモルファスシリコン半導体からなっていることが好ましい。 In the circuit board of the present invention, the channel layer provided in the first thin film transistor element is made of an oxide semiconductor, and the channel layer provided in the second thin film transistor element is made of an amorphous silicon semiconductor. It is preferable.
　上記構成により、上記第１の特性を備えた第１の薄膜トランジスタ素子、及び上記第２の特性を備えた第２の薄膜トランジスタ素子を構成することができる。 With the above configuration, the first thin film transistor element having the first characteristic and the second thin film transistor element having the second characteristic can be configured.
　本発明の回路基板は、上記第１の薄膜トランジスタ素子の上記チャネル層とゲート電極との間には、ＳｉＯ２を主成分とするゲート絶縁膜が挟持され、上記第２の薄膜トランジスタ素子の上記チャネル層とゲート電極との間には、チャネル層側からＳｉＮＸを主成分とするゲート絶縁膜およびＳｉＯ２を主成分とするゲート絶縁膜が順に積層されて挟持され、かつ、両ゲート絶縁膜に共通するＳｉＯ２の層は、同一の層として形成されていることを特徴とする。 In the circuit board of the present invention, a gate insulating film mainly composed of SiO 2 is sandwiched between the channel layer and the gate electrode of the first thin film transistor element, and the channel layer of the second thin film transistor element Between the gate layer and the gate electrode, a gate insulating film mainly composed of SiN X and a gate insulating film mainly composed of SiO 2 are sequentially stacked and sandwiched from the channel layer side, and are common to both gate insulating films The SiO 2 layers to be formed are formed as the same layer.
　上記の構成によれば、第１の薄膜トランジスタ素子のチャネル層を構成する酸化物半導体と、第２の薄膜トランジスタ素子のチャネル層を構成するアモルファスシリコン半導体とが、それぞれに適したゲート絶縁膜と接することができる。 According to said structure, the oxide semiconductor which comprises the channel layer of a 1st thin-film transistor element, and the amorphous silicon semiconductor which comprises the channel layer of a 2nd thin-film transistor element are in contact with the gate insulating film suitable for each, Can do.
　つまり、酸化物半導体に還元性材料が接すると、還元され、その特性が劣化するが、上記の構成では、酸化物半導体に酸化物が接するため、その特性が劣化するのを防止できる。 That is, when a reducing material is in contact with the oxide semiconductor, it is reduced and its characteristics are deteriorated. However, in the above structure, since the oxide is in contact with the oxide semiconductor, the characteristics can be prevented from being deteriorated.
　また、アモルファスシリコン半導体に酸化物が接すると、酸化され、その特性が劣化するが、上記の構成では、アモルファスシリコン半導体に還元性材料が接するため、その特性が劣化するのを防止できる。 In addition, when an oxide comes into contact with an amorphous silicon semiconductor, it is oxidized and its characteristics deteriorate. However, in the above configuration, since the reducing material comes into contact with the amorphous silicon semiconductor, it is possible to prevent the characteristics from deteriorating.
　加えて、両ゲート絶縁膜に共通するＳｉＯ２の層は、同一の層として形成されているので、製造工程の簡素化とコストダウンとを図ることもできる。 In addition, since the SiO 2 layer common to both gate insulating films is formed as the same layer, the manufacturing process can be simplified and the cost can be reduced.
　上記複数のトランジスタ素子の一部となる第１のトランジスタ素子を回路的に保護する保護回路であって、上記複数のトランジスタ素子の一部となる第２のトランジスタ素子を備えた保護回路を含み、上記第１のトランジスタ素子は、上記第１の薄膜トランジスタ素子からなり、上記第２のトランジスタ素子は、上記第２の薄膜トランジスタ素子からなっていることが好ましい。 A protection circuit that protects the first transistor element that is a part of the plurality of transistor elements in a circuit, the protection circuit including a second transistor element that is a part of the plurality of transistor elements; Preferably, the first transistor element is composed of the first thin film transistor element, and the second transistor element is composed of the second thin film transistor element.
　上記の構成によれば、保護回路を構成する第２のトランジスタ素子を、アモルファスシリコン半導体をチャネル層として備えた第２の薄膜トランジスタ素子とすることによって、上記第２のトランジスタ素子を酸化物半導体をチャネル層として備えた第１の薄膜トランジスタ素子とする場合と比較して、保護回路の占有面積を小さくすることができる。 According to the above configuration, the second transistor element constituting the protection circuit is a second thin film transistor element including an amorphous silicon semiconductor as a channel layer, whereby the second transistor element is a channel of the oxide semiconductor. Compared with the case of the first thin film transistor element provided as a layer, the occupation area of the protection circuit can be reduced.
　また、回路的に保護される第１のトランジスタ素子を第１の薄膜トランジスタ素子としているので、例えば、液晶表示装置の各画素のスイッチング素子や、あるいは、このスイッチング素子と同一の絶縁性基板上にモノリシックに形成された駆動回路に含まれるトランジスタ素子のように、主たる動作を行うトランジスタ素子の応答性または駆動能力を高くすることができる。 Further, since the first transistor element that is protected in terms of the circuit is the first thin film transistor element, for example, the switching element of each pixel of the liquid crystal display device or a monolithic on the same insulating substrate as the switching element. As in the transistor elements included in the driving circuit formed in the above, the responsiveness or driving capability of the transistor elements that perform the main operation can be increased.
　このように、同一の絶縁性基板上において、回路的な役割毎に適したトランジスタ素子を実装することにより、小型で高性能の電気回路を搭載した回路基板を提供することができる。 Thus, by mounting transistor elements suitable for each circuit role on the same insulating substrate, it is possible to provide a circuit board on which a small and high-performance electric circuit is mounted.
　本発明に係る表示パネルは、上記いずれかの回路基板を備えたことを特徴とする。上記の構成によれば、既に説明した各回路基板の各利点を備えた表示パネルを提供することができる。 The display panel according to the present invention includes any one of the circuit boards described above. According to said structure, the display panel provided with each advantage of each circuit board already demonstrated can be provided.
　本発明に係る表示装置は、上記いずれかの回路基板を備えたことを特徴とする。上記の構成によれば、既に説明した各回路基板の各利点を備えた表示装置を提供することができる。 A display device according to the present invention includes any one of the circuit boards described above. According to said structure, the display apparatus provided with each advantage of each circuit board already demonstrated can be provided.
　本発明の回路基板の製造方法は、チャネル層を形成する半導体の種類が異なることにより、回路的な役割が互いに異なる第１の薄膜トランジスタ素子と第２の薄膜トランジスタ素子とを同一の絶縁性基板上に形成する回路基板の製造方法であって、上記絶縁性基板上にパターニングされた、上記第１の薄膜トランジスタ素子のチャネル層、及び、上記第２の半導体トランジスタ素子のゲート電極上に絶縁膜を形成する工程と、上記絶縁膜上に、同一の導電層のパターニングによって、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の半導体トランジスタのソース電極及びドレイン電極とを形成する工程とを含むことを特徴としている。 According to the method for manufacturing a circuit board of the present invention, the first thin film transistor element and the second thin film transistor element having different circuit roles are arranged on the same insulating substrate due to different types of semiconductors forming the channel layer. A method for manufacturing a circuit board, wherein an insulating film is formed on a channel layer of the first thin film transistor element and a gate electrode of the second semiconductor transistor element patterned on the insulating substrate. And forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second semiconductor transistor by patterning the same conductive layer on the insulating film. It is a feature.
　上記の構成によれば、回路基板の発明について既に説明したように、電気回路を設置するために必要な領域の面積を低減することができ、画素の開口率低下を抑制して高性能の回路基板を安価に製造することができる。 According to the above configuration, as already described in the invention of the circuit board, it is possible to reduce the area of the region necessary for installing the electric circuit, and to suppress a decrease in the aperture ratio of the pixel, thereby achieving a high-performance circuit. The substrate can be manufactured at a low cost.
　本発明は、前段の回路からの出力信号を、複数の分配線を介して後段の回路へ時分割して供給する信号分配装置に適用することができ、そのような信号分配装置を用いる表示装置等の電子機器に適用することができる。 INDUSTRIAL APPLICABILITY The present invention can be applied to a signal distribution device that supplies an output signal from a front-stage circuit to a subsequent-stage circuit through a plurality of distribution lines, and a display device using such a signal distribution device It can be applied to electronic devices such as.
１、１ａ、１ｂ　　　　回路基板
２　　　　　　　　　　絶縁性基板
３、３Ｂ　　　　　　　ゲート絶縁膜
１０　　　　　　　　酸化物ＴＦＴ（第１の薄膜トランジスタ素子）
１０ａ、１０ｂ、１０ｃ、１０ｄ　酸化物ＴＦＴ（第１の薄膜トランジスタ素子）
１１、２１　　　　　　チャネル層
１２、１２ａ、１２ｂ、２２　　　ゲート電極
１５、１５ａ、１５ｂ、２５　　　ソース電極
１６、１６ａ、１６ｂ、２６　　　ドレイン電極
２０、２０ａ、２０ｂ　　　　　ａ－ＳｉＴＦＴ（第２の薄膜トランジスタ素子）
２３、２３ａ、２３ｂ、２３Ｂ　ゲート絶縁膜
２４　　　　　　　　　導電層
２７、４２　　　　　　コンタクトホール
３０　　　　　　　　　画素
４０　　　　　　　　　光センサ回路
４１　　　　　　　　　昇圧用コンデンサ
４１ａ、４１ｂ　　　　端子部
５０、５８　　　　　　液晶表示装置（表示装置）
６０　　　　　　　　　保護回路
６０ａ，６０ｂ　　　　ＴＦＴ（第２のトランジスタ素子）
６１　　　　　　　　　ダイオード 1, 1a, 1b Circuit board 2 Insulating board 3, 3B Gate insulation film 10 Oxide TFT (first thin film transistor element)
10a, 10b, 10c, 10d Oxide TFT (first thin film transistor element)
11, 21 Channel layers 12, 12a, 12b, 22 Gate electrodes 15, 15a, 15b, 25 Source electrodes 16, 16a, 16b, 26 Drain electrodes 20, 20a, 20b a-Si TFT (second thin film transistor element)
23, 23a, 23b, 23B Gate insulating film 24 Conductive layer 27, 42 Contact hole 30 Pixel 40 Photosensor circuit 41 Capacitor for boosting 41a, 41b Terminal portion 50, 58 Liquid crystal display device (display device)
60 protection circuit 60a, 60b TFT (second transistor element)
61 Diode

Claims (10)

  1. 　同一の絶縁性基板上に複数のトランジスタ素子を備えた回路基板であって、
    　上記複数のトランジスタ素子の少なくとも１つは、相対的に、移動度が大きく、かつ光に対する感度が低い半導体をチャネル層として備えた第１の薄膜トランジスタ素子であり、
    　上記複数のトランジスタ素子の少なくとも他の１つは、上記第１の薄膜トランジスタ素子と回路的な役割が異なっており、かつ、相対的に、移動度が小さく、かつ光に対する感度が高い半導体をチャネル層として備えた第２の薄膜トランジスタ素子であり、
    　上記第１の薄膜トランジスタ素子がトップゲート型のトランジスタであり、上記第２の薄膜トランジスタ素子がボトムゲート型のトランジスタであることを特徴とする回路基板。     A circuit board having a plurality of transistor elements on the same insulating substrate,
    At least one of the plurality of transistor elements is a first thin film transistor element including a semiconductor having a relatively high mobility and low sensitivity to light as a channel layer,
    At least one other of the plurality of transistor elements has a channel role different from that of the first thin film transistor element, and has a relatively low mobility and a high sensitivity to light as a channel layer. A second thin film transistor element provided as
    A circuit board, wherein the first thin film transistor element is a top gate type transistor and the second thin film transistor element is a bottom gate type transistor.
  2. 　上記第１の薄膜トランジスタ素子および第２の薄膜トランジスタ素子は、光センサ回路を構成しており、
    　上記第１の薄膜トランジスタ素子は、上記光センサ回路のセンサ出力の役割を担い、
    　上記第２の薄膜トランジスタ素子は、上記光センサ回路の光センサ素子の役割を担っていることを特徴とする請求項１に記載の回路基板。     The first thin film transistor element and the second thin film transistor element constitute an optical sensor circuit,
    The first thin film transistor element plays a role of a sensor output of the optical sensor circuit,
    The circuit board according to claim 1, wherein the second thin film transistor element plays a role of an optical sensor element of the optical sensor circuit.
  3. 　上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の薄膜トランジスタ素子のドレイン電極とが、同一の導電層によって形成されていることを特徴とする請求項１または２に記載の回路基板。 3. The circuit board according to claim 1, wherein the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element are formed of the same conductive layer.
  4. 　上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の薄膜トランジスタ素子のドレイン電極とが配線で接続されていることを特徴とする請求項３に記載の回路基板。 4. The circuit board according to claim 3, wherein the gate electrode of the first thin film transistor element and the drain electrode of the second thin film transistor element are connected by wiring.
  5. 　上記第１の薄膜トランジスタ素子が備えている上記チャネル層は、酸化物半導体からなり、
    　上記第２の薄膜トランジスタ素子が備えている上記チャネル層は、アモルファスシリコン半導体からなっていることを特徴とする請求項１～４の何れか１項に記載の回路基板。     The channel layer provided in the first thin film transistor element is made of an oxide semiconductor,
    5. The circuit board according to claim 1, wherein the channel layer included in the second thin film transistor element is made of an amorphous silicon semiconductor.
  6. 　上記第１の薄膜トランジスタ素子の上記チャネル層とゲート電極との間には、ＳｉＯ２を主成分とするゲート絶縁膜が挟持され、
    　上記第２の薄膜トランジスタ素子の上記チャネル層とゲート電極との間には、チャネル層側からＳｉＮＸを主成分とするゲート絶縁膜およびＳｉＯ２を主成分とするゲート絶縁膜が順に積層されて挟持され、かつ、両ゲート絶縁膜に共通するＳｉＯ２の層は、同一の層として形成されていることを特徴とする請求項５に記載の回路基板。     Between the channel layer and the gate electrode of the first thin film transistor element, a gate insulating film mainly composed of SiO 2 is sandwiched,
    Between the channel layer and the gate electrode of the second thin film transistor element, a gate insulating film mainly composed of SiN X and a gate insulating film mainly composed of SiO 2 are sequentially stacked and sandwiched from the channel layer side. The circuit board according to claim 5, wherein the SiO 2 layer common to both gate insulating films is formed as the same layer.
  7. 　上記複数のトランジスタ素子の一部となる第１のトランジスタ素子を回路的に保護する保護回路であって、上記複数のトランジスタ素子の一部となる第２のトランジスタ素子を備えた保護回路を含み、
    　上記第１のトランジスタ素子は、上記第１の薄膜トランジスタ素子からなり、
    　上記第２のトランジスタ素子は、上記第２の薄膜トランジスタ素子からなっていること
    を特徴とする請求項２に記載の回路基板。     A protection circuit that protects the first transistor element that is a part of the plurality of transistor elements in a circuit, the protection circuit including a second transistor element that is a part of the plurality of transistor elements;
    The first transistor element comprises the first thin film transistor element,
    The circuit board according to claim 2, wherein the second transistor element is the second thin film transistor element.
  8. 　請求項１～７の何れか１項に記載の回路基板を備えたことを特徴とする表示パネル。 A display panel comprising the circuit board according to any one of claims 1 to 7.
  9. 　請求項１から７のいずれか１項に記載の回路基板を備えたことを特徴とする表示装置。 A display device comprising the circuit board according to any one of claims 1 to 7.
  10. 　チャネル層を形成する半導体の種類が異なることにより、回路的な役割が互いに異なる第１の薄膜トランジスタ素子と第２の薄膜トランジスタ素子とを同一の絶縁性基板上に形成する回路基板の製造方法であって、
    　上記絶縁性基板上にパターニングされた、上記第１の薄膜トランジスタ素子のチャネル層、及び、上記第２の薄膜トランジスタ素子のゲート電極上に絶縁膜を形成する工程と、
    　上記絶縁膜上に、同一の導電層のパターニングによって、上記第１の薄膜トランジスタ素子のゲート電極と、上記第２の薄膜トランジスタ素子のソース電極及びドレイン電極とを形成する工程とを含むことを特徴とする回路基板の製造方法。     A method of manufacturing a circuit board, wherein a first thin film transistor element and a second thin film transistor element having different circuit roles are formed on the same insulating substrate due to different types of semiconductors forming a channel layer. ,
    Forming an insulating film on the channel layer of the first thin film transistor element and the gate electrode of the second thin film transistor element patterned on the insulating substrate;
    Forming a gate electrode of the first thin film transistor element and a source electrode and a drain electrode of the second thin film transistor element on the insulating film by patterning the same conductive layer. A method of manufacturing a circuit board.
PCT/JP2011/054796 2010-04-30 2011-03-02 Circuit board, display device, and method for producing circuit board WO2011135920A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/643,652 US9111810B2 (en) 2010-04-30 2011-03-02 Circuit board and display device including first and second channel layers made of different semiconductor materials

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010105660 2010-04-30
JP2010-105660 2010-04-30

Publications (1)

Publication Number Publication Date
WO2011135920A1 true WO2011135920A1 (en) 2011-11-03

Family

ID=44861241

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/054796 WO2011135920A1 (en) 2010-04-30 2011-03-02 Circuit board, display device, and method for producing circuit board

Country Status (2)

Country Link
US (1) US9111810B2 (en)
WO (1) WO2011135920A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102854684A (en) * 2012-09-26 2013-01-02 南京中电熊猫液晶显示科技有限公司 Metallic oxide fringing field switching mode liquid crystal display panel and manufacture method thereof
US8581257B2 (en) 2010-04-07 2013-11-12 Sharp Kabushiki Kaisha Circuit board and display device
WO2014165149A1 (en) * 2013-03-12 2014-10-09 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University Thin film transistor detection systems and related methods
EP2743990A3 (en) * 2012-12-12 2017-02-01 Boe Technology Group Co. Ltd. Complementary metal oxide semiconductor circuit structure, preparation method thereof and display device
JP2017038038A (en) * 2015-08-10 2017-02-16 Ｎｌｔテクノロジー株式会社 Optical sensor element and photoelectric conversion element
US10439069B2 (en) 2015-08-10 2019-10-08 Nlt Technologies, Ltd. Optical sensor element and photoelectric conversion device

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9564478B2 (en) 2013-08-26 2017-02-07 Apple Inc. Liquid crystal displays with oxide-based thin-film transistors
US9818765B2 (en) 2013-08-26 2017-11-14 Apple Inc. Displays with silicon and semiconducting oxide thin-film transistors
US9461072B2 (en) * 2013-12-25 2016-10-04 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid crystal display array substrates and a method for manufacturing the same
CN107918235A (en) * 2013-12-31 2018-04-17 上海天马微电子有限公司 A kind of array base palte and display device
KR102298336B1 (en) * 2014-06-20 2021-09-08 엘지디스플레이 주식회사 Organic Light Emitting diode Display
JP2016058645A (en) * 2014-09-11 2016-04-21 株式会社東芝 Semiconductor device
US10269839B2 (en) 2015-03-26 2019-04-23 Carestream Health, Inc. Apparatus and method using a dual gate TFT structure
CN104699344B (en) * 2015-03-30 2017-11-28 京东方科技集团股份有限公司 Contact panel and its manufacture method, touch control display apparatus
CN104900653B (en) * 2015-04-14 2017-12-29 深圳市华星光电技术有限公司 TFT layout structures
CN106558592B (en) * 2015-09-18 2019-06-18 鸿富锦精密工业（深圳）有限公司 The preparation method of array substrate, display device and array substrate
US9818344B2 (en) 2015-12-04 2017-11-14 Apple Inc. Display with light-emitting diodes
JP6832656B2 (en) * 2016-09-14 2021-02-24 株式会社ジャパンディスプレイ Manufacturing method of semiconductor devices
KR20210013460A (en) * 2019-07-25 2021-02-04 삼성디스플레이 주식회사 Display apparatus
CN112740421A (en) * 2019-08-23 2021-04-30 京东方科技集团股份有限公司 Display device and method for manufacturing the same
CN112786636A (en) * 2021-01-06 2021-05-11 Tcl华星光电技术有限公司 Preparation method of X-ray sensor and X-ray sensor
KR20230046331A (en) * 2021-09-29 2023-04-06 삼성디스플레이 주식회사 Display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468731A (en) * 1987-09-10 1989-03-14 Matsushita Electric Ind Co Ltd Manufacture of thin film transistor array
JPH03132723A (en) * 1989-10-19 1991-06-06 Nec Corp Protecting circuit for static electricity
JP2005235810A (en) * 2004-02-17 2005-09-02 Casio Comput Co Ltd Driver circuit and its manufacturing method
JP2009246362A (en) * 2008-03-28 2009-10-22 Samsung Electronics Co Ltd Inverter and logic circuit including the same
JP2009540623A (en) * 2007-05-31 2009-11-19 パナソニック株式会社 Organic EL device and manufacturing method thereof
JP2010028021A (en) * 2008-07-24 2010-02-04 Fujifilm Corp Thin film field-effect transistor

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10293322A (en) 1997-04-21 1998-11-04 Canon Inc Liquid crystal display and manufacture therefor
US6706544B2 (en) * 2000-04-19 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and fabricating method thereof
JP3659250B2 (en) * 2002-07-11 2005-06-15 セイコーエプソン株式会社 Electro-optical device, driving device for electro-optical device, driving method for electro-optical device, and electronic apparatus
JP2005072126A (en) 2003-08-21 2005-03-17 Toshiba Matsushita Display Technology Co Ltd Circuit board, array substrate, manufacturing method therefor, liquid crystal display device and manufacturing method therefor
KR100685239B1 (en) 2004-01-29 2007-02-22 가시오게산키 가부시키가이샤 A transistor array, manufacturing method thereof, and image processing device
KR101154338B1 (en) * 2006-02-15 2012-06-13 삼성전자주식회사 Shift register, and scan drive circuit and display device having the same
EP1821386A2 (en) * 2006-02-17 2007-08-22 Power Systems Co., Ltd. Charging apparatus for capacitor storage type power source and discharging apparatus for capacitor storage type power source
GB2439098A (en) 2006-06-12 2007-12-19 Sharp Kk Image sensor and display
JP5305630B2 (en) 2006-12-05 2013-10-02 キヤノン株式会社 Manufacturing method of bottom gate type thin film transistor and manufacturing method of display device
KR101146574B1 (en) 2006-12-05 2012-05-16 캐논 가부시끼가이샤 Method for manufacturing thin film transistor using oxide semiconductor and display apparatus
TWI412125B (en) * 2007-07-17 2013-10-11 Creator Technology Bv An electronic device and a method of manufacturing an electronic device
JP5080172B2 (en) * 2007-08-23 2012-11-21 富士フイルム株式会社 Image detection device
JP5567770B2 (en) * 2007-09-21 2014-08-06 株式会社ジャパンディスプレイ Display device and manufacturing method of display device
JP2009128577A (en) * 2007-11-22 2009-06-11 Hitachi Ltd Organic light emitting display device
JP5388632B2 (en) * 2008-03-14 2014-01-15 株式会社半導体エネルギー研究所 Semiconductor device
JP2010003910A (en) 2008-06-20 2010-01-07 Toshiba Mobile Display Co Ltd Display element
TWI585955B (en) 2008-11-28 2017-06-01 半導體能源研究所股份有限公司 Photosensor and display device
KR101280743B1 (en) 2010-04-07 2013-07-05 샤프 가부시키가이샤 Circuit board and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468731A (en) * 1987-09-10 1989-03-14 Matsushita Electric Ind Co Ltd Manufacture of thin film transistor array
JPH03132723A (en) * 1989-10-19 1991-06-06 Nec Corp Protecting circuit for static electricity
JP2005235810A (en) * 2004-02-17 2005-09-02 Casio Comput Co Ltd Driver circuit and its manufacturing method
JP2009540623A (en) * 2007-05-31 2009-11-19 パナソニック株式会社 Organic EL device and manufacturing method thereof
JP2009246362A (en) * 2008-03-28 2009-10-22 Samsung Electronics Co Ltd Inverter and logic circuit including the same
JP2010028021A (en) * 2008-07-24 2010-02-04 Fujifilm Corp Thin film field-effect transistor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8581257B2 (en) 2010-04-07 2013-11-12 Sharp Kabushiki Kaisha Circuit board and display device
CN102854684A (en) * 2012-09-26 2013-01-02 南京中电熊猫液晶显示科技有限公司 Metallic oxide fringing field switching mode liquid crystal display panel and manufacture method thereof
EP2743990A3 (en) * 2012-12-12 2017-02-01 Boe Technology Group Co. Ltd. Complementary metal oxide semiconductor circuit structure, preparation method thereof and display device
WO2014165149A1 (en) * 2013-03-12 2014-10-09 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University Thin film transistor detection systems and related methods
US9910171B2 (en) 2013-03-12 2018-03-06 Arizona Board Of Regents On Behalf Of Arizona State University Thin film transistor detection systems and related methods
JP2017038038A (en) * 2015-08-10 2017-02-16 Ｎｌｔテクノロジー株式会社 Optical sensor element and photoelectric conversion element
US10439069B2 (en) 2015-08-10 2019-10-08 Nlt Technologies, Ltd. Optical sensor element and photoelectric conversion device

Also Published As

Publication number Publication date
US20130146866A1 (en) 2013-06-13
US9111810B2 (en) 2015-08-18

Similar Documents

Publication Publication Date Title
WO2011135920A1 (en) Circuit board, display device, and method for producing circuit board
JP5174988B2 (en) Circuit board and display device
JP5275515B2 (en) Circuit board and display device
US8436358B2 (en) Image display device and manufacturing method thereof
US10439010B2 (en) Display device
JP7370375B2 (en) Display devices and semiconductor devices
JP2007316104A (en) Display device
WO2010116433A1 (en) Display device
WO2014054569A1 (en) Semiconductor device and display device
US7329901B2 (en) Thin-film semiconductor device, electro-optical device, and electronic apparatus
JP2010243524A (en) Electro-optical device
KR101620527B1 (en) Thin film transistor array panel and method of manufacturing the same
US8810762B2 (en) Display device equipped with touch sensor
WO2014054558A1 (en) Semiconductor device and display device
US7388625B2 (en) Thin-film transistor array substrate and liquid crystal display device
JP2007093685A (en) Electro-optical device and electronic equipment
WO2018043643A1 (en) Active matrix substrate and display device provided with active matrix substrate
KR20080038538A (en) Liquid crystal display
JP2000206565A (en) Semiconductor device for display and liquid crystal display using such device
KR20150064482A (en) Active matrix type display device and manufacturing method the same
JP2007316105A (en) Display device
JP5293240B2 (en) Display device
US20220404655A1 (en) Display device
JP2008122504A (en) Display apparatus and its manufacturing method
JP2008293048A (en) Display

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11774704

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 13643652

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 11774704

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP