CN111081719A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN111081719A CN111081719A CN201911273331.1A CN201911273331A CN111081719A CN 111081719 A CN111081719 A CN 111081719A CN 201911273331 A CN201911273331 A CN 201911273331A CN 111081719 A CN111081719 A CN 111081719A
- Authority
- CN
- China
- Prior art keywords
- layer
- manufacturing
- capacitor
- grid
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
Abstract
The invention provides an array substrate and a manufacturing method thereof. The array substrate is provided with a display area and an array substrate row driving area, and comprises a substrate, a low-temperature polycrystalline silicon thin film transistor unit, a metal oxide transistor unit, a first capacitor and a second capacitor; the low-temperature polycrystalline silicon thin film transistor unit is positioned on the substrate base plate and positioned in the display area and the array base plate row driving area; the first capacitor is arranged corresponding to the low-temperature polycrystalline silicon thin film transistor unit; the metal oxide transistor unit is positioned on the substrate base plate, positioned in the array base plate row driving area and arranged at an interval with the low-temperature polycrystalline silicon thin film transistor unit; the second capacitor is arranged corresponding to the metal oxide transistor unit. The invention realizes the ultra-narrow frame by adopting the low-temperature polycrystalline silicon thin film transistor unit circuit structure in the display area of the array substrate, simplifies the process and has low production cost.
Description
Technical Field
The invention relates to the field of display, in particular to an array substrate and a manufacturing method thereof.
Background
An organic light-emitting diode (OLED) display is a new flat panel display, and has excellent characteristics of self-luminescence, high contrast, thin thickness, wide viewing angle, and fast response speed, and can be used for a flexible display panel, and the like, thereby having a very good development prospect.
The thin film transistor is classified into an amorphous silicon thin film transistor (a-Si TFT), a Low temperature poly-silicon (LTPS) thin film transistor, and a metal oxide (metal oxide) thin film transistor. The amorphous silicon thin film transistor and the low-temperature polycrystalline silicon thin film transistor are silicon-based thin film transistors, have the advantages of high switching speed and large driving current, and can be used for OLED display pixel driving and LCD grid driving; the metal oxide thin film transistor has the advantages of good uniformity and low leakage current, and can be used for OLED display pixel driving, LCD display pixel driving and peripheral driving circuits.
As a self-luminous display, the OLED is currently manufactured by using Low Temperature Polysilicon (LTPS) to prepare semiconductor layers of a PMOS region and an NMOS region of a CMOS circuit, respectively, to drive the OELD display. In the process of preparing the CMOS circuit by utilizing the LTPS process, at least more than 9 photoresist masks and at least more than 4 doping processes (p-type ion doping, n-type ion doping, LDD doping and Ch doping) are needed, the manufacturing process is complex, the production cost is high, and the frame is wide.
Therefore, how to realize a thin film transistor array substrate with simple manufacturing process, low production cost and narrow frame and a manufacturing method thereof are a problem to be solved urgently.
Disclosure of Invention
The invention aims to provide an array substrate and a manufacturing method thereof, wherein a circuit structure of a low-temperature polycrystalline silicon thin film transistor unit is adopted in a display area of the array substrate, and a CMOS circuit structure formed by a low-temperature polycrystalline silicon thin film transistor unit and a metal oxide thin film transistor unit which are driven independently is adopted in a row driving area of the array substrate, so that an ultra-narrow frame is realized, the process is simplified, and the production cost is low.
In order to achieve the above object, the present invention provides an array substrate, which is provided with a display area and an array substrate row driving area, wherein the array substrate comprises a substrate, a low temperature polysilicon thin film transistor unit, a metal oxide transistor unit, a first capacitor and a second capacitor; specifically, the low-temperature polycrystalline silicon thin film transistor unit is positioned on the substrate and positioned in the display area and the array substrate row driving area; the first capacitor is positioned in the low-temperature polycrystalline silicon thin film transistor unit; the metal oxide transistor units are positioned on the substrate base plate, positioned in the array base plate row driving area and arranged at intervals with the low-temperature polycrystalline silicon thin film transistor units; the second capacitor is located in the metal oxide transistor unit.
Furthermore, the array substrate further comprises a polysilicon layer, a semiconductor oxide layer, a first grid insulating layer, a first metal layer, a second grid insulating layer, an interlayer insulating layer and a second metal layer which are arranged at intervals; specifically, the polycrystalline silicon layer and the semiconductor oxide layer are both positioned on the substrate base plate; the first grid insulating layer is positioned on the polycrystalline silicon layer and the semiconductor oxide layer; the first metal layer is positioned on the first grid insulating layer; the first metal layer comprises a first grid and a second grid which are arranged at intervals, wherein the first grid is positioned above the polycrystalline silicon layer, and the second grid is positioned above the semiconductor oxide layer; the second gate insulating layer is positioned on the first metal layer; the interlayer insulating layer is positioned on the second grid insulating layer; the second metal layer is positioned on the interlayer insulating layer; the second metal layer comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode which are arranged at intervals, wherein the first source electrode and the first drain electrode are respectively and electrically connected with the polycrystalline silicon layer, and the second source electrode and the second drain electrode are respectively and electrically connected with the semiconductor oxide layer; wherein the polysilicon layer, the first gate insulating layer, the first gate, the second gate insulating layer, the first source and the first drain form the silicon thin film transistor unit; the semiconductor oxide layer, the first gate insulating layer, the second gate insulating layer, the second source, and the second drain form the metal oxide transistor unit.
Further, the array substrate further comprises a third metal layer, and the third metal layer is located between the first gate insulating layer and the second gate insulating layer; the third metal layer comprises a first capacitor polar plate and a second capacitor polar plate which are arranged at intervals, the first capacitor polar plate is arranged opposite to the first grid and is positioned above the second grid, and the second capacitor polar plate is arranged opposite to the second grid and is positioned above the second grid; the first gate, the first gate insulating layer and the first capacitor plate form the first capacitor, and the second gate, the first gate insulating layer and the second capacitor plate form the second capacitor.
Further, the first metal layer further comprises a wire changing layer, the wire changing layer is located between the first grid and the second grid, and the wire changing layer is electrically connected with the first drain.
Further, the array substrate further comprises a passivation layer, a flat layer, an anode layer, a pixel defining layer and a light emitting layer; in particular, the passivation layer is located on the second metal layer; the flat layer is positioned on the passivation layer; the anode layer is positioned on the flat layer and is electrically connected with the second drain electrode; the pixel defining layer is positioned on the anode layer; the light emitting layer is located on the pixel defining layer and electrically connected with the anode layer.
The invention also provides a manufacturing method of the array substrate, the array substrate is provided with a display area and an array substrate row driving area, and the method comprises the following steps:
manufacturing a substrate base plate;
manufacturing a low-temperature polycrystalline silicon thin film transistor unit, and manufacturing the low-temperature polycrystalline silicon thin film transistor unit on the substrate and in the display area and the array substrate row driving area;
manufacturing a first capacitor, and manufacturing the first capacitor in an overlapping area of the low-temperature polycrystalline silicon thin film transistor unit;
manufacturing a metal oxide transistor unit on the substrate and in the array substrate row driving area, wherein the metal oxide transistor unit and the low-temperature polycrystalline silicon thin film transistor unit are arranged at intervals; and
and manufacturing a second capacitor in an overlapping area of the second capacitor and the metal oxide transistor unit.
Further, the step of fabricating the low temperature polysilicon thin film transistor unit and the step of fabricating the metal oxide transistor unit specifically include the steps of:
manufacturing an interval polycrystalline silicon layer and an interval semiconductor oxide layer on the substrate;
manufacturing a first grid insulating layer, and manufacturing the first grid insulating layer on the polycrystalline silicon layer and the semiconductor oxide layer;
manufacturing a first metal layer, and manufacturing the first metal layer on the first grid insulating layer; patterning the first metal layer to form a first grid and a second grid which are arranged at intervals, wherein the first grid is positioned above the polycrystalline silicon layer, and the second grid is positioned above the semiconductor oxide layer;
manufacturing a second grid electrode insulating layer, and manufacturing the second grid electrode insulating layer on the first metal layer;
manufacturing an interlayer insulating layer, and manufacturing the interlayer insulating layer on the second grid insulating layer; and
manufacturing a second metal layer, and manufacturing the second metal layer on the interlayer insulating layer; patterning the second metal layer to form a first source electrode, a first drain electrode, a second source electrode and a second drain electrode which are arranged at intervals, wherein the first source electrode and the first drain electrode are respectively and electrically connected with the polycrystalline silicon layer, and the second source electrode and the second drain electrode are respectively and electrically connected with the semiconductor oxide layer;
wherein the polysilicon layer, the first gate insulating layer, the first gate, the second gate insulating layer, the first source and the first drain form the silicon thin film transistor unit; the semiconductor oxide layer, the first gate insulating layer, the second gate insulating layer, the second source, and the second drain form the metal oxide transistor unit.
Further, the step of manufacturing the first capacitor and the step of manufacturing the second capacitor specifically include the steps of:
manufacturing a third metal layer, and manufacturing the third metal layer between the first grid insulation layer and the second grid insulation layer; and
patterning the third metal layer to form a first capacitor electrode plate and a second capacitor electrode plate which are arranged at intervals, wherein the first capacitor electrode plate is arranged opposite to the first grid electrode and is positioned above the second grid electrode, and the second capacitor electrode plate is arranged opposite to the second grid electrode and is positioned above the second grid electrode;
the first gate, the first gate insulating layer and the first capacitor plate form the first capacitor, and the second gate, the first gate insulating layer and the second capacitor plate form the second capacitor.
Further, the step of manufacturing the first metal layer further includes:
and manufacturing a wire changing layer, wherein the first metal layer is patterned to form the wire changing layer positioned between the first grid and the second grid, and the wire changing layer is electrically connected with the first drain.
Further, after the step of fabricating the second metal layer, the method further includes the steps of:
manufacturing a passivation layer, and manufacturing the passivation layer on the second metal layer;
manufacturing a flat layer, and manufacturing the flat layer on the passivation layer;
manufacturing an anode layer, wherein the anode layer is manufactured on the flat layer and is electrically connected with the second drain electrode;
manufacturing a pixel definition layer, and manufacturing the pixel definition layer on the anode layer; and
and manufacturing a light emitting layer on the pixel definition layer, wherein the light emitting layer is electrically connected with the anode layer.
The invention has the advantages that the invention provides the array substrate and the manufacturing method thereof, the ultra-narrow frame is realized by adopting the circuit structure of the low-temperature polycrystalline silicon thin film transistor unit in the display area of the array substrate and adopting the CMOS circuit structure formed by the low-temperature polycrystalline silicon thin film transistor unit and the metal oxide thin film transistor unit which are independently driven in the row driving area of the array substrate, and the low-temperature polycrystalline silicon thin film transistor unit and the metal oxide thin film transistor unit are compatible in the manufacturing process, the process is simplified and the production cost is low.
Drawings
FIG. 1 is a schematic plan view illustrating an array substrate according to an embodiment;
fig. 2 is a schematic structural diagram of an array substrate in an embodiment, which mainly shows a structure of a row driving region of the array substrate;
FIG. 3 is a schematic circuit diagram of the LTPS TFT unit according to an embodiment;
FIG. 4 is a schematic circuit diagram of the MOS transistor unit in an embodiment;
FIG. 5 is a schematic diagram of the structure of the latch in the embodiment;
FIG. 6 is a schematic circuit diagram of the inverter according to the embodiment;
FIG. 7 is a flow chart illustrating a method of fabricating an array substrate according to an embodiment;
FIG. 8 is a manufacturing flow chart of the step of fabricating the LTPS TFT cell and the step of fabricating the MOS transistor cell in FIG. 7;
fig. 9 is a manufacturing flow chart of the step of fabricating the first capacitor and the step of fabricating the second capacitor in fig. 7.
The components in the figure are identified as follows:
1. a substrate base plate, 1a, a flexible substrate layer, 1b, a buffer layer, 2a, a polycrystalline silicon layer, 2b, a semiconductor oxide layer, 3, a first grid insulation layer, 4, a first metal layer, 41, a first grid, 42, a second grid, 43, a wire changing layer, 5, a second grid insulation layer, 6, an interlayer insulation layer, 7, a second metal layer, 71, a first source electrode, 72, a first drain electrode, 73, a second source electrode, 74, the display device comprises a second drain electrode, 8, a third metal layer, 81, a first capacitor plate, 82, a second capacitor plate, 9, a passivation layer, 10, a flat layer, 11, an anode layer, 12, a pixel definition layer, 13, a light emitting layer, 100, an array substrate, 101, a display area, 102, an array substrate row driving area, 120, a low-temperature polycrystalline silicon thin film transistor unit, 130, a metal oxide transistor unit, 130, a first capacitor, 140 and a second capacitor.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The drawings of the present invention are only for illustrating the relative positional relationship and the electrical connection relationship, the layer thicknesses of some parts are exaggerated in a drawing manner for easy understanding, and the layer thicknesses in the drawings do not represent the proportional relationship of the actual layer thicknesses.
Referring to fig. 1 and 2, an embodiment of the invention provides an array substrate 100, which includes a display area 101 and an array substrate row driving area 102, where the array substrate 100 includes a substrate 1, a plurality of low temperature polysilicon thin film transistor units 110, a plurality of metal oxide transistor units 120, a first capacitor 130, and a second capacitor 140; specifically, the substrate base plate 1 comprises a flexible substrate layer 1a and a buffer layer 1b positioned on the flexible substrate layer 1a, and the low-temperature polysilicon thin film transistor unit 110 is positioned on the substrate base plate 1 and positioned in the display area 101 and the array base plate row driving area 102; the first capacitor 130 is located in the low temperature polysilicon thin film transistor unit 110; the metal oxide transistor unit 120 is located on the substrate 1 and in the array substrate row driving region 102, and the second capacitor 140 is located in the metal oxide transistor unit 120. The metal oxide transistor unit 120 is disposed at an interval from the low temperature polysilicon thin film transistor unit 110.
Referring to fig. 3, a schematic diagram of a circuit structure of the low temperature polysilicon tft unit 110 is shown, where the circuit structure of the low temperature polysilicon tft unit 110 includes 2T1C or 7T 1C.
Referring to fig. 4, a circuit structure of the metal oxide transistor unit 120 is shown, and the circuit structure of the metal oxide transistor unit 120 includes 2T1C or 3T 1C.
In this embodiment, the array substrate 100 further includes a polysilicon layer 2a, a semiconductor oxide layer 2b, a first gate insulating layer 3, a first metal layer 4, a second gate insulating layer 5, an interlayer insulating layer 6, and a second metal layer 7. The polycrystalline silicon layer 2a is doped with P-type ions, the semiconductor oxide layer 2b is doped with N-type ions, and the material of the semiconductor oxide layer 2b includes IGZO, IZTO or IGZTO, preferably IGZO.
Referring to fig. 2, specifically, the polysilicon layer 2a and the semiconductor oxide layer 2b are both located on the substrate 1; the first gate insulating layer 3 is located on the polysilicon layer 2a and the semiconductor oxide layer 2 b; the first metal layer 4 is positioned on the first gate insulating layer 3; the first metal layer 4 comprises a first gate 41 and a second gate 42 which are arranged at intervals, wherein the first gate 41 is positioned above the polysilicon layer 2a, and the second gate 42 is positioned above the semiconductor oxide layer 2 b; the second gate insulating layer 5 is located on the first metal layer 4; the interlayer insulating layer 6 is located on the second gate insulating layer 5; the second metal layer 7 is positioned on the interlayer insulating layer 6; the second metal layer 7 includes a first source 71, a first drain 72, a second source 73 and a second drain 74, which are disposed at intervals, wherein the first source 71 and the first drain 72 are respectively electrically connected to the polysilicon layer 2a, and the second source 73 and the second drain 74 are respectively electrically connected to the semiconductor oxide layer 2 b.
Wherein the polysilicon layer 2a, the first gate insulating layer 3, the first gate 41, the second gate insulating layer 5, the first source 71 and the first drain 72 form the silicon thin film transistor unit 110; the semiconductor oxide layer 2b, the first gate insulating layer 3, the second gate 42, the second gate insulating layer 5, the second source 73, and the second drain 74 form the metal oxide transistor unit 120.
As shown in fig. 2, in the present embodiment, the array substrate 100 further includes a third metal layer 8, and the third metal layer 8 is located between the first gate insulating layer 3 and the second gate insulating layer 5; the third metal layer 8 includes a first capacitor plate 81 and a second capacitor plate 82 which are arranged at an interval, the first capacitor plate 81 is arranged opposite to the first gate 41 and above the second gate 42, and the second capacitor plate 82 is arranged opposite to the second gate 42 and above the second gate 42; the first gate 41, the first gate insulating layer 3 and the first capacitor plate 81 form the first capacitor 130, and the second gate 42, the first gate insulating layer 3 and the second capacitor plate 82 form the second capacitor 140.
Referring to fig. 2, in the present embodiment, the first metal layer 4 further includes a line changing layer 43, the line changing layer 43 is located between the first gate 41 and the second gate 42, and the line changing layer 43 is electrically connected to the first drain 72.
Referring to fig. 2, in the embodiment, the array substrate 100 further includes a passivation layer 9, a planarization layer 10, an anode layer 11, a pixel defining layer 12, and a light emitting layer 13; in particular, the passivation layer 9 is located on the second metal layer 7; the planarization layer 10 is located on the passivation layer 9; the anode layer 11 is located on the planarization layer 10 and electrically connected to the second drain electrode 74; the pixel defining layer 12 is located on the anode layer 11; the light emitting layer 13 is located on the pixel defining layer 12 and electrically connected to the anode layer 11.
The anode layer 11 may be a transparent electrode, and the material of the anode layer 11 includes Indium Tin Oxide (ITO) or nano silver.
By adopting the array substrate 100 of this embodiment, a CMOS circuit structure formed by the separately driven low-temperature polysilicon thin film transistor unit 110 and the metal oxide thin film transistor unit 120 may be adopted in the array substrate row driving region 102, so as to realize an ultra-narrow frame, and the CMOS circuit structure may be used to form a latch or an inverter, etc.
Fig. 5 is a schematic diagram of a latch. The latch is formed by cross-connecting the input and output terminals of two nand gates, and has two input terminals R, S and two output terminals Q, Q. The method can be realized by applying a CMOS circuit in which a plurality of the ltps tft units 110 and a plurality of the mos tft units 120 form a nand gate.
Fig. 6 is a schematic diagram of the circuit structure of the inverter. The inverter is connected with an output end by the drain electrode of the polycrystalline silicon layer 2a of the low-temperature polycrystalline silicon thin film transistor unit 110 and the drain electrode of the semiconductor oxide layer 2b of the metal oxide transistor unit 120 at the same time; the first gate 41 of the low temperature polysilicon thin film transistor unit 110 and the second gate 42 of the metal oxide transistor unit 120 are connected to an input terminal, the input terminal is connected to an IN signal, the IN signal is simultaneously used as the gate signals of the low temperature polysilicon thin film transistor unit 110 and the metal oxide transistor unit 120, and one of the low temperature polysilicon thin film transistor unit 110 or the metal oxide transistor unit 120 is selectively turned on according to the high and low potentials of the gate signals, so that the data signal of the low temperature polysilicon thin film transistor unit 110 or the metal oxide transistor unit 120 is selectively turned on as an output signal. When the IN signal is Vgh, the metal oxide transistor unit 120 is turned on, and the output end outputs the data signal of the metal oxide transistor unit 120; when the IN signal is Vgl, the low temperature polysilicon thin film transistor unit 110 is turned on, and the output end outputs the data signal of the low temperature polysilicon thin film transistor unit 110.
Referring to fig. 7, the present invention further provides a method for manufacturing an array substrate 100, where the array substrate 100 has a display area 101 and an array substrate row driving area 102, and the method includes the following steps:
s1, manufacturing a substrate base plate 1;
s2, manufacturing a low-temperature polycrystalline silicon thin film transistor unit 110, and manufacturing the low-temperature polycrystalline silicon thin film transistor unit 110 on the substrate base plate 1 and in the display area 101 and the array base plate row driving area 102;
s3, manufacturing a first capacitor 130, and manufacturing the first capacitor 130 in the overlapping area of the low-temperature polycrystalline silicon thin film transistor unit 110;
s4, fabricating a metal oxide transistor unit 120, fabricating the metal oxide transistor unit 120 on the substrate 1 and in the array substrate row driving region 102, wherein the metal oxide transistor unit 120 and the low temperature polysilicon thin film transistor unit 110 are disposed at an interval; and
s5, fabricating a second capacitor 140, and fabricating the second capacitor 140 in the overlapping region of the metal oxide transistor cell 120.
Referring to fig. 3, a schematic diagram of a circuit structure of the low temperature polysilicon tft unit 110 is shown, where the circuit structure of the low temperature polysilicon tft unit 110 includes 2T1C or 7T 1C. Referring to fig. 4, a circuit structure of the metal oxide transistor unit 120 is shown, and the circuit structure of the metal oxide transistor unit 120 includes 2T1C or 3T 1C.
Referring to fig. 8, in the present embodiment, the step S2 of fabricating the low temperature polysilicon thin film transistor cell 110 and the step S4 of fabricating the metal oxide transistor cell 120 specifically include the steps of:
s21, manufacturing an interval polycrystalline silicon layer 2a and a semiconductor oxide layer 2b, and manufacturing the interval polycrystalline silicon layer 2a and the semiconductor oxide layer 2b on the substrate base plate 1; the polycrystalline silicon layer 2a is doped with P-type ions, the semiconductor oxidation layer 2b is doped with N-type ions, and the material of the semiconductor oxidation layer 2b comprises IGZO, IZTO or IGZTO, preferably IGZO;
s22, manufacturing a first gate insulating layer 3, and manufacturing the first gate insulating layer 3 on the polycrystalline silicon layer 2a and the semiconductor oxide layer 2 b;
s23, forming a first metal layer 4, and forming the first metal layer 4 on the first gate insulating layer 3; the first metal layer 4 is patterned to form a first gate 41 and a second gate 42 which are arranged at intervals, wherein the first gate 41 is located above the polysilicon layer 2a, and the second gate 42 is located above the semiconductor oxide layer 2 b;
s24, forming a second gate insulating layer 5, and forming the second gate insulating layer 5 on the first metal layer 4;
s25, forming an interlayer insulating layer 6, and forming the interlayer insulating layer 6 on the second gate insulating layer 5; and
s26, forming a second metal layer 7, and forming the second metal layer 7 on the interlayer insulating layer 6; the second metal layer 7 is patterned to form a first source 71, a first drain 72, a second source 73 and a second drain 74 which are arranged at intervals, wherein the first source 71 and the first drain 72 are respectively electrically connected with the polysilicon layer 2a, and the second source 73 and the second drain 74 are respectively electrically connected with the semiconductor oxide layer 2 b;
wherein the polysilicon layer 2a, the first gate insulating layer 3, the first gate 41, the second gate insulating layer 5, the first source 71 and the first drain 72 form the silicon thin film transistor unit 110; the semiconductor oxide layer 2b, the first gate insulating layer 3, the second gate 42, the second gate insulating layer 5, the second source 73, and the second drain 74 form the metal oxide transistor unit 120.
In this embodiment, the processes of the low temperature polysilicon thin film transistor unit 110 and the metal oxide thin film transistor unit 120 are compatible, so that the process is simplified and the production cost is low. Particularly, the first source electrode 71, the first drain electrode 72, the second source electrode 73 and the second drain electrode 74 can be formed by patterning through a mask process, and the first source electrode 71, the first drain electrode 72, the second source electrode 73 and the second drain electrode 74 can be formed by patterning through a mask process.
In this embodiment, the step S23 of fabricating the first metal layer 4 further includes:
and manufacturing a line changing layer 43, wherein the first metal layer 4 is patterned to form the line changing layer 43 between the first grid 41 and the second grid 42, and the line changing layer 43 is electrically connected with the first drain 72.
The first gate 41, the second gate 42 and the wire changing layer 43 can be patterned by a mask process, so that the process is simplified and the production cost is low.
Referring to fig. 9, in the present embodiment, the step S3 of fabricating the first capacitor 130 and the step S5 of fabricating the second capacitor 140 specifically include the steps of:
s31, forming a third metal layer 8, and forming the third metal layer 8 between the first gate insulating layer 3 and the second gate insulating layer 5; and
s32, patterning the third metal layer 8 to form a first capacitor plate 81 and a second capacitor plate 82 disposed at an interval, where the first capacitor plate 81 is disposed opposite to the first gate 41 and above the second gate 42, and the second capacitor plate 82 is disposed opposite to the second gate 42 and above the second gate 42;
the first gate 41, the first gate insulating layer 3 and the first capacitor plate 81 form the first capacitor 130, and the second gate 42, the first gate insulating layer 3 and the second capacitor plate 82 form the second capacitor 140.
Referring to fig. 7, in the present embodiment, after the step of fabricating the second metal layer 7, the method further includes the steps of:
s6, manufacturing a passivation layer 9, and manufacturing the passivation layer 9 on the second metal layer 7;
s7, manufacturing a flat layer 10, and manufacturing the flat layer 10 on the passivation layer 9;
s8, forming an anode layer 11, forming the anode layer 11 on the flat layer 10, wherein the anode layer 11 is electrically connected to the second drain 74; the anode layer 11 is preferably a transparent electrode, and the material of the anode layer 11 includes Indium Tin Oxide (ITO) or nano silver;
s9, manufacturing a pixel definition layer 12, and manufacturing the pixel definition layer 12 on the anode layer 11; and
s10, forming a light emitting layer 13, forming the light emitting layer 13 on the pixel defining layer 12, and electrically connecting the light emitting layer 13 with the anode layer 11.
The invention has the advantages that the invention provides the array substrate and the manufacturing method thereof, the ultra-narrow frame is realized by adopting the circuit structure of the low-temperature polycrystalline silicon thin film transistor unit in the display area of the array substrate and adopting the CMOS circuit structure formed by the low-temperature polycrystalline silicon thin film transistor unit and the metal oxide thin film transistor unit which are independently driven in the row driving area of the array substrate, and the low-temperature polycrystalline silicon thin film transistor unit and the metal oxide thin film transistor unit are compatible in the manufacturing process, the process is simplified and the production cost is low.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. An array substrate is provided with a display area and an array substrate row driving area, and is characterized by comprising:
a substrate base plate;
the low-temperature polycrystalline silicon thin film transistor unit is positioned on the substrate base plate and positioned in the display area and the array base plate row driving area;
the first capacitor is positioned in the low-temperature polycrystalline silicon thin film transistor unit;
the metal oxide transistor units are positioned on the substrate base plate, positioned in the array base plate row driving area and arranged at intervals with the low-temperature polycrystalline silicon thin film transistor units; and
and the second capacitor is positioned in the metal oxide transistor unit.
2. The array substrate of claim 1, further comprising:
the polycrystalline silicon layer and the semiconductor oxide layer are arranged at intervals and are positioned on the substrate base plate;
a first gate insulating layer on the polysilicon layer and the semiconductor oxide layer;
a first metal layer on the first gate insulating layer; the first metal layer comprises a first grid and a second grid which are arranged at intervals, wherein the first grid is positioned above the polycrystalline silicon layer, and the second grid is positioned above the semiconductor oxide layer;
a second gate insulating layer on the first metal layer;
an interlayer insulating layer on the second gate insulating layer; and
a second metal layer on the interlayer insulating layer; the second metal layer comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode which are arranged at intervals, wherein the first source electrode and the first drain electrode are respectively and electrically connected with the polycrystalline silicon layer, and the second source electrode and the second drain electrode are respectively and electrically connected with the semiconductor oxide layer;
wherein the polysilicon layer, the first gate insulating layer, the first gate, the second gate insulating layer, the first source and the first drain form the silicon thin film transistor unit; the semiconductor oxide layer, the first gate insulating layer, the second gate insulating layer, the second source, and the second drain form the metal oxide transistor unit.
3. The array substrate of claim 2, further comprising:
a third metal layer between the first gate insulating layer and the second gate insulating layer; the third metal layer comprises a first capacitor polar plate and a second capacitor polar plate which are arranged at intervals, the first capacitor polar plate is arranged opposite to the first grid and is positioned above the second grid, and the second capacitor polar plate is arranged opposite to the second grid and is positioned above the second grid;
the first gate, the first gate insulating layer and the first capacitor plate form the first capacitor, and the second gate, the first gate insulating layer and the second capacitor plate form the second capacitor.
4. The array substrate of claim 2, wherein the first metal layer further comprises a cross-line layer between the first gate and the second gate, the cross-line layer being electrically connected to the first drain.
5. The array substrate of claim 2, further comprising:
a passivation layer on the second metal layer;
a planarization layer on the passivation layer;
the anode layer is positioned on the flat layer and is electrically connected with the second drain electrode;
a pixel defining layer on the anode layer; and
and the light-emitting layer is positioned on the pixel definition layer and is electrically connected with the anode layer.
6. A manufacturing method of an array substrate, wherein the array substrate is provided with a display area and an array substrate row driving area, and is characterized by comprising the following steps:
manufacturing a substrate base plate;
manufacturing a low-temperature polycrystalline silicon thin film transistor unit, and manufacturing the low-temperature polycrystalline silicon thin film transistor unit on the substrate and in the display area and the array substrate row driving area;
manufacturing a first capacitor, and manufacturing the first capacitor in an overlapping area of the low-temperature polycrystalline silicon thin film transistor unit;
manufacturing a metal oxide transistor unit on the substrate and in the array substrate row driving area, wherein the metal oxide transistor unit and the low-temperature polycrystalline silicon thin film transistor unit are arranged at intervals; and
and manufacturing a second capacitor in an overlapping area of the second capacitor and the metal oxide transistor unit.
7. The method for manufacturing the array substrate according to claim 6, wherein the step of manufacturing the low temperature polysilicon thin film transistor unit and the step of manufacturing the metal oxide transistor unit specifically comprise the steps of:
manufacturing an interval polycrystalline silicon layer and an interval semiconductor oxide layer on the substrate;
manufacturing a first grid insulating layer, and manufacturing the first grid insulating layer on the polycrystalline silicon layer and the semiconductor oxide layer;
manufacturing a first metal layer, and manufacturing the first metal layer on the first grid insulating layer; patterning the first metal layer to form a first grid and a second grid which are arranged at intervals, wherein the first grid is positioned above the polycrystalline silicon layer, and the second grid is positioned above the semiconductor oxide layer;
manufacturing a second grid electrode insulating layer, and manufacturing the second grid electrode insulating layer on the first metal layer;
manufacturing an interlayer insulating layer, and manufacturing the interlayer insulating layer on the second grid insulating layer; and
manufacturing a second metal layer, and manufacturing the second metal layer on the interlayer insulating layer; patterning the second metal layer to form a first source electrode, a first drain electrode, a second source electrode and a second drain electrode which are arranged at intervals, wherein the first source electrode and the first drain electrode are respectively and electrically connected with the polycrystalline silicon layer, and the second source electrode and the second drain electrode are respectively and electrically connected with the semiconductor oxide layer;
wherein the polysilicon layer, the first gate insulating layer, the first gate, the second gate insulating layer, the first source and the first drain form the silicon thin film transistor unit; the semiconductor oxide layer, the first gate insulating layer, the second gate insulating layer, the second source, and the second drain form the metal oxide transistor unit.
8. The method for manufacturing the array substrate according to claim 6, wherein the step of manufacturing the first capacitor and the step of manufacturing the second capacitor specifically comprise the steps of:
manufacturing a third metal layer, and manufacturing the third metal layer between the first grid insulation layer and the second grid insulation layer; and
patterning the third metal layer to form a first capacitor electrode plate and a second capacitor electrode plate which are arranged at intervals, wherein the first capacitor electrode plate is arranged opposite to the first grid electrode and is positioned above the second grid electrode, and the second capacitor electrode plate is arranged opposite to the second grid electrode and is positioned above the second grid electrode;
the first gate, the first gate insulating layer 3 and the first capacitor plate form the first capacitor, and the second gate, the first gate insulating layer and the second capacitor plate form the second capacitor.
9. The method for manufacturing the array substrate according to claim 6, wherein the step of fabricating the first metal layer further comprises:
and manufacturing a wire changing layer, wherein the first metal layer is patterned to form the wire changing layer positioned between the first grid and the second grid, and the wire changing layer is electrically connected with the first drain.
10. The method for manufacturing the array substrate according to claim 6, further comprising, after the step of forming the second metal layer:
manufacturing a passivation layer, and manufacturing the passivation layer on the second metal layer;
manufacturing a flat layer, and manufacturing the flat layer on the passivation layer;
manufacturing an anode layer, wherein the anode layer is manufactured on the flat layer and is electrically connected with the second drain electrode;
manufacturing a pixel definition layer, and manufacturing the pixel definition layer on the anode layer; and
and manufacturing a light emitting layer on the pixel definition layer, wherein the light emitting layer is electrically connected with the anode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911273331.1A CN111081719A (en) | 2019-12-12 | 2019-12-12 | Array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911273331.1A CN111081719A (en) | 2019-12-12 | 2019-12-12 | Array substrate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111081719A true CN111081719A (en) | 2020-04-28 |
Family
ID=70314119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911273331.1A Pending CN111081719A (en) | 2019-12-12 | 2019-12-12 | Array substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111081719A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584565A (en) * | 2020-05-11 | 2020-08-25 | 武汉华星光电半导体显示技术有限公司 | Flexible array substrate and display panel |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456739A (en) * | 2013-08-16 | 2013-12-18 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| US20140131703A1 (en) * | 2011-06-24 | 2014-05-15 | Sharp Kabushiki Kaisha | Display device and method for manufacturing same |
| CN105408813A (en) * | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon and semiconducting oxide thin-film transistors |
| CN105929615A (en) * | 2016-06-21 | 2016-09-07 | 武汉华星光电技术有限公司 | Thin film transistor array substrate and liquid crystal panel |
| CN106298648A (en) * | 2016-09-12 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN106558592A (en) * | 2015-09-18 | 2017-04-05 | 鸿富锦精密工业（深圳）有限公司 | The preparation method of array base palte, display device and array base palte |
| CN107799521A (en) * | 2017-10-10 | 2018-03-13 | 深圳市华星光电半导体显示技术有限公司 | CMOS inverter and array base palte |
| CN107818991A (en) * | 2017-10-23 | 2018-03-20 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN108493198A (en) * | 2018-04-11 | 2018-09-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, organic LED display device |
| CN109300915A (en) * | 2018-09-30 | 2019-02-01 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
-
2019
- 2019-12-12 CN CN201911273331.1A patent/CN111081719A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140131703A1 (en) * | 2011-06-24 | 2014-05-15 | Sharp Kabushiki Kaisha | Display device and method for manufacturing same |
| CN103456739A (en) * | 2013-08-16 | 2013-12-18 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105408813A (en) * | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon and semiconducting oxide thin-film transistors |
| CN106558592A (en) * | 2015-09-18 | 2017-04-05 | 鸿富锦精密工业（深圳）有限公司 | The preparation method of array base palte, display device and array base palte |
| CN106558538A (en) * | 2015-09-18 | 2017-04-05 | 鸿富锦精密工业（深圳）有限公司 | The preparation method of array base palte, display device and array base palte |
| CN105929615A (en) * | 2016-06-21 | 2016-09-07 | 武汉华星光电技术有限公司 | Thin film transistor array substrate and liquid crystal panel |
| CN106298648A (en) * | 2016-09-12 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN107799521A (en) * | 2017-10-10 | 2018-03-13 | 深圳市华星光电半导体显示技术有限公司 | CMOS inverter and array base palte |
| CN107818991A (en) * | 2017-10-23 | 2018-03-20 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN108493198A (en) * | 2018-04-11 | 2018-09-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, organic LED display device |
| CN109300915A (en) * | 2018-09-30 | 2019-02-01 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584565A (en) * | 2020-05-11 | 2020-08-25 | 武汉华星光电半导体显示技术有限公司 | Flexible array substrate and display panel |
| CN111584565B (en) * | 2020-05-11 | 2023-09-26 | 武汉华星光电半导体显示技术有限公司 | Flexible array substrate and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103715196B (en) | Array substrate, manufacturing method thereof and display device | |
| CN106558593B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| JP6215053B2 (en) | Display device and manufacturing method thereof | |
| EP2278618B1 (en) | Organic light emitting display device and fabricating method thereof | |
| KR101987218B1 (en) | Array substrate, manufacturing method thereof, and display apparatus | |
| KR101540341B1 (en) | Panel structure, display device comprising the panel structure and manufacturing methods thereof | |
| US8946008B2 (en) | Organic light emitting diode display, thin film transitor array panel, and method of manufacturing the same | |
| JP6239606B2 (en) | Thin film transistor, array substrate, and manufacturing method thereof | |
| US10038074B2 (en) | Manufacture method of TFT substrate and manufactured TFT substrate | |
| US20180083142A1 (en) | Manufacture method of tft substrate and manufactured tft substrate | |
| KR20170028986A (en) | Manufacturing method and structure of oxide semiconductor tft substrate | |
| US6635504B2 (en) | Method of manufacturing organic EL display | |
| CN112635571A (en) | Thin film transistor, method of manufacturing the same, and display device including the same | |
| WO2018023955A1 (en) | Array substrate of oled display device and manufacturing method therefor | |
| CN111081719A (en) | Array substrate and manufacturing method thereof | |
| US20140077216A1 (en) | Poly-silicon tft, poly-silicon array substrate and preparing method thereof, display device | |
| KR20210086247A (en) | Display apparatus | |
| CN113450715B (en) | Display substrate, preparation method thereof and display device | |
| US11678530B2 (en) | Display substrate and preparation method thereof, and display apparatus | |
| CN115735427A (en) | Display substrate, preparation method thereof and display device | |
| CN206471332U (en) | Display panel and display device | |
| US20120104402A1 (en) | Architecture of analog buffer circuit | |
| CN114203726B (en) | Display panel and preparation method thereof | |
| CN117476683A (en) | Display panel, preparation method thereof and display device | |
| CN113658958A (en) | Display panel and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200428 |