WO2015074420A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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WO2015074420A1
WO2015074420A1 PCT/CN2014/081196 CN2014081196W WO2015074420A1 WO 2015074420 A1 WO2015074420 A1 WO 2015074420A1 CN 2014081196 W CN2014081196 W CN 2014081196W WO 2015074420 A1 WO2015074420 A1 WO 2015074420A1
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layer
drain
plate
forming
electrode
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PCT/CN2014/081196
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English (en)
French (fr)
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WO2015074420A9 (zh
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徐文清
田慧
许晓伟
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京东方科技集团股份有限公司
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Priority to US14/422,343 priority Critical patent/US9524991B2/en
Publication of WO2015074420A1 publication Critical patent/WO2015074420A1/zh
Publication of WO2015074420A9 publication Critical patent/WO2015074420A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present invention belongs to the field of display technology, and relates to an array substrate and a method of fabricating the same, and a display device including the array substrate. Background technique
  • Thin Film Transistor is the main driving device of flat panel display panels, which is directly related to the development direction of high performance flat panel display devices.
  • thin film transistors There are various types of thin film transistors, and there are also various materials for preparing thin film transistors of corresponding structures.
  • amorphous silicon and polycrystalline silicon are currently commonly used materials for preparing thin film transistors.
  • amorphous silicon itself has many unavoidable disadvantages, such as low mobility and low stability.
  • low temperature poly-Silicon (LTPS) has high mobility and stability. Its mobility can reach tens or even hundreds of times of amorphous silicon. Therefore, the technology for preparing thin film transistors using low-temperature polysilicon materials has been rapidly developed.
  • LCDs liquid crystal display devices
  • OLEDs Organic Light-Emitting Diodes
  • the low-temperature polysilicon thin film transistor has the above advantages, in the low-temperature polysilicon thin film transistor (LTPS TFT) array substrate, in order to achieve continuous driving capability, it is also necessary to simultaneously set a storage capacitor (Storing Capacity: Cs for short), especially at a high resolution. In the rate display panel, it is usually necessary to equip the low temperature polysilicon thin film transistor with a storage capacitor that can be charged faster to meet the driving needs.
  • 1 is a cross-sectional view showing the structure of a LTPS TFT array substrate in the prior art.
  • the array substrate includes a buffer layer 2, an active layer 3, a first insulating layer 4', a gate 5, a second insulating layer 6', a source 71, and a drain 72, which are sequentially disposed above the substrate 1.
  • the eight patterning processes are: using an active layer mask (a-Si Mask), through the first patterning process.
  • the storage capacitor has a disadvantage of a slow charge and discharge speed; and a pattern of the second plate 12 including the gate 5 and the storage capacitor C s is formed by a third patterning process using a gate mask (Gate Mask) In this step, the second plate of the storage capacitor C s is formed by using the gate metal; forming a contact in the second insulating layer 6 ′ by the fourth patterning process by using a contact mask (Contact Mask) for connecting Source 7 1.
  • Gate Mask gate mask
  • a pattern of the display electrode 10 is formed by an eighth patterning process using a pixel electrode mask (I TO Ma sk).
  • the invention provides an array substrate, a preparation method thereof, and a display device comprising the array substrate, wherein the preparation process of the array substrate is simplified, and the storage capacitor therein has a faster charging speed.
  • the technical solution for solving the technical problem to be solved by the present invention is an array substrate comprising a substrate and a thin film transistor and a storage capacitor disposed on the substrate, the thin film transistor including a gate, a source, a drain, and a gate insulating layer disposed between the source, the drain, and the gate, the storage capacitor including a first plate, a second plate, and the first plate and the first a dielectric layer between the two plates, wherein the first plate and the second plate are each formed of a metal material, and the dielectric layer and the gate insulating layer are formed of the same material.
  • the first plate is disposed on the substrate in the same layer as the source and the drain.
  • the array substrate further includes a buffer layer disposed above the source and the drain, the buffer layer partially covering the source and opening a source via, and partially covering The drain is open with a drain via.
  • the array substrate further includes a drain via disposed above the buffer layer and connected to the drain.
  • the array substrate further includes the gate insulating layer disposed above the active layer, the gate insulating layer extending above the first plate to form the dielectric layer, the dielectric The layer completely covers the first plate.
  • the gate and the second plate are formed of the same material, the gate is disposed above the gate insulating layer, and the second plate is disposed at a corresponding layer of the dielectric layer Above the first plate.
  • the source, the drain, the gate, the first plate, and the second plate are both made of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium and copper.
  • the active layer is formed of a low temperature polysilicon material.
  • the buffer layer is a single layer structure or a stacked structure of a plurality of sublayers, and the buffer layer is formed of silicon oxide or silicon nitride.
  • an upper interlayer insulating layer and a display electrode are disposed above the gate electrode and the second electrode plate, and a via hole is formed in a region of the interlayer insulating layer corresponding to the drain. The display electrode is electrically connected to the drain through the via.
  • the interlayer insulating layer comprises a passivation layer and a organic layer
  • the passivation layer is a single layer structure or a stacked structure of a plurality of sublayers, using silicon oxide, silicon nitride, germanium oxide or Forming an aluminum oxide
  • the organic layer is formed of an organic resin
  • the organic resin includes an acrylic film-forming resin, a phenol resin film-forming resin, a vinyl polymer film-forming resin, or a polyimide film-forming resin
  • the display electrode is a metal anode, and the metal anode is formed of an inorganic metal oxide, an organic conductive polymer or a metal material having an electrical conductivity and a high work function value, and the inorganic metal oxide includes indium tin oxide or an oxidized word.
  • the organic conductive polymer includes PEDOT: SS, PAN I, and the metal material includes gold, copper, silver or platinum.
  • the interlayer insulating layer comprises a passivation layer
  • the passivation layer is a single layer structure or a stacked structure of a plurality of sublayers, using silicon oxide, silicon nitride, tantalum oxide or aluminum oxide.
  • the display electrode is a pixel electrode, and the pixel electrode is made of at least one of indium gallium oxide, indium oxide, oxidized, indium oxide, indium tin oxide, indium gallium tin oxide, and indium tin oxide. form.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate includes a substrate and a thin film transistor and a storage capacitor disposed on the substrate, the thin film transistor including a source, a drain, a gate, and a source, a gate insulating layer between the drain and the gate, the storage capacitor comprising a first plate, a second plate, and a dielectric layer disposed between the first plate and the second plate
  • the method includes: forming a first plate with the source and the drain by using the same patterning process; forming the dielectric layer and the gate insulating layer by the same process; and using the same composition The process forms the second plate and the gate.
  • the forming of the first plate and the source and the drain by the same patterning process comprises: Step S 1 ): forming a source/drain metal electrode film and a buffer film on the substrate, a patterning process of forming a pattern including the source, the drain, and the first plate, and forming the source and the drain over the drain The pattern of the buffer layer.
  • the preparation method further includes a step S2): forming an amorphous silicon film on the substrate on which the source, the drain and the first plate are formed, to the amorphous
  • the silicon film is crystallized to form a polysilicon film, the polysilicon film is doped, and a patterning process is performed to form a pattern including the active layer.
  • the forming the dielectric layer and the gate insulating layer by using the same process includes: Step S3): forming the gate insulating layer and the gate metal electrode film on the substrate on which step S2) is completed,
  • the gate insulating layer also extends to a region that completely covers the first plate to form the dielectric layer of the storage capacitor.
  • the forming the second plate and the gate by using the same patterning process comprises: forming a pattern including the gate and the second plate by using a patterning process, The two plates are disposed corresponding to the first plates.
  • the preparation method further comprises: doping the region of the active layer corresponding to the source and the drain by ion implantation to enhance the active layer and the An ohmic contact of the source and the drain.
  • the manufacturing method further includes: forming a pattern including an interlayer insulating layer and a display electrode over the gate electrode and the second electrode plate, the interlayer insulating layer corresponding to the drain electrode A via hole is formed in the region, and the drain and the display electrode are electrically connected through the via.
  • forming the pattern including the interlayer insulating layer and the display electrode comprises: Step S4): forming a passivation film on the substrate on which step S3) is completed, using a patterning process, forming including blunt Forming a pattern of a layer, and forming a passivation layer via in a region of the passivation layer corresponding to the drain; step S5): forming an organic film on the substrate on which step S4) is completed, using a patterning process, forming a pattern including an organic layer, and forming an organic layer via in a region of the organic layer corresponding to the drain; step S6): forming a conductive on the substrate on which step S5) is completed
  • the metal film is patterned by a patterning process including a metal anode through which the metal anode is electrically connected to the drain through the organic layer via and the passivation layer via.
  • the pattern of the pole includes: Step S4): forming a passivation film on the substrate on which step S3) is completed, forming a pattern including a passivation layer by using a patterning process, and corresponding to the passivation layer Forming a passivation layer via in the region of the drain; Step S5): forming a transparent conductive metal film on the substrate on which step S4) is completed, and forming a pattern including the pixel electrode by using a patterning process, The pixel electrode is electrically connected to the drain through the passivation layer via.
  • the beneficial effects of the present invention are: Compared with the low temperature polysilicon thin film transistor (LTPS TFT) array substrate in the prior art, the LTPS TFT array substrate of the present invention has a surface resistance of a plate due to a storage capacitor formed by a metal material. Smaller, the charging speed of the storage capacitor C s in the array substrate can be increased, and the display quality of the display device including the array substrate can be improved, thereby ensuring the preparation of the high-resolution display device.
  • the method for fabricating the array substrate reduces the number of patterning processes and one ion implantation process, and simplifies the fabrication process of the array substrate.
  • FIG. 1 is a cross-sectional view of an array substrate in the prior art.
  • Fig. 2 is a cross-sectional view showing the array substrate in the first embodiment of the present invention.
  • 3A to 3M are cross-sectional views of the array substrate of Fig. 2 in various steps of the preparation process.
  • Fig. 3A is a cross-sectional view showing formation of a source/drain metal electrode film and a buffer film.
  • Figure 3B is a cross-sectional view of a pattern forming a first plate including a source, a drain, a buffer layer, and a storage capacitor.
  • Fig. 3C is a cross-sectional view showing the formation of an active film.
  • Fig. 3D is a cross-sectional view showing the formation of a pattern including an active layer.
  • Fig. 3E is a cross-sectional view showing the formation of a gate insulating layer.
  • Fig. 3F is a cross-sectional view showing a pattern of a gate metal electrode film.
  • Figure 3G is a cross-sectional view of a pattern forming a second plate including a gate and a storage capacitor.
  • Fig. 3H is a cross-sectional view showing the formation of a passivation film.
  • Figure 31 is a cross-sectional view showing a pattern including via holes of a passivation layer and a passivation layer.
  • 3J is a cross-sectional view showing the formation of an organic film.
  • Fig. 3K is a cross-sectional view showing a pattern including via holes of an organic layer and an organic layer.
  • Fig. 3L is a cross-sectional view showing the formation of a conductive metal film.
  • Figure 3M is a cross-sectional view of a pattern forming a display electrode.
  • the array substrate of the present invention a method for fabricating the same, and a display device including the array substrate will be further described in detail below with reference to the accompanying drawings and embodiments.
  • the array substrate includes a substrate and a thin film transistor and a storage capacitor disposed on the substrate, the thin film transistor including a gate, a source, a drain, and a source, the drain and the gate a gate insulating layer, the storage capacitor includes a first plate, a second plate, and a dielectric layer disposed between the first plate and the second plate, wherein the first pole
  • the plate and the second plate are each formed of a metal material, and the dielectric layer and the gate insulating layer are formed of the same material.
  • the display device includes the above array substrate.
  • the method for fabricating the array substrate includes the steps of forming a thin film transistor and a storage capacitor on a substrate, and the step of forming the thin film transistor includes the steps of forming a source, a drain, and a gate, and the source and the drain.
  • a step of forming a gate insulating layer with the gate the step of forming the storage capacitor includes forming a first plate, a second plate, and forming between the first plate and the second plate a step of forming a dielectric layer, wherein the first plate is formed by the same patterning process as the source and the drain, and the second plate and the gate are formed by the same patterning process, The dielectric layer is formed using the same process as the gate insulating layer.
  • Example 1 Example 1:
  • This embodiment provides an array substrate suitable for an OLED display device.
  • the array substrate comprises a substrate 1, a substrate 1 is formed on the thin film transistor TFT and a storage capacitor C s, the thin film transistor TFT includes a gate electrode 5, the source electrode 71, drain electrode 72 and the source 71 is provided, a gate insulating layer 4 between the drain 72 and the gate 5, the storage capacitor ( 3 includes a first plate 11, a second plate 12, and a dielectric layer disposed between the first plate 11 and the second plate 12) 13.
  • the first plate 11 and the second plate 12 are both formed of a metal material, and the dielectric layer 13 and the gate insulating layer 4 are formed of the same material.
  • the source 71 and the drain 72 are disposed on the substrate 1 , and the buffer layer 2 is disposed above the source 71 and the drain 72 .
  • the buffer layer 2 partially covers the source 71 and opens the source via.
  • the via holes involved in the structure are not specifically shown in the figure), and the drain 72 is partially covered and the drain via is opened.
  • the active layer 3 is disposed above the buffer layer 2, and the active layer 3 passes through the source.
  • the pole via is connected to the source 71, connected to the drain 72 through the drain via, the gate insulating layer 4 is disposed above the active layer 3, and the gate 5 is disposed above the gate insulating layer 4, and the first plate 11 is provided.
  • the same layer as the source 71 and the drain 72 is disposed on the substrate 1, and the gate insulating layer 4 extends over the first plate 11 to form a dielectric layer 13.
  • the dielectric layer 13 completely covers the first plate 11, and the dielectric layer 13 corresponds to A second plate 12 is disposed above the first plate 11.
  • the source 71, the drain 72 and the first plate 11 are formed of at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium or copper.
  • the buffer layer 1 is a single layer structure or a stacked structure of a plurality of sublayers, and the buffer layer 2 is formed of silicon oxide or silicon nitride.
  • the buffer layer 2 is disposed above the source 71 and the drain 72, so that the gate insulating layer 4 in the subsequent thin film transistor TFT and the dielectric layer 13 in the storage capacitor C s can be in the same patterning process. Formed in the middle without having to be formed by doping.
  • the structure in which the buffer layer 2 is disposed above the source 71 and the drain 72 facilitates formation of the source 71, the drain 72, and the buffer in the same patterning process.
  • the storage capacitor C s can be formed by using the source/drain metal electrode film, the gate insulating layer and the gate metal electrode film, thereby avoiding the step of forming the plate of the storage capacitor by the doping method in the prior art, thereby improving the storage. Capacitor charging and discharging performance.
  • the gate electrode 5 and the second electrode plate 12 are formed of at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-iridium alloy, titanium or copper.
  • an interlayer insulating layer and a display electrode 10 are disposed above the gate electrode 5 and the second electrode plate 12, and a region corresponding to the drain of the interlayer insulating layer is opened.
  • the interlayer insulating layer includes a passivation layer 6 and an organic layer (flat layer) 8
  • the passivation layer 6 is a single layer structure or a stacked structure of a plurality of sub-layers, using silicon oxide, silicon nitride
  • the organic layer 8 is formed of an organic resin, and the organic resin includes an acrylic film-forming resin, a phenol resin film-forming resin, a vinyl polymer film-forming resin, or a polyimide film-forming resin.
  • the display electrode 10 is a metal anode of the OLED device, and the metal anode is formed of an inorganic metal oxide, an organic conductive polymer or a metal material having electrical conductivity and a high work function value, and the inorganic metal oxide includes oxidation.
  • Indium tin or oxidized, organic conductive polymers include PEDOT: PSS, PANI, and metallic materials include gold, copper, silver or platinum.
  • the production method of the array substrate according to the present embodiment includes a thin film transistor TFT and a storage capacitor (step 3 on the substrate 1, a thin film transistor TFT includes the step of forming a source electrode 71, drain electrode 72, the gate 5 and a source electrode 71 step, the step of forming the gate insulating layer 4 between the drain 72 and the gate electrode 5, the storage capacitor C s is formed in the step of forming comprises a first plate 11, second plate 12 and a first a step of forming a dielectric layer 13 between the plate 1 1 and the second plate 12, wherein the first plate 11 and the source 71 and the drain 72 are formed by the same patterning process, and the second plate 12 and the gate are formed.
  • the pole 5 is formed by the same patterning process, and the dielectric layer 13 and the gate insulating layer 4 are formed by the same process.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc., and the photolithography process is referred to as film formation.
  • the structure formed in the selection selects the corresponding patterning process.
  • the method for preparing the above array substrate specifically includes the following steps S1 to S6.
  • the substrate 1 is made of a transparent material such as glass and pre-cleaned. Specifically, a sputtering method, a thermal evaporation method, a plasma enhanced chemical vapor deposition (PECVD) method, a low pressure chemical vapor deposition (LPCVD) method, and an atmospheric pressure chemistry are performed on the substrate 1.
  • a sputtering method, a thermal evaporation method, a plasma enhanced chemical vapor deposition (PECVD) method, a low pressure chemical vapor deposition (LPCVD) method, and an atmospheric pressure chemistry are performed on the substrate 1.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • the buffer film 20 is formed by a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method, as shown in Fig. 3A.
  • the source 71, the drain 72, and the first plate 11 are formed of a metal such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium or copper, or a metal alloy (conductive material).
  • HTM Half Tone Mask
  • GTM Gray Tone Mask
  • the buffer layer 2 can be made of a material similar to the lattice structure of Si, so as to form an a-Si film (ie, the amorphous silicon film 30 in the next step) over the buffer layer 2, so that In the formation of the gate insulating layer 4 in the thin film transistor TFT, the dielectric layer 13 in the storage capacitor C s is formed by etching away a portion other than the region where the a-Si film overlaps the plate of the storage capacitor. Bian plate so that no storage capacitor C s is formed by the doping method.
  • the halftone mask or the gray tone mask is used once.
  • the patterning process completes the preparation of the source 71, the drain 72, and the buffer layer 2, reducing the number of exposures using the mask.
  • an amorphous silicon (a-S i ) film 30 is formed on the buffer layer 2 by deposition as shown in Fig. 3C.
  • the deposition method includes a plasma enhanced chemical vapor deposition method or a low pressure chemical vapor deposition method.
  • the amorphous silicon film 30 is crystallized, and the crystallization method includes converting the amorphous silicon film 30 into polysilicon (PS i ) by using an excimer laser crystallization method, a metal induced crystallization method or a solid phase crystallization method.
  • the film is then doped (P-type doped or N-type doped) to the polysilicon (pS i ) film to determine the conductivity type of the channel region of the thin film transistor TFT.
  • the excimer laser crystallization method and the metal induced crystallization method are two low-temperature polysilicon methods, which are commonly used to convert amorphous silicon into polycrystalline silicon.
  • the method of converting amorphous silicon into polycrystalline silicon according to the present invention is not limited to the method of using low temperature polycrystalline silicon, as long as the active layer 30 can be converted into a desired polycrystalline silicon thin film.
  • a second patterning process is used to form a pattern including the active layer 3, as shown in Fig. 3D. Namely, a photoresist is formed on the polysilicon film 30, the photoresist is exposed and developed, and then the polysilicon film 30 is dry etched to form a pattern including the active layer 3.
  • Step S 3) On completion of step S2), the substrate 50 is formed, the gate insulating layer further region the metal electrode film 4 and the gate insulating layer 4 extends to the gate completely covers the first plate 11 to form a storage capacitor C s
  • the dielectric layer 13 is formed by a patterning process to form a pattern including the gate 5 and the second plate 12, and the second plate 12 is disposed corresponding to the first plate 11.
  • the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, the electron cyclotron resonance chemical vapor deposition method, or the sputtering method in the active layer 3 and the first electrode A gate insulating layer 4 and a dielectric layer 13 are formed over the board 11 as shown in Fig. 3E.
  • the gate metal electrode film 50 is formed by a mode, a thermal evaporation method, a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or an electron cyclotron resonance chemical vapor deposition method, as shown in FIG. 3F.
  • a third patterning process a pattern including the gate 5 and the second plate 12 is formed, and the second plate 12 is disposed corresponding to the first plate 11 as shown in FIG. 3G.
  • the method further includes: doping the region of the active layer 3 (-S i ) corresponding to the source 71 and the drain 72 with an ion implantation method to enhance the active layer 3 and the source.
  • the ohmic contact of the 71 and the drain 72 ensures that the active layer 3 forms a good ohmic contact with the source 71 and the drain 72 without doping the region of the active layer 3 corresponding to the gate 5, which is Because the doping is performed after the pattern of the gate 5 is etched, the portion of the active layer 3 corresponding to the gate 5 cannot be doped due to the blocking action of the gate 5. At the same time, since this portion of PS i corresponding to the gate 5 will exist as a channel, doping is not required.
  • the ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud injection method without a mass analyzer, a plasma injection method, or a solid state diffusion injection method.
  • the low temperature polysilicon material is subjected to a plurality of steps such as crystallization, doping, ion implantation, etc., to finally form the active layer 3 having good semiconductor properties.
  • the preparation method further includes: forming a layer including the gate 5 and the second plate 1 2
  • the insulating layer and the pattern of the display electrode 10 form a via hole in a region of the interlayer insulating layer corresponding to the drain 72, and the drain electrode 72 is electrically connected to the display electrode 10 through the via hole.
  • the interlayer insulating layer includes a passivation layer 6 and an organic layer 8, and the display electrode 10 is a metal anode.
  • Forming the pattern including the interlayer insulating layer and the display electrode 10 specifically includes steps S4 to S6.
  • the passivation film 60 can be formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.
  • 60 may be a single layer of silicon oxide material, or a silicon oxide material or a silicon nitride material to form a stack of a plurality of sublayers.
  • a pattern including the passivation layer 6 is formed, and a passivation layer via hole is formed in a region corresponding to the drain electrode 72, as shown in FIG.
  • Step S5) On the substrate on which the step S4) is completed, the organic film 80 is formed, and a pattern including the organic layer 8 is formed by a patterning process, and an organic layer via hole is formed in a region corresponding to the drain electrode 72.
  • an organic film 80 is formed over the passivation layer 6 by a coating (including spin coating) method, as shown in Fig. 3J.
  • the organic film 80 is formed of an organic resin including an acrylic film-forming resin, a phenol resin film-forming resin, a vinyl polymer film-forming resin, or a polyimide film-forming resin.
  • a pattern including the organic layer 8 is formed, and an organic layer via hole is formed in the region of the organic layer 8 corresponding to the drain 72, as shown in Fig. 3K.
  • Step S6) On the substrate 1 on which the step S5) is completed, the conductive metal film 100 is formed, and a pattern including a metal anode is formed by a patterning process, the metal anode passes through the organic layer via and the passivation layer via and the drain 72. Electrical connection.
  • the conductive layer is deposited on the upper layer of the organic layer 8 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.
  • Metal film 100 is deposited on the upper layer of the organic layer 8 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.
  • the conductive metal film 100 has high reflectivity and satisfies a certain metal work function requirement, and often uses a two-layer film or a three-layer film structure, such as IT0 (indium tin oxide) / Ag (silver) / ITO (indium oxide) Tin) or Ag (silver) / IT0 (indium tin oxide) structure, or replace IT0 in the above structure with IZ0 (indium oxide), I GZ0 (indium gallium oxide) or InGaSnO (indium gallium oxide) .
  • an inorganic metal oxide an organic conductive polymer or a metal material having an electrical conductivity and a high work function value
  • the inorganic metal oxide includes indium tin oxide or an oxidized word
  • the organic conductive polymer includes PEDOT: SS, PANI, metallic materials including gold, copper, silver or Platinum.
  • a pattern including the display electrode 10 is formed, and the display electrode 10 is electrically connected to the drain electrode 72 through the organic layer via hole and the passivation layer via hole as shown in Fig. 3L.
  • a pixel defining layer (PDL) is further prepared, followed by evaporation or coating of an illuminating layer (EL), and finally sputtering or evaporation.
  • a metal cathode layer is formed, which is packaged to form an array substrate with OLED devices.
  • one of the two plates of the storage capacitor C s is formed of the same metal material as the source and the drain of the thin film transistor TFT, and the other plate is used with the gate of the thin film transistor.
  • the same metal material is formed, and the dielectric layer between the two plates is formed of the same material as the gate insulating layer, which reduces the step of forming a storage capacitor by using a single patterning process, and reduces the ion implantation process.
  • the preparation process of the array substrate is simplified.
  • the storage capacitor C s in the array substrate of the embodiment is The charging speed is faster, that is, the array substrate of the embodiment can increase the charging speed of the storage capacitor C s , and at the same time, obtain a thin film transistor with stable driving capability, thereby improving the display quality of the display device including the array substrate. It provides a guarantee for the preparation of high resolution LTPS TFT-0LED display devices.
  • This embodiment provides an array substrate suitable for a liquid crystal display device in a TN mode, a VA mode, or an ADS mode.
  • the structure of the array substrate in this embodiment is the same as that of the first embodiment except for the interlayer insulating layer and the display electrodes, and details are not described herein again.
  • the interlayer insulating layer includes a passivation layer, and the passivation layer is a single layer structure or a stacked structure of a plurality of sublayers, and is oxidized by using silicon oxide, silicon nitride, germanium oxide or aluminum oxide.
  • the display electrode is a pixel electrode, and the pixel electrode is made of indium gallium oxide, indium oxide, oxidized, indium oxide, indium tin oxide, indium gallium oxide. At least one material of tin or indium tin oxide is formed.
  • the method for preparing the array substrate in this embodiment includes steps S1 to S5.
  • Step S3) On completion of step S2), a substrate, forming a gate insulating layer and a gate metal electrode film, the gate insulating layer also extends to completely cover the area of the first plate to form the dielectric layer of the storage capacitor c s, preclude the use of a
  • the patterning process forms a pattern including a gate electrode and a second electrode plate, and the second electrode plate is disposed corresponding to the first electrode plate.
  • Step S5) On the substrate on which step S4) is completed, a transparent conductive metal film is formed, and a pattern including a pixel electrode is formed by a patterning process, and the pixel electrode is electrically connected to the drain through the passivation layer via.
  • the transparent conductive metal is at least one of transparent conductive materials such as indium gallium oxide (IGZ0), indium oxide (IZ0), indium tin oxide (IT0), or indium gallium tin oxide (InGaSnO).
  • the above array substrate in the present embodiment is suitable for a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode liquid crystal display device.
  • an insulating layer and a common electrode are formed on the array substrate, and an array substrate suitable for a liquid crystal display device of an ADS (ADvanced Super Dimension Switch) mode can be formed.
  • ADS Advanced Super Dimension Switch
  • a multi-dimensional electric field is formed by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that all the orientations between the slit electrodes in the liquid crystal cell and the electrode directly above are formed.
  • the liquid crystal molecules are capable of rotating, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology It can improve the picture quality of LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • the embodiment provides a display device comprising the array substrate of Embodiment 1 or 2.
  • the display device may be a liquid crystal display device or an electroluminescence display device, and may have any display such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like. Functional product or part.
  • the display device in this embodiment has better display quality.
  • the invention discloses a structure and a corresponding preparation method of a low temperature polysilicon thin film transistor (LTPS TFT) array substrate.
  • the storage capacitor is formed by using a metal material.
  • the surface resistance of the plate and the plate is small, which can increase the charging speed of the storage capacitor C s in the array substrate, thereby improving the display quality of the display device including the array substrate, and providing a guarantee for the preparation of the high-resolution display device.
  • TFT-0LED display devices Especially suitable for TFT-0LED display devices.
  • the two patterning processes and the one-time ion implantation process are reduced, and the fabrication process of the array substrate is simplified.

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Abstract

本发明提供一种阵列基板及其制备方法、和包含该阵列基板的显示装置，所述阵列基板包括基底以及设置于所述基底上的薄膜晶体管和存储电容，所述薄膜晶体管包括栅极、源极、漏极以及设置于所述源极、所述漏极与所述栅极之间的栅绝缘层，所述存储电容包括第一极板、第二极板以及设置于所述第一极板与所述第二极板之间的电介质层，其中，所述第一极板与所述第二极板均采用金属材料形成，所述电介质层与所述栅绝缘层采用相同的材料形成。该阵列基板相比现有技术中的阵列基板，能提高阵列基板中存储电容的充电速度，进而提高包含该阵列基板的显示装置的显示质量。此外，该阵列基板的制备方法简单。

Description

阵列基板及其制备方法和显示装置
技术领域
本发明属于显示技术领域， 涉及阵列基板及其制备方法、 和 包含该阵列基板的显示装置。 背景技术
随着显示技术的发展， 人们对显示画质的需求日益增长， 对 高画质、 高分辨率的平板显示装置的需求越来越普遍， 也越来越 受到显示面板厂家的重视。
薄膜晶体管 （Thin Film Transistor, 简称 TFT) 是平板显 示面板的主要驱动器件， 直接关系到高性能平板显示装置的发展 方向。 存在多种结构的薄膜晶体管， 也存在多种制备相应结构的 薄膜晶体管的材料， 例如， 非晶硅和多晶硅都是目前常用的制备 薄膜晶体管的材料。 然而， 非晶硅本身存在很多无法避免的缺点， 比如低迁移率、 低稳定性等， 与此相比， 低温多晶硅 （ Low Temperature Poly-Silicon, 简称 LTPS) 具有较高的迁移率及稳 定性， 其迁移率可达非晶硅的几十甚至几百倍。 因此， 釆用低温 多晶硅材料制备薄膜晶体管的技术得到了迅速发展， 由 LTPS衍生 的新一代液晶显示装置 （Liquid Crystal Display: 简称 LCD ) 或 有机电致发光显示装置 （Organic Light-Emitting Diode: 简称 0LED) 成了重要的显示技术， 尤其是 0LED显示装置， 由于 0LED 具有超薄、 低功耗、 自身发光等特点， 备受用户的青睐。
虽然低温多晶硅薄膜晶体管具有上述优点， 但是， 在低温多 晶硅薄膜晶体管 （LTPS TFT) 阵列基板中， 为了实现持续的驱动 能力， 还需要同时设置存储电容（ Storing Capacity: 简称 Cs) , 尤其是在高分辨率显示面板中， 通常需要为低温多晶硅薄膜晶体 管配备能较快充电的存储电容， 才能满足驱动需要。 图 1为现有技术中的 LTPS TFT阵列基板的结构剖视图。其中 , 该阵列基板包括依次设置于基底 1上方的緩冲层 2、 有源层 3、 第 一绝缘层 4' 、 栅极 5、 第二绝缘层 6' 、 源极 71、 漏极 72、 第三 绝缘层 8' 、 平坦层 9和显示电极 10。 目前， 该结构的阵列基板 需要釆用八张掩模板进行八次构图工艺才能制备完成， 这八次构 图工艺分别是： 利用有源层掩模板（a-Si Mask) , 通过第一次构图 工艺形成包括有源层 3的图形； 利用存储电容掩模板（Cs Mask) , 通过第二次构图工艺在第一绝缘层 4' 中进行部分 p-Si掺杂， 以 形成包括存储电容 Cs的第一极板 11的图形， 在该步骤中， 通过第 一次离子注入进行掺杂， 以形成存储电容 cs的第一极板， 但是， 由于存储电容的第一极板釆用离子注入的方法形成， 因此， 存储 电容存在充放电速度较慢的缺点； 利用栅极掩模板（Gate Mask) , 通过第三次构图工艺形成包括栅极 5及存储电容 Cs的第二极板 12 的图形， 在该步骤中， 釆用栅金属形成存储电容 Cs的第二极板； 利用接触孔掩模板（Contact Mask) , 通过第四次构图工艺在第二 绝缘层 6' 中形成包括用于连接源极 71、 漏极 72与有源层 3的接 触孔的图形； 利用源漏极掩模板（S/D Mask) , 通过第五次构图工 艺形成包括源极 71、 漏极 72的图形； 利用过孔掩模板（VIA Hole Mask) , 通过第六次构图工艺在第三绝缘层 8' 中形成包括显示电 极 10与漏极 72之间的桥接过孔的图形； 利用平坦层掩模板（PLN
Mask) , 通过第七次构图工艺在平坦层 9 中形成包括显示电极 10 与漏极 72之间的桥接过孔的图形， 并使阵列基板平坦化， 以便在 平坦的阵列基板上沉积电极层； 利用像素电极掩模板（ I TO Ma s k) , 通过第八次构图工艺形成显示电极 10的图形。
可见， 现有技术中， 制作包含 LTPS TFT和 Cs的阵列基板的工 艺复杂、 流程较多， 造成了较高的生产成本， 同时， 由于存储电 容的一个极板釆用掺杂方式形成， 导致存储电容的充电速度受影 响， 降低了 LTPS TFT阵列基板的竟争优势。 发明内容 足， 提供一种阵列基板及其制备方法、 和包含该阵列基板的显示 装置， 该阵列基板的制备工艺简化， 且其中的存储电容具有较快 的充电速度。
解决本发明所要解决的技术问题所釆用的技术方案是一种阵 列基板， 包括基底以及设置于所述基底上的薄膜晶体管和存储电 容， 所述薄膜晶体管包括栅极、 源极、 漏极以及设置于所述源极、 所述漏极与所述栅极之间的栅绝缘层， 所述存储电容包括第一极 板、 第二极板以及设置于所述第一极板与所述第二极板之间的电 介质层， 其中， 所述第一极板与所述第二极板均釆用金属材料形 成， 所述电介质层与所述栅绝缘层釆用相同的材料形成。
优选的是， 所述第一极板与所述源极、 所述漏极同层设置于 所述基底上。
优选的是， 所述阵列基板还包括设置在所述源极与所述漏极 的上方的緩冲层， 所述緩冲层局部覆盖所述源极且开设有源极过 孔、 还局部覆盖所述漏极且开设有漏极过孔。
优选的是， 所述阵列基板还包括设置在所述緩冲层的上方的 述漏极过孔与所述漏极连接。
优选的是， 所述阵列基板还包括设置在所述有源层的上方的 所述栅绝缘层， 所述栅绝缘层延伸至所述第一极板的上方形成所 述电介质层， 所述电介质层完全覆盖所述第一极板。
优选的是， 所述栅极与所述第二极板釆用相同材料形成， 所 述栅极设置在所述栅绝缘层的上方， 所述第二极板设置在所述电 介质层的对应着所述第一极板的上方。
优选的是， 所述源极、 所述漏极、 所述栅极与所述第一极板、 所述第二极板均釆用钼、 钼铌合金、 铝、 铝钕合金、 钛和铜中的 至少一种形成， 所述有源层釆用低温多晶硅材料形成。
优选的是， 所述緩冲层为单层结构或多个子层的叠层结构， 所述緩冲层釆用硅氧化物或硅氮化物形成。 优选的是， 所述栅极和所述第二极板的上方还设置有层间绝 缘层和显示电极， 所述层间绝缘层的对应着所述漏极的区域中开 设有过孔， 所述显示电极通过所述过孔与所述漏极电连接。
优选的是， 所述层间绝缘层包括钝化层和有机层， 所述钝化 层为单层结构或多个子层的叠层结构， 釆用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物形成， 所述有机层釆用有机树脂形成， 所述 有机树脂包括丙烯酸类成膜树脂、 酚醛树脂类成膜树脂、 乙烯基 聚合物成膜树脂或聚亚胺成膜树脂， 所述显示电极为金属阳极， 所述金属阳极釆用具有导电性能及高功函数值的无机金属氧化 物、 有机导电聚合物或金属材料形成， 所述无机金属氧化物包括 氧化铟锡或氧化辞， 所述有机导电聚合物包括 PEDOT: SS、 PAN I , 所述金属材料包括金、 铜、 银或铂。
优选的是， 所述层间绝缘层包括钝化层， 所述钝化层为单层 结构或多个子层的叠层结构， 釆用硅氧化物、 硅氮化物、 铪氧化 物或铝氧化物形成， 所述显示电极为像素电极， 所述像素电极釆 用氧化铟镓辞、 氧化铟、 氧化辞、 氧化铟辞、 氧化铟锡、 氧化铟 镓锡和氧化铟锡辞中的至少一种材料形成。
一种显示装置， 包括上述的阵列基板。
一种阵列基板的制备方法， 所述阵列基板包括基底以及设置 于所述基底上的薄膜晶体管和存储电容， 所述薄膜晶体管包括源 极、 漏极、 栅极以及设置于所述源极、 所述漏极与所述栅极之间 的栅绝缘层， 所述存储电容包括第一极板、 第二极板以及设置于 所述第一极板与所述第二极板之间的电介质层， 其中， 所述方法 包括： 釆用同一构图工艺形成第一极板与所述源极和所述漏极； 釆用同一工艺形成所述电介质层与所述栅绝缘层； 以及釆用同一 构图工艺形成所述第二极板与所述栅极。
优选的是， 釆用同一构图工艺形成所述第一极板与所述源极 和所述漏极包括： 步骤 S 1 ) : 在所述基底上形成源漏金属电极膜 和緩冲膜， 釆用一次构图工艺， 形成包括所述源极、 所述漏极和 所述第一极板的图形， 以及在所述源极、 所述漏极上方形成包括 緩冲层的图形。
优选的是， 所述制备方法还包括步骤 S2 ) ： 在形成有所述源 极、 所述漏极和所述第一极板的所述基底上， 形成非晶硅膜， 对 所述非晶硅膜进行晶化以形成多晶硅膜， 对所述多晶硅膜进行掺 杂， 并釆用一次构图工艺， 形成包括有源层的图形。
优选的是， 所述釆用同一工艺形成所述电介质层与所述栅绝 缘层包括： 步骤 S3 ) : 在完成步骤 S2 ) 的所述基底上， 形成所述 栅绝缘层和栅金属电极膜， 所述栅绝缘层还延伸至完全覆盖所述 第一极板的区域， 以形成所述存储电容的所述电介质层。
优选的是， 所述釆用同一构图工艺形成所述第二极板与所述 栅极包括： 釆用一次构图工艺， 形成包括所述栅极和所述第二极 板的图形， 所述第二极板与所述第一极板对应设置。
优选的是， 该制备方法进一步包括： 釆用离子注入法， 将所 述有源层的对应着所述源极和所述漏极的区域进行掺杂， 以增强 所述有源层与所述源极和所述漏极的欧姆接触。
优选的是， 该制备方法进一步包括： 在所述栅极和所述第二 极板的上方形成包括层间绝缘层以及显示电极的图形， 所述层间 绝缘层的对应着所述漏极的区域中形成过孔， 所述漏极与所述显 示电极通过所述过孔电连接。
优选的是， 形成包括所述层间绝缘层以及所述显示电极的图 形包括： 步骤 S4 ) : 在完成步骤 S3 )的所述基底上， 形成钝化膜， 釆用一次构图工艺， 形成包括钝化层的图形， 并在所述钝化层的 对应着所述漏极的区域中形成钝化层过孔； 步骤 S5 ) : 在完成步 骤 S4 ) 的所述基底上， 形成有机膜， 釆用一次构图工艺， 形成包 括有机层的图形， 并在所述有机层的对应着所述漏极的区域中形 成有机层过孔； 步骤 S6 ) : 在完成步骤 S5 ) 的所述基底上， 形成 导电金属膜， 釆用一次构图工艺， 形成包括金属阳极的图形， 所 述金属阳极通过所述有机层过孔和所述钝化层过孔与所述漏极电 连接。
或者， 优选的是， 形成包括所述层间绝缘层以及所述显示电 极的图形包括： 步骤 S4 ) : 在完成步骤 S 3 ) 的所述基底上， 形成 钝化膜， 釆用一次构图工艺， 形成包括钝化层的图形， 并在所述 钝化层的对应着所述漏极的区域中形成钝化层过孔； 步骤 S 5 ) ： 在完成步骤 S 4 ) 的所述基底上， 形成透明导电金属膜， 釆用一次 构图工艺， 形成包括像素电极的图形， 所述像素电极通过所述钝 化层过孔与所述漏极电连接。
本发明的有益效果是： 相比现有技术中的低温多晶硅薄膜晶 体管 （LTPS TFT ) 阵列基板， 本发明的 LTPS TFT阵列基板由于釆 用金属材料形成的存储电容的极板， 极板的面电阻较小， 能提高 阵列基板中存储电容 Cs的充电速度， 进而提高包含该阵列基板的 显示装置的显示质量， 为高分辨率的显示装置的制备提供了保证。 此外， 该阵列基板的制备方法减少了两次构图工艺和一次离子注 入工艺， 简化了阵列基板的制作流程。
图 1为现有技术中的阵列基板的剖视图。
图 2为本发明的实施例 1中的阵列基板的剖视图。
图 3A至图 3M为图 2中的阵列基板在制备过程的各步骤中的 剖视图。
图 3A为形成源漏金属电极膜和緩冲膜的剖视图。
图 3B为形成包括源极、 漏极、 緩冲层和存储电容的第一极板 的图形的剖视图。
图 3C为形成有源膜的剖视图。
图 3D为形成包括有源层的图形的剖视图。
图 3E为形成栅绝缘层的剖视图。
图 3F为形成栅金属电极膜的图形的剖视图。
图 3G 为形成包括栅极和存储电容的第二极板的图形的剖视 图。
图 3H为形成钝化膜的剖视图。
图 31为形成包括钝化层和钝化层过孔的图形的剖视图。 图 3J为形成有机膜的剖视图。
图 3K为形成包括有机层和有机层过孔的图形的剖视图。
图 3L为形成导电金属膜的剖视图。
图 3M为形成显示电极的图形的剖视图。
附图标记： 1 -基底； 2 -緩冲层； 20 -緩冲膜； 3 -有源层； 30- 非晶硅膜； 4-栅绝缘层； 4 ' -第一绝缘层； 5-栅极； 50-栅金属电 极膜； 6-钝化层； 60-钝化膜； 6 ' -第二绝缘层； 70-源漏金属电 极膜； 71-源极； 72-漏极； 8-有机层； 80-有机膜； 8 ' -第三绝缘 层； 9-平坦层； 1 0-显示电极； 1 00-导电金属膜； 1 1 -第一极板； 1 2-第二极板； 1 3-电介质层。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明的阵列基板及其制备方法、 和包 含该阵列基板的显示装置作进一步详细描述。
所述阵列基板包括基底以及设置于所述基底上的薄膜晶体管 和存储电容， 所述薄膜晶体管包括栅极、 源极、 漏极以及设置于 所述源极、 所述漏极与所述栅极之间的栅绝缘层， 所述存储电容 包括第一极板、 第二极板以及设置于所述第一极板与所述第二极 板之间的电介质层， 其中， 所述第一极板与所述第二极板均釆用 金属材料形成， 所述电介质层与所述栅绝缘层釆用相同的材料形 成。
所述显示装置包括上述的阵列基板。
所述阵列基板的制备方法包括在基底上形成薄膜晶体管和存 储电容的步骤， 形成所述薄膜晶体管的步骤包括形成源极、 漏极、 栅极的步骤以及在所述源极、 所述漏极与所述栅极之间形成栅绝 缘层的步骤， 形成所述存储电容的步骤包括形成第一极板、 第二 极板以及在所述第一极板与所述第二极板之间形成电介质层的步 骤， 其中， 所述第一极板与所述源极和所述漏极釆用同一构图工 艺形成， 所述第二极板与所述栅极釆用同一构图工艺形成， 所述 电介质层与所述栅绝缘层釆用同一工艺形成。 实施例 1:
本实施例提供一种阵列基板，该阵列基板适用于 0LED显示装 置。
如图 2所示， 该阵列基板包括基底 1、 形成在基底 1上的薄 膜晶体管 TFT和存储电容 Cs, 薄膜晶体管 TFT包括栅极 5、 源极 71、 漏极 72以及设置于源极 71、 漏极 72与栅极 5之间的栅绝缘 层 4, 存储电容（3包括第一极板 11、 第二极板 12以及设置于第一 极板 11与第二极板 12之间的电介质层 13,第一极板 11与第二极 板 12均釆用金属材料形成， 电介质层 13与栅绝缘层 4釆用相同 的材料形成。
其中， 源极 71与漏极 72设置于基底 1上， 源极 71与漏极 72的上方设置有緩冲层 2, 緩冲层 2局部覆盖源极 71且开设有源 极过孔 （本发明的结构中所涉及的过孔在图中均未具体标示） 、 还局部覆盖漏极 72且开设有漏极过孔， 緩冲层 2的上方设置有有 源层 3, 有源层 3通过源极过孔与源极 71连接、 通过漏极过孔与 漏极 72连接， 有源层 3的上方设置有栅绝缘层 4, 栅绝缘层 4的 上方设置有栅极 5, 第一极板 11与源极 71、 漏极 72 同层设置于 基底 1上，栅绝缘层 4延伸至第一极板 11的上方形成电介质层 13, 电介质层 13完全覆盖第一极板 11, 电介质层 13的对应着第一极 板 11的上方设置有第二极板 12。
在本实施例中， 源极 71、 漏极 72与第一极板 11釆用钼、 钼 铌合金、 铝、 铝钕合金、 钛或铜中的至少一种形成。
緩冲层 1为单层结构或多个子层的叠层结构， 緩冲层 2釆用 硅氧化物或硅氮化物形成。 与现有技术相比， 緩冲层 2设置于源 极 71与漏极 72的上方， 使得后续的薄膜晶体管 TFT中的栅绝缘 层 4与存储电容 Cs中的电介质层 13能在同一构图工艺中形成，而 不必釆用掺杂方式形成。 緩冲层 2设置于源极 71与漏极 72的上 方的结构， 既便于在同一构图工艺中形成源极 71、 漏极 72及緩冲 层 2 , 又可以利用源漏金属电极膜、栅绝缘层及栅金属电极膜形成 存储电容 Cs , 避免了现有技术中釆用掺杂方式形成存储电容的极 板的步骤， 从而改善了存储电容的充放电性能。
同时， 栅极 5与第二极板 12釆用钼、 钼铌合金、 铝、 铝钕合 金、 钛或铜中的至少一种形成。
为了利用薄膜晶体管 TFT实现对图像显示的控制， 栅极 5和 第二极板 12的上方还设置有层间绝缘层和显示电极 1 0 ,层间绝缘 层的对应着漏极的区域中开设有过孔， 显示电极 1 0通过该过孔与 漏极 72电连接。 从图 1中可见， 层间绝缘层包括钝化层 6和有机 层 （平坦层） 8 , 钝化层 6为单层结构或多个子层的叠层结构， 釆 用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物形成， 有机层 8 釆 用有机树脂形成， 有机树脂包括丙烯酸类成膜树脂、 酚醛树脂类 成膜树脂、 乙烯基聚合物成膜树脂或聚亚胺成膜树脂。 在本实施 例中， 显示电极 1 0为 0LED器件的金属阳极， 金属阳极釆用具有 导电性能及高功函数值的无机金属氧化物、 有机导电聚合物或金 属材料形成， 无机金属氧化物包括氧化铟锡或氧化辞， 有机导电 聚合物包括 PEDOT: PSS、 PANI , 金属材料包括金、 铜、 银或铂。
相应的， 本实施例中的阵列基板的制备方法包括在基底 1上 形成薄膜晶体管 TFT和存储电容（3的步骤， 形成薄膜晶体管 TFT 的步骤包括形成源极 71、 漏极 72、 栅极 5的步骤以及在源极 71、 漏极 72与栅极 5之间形成栅绝缘层 4 的步骤， 形成存储电容 Cs 的步骤包括形成第一极板 1 1、 第二极板 1 2以及在第一极板 1 1与 第二极板 12之间形成电介质层 1 3的步骤， 其中， 第一极板 1 1与 源极 71和漏极 72釆用同一构图工艺形成， 第二极板 12与栅极 5 釆用同一构图工艺形成， 电介质层 1 3与栅绝缘层 4釆用同一工艺 形成。
在本发明中， 构图工艺可只包括光刻工艺， 或者包括光刻工 艺和刻蚀步骤， 同时还可以包括打印、 喷墨等其他用于形成预定 图形的工艺， 光刻工艺是指包括成膜、 曝光、 显影等工艺过程的 利用光刻胶、 掩模板、 曝光机等形成图形的工艺。 可根据本发明 中所形成的结构选择相应的构图工艺。
上述阵列基板的制备方法具体包括如下步骤 S1至 S6。
步骤 S1 )： 在基底 1上形成源漏金属电极膜 70和緩冲膜 20, 釆用一次构图工艺， 形成包括源极 71、 漏极 72和第一极板 11的 图形， 以及在源极 71、 漏极 72上方形成包括緩冲层 2的图形。
在该步骤中， 基底 1釆用玻璃等透明材料制成、 且经过预先 清洗。 具体的， 在基底 1 上釆用溅射方式、 热蒸发方式、 等离子 体增强化学气相沉积 （Plasma Enhanced： 简称 PECVD) 方式、 低 压化学气相沉积 ( Low Pressure Chemical Vapor Deposition: 简称 LPCVD)方式、 大气压化学气相沉积（ Atmospheric Pressure
Chemical Vapor Deposition: 简称 APCVD) 方式或电子回旋 i皆振 化学气相沉积 ( Electron Cyclotron Resonance Chemical Vapor Deposition: 简称 ECR-CVD ) 方式形成源漏金属电极膜 70, 然后 釆用等离子体增强化学气相沉积方式、 低压化学气相沉积方式、 大气压化学气相沉积方式、 电子回旋谐振化学气相沉积方式、 或 溅射方式形成緩冲膜 20, 如图 3A所示。
然后， 通过釆用半色调掩模（Half Tone Mask, 简称 HTM)或 灰色调掩模（Gray Tone Mask,简称 GTM) ,通过第一次构图工艺（成 膜、 曝光、 显影、 湿法刻蚀或干法刻蚀） ， 形成同时包括源极 71、 漏极 72和第一极板 11的图形， 以及在源极 71、 漏极 72上方形成 包括緩冲层 2的图形， 如图 3Β所示。 源极 71、 漏极 72和第一极 板 11釆用如钼、 钼铌合金、 铝、 铝钕合金、 钛或铜等的金属或金 属合金（导电材料） 形成。
其中， 緩冲层 2可以选择与 Si的晶格结构相近的材料制作， 以便于在緩冲层 2的上方形成 a-Si薄膜（即下一步骤中的非晶硅 膜 30) , 使得在后续的薄膜晶体管 TFT中的栅绝缘层 4的形成过 程中， 只需将 a-Si薄膜与存储电容的极板重叠的区域以外的部分 刻蚀掉即可形成存储电容 Cs中的电介质层 13, 从而不必釆用掺杂 方式形成存储电容 Cs的极板。
本实施例中， 通过半色调掩模板或灰色调掩模板， 釆用一次 构图工艺完成源极 71、 漏极 72和緩冲层 2的制备， 减少了利用掩 模板曝光的次数。
步骤 S2 ) ： 在完成步骤 S 1 ) 的基底上， 形成非晶硅膜 30 , 对非晶硅膜 30进行晶化以形成多晶硅膜， 对多晶硅膜进行掺杂， 并釆用一次构图工艺， 形成包括有源层 3的图形。
在该步骤中， 首先， 通过沉积方式在緩冲层 2上形成非晶硅 ( a-S i )膜 30 , 如图 3C所示。 沉积方式包括等离子体增强化学气 相沉积方式、 或低压化学气相沉积方式。
接着， 对非晶硅膜 30进行晶化， 晶化方式包括釆用准分子激 光晶化方式、 金属诱导晶化方式或固相晶化方式， 将非晶硅膜 30 转变为多晶硅（ P-S i ) 膜， 然后， 对多晶硅 （p-S i ) 膜进行掺杂 ( P型掺杂或者 N型掺杂 ) , 以决定薄膜晶体管 TFT的沟道区导电 类型。 其中， 准分子激光晶化方式、 和金属诱导晶化方式为两种 低温多晶硅的方法， 是较为常用的把非晶硅转变为多晶硅的方法。 然而， 本发明将非晶硅转变为多晶硅的方法， 并不限制于釆用低 温多晶硅的方法， 只要能够将有源层 30转变为所需的多晶硅薄膜 就可以。
最后， 釆用第二次构图工艺， 形成包括有源层 3的图形， 如 图 3D所示。 即， 在多晶硅膜 30上形成一层光刻胶， 对光刻胶进 行曝光和显影， 然后对多晶硅膜 30进行干法刻蚀， 以形成包括有 源层 3的图形。
步骤 S 3 )： 在完成步骤 S2 ) 的基底上， 形成栅绝缘层 4和栅 金属电极膜 50 ,栅绝缘层 4还延伸至完全覆盖第一极板 1 1的区域， 以形成存储电容 Cs的电介质层 1 3 , 釆用一次构图工艺， 形成包括 栅极 5和第二极板 12的图形， 第二极板 12与第一极板 1 1对应设 置。
在该步骤中， 首先， 釆用等离子体增强化学气相沉积方式、 低压化学气相沉积方式、 大气压化学气相沉积方式、 电子回旋谐 振化学气相沉积方式、 或溅射方式在有源层 3和第一极板 1 1的上 方形成栅绝缘层 4和电介质层 1 3 , 如图 3E所示。 接着， 釆用溅射 方式、 热蒸发方式、 等离子体增强化学气相沉积方式、 低压化学 气相沉积方式、 大气压化学气相沉积方式或电子回旋谐振化学气 相沉积方式形成栅金属电极膜 50 , 如图 3F所示。 最后， 釆用第三 次构图工艺， 形成包括栅极 5和第二极板 12的图形， 第二极板 12 与第一极板 1 1对应设置， 如图 3G所示。
在该步骤中， 还进一步包括： 釆用离子注入法， 将有源层 3 ( -S i ) 的对应着源极 71和漏极 72的区域进行掺杂， 以增强有 源层 3与源极 71和漏极 72的欧姆接触，保证有源层 3与源极 71、 漏极 72形成良好的欧姆接触， 而不需要对有源层 3的对应着栅极 5的区域进行掺杂， 这是因为， 此次掺杂是在刻蚀完成栅极 5的图 形后进行的， 由于有栅极 5的阻挡作用， 因此无法对与栅极 5对 应的有源层 3的部分 P-S i进行掺杂， 同时， 由于与栅极 5对应的 这部分 P-S i将作为沟道存在， 也无需进行掺杂。 其中， 离子注入 方式包括具有质量分析仪的离子注入方式、 不具有质量分析仪的 离子云式注入方式、 等离子注入方式或固态扩散式注入方式。 本 实施例中， 由低温多晶硅材料经晶化、 掺杂、 离子注入等多个步 骤， 最终形成具有良好半导体性质的有源层 3。
至此， 薄膜晶体管 TFT和存储电容 Cs即制备完成。 为了对薄 膜晶体管 TFT和存储电容（3进行绝缘保护， 且便于利用薄膜晶体 管 TFT 实现对图像显示的控制， 该制备方法还进一步包括： 在栅 极 5和第二极板 1 2 的上方形成包括层间绝缘层以及显示电极 1 0 的图形， 在层间绝缘层的对应着漏极 72的区域中形成过孔， 漏极 72与显示电极 1 0通过该过孔电连接。在本实施例中， 层间绝缘层 包括钝化层 6和有机层 8 , 显示电极 1 0为金属阳极。
形成包括层间绝缘层以及显示电极 1 0 的图形具体包括步骤 S4至 S 6。
步骤 S4 ) ： 在完成步骤 S 3 ) 的基底上， 形成钝化膜 60 , 釆 用一次构图工艺， 形成包括钝化层 6的图形， 并在钝化层 6的对 应着漏极 72的区域中形成钝化层过孔。
在该步骤中， 如图 3H 所示， 在薄膜晶体管 TFT与存储电容 Cs的上方沉积钝化膜 60。 与沉积栅绝缘层 4的方式相同， 钝化膜 60可釆用等离子体增强化学气相沉积方式、 低压化学气相沉积方 式、 大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式 沉积形成， 钝化膜 60可釆用单层的氧化硅材料， 或者釆用氧化硅 材料、 氮化硅材料形成多个子层的叠层。 然后， 通过第四次构图 工艺， 形成包括钝化层 6的图形， 并在对应着漏极 72的区域形成 钝化层过孔， 如图 31所示。
步骤 S5 ) ： 在完成步骤 S4 ) 的基底上， 形成有机膜 80 , 釆 用一次构图工艺， 形成包括有机层 8的图形， 并在对应着漏极 72 的区域形成有机层过孔。
在该步骤中， 釆用涂覆（包括旋涂） 方法， 在钝化层 6 的上 方形成有机膜 80 , 如图 3J所示。 有机膜 80釆用有机树脂形成， 有机树脂包括丙烯酸类成膜树脂、 酚醛树脂类成膜树脂、 乙烯基 聚合物成膜树脂或聚亚胺成膜树脂。 然后， 通过第五次构图工艺， 形成包括有机层 8的图形， 并在有机层 8的对应着漏极 72的区域 中形成有机层过孔， 如图 3K所示。
步骤 S6 ) ： 在完成步骤 S5 ) 的基底 1 上， 形成导电金属膜 100 , 釆用一次构图工艺， 形成包括金属阳极的图形， 金属阳极通 过有机层过孔和钝化层过孔与漏极 72电连接。
在该步骤中， 在有机层 8的上方釆用溅射方式、 热蒸发方式、 等离子体增强化学气相沉积方式、 低压化学气相沉积方式、 大气 压化学气相沉积方式或电子回旋谐振化学气相沉积方式沉积导电 金属膜 100。 其中， 导电金属膜 100具有高反射率并且满足一定的 金属功函数要求， 常釆用双层膜或三层膜结构， 比如釆用 IT0 (氧 化铟锡） /Ag (银） / ITO (氧化铟锡）或者 Ag (银） / IT0 (氧化铟 锡） 的结构， 或者， 把上述结构中的 IT0换成 IZ0 (氧化铟辞） 、 I GZ0 (氧化铟镓辞）或 InGaSnO (氧化铟镓锡） 。 当然， 也可以釆 用具有导电性能及高功函数值的无机金属氧化物、 有机导电聚合 物或金属材料形成， 无机金属氧化物包括氧化铟锡或氧化辞， 有 机导电聚合物包括 PEDOT: SS、 PANI , 金属材料包括金、 铜、 银或 铂。
然后， 通过第六次构图工艺， 形成包括显示电极 10的图形， 显示电极 10通过有机层过孔和钝化层过孔与漏极 72 电连接， 如 图 3L所示。
在上述阵列基板的结构基础上， 进一步制备像素限定层 ( P ixe l Def ine Layer , 简称 PDL ) , 接着蒸镀或者涂覆发光层 ( Emi t t ing Layer： 简称 EL ) , 最后溅射或蒸镀形成金属阴极层， 经封装即可形成带有 0LED器件的阵列基板。
在本实施例中， 存储电容 Cs的两个极板中， 其中一个极板釆 用与薄膜晶体管 TFT 的源极和漏极相同的金属材料形成， 另一个 极板釆用与薄膜晶体管的栅极相同的金属材料形成， 而两个极板 之间的电介质层釆用与栅绝缘层相同的材料形成， 减少了单独釆 用一次构图工艺形成存储电容的步骤， 还减少了一次离子注入工 艺， 简化了阵列基板的制备工艺。 同时， 由于釆用金属材料形成 的极板相对于现有技术中釆用掺杂方式形成的极板而言， 其面电 阻较小， 因此， 本实施例的阵列基板中的存储电容 Cs的充电速度 较快， 即， 本实施例的阵列基板能提高存储电容 Cs的充电速度， 同时还能获得具有稳定的驱动能力的薄膜晶体管， 进而能提高包 含该阵列基板的显示装置的显示质量， 为高分辨率的 LTPS TFT-0LED显示装置的制备提供了保证。 实施例 2 :
本实施例提供一种阵列基板， 该阵列基板适用于 TN模式、 VA 模式或 ADS模式的液晶显示装置。
本实施例中的阵列基板的结构， 在层间绝缘层以及显示电极 以下的结构均与实施例 1相同， 这里不再赘述。
在本实施例的阵列基板中， 层间绝缘层包括钝化层， 钝化层 为单层结构或多个子层的叠层结构， 釆用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物形成， 显示电极为像素电极， 像素电极釆用 氧化铟镓辞、 氧化铟、 氧化辞、 氧化铟辞、 氧化铟锡、 氧化铟镓 锡或氧化铟锡辞中的至少一种材料形成。
本实施例中的阵列基板的制备方法包括步骤 S1至 S5。
步骤 SI ) : 在基底上形成源漏金属电极膜和緩冲膜， 釆用一 次构图工艺， 形成包括源极、 漏极和第一极板的图形， 以及在源 极、 漏极上方形成包括緩冲层的图形。
步骤 S2 ) ： 在完成步骤 S1 ) 的基底上， 形成非晶硅膜， 对非 晶硅膜进行晶化以形成多晶硅膜， 对多晶硅膜进行掺杂， 并釆用 一次构图工艺， 形成包括有源层的图形。
步骤 S3 )： 在完成步骤 S2 ) 的基底上， 形成栅绝缘层和栅金 属电极膜， 栅绝缘层还延伸至完全覆盖第一极板的区域以形成存 储电容 cs的电介质层， 釆用一次构图工艺， 形成包括栅极和第二 极板的图形， 第二极板与第一极板对应设置。
步骤 S4 ) ： 在完成步骤 S3) 的基底上， 形成钝化膜， 釆用一 次构图工艺， 形成包括钝化层的图形， 并在对应着漏极的区域形 成钝化层过孔。
步骤 S5 ) 在完成步骤 S4 )的基底上， 形成透明导电金属膜， 釆用一次构图工艺， 形成包括像素电极的图形， 像素电极通过钝 化层过孔与漏极电连接。 其中， 透明导电金属釆用氧化铟镓辞 ( IGZ0 )、氧化铟辞（ IZ0 )、氧化铟锡（ IT0 )或氧化铟镓锡 ( InGaSnO ) 等透明导电材料中的至少一种。
本实施例中的上述阵列基板适用于 TN ( Twisted Nematic, 扭曲向歹 ij )模式、 VA ( Vertical Alignment, 垂直取向 )模式的 液晶显示装置。
进一步的， 在上述阵列基板的上方形成一层绝缘层和公共电 极， 可以形成适用于 ADS ( ADvanced Super Dimension Switch, 高级超维场转换技术）模式的液晶显示装置的阵列基板。 其中， ADS模式中，通过同一平面内狭缝电极边缘所产生的电场以及狭缝 电极层与板状电极层间产生的电场形成多维电场， 使液晶盒内狭 缝电极间、 电极正上方所有取向的液晶分子都能够产生旋转， 从 而提高了液晶工作效率并增大了透光效率。 高级超维场转换技术 可以提高 LCD产品的画面品质， 具有高分辨率、 高透过率、 低功 耗、 宽视角、 高开口率、 低色差、 无挤压水波紋（push Mura ) 等 优点。 实施例 3 :
本实施例提供一种显示装置， 包括实施例 1或 2中的阵列基 板。
其中，显示装置可以为液晶显示装置或者电致发光显示装置， 例如可以为液晶面板、 电子纸、 0LED面板、 手机、 平板电脑、 电 视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示 功能的产品或部件。
本实施例中的显示装置具有较好的显示质量。 本发明公开了一种低温多晶硅薄膜晶体管 （LTPS TFT ) 阵列 基板的结构和相应的制备方法， 该阵列基板相比现有技术中的低 温多晶硅薄膜晶体管阵列基板， 由于釆用金属材料形成存储电容 的极板， 极板的面电阻较小， 能提高阵列基板中存储电容 Cs的充 电速度， 进而提高包含该阵列基板的显示装置的显示质量， 为高 分辨率的显示装置的制备提供了保证， 尤其适用于 TFT-0LED显示 装置。 此外， 该阵列基板的制备方法中， 减少了两次构图工艺和 一次离子注入工艺， 简化了阵列基板的制作流程。
而釆用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

1. 一种阵列基板， 包括基底以及设置于所述基底上的薄膜晶 体管和存储电容， 所述薄膜晶体管包括栅极、 源极、 漏极以及设 置于所述源极、 所述漏极与所述栅极之间的栅绝缘层， 所述存储 电容包括第一极板、 第二极板以及设置于所述第一极板与所述第 二极板之间的电介质层， 其特征在于， 所述第一极板与所述第二 极板均釆用金属材料形成， 所述电介质层与所述栅绝缘层釆用相 同的材料形成。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述第一 极板与所述源极、 所述漏极同层设置于所述基底上。
3. 根据权利要求 1或 2所述的阵列基板， 还包括设置在所述 源极与所述漏极的上方的緩冲层， 所述緩冲层局部覆盖所述源极 且开设有源极过孔、 还局部覆盖所述漏极且开设有漏极过孔。
4. 根据权利要求 3所述的阵列基板， 还包括设置在所述緩冲 接、 通过所述漏极过孔与所述漏极连接。
5. 根据权利要求 4所述的阵列基板， 还包括设置在所述有源 层的上方的所述栅绝缘层， 所述栅绝缘层延伸至所述第一极板的 上方形成所述电介质层， 所述电介质层完全覆盖所述第一极板。
6. 根据权利要求 3至 5中任意一项所述的阵列基板， 其特征 在于， 所述栅极与所述第二极板釆用相同材料形成， 所述栅极设 置在所述栅绝缘层的上方， 所述第二极板设置在所述电介质层的 对应着所述第一极板的上方。
7. 根据权利要求 1至 6中任意一项所述的阵列基板， 其特征 在于， 所述源极、 所述漏极、 所述栅极与所述第一极板、 所述第 二极板均釆用钼、 钼铌合金、 铝、 铝钕合金、 钛和铜中的至少一 种形成， 所述有源层釆用低温多晶硅材料形成。
8. 根据权利要求 3至 6中任意一项所述的阵列基板， 其特征 在于， 所述緩冲层为单层结构或多个子层的叠层结构， 所述緩冲 层釆用硅氧化物或硅氮化物形成。
9. 根据权利要求 1至 8中任意一项所述的阵列基板， 其特征 在于， 所述栅极和所述第二极板的上方还设置有层间绝缘层和显 示电极， 所述层间绝缘层的对应着所述漏极的区域中开设有过孔， 所述显示电极通过所述过孔与所述漏极电连接。
1 0. 根据权利要求 9所述的阵列基板， 其特征在于， 所述层 间绝缘层包括钝化层和有机层， 所述钝化层为单层结构或多个子 层的叠层结构， 釆用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物 形成， 所述有机层釆用有机树脂形成， 所述有机树脂包括丙烯酸 类成膜树脂、 酚醛树脂类成膜树脂、 乙烯基聚合物成膜树脂或聚 亚胺成膜树脂，
所述显示电极为金属阳极， 所述金属阳极釆用具有导电性能 及高功函数值的无机金属氧化物、 有机导电聚合物或金属材料形 成， 所述无机金属氧化物包括氧化铟锡或氧化辞， 所述有机导电 聚合物包括 PEDOT: SS、 PANI , 所述金属材料包括金、 铜、 银或铂。
1 1. 根据权利要求 9所述的阵列基板， 其特征在于， 所述层 间绝缘层包括钝化层， 所述钝化层为单层结构或多个子层的叠层 结构， 釆用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物形成， 所述显示电极为像素电极， 所述像素电极釆用氧化铟镓辞、 氧化铟、 氧化辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡和氧化铟锡 辞中的至少一种材料形成。
12.—种显示装置， 其特征在于， 包括权利要求 1至 1 1 中任 一项所述的阵列基板。
1 3. 一种阵列基板的制备方法， 所述阵列基板包括基底以及 设置于所述基底上的薄膜晶体管和存储电容， 所述薄膜晶体管包 括源极、 漏极、 栅极以及设置于所述源极、 所述漏极与所述栅极 之间的栅绝缘层， 所述存储电容包括第一极板、 第二极板以及设 置于所述第一极板与所述第二极板之间的电介质层， 其特征在于， 所述方法包括：
釆用同一构图工艺形成所述第一极板与所述源极和所述漏 极；
釆用同一工艺形成所述电介质层与所述栅绝缘层； 以及 釆用同一构图工艺形成所述第二极板与所述栅极。
14. 根据权利要求 1 3所述的制备方法， 其特征在于， 釆用同 一构图工艺形成所述第一极板与所述源极和所述漏极包括：
步骤 S 1 ) : 在所述基底上形成源漏金属电极膜和緩冲膜， 釆 用一次构图工艺， 形成包括所述源极、 所述漏极和所述第一极板 的图形， 以及在所述源极、 所述漏极上方形成包括緩冲层的图形。
15. 根据权利要求 1 3或 14所述的制备方法， 还包括： 步骤 S2 ) ： 在形成有所述源极、 所述漏极和所述第一极板的 所述基底上， 形成非晶硅膜， 对所述非晶硅膜进行晶化以形成多 晶硅膜， 对所述多晶硅膜进行掺杂， 并釆用一次构图工艺， 形成 包括有源层的图形。
16. 根据权利要求 1 5所述的制备方法， 其特征在于， 釆用同 一工艺形成所述电介质层与所述栅绝缘层包括： 步骤 S 3 )： 在完成步骤 S2 ) 的所述基底上， 形成所述栅绝缘 层和栅金属电极膜， 所述栅绝缘层延伸至完全覆盖所述第一极板 的区域， 以形成所述存储电容的所述电介质层。
17. 根据权利要求 1 6所述的制备方法， 其特征在于， 所述釆 用同一构图工艺形成所述第二极板与所述栅极包括： 釆用一次构 图工艺形成包括所述栅极和所述第二极板的图形， 所述第二极板 与所述第一极板对应设置。
18. 根据权利要求 1 5所述的制备方法， 进一步包括： 釆用离 子注入法， 将所述有源层的对应着所述源极和所述漏极的区域进 行掺杂， 以增强所述有源层与所述源极和所述漏极的欧姆接触。
19. 根据权利要求 1 7所述的制备方法， 进一步包括： 在所述 栅极和所述第二极板的上方形成包括层间绝缘层以及显示电极的 图形， 所述层间绝缘层的对应着所述漏极的区域中形成过孔， 所 述漏极与所述显示电极通过所述过孔电连接。
20. 根据权利要求 1 9所述的制备方法， 其特征在于， 形成包 括所述层间绝缘层以及所述显示电极的图形包括：
步骤 S4 ) ： 在完成步骤 S 3 ) 的所述基底上， 形成钝化膜， 釆 用一次构图工艺， 形成包括钝化层的图形， 并在所述钝化层的对 应着所述漏极的区域中形成钝化层过孔；
步骤 S5 ) ： 在完成步骤 S4 ) 的所述基底上， 形成有机膜， 釆 用一次构图工艺， 形成包括有机层的图形， 并在所述有机层的对 应着所述漏极的区域中形成有机层过孔；
步骤 S6 )： 在完成步骤 S5 )的所述基底上， 形成导电金属膜， 釆用一次构图工艺， 形成包括金属阳极的图形， 所述金属阳极通 过所述有机层过孔和所述钝化层过孔与所述漏极电连接。
21. 根据权利要求 19所述的制备方法， 其特征在于， 形成包 括所述层间绝缘层以及所述显示电极的图形包括：
步骤 S4 ) ： 在完成步骤 S3) 的所述基底上， 形成钝化膜， 釆 用一次构图工艺， 形成包括钝化层的图形， 并在所述钝化层的对 应着所述漏极的区域中形成钝化层过孔；
步骤 S5 )： 在完成步骤 S4) 的所述基底上， 形成透明导电金 属膜， 釆用一次构图工艺， 形成包括像素电极的图形， 所述像素 电极通过所述钝化层过孔与所述漏极电连接。
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