CN105161454B - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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CN105161454B
CN105161454B CN201510405436.3A CN201510405436A CN105161454B CN 105161454 B CN105161454 B CN 105161454B CN 201510405436 A CN201510405436 A CN 201510405436A CN 105161454 B CN105161454 B CN 105161454B
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肖志莲
赵海生
彭志龙
裴晓光
刘冲
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种阵列基板及其制备方法、显示装置，属于显示技术领域，其可解决现有的半导体材料层曝光显影后的光刻胶与基板接触的面积小，导致光刻胶易脱落的问题。本发明的制备方法中，采用掩膜板对光刻胶进行曝光、显影，使第一区域保留第一厚度的光刻胶，第二区域保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域为对应薄膜晶体管的有源区的区域，且每个第一区域均至少部分与第二区域相连，使得曝光后的光刻胶与基板接触的面积大，第一区域的光刻胶不易脱落。本发明的阵列基板的制备方法适用于制备各种阵列基板。

Description

一种阵列基板及其制备方法、显示装置
技术领域
本发明属于显示技术领域，具体涉及一种阵列基板、及其制备方法、显示装置。
背景技术
阵列基板中的薄膜晶体管是关键器件，由于薄膜晶体管所在区域不透光，因此希望薄膜晶体管在整个阵列基板中所占区域的面积要小，相应的有源区的设计逐渐缩小。
发明人发现现有技术中至少存在如下问题：如图1、2所示，有源区是半导体材料层4经刻蚀形成的，刻蚀中被光刻胶5覆盖的部分保留下来即为有源区，由于有源区的尺寸小，故在对半导体材料层4上的光刻胶5进行曝光显影后，剩余光刻胶5与基板1接触的面积小，导致在显影工艺中，较小的光刻胶5十分容易脱落，脱落后会造成刻蚀有源区时有源区开裂，进而导致像素不良。当然，图1中还包括掩膜板6，图1、图2中还包括栅极2、栅极绝缘层3等其他常规结构，在此不再详细描述。
此外，现有技术中，原本在涂覆光刻胶前应该有对基板1清洗的步骤，以除去基板1上(或者说有源区上)的污染物，改善薄膜晶体管的质量，但是清洗基板1后再涂覆光刻胶5，光刻胶5的粘附性更差，光刻胶5更容易脱落，不得已放弃对基板1清洗的步骤。
发明内容
本发明针对现有的半导体材料层上的光刻胶曝光显影后与基板接触的面积小，导致光刻胶易脱落的问题，提供一种阵列基板及其制备方法、显示装置。
解决本发明技术问题所采用的技术方案是：
一种阵列基板的制备方法，包括以下步骤：
在基板上形成半导体材料层，
在半导体材料层上涂覆光刻胶，
采用掩膜板对光刻胶进行曝光、显影，使第一区域保留第一厚度的光刻胶，第二区域保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域为对应薄膜晶体管的有源区的区域，且每个第一区域均至少部分与第二区域相连；
灰化，将第二区域的光刻胶除去，第一区域仍保留至少部分光刻胶；
将完成上述步骤的基板进行刻蚀，去除暴露的半导体材料层，形成薄膜晶体管的有源区。
优选的，所述半导体材料层为多晶硅层。
优选的，所述在基板上形成半导体材料层与涂覆光刻胶之间还包括对基板进行清洗的步骤。
优选的，所述采用掩膜板对光刻胶进行曝光、显影时还形成无光刻胶的第三区域。
优选的，所述每个第一区域均被第二区域围绕，在第一区域外的任意方向上，第二区域的宽度至少为5±2μm。
优选的，所述基板上的全部第二区域连为一体。
优选的，所述第一厚度为10±2μm。
优选的，所述第二厚度为0.4±0.2μm。
本发明还提供一种阵列基板，所述阵列基板由上述的方法制成。
本发明还提供一种显示装置，所述显示装置包括上述的阵列基板。
本发明的阵列基板的制备方法中，采用掩膜板对光刻胶进行曝光、显影，使第一区域保留第一厚度的光刻胶，第二区域保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域为对应薄膜晶体管的有源区的区域，且每个第一区域均至少部分与第二区域相连，使得曝光后的光刻胶与基板接触的面积大，第一区域的光刻胶不易脱落。本发明的阵列基板的制备方法适用于制备各种阵列基板。
附图说明
图1为现有的阵列基板的制备方法示意图；
图2为现有的阵列基板曝光显影后示意图；
图3为本发明的实施例2的阵列基板的制备方法示意图；
图4为本发明的实施例2的阵列基板曝光显影后示意图；
图5为本发明的实施例2的阵列基板曝光显影后俯视示意图；
其中，附图标记为：1、基板；2、栅极；3、栅极绝缘层；4、半导体材料层；5、光刻胶；51、第一区域；52、第二区域；6、掩膜板。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
本实施例提供一种阵列基板的制备方法，包括以下步骤：
在基板上形成半导体材料层，
在半导体材料层上涂覆光刻胶，
采用掩膜板对光刻胶进行曝光、显影，使第一区域保留第一厚度的光刻胶，第二区域保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域为对应薄膜晶体管的有源区的区域，且每个第一区域均至少部分与第二区域相连；
灰化，将第二区域的光刻胶除去，第一区域仍保留至少部分光刻胶；
将完成上述步骤的基板进行刻蚀，去除暴露的半导体材料层，形成薄膜晶体管的有源区。
本实施例的阵列基板的制备方法中，采用掩膜板对光刻胶进行曝光、显影，使第一区域保留第一厚度的光刻胶，第二区域保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域为对应薄膜晶体管的有源区的区域，且每个第一区域均至少部分与第二区域相连，使得曝光后的对应有源区的光刻胶还与其他的光刻胶(第二区域的光刻胶)相连，从而光刻胶与基板接触的面积大，在后续的步骤中第一区域的光刻胶不会脱落。本实施例的阵列基板的制备方法适用于制备各种阵列基板。
实施例2：
如图3-5所示，本实施例提供一种阵列基板的制备方法，包括以下步骤：
S01、在基板1上形成半导体材料层4。
该半导体材料层4优选为多晶硅层。
优选的，在基板1上形成半导体材料层与涂覆光刻胶5之间还包括对基板1进行清洗的步骤。
也就是说，现有技术中，原本在涂覆光刻胶前应该有对基板1清洗的步骤，但是清洗基板1后再涂覆光刻胶5，光刻胶5的粘附性更差，光刻胶5更容易脱落，不得已放弃对基板1清洗的步骤。由于采用了半透曝光的方式，增大了显影后光刻胶5与基板1的接触面积，即使清洗基板1后再涂覆光刻胶5，也不会造成光刻胶5脱落。
S02、在半导体材料层4上涂覆光刻胶5。
S03、采用掩膜板6对光刻胶5进行曝光、显影，使第一区域51保留第一厚度的光刻胶，第二区域52保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域51为对应薄膜晶体管的有源区的区域，且每个第一区域51均至少部分与第二区域52相连。
优选的，采用掩膜板6对光刻胶5进行曝光、显影时还形成无光刻胶的第三区域。
优选的，每个第一区域51均被第二区域52围绕，在第一区域51外的任意方向上，第二区域52的宽度至少在5±2μm。
优选的，基板1上的全部第二区域52连为一体。
也就是说，为了减少灰化光刻胶5的量，可以使独立的半导体材料层4之间相连，连接部分采取上述的半透曝光的方式，只要保证第一区域51周围有第二区域52的薄层光刻胶5围绕，即可增大显影后光刻胶5与基板1的接触面积，保证光刻胶5不会脱落。如图5所示，本实施例给出一种阵列基板曝光显影后俯视示意图，图5中示出的是相邻的4个有源区的光刻胶5曝光显影后的第一区域51与第二区域52的面积大小俯视示意图。
优选的，第一厚度在10±2μm。
优选的，第二厚度在0.4±0.2μm。
S04、灰化，将第二区域52的光刻胶5除去，第一区域51仍保留至少部分光刻胶5；
S05、将完成上述步骤的基板1进行刻蚀，去除暴露的半导体材料层4，形成薄膜晶体管的有源区。
也就是说，本实施例通过半透曝光，减少第二区域52的曝光量，增大显影后光刻胶5与基板1的接触面积，解决了由于光刻胶5与基板1的接触面积小而导致的显影时光刻胶5脱落造成的刻蚀有源区时有源区开裂的现象。为了不影响后续的刻蚀工艺，增加了灰化步骤，通过灰化将第二区域52较薄的光刻胶除去。
当然，在阵列基板的制备过程中，还包括形成栅极2、栅绝缘层3、源极、漏极等其他已知结构的步骤，在此不再详细描述。
实施例3：
本实施例提供一种阵列基板，其采用实施例2的方法制备。
显然，上述各实施例的具体实施方式还可进行许多变化；例如：第一区域和第二区域的具体面积、形式可以根据需要进行设计，或者可以根据不同需要更换不同掩膜板以实现一定数值的第一厚度和第二厚度。
实施例4：
本实施例提供了一种显示装置，其包括上述任意一种方法制备的阵列基板。所述显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (9)

1.一种阵列基板的制备方法，其特征在于，包括以下步骤：
在基板上形成半导体材料层，
在半导体材料层上涂覆光刻胶，
采用掩膜板对光刻胶进行曝光、显影，使第一区域保留第一厚度的光刻胶，第二区域保留第二厚度的光刻胶，其中第一厚度大于第二厚度，第一区域为对应薄膜晶体管的有源区的区域，且每个第一区域均至少部分与第二区域相连；其中，每个第一区域均被第二区域围绕，所述基板上的全部第二区域连为一体；
灰化，将第二区域的光刻胶除去，第一区域仍保留至少部分光刻胶；
将完成上述步骤的基板进行刻蚀，去除暴露的半导体材料层，形成薄膜晶体管的有源区。
2.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述半导体材料层为多晶硅层。
3.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述在基板上形成半导体材料层与涂覆光刻胶的步骤之间还包括对基板进行清洗的步骤。
4.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述采用掩膜板对光刻胶进行曝光、显影时还形成无光刻胶的第三区域。
5.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述每个第一区域均被第二区域围绕，在第一区域外的任意方向上，第二区域的宽度至少为5±2μm。
6.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述第一厚度为10±2μm。
7.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述第二厚度为0.4±0.2μm。
8.一种阵列基板，其特征在于，由权利要求1-7任一项所述的方法制成。
9.一种显示装置，其特征在于，包括权利要求8所述的阵列基板。
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CN105914183B (zh) * 2016-06-22 2019-04-30 深圳市华星光电技术有限公司 Tft基板的制造方法
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543860A (zh) * 2010-12-29 2012-07-04 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制造方法
CN104091810A (zh) * 2014-06-30 2014-10-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3796070B2 (ja) * 1999-07-21 2006-07-12 シャープ株式会社 液晶表示装置
JP4084039B2 (ja) * 2001-11-19 2008-04-30 株式会社 液晶先端技術開発センター 薄膜半導体装置及びその製造方法
KR100662790B1 (ko) * 2004-12-28 2007-01-02 엘지.필립스 엘시디 주식회사 액정표시장치 및 그 제조방법
KR101385190B1 (ko) * 2007-02-07 2014-04-15 삼성디스플레이 주식회사 액정 표시 패널 및 이의 제조 방법
KR101326580B1 (ko) * 2008-06-27 2013-11-08 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
KR101425064B1 (ko) * 2011-06-09 2014-08-01 엘지디스플레이 주식회사 산화물 박막 트랜지스터 및 그 제조방법
US8906782B2 (en) * 2011-11-07 2014-12-09 Infineon Technologies Ag Method of separating semiconductor die using material modification
US20140071362A1 (en) * 2012-09-07 2014-03-13 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid crystal display panel
CN103035568B (zh) * 2012-12-21 2014-12-31 北京京东方光电科技有限公司 一种tft阵列基板及制作方法、显示装置
CN103066017A (zh) * 2012-12-28 2013-04-24 北京京东方光电科技有限公司 一种阵列基板的制备方法
KR102178196B1 (ko) * 2013-11-29 2020-11-12 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543860A (zh) * 2010-12-29 2012-07-04 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制造方法
CN104091810A (zh) * 2014-06-30 2014-10-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

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