WO2015180320A1 - 阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法 - Google Patents

阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法 Download PDF

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WO2015180320A1
WO2015180320A1 PCT/CN2014/087139 CN2014087139W WO2015180320A1 WO 2015180320 A1 WO2015180320 A1 WO 2015180320A1 CN 2014087139 W CN2014087139 W CN 2014087139W WO 2015180320 A1 WO2015180320 A1 WO 2015180320A1
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layer
drain
source
gate
contact hole
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PCT/CN2014/087139
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English (en)
French (fr)
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龙春平
刘政
王祖强
任章淳
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京东方科技集团股份有限公司
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Priority to US14/646,416 priority Critical patent/US9478562B2/en
Publication of WO2015180320A1 publication Critical patent/WO2015180320A1/zh

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Definitions

  • At least one embodiment of the present invention is directed to an array substrate and a method of fabricating the same, a display device, a thin film transistor, and a method of fabricating the same.
  • An active matrix type display device is a display device that uses a thin film transistor (TFT) for pixel display driving, and has many advantages such as lightness, low power consumption, low radiation, low cost, etc. Mainstream display technology.
  • TFT thin film transistor
  • the active matrix type display devices each include a TFT array substrate.
  • the TFT array substrate can be classified into amorphous silicon (a-Si:H) and low temperature polysilicon (Low Temperature Poly-Silicon, depending on the material of the active layer of the TFT). It is abbreviated as LTPS), high temperature poly-Silicon (HTPS), and oxide semiconductor array substrate.
  • LTPS TFT array substrate has become one of the hotspots in the field because of its high carrier mobility, high integration and strong anti-interference ability.
  • the LTPS TFT array substrate generally includes a plurality of gate lines along a first direction and a plurality of data lines along a second direction, the first direction and the second direction being perpendicular to each other to define a plurality of pixel units arranged in a matrix arrangement .
  • each pixel unit includes: a pixel electrode 115; a storage electrode 104 located under the pixel electrode 115; at a intersection of a gate line (not shown) and a data line (not shown)
  • the TFT the TFT is connected to the pixel electrode 115 for driving the pixel electrode.
  • the TFT includes an active layer 103, a gate 106, a source 110, and a drain 111.
  • the gate 106 is connected to the gate line
  • the source 110 is connected to the data line
  • the drain 111 is connected to the pixel electrode 115.
  • the method of fabricating the LTPS TFT array substrate generally includes sequentially forming a buffer layer 102, a pattern including the active layer 103 and the storage electrode 104, a gate insulating layer 105, a pattern including the gate electrode 106 and the gate line on the base substrate 101.
  • an interlayer insulating layer 107 a source contact hole, a drain contact hole, a pattern including the source electrode 110, the drain electrode 111 and the data line, a passivation layer 112, a pixel electrode contact hole in the passivation layer, a flat layer 113, The pixel electrode contact hole (which is in communication with the pixel electrode contact hole in the passivation layer 112) in the flat layer 113, the pixel electrode 115, and the pixel defining layer 116.
  • the method also includes: After the pattern including the active layer 103 and the storage electrode 104 is formed, the photoresist layer 103 is formed to block the active layer 103, but the photoresist pattern of the storage electrode 104 is exposed to achieve ion doping of the storage electrode 104, and then the photoresist is removed. The steps of the graphics.
  • At least one embodiment of the present invention provides an array substrate and a method of fabricating the same, a display device, a thin film transistor, and a method of fabricating the same, to simplify the fabrication method of the array substrate, improve production efficiency, and improve the yield of the array substrate.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising: sequentially forming an active material layer, a gate insulating layer, and a metal thin film on a substrate, and patterning the pattern by a first patterning process
  • An active material layer, the gate insulating layer, and the metal thin film form a pattern including an active layer and a pattern including a gate, a source, a drain, a gate line, and a data line, the periphery of the gate Exposing a portion of the gate insulating layer, the gate line or the data line being disconnected at an intersection of the gate line and the data line; forming a passivation layer on the base substrate, passing the second Sub-patterning process patterning the passivation layer to form a source contact hole exposing a portion of the source and a portion of the active layer, exposing a portion of the drain to contact a drain of a portion of the active layer a hole and a cross-bridge structure contact hole exposing a partially broken gate line
  • At least one embodiment of the present invention also provides an array substrate comprising: an active layer on a substrate substrate; a gate insulating layer covering the active layer; on the gate insulating layer and located a gate, a source, a drain, a gate line, and a data line of the same film layer, and a residual is formed between the source and the substrate, and between the drain and the substrate
  • An active material layer, the gate line or the data line being disconnected at an intersection of the gate line and the data line; covering the gate, the source, the drain, the a gate line and a passivation layer of the data line; a source contact hole, a drain contact hole, and a bridge structure contact hole located inside the passivation layer and the gate insulating layer, the source contact hole Exposing a portion of the source and a portion of the active layer, the drain contact hole Exposing a portion of the drain and a portion of the active layer, the bridge structure contact hole exposing a partially broken gate line or data line; a source contact portion, a drain contact
  • At least one embodiment of the present invention also provides a display device comprising the array substrate described above.
  • At least one embodiment of the present invention also provides a thin film transistor including: an active layer on a substrate; a gate insulating layer covering the active layer; on the gate insulating layer and located a gate electrode, a source and a drain of the same film layer, a residual active material layer formed between the source and the substrate, and between the drain and the substrate; a passivation layer of the gate, the source and the drain; a source contact hole and a drain contact hole located inside the passivation layer and the gate insulating layer, the source contact hole being exposed a portion of the source and a portion of the active layer, the drain contact hole exposing a portion of the drain and a portion of the active layer; a source contact portion and a drain contact portion of the same film layer, The source contact portion is located inside the source contact hole, electrically connecting the source and the active layer; the drain contact portion is located inside the drain contact hole, electrically connecting the drain and The active layer.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, comprising: sequentially forming an active material layer, a gate insulating layer, and a metal thin film on a substrate, and patterning by a first patterning process
  • the active material layer, the gate insulating layer, and the metal thin film form a pattern including an active layer and a pattern including a gate, a source, and a drain, and a portion of the gate is exposed around the gate a permanent insulating layer;
  • 1 is a schematic structural view of a TFT array substrate
  • FIG. 4 are schematic diagrams showing steps of a method for fabricating an array substrate according to Embodiment 1 of the present invention.
  • FIG. 9 are schematic diagrams showing specific steps of step S11 in the method for fabricating an array substrate according to the first embodiment of the present invention.
  • FIG. 12 are schematic diagrams showing specific steps of step S12 in the method for fabricating an array substrate according to the first embodiment of the present invention.
  • FIG. 13 to FIG. 15 are schematic diagrams showing specific steps of step S13 in the method for fabricating an array substrate according to the first embodiment of the present invention.
  • FIG. 16 is a schematic diagram of a step of electrically disconnecting a data line in a method of fabricating an array substrate according to Embodiment 1 of the present invention.
  • FIG. 17 is a basic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • the inventors of the present application have noticed that the entire fabrication process of the array substrate shown in FIG. 1 requires at least 8 to 9 patterning processes, and each patterning process requires multiple processes such as gluing, exposure, development, and cleaning. As a result, the fabrication steps of the array substrate are very complicated, and the production efficiency is low; in addition, high alignment accuracy is required in the patterning process, and high-precision alignment is difficult, and the misalignment directly causes the yield of the product to decrease. .
  • Embodiments of the present invention provide a method for fabricating an array substrate, the method comprising the following steps S11 to S13.
  • Step S11 sequentially forming an active material layer, a gate insulating layer 204, and a metal thin film on the base substrate 201, and patterning the active material layer, the gate insulating layer 204, and the metal thin film by a first patterning process, including forming A pattern of the source layer 203 and a pattern including a gate electrode 205, a source 206, a drain 207, a gate line (not shown), and a data line (not shown) are exposed around the gate 205.
  • the gate insulating layer 204, the gate line or the data line is disconnected at the intersection of the gate line and the data line, as shown in FIG.
  • step S11 may include the following steps S111 to S115, for example.
  • Step S111 The active material layer 501, the gate insulating layer 204, and the metal thin film 502 are sequentially formed on the base substrate 201, as shown in FIG.
  • the substrate substrate 201 may be initially cleaned to remove foreign particles remaining on the surface of the substrate during the production process.
  • the specific material of the substrate substrate 201 provided may be determined according to actual conditions. If the display device to be fabricated is inflexible, the substrate substrate 201 may be, for example, a glass substrate; if a flexible or bendable display device is required, the substrate 201 may be flexible or bendable, for example, a plastic film. material.
  • the forming material of the active layer may be selected differently according to actual needs, for example, materials such as amorphous silicon, polycrystalline silicon, and oxide may be selected.
  • forming the active material layer 501 in this embodiment may include, for example, depositing an amorphous silicon material on the substrate; and converting the amorphous silicon material into polysilicon by using a crystallization process. The material forms an active material layer 501.
  • an amorphous silicon material may be deposited on one side of the substrate by a sputtering process or a deposition process such as PECVD.
  • the thickness of the deposited amorphous silicon material is, for example, 40 nm to 100 nm, and then the amorphous silicon material is subjected to a sputtering process.
  • a crystallization process such as laser annealing crystallization, metal induced crystallization, solid phase crystallization, etc., converts the amorphous silicon material into a polysilicon material to form an active material layer 501.
  • the amorphous silicon material may be subjected to a dehydrogenation process, for example, using a heat treatment furnace to prevent hydrogen explosion during subsequent crystallization; after the crystallization is finished, for example, The formed active material layer 501 may be cleaned with a diluted hydrofluoric acid solution to reduce the surface roughness of the active material layer 501.
  • a thin film transistor channel doping may be performed on the active material layer 501 by using a doping method such as ion implantation or ion cloud implantation to adjust the threshold voltage of the thin film transistor and improve the switching of the thin film transistor.
  • the doping ions are, for example, H 2 -containing PH 3 or H 2 -containing B 2 H 6
  • the ion implantation dose is, for example, in the range of 10 11 to 13 ⁇ 16 ions/cm 2
  • the implantation energy is, for example, 10 KeV to 100 KeV.
  • the method of fabricating the array substrate may further include: forming a buffer layer 202 on the substrate substrate 201.
  • a silicon nitride film and a silicon oxide film may be sequentially formed on the base substrate 201 by PECVD (Plasma Enhanced Chemical Vapor Deposition) or other processes, and the stack of the two films may be used as a buffer.
  • the thickness of the silicon nitride film is, for example, 50 nm to 100 nm, and the thickness of the silicon oxide film is, for example, 100 nm to 400 nm.
  • the silicon nitride film has a strong diffusion barrier property, and can suppress the influence of metal ions on the subsequently formed polysilicon film, and the silicon oxide film can form an excellent interface with the subsequently formed polysilicon film, thereby preventing defects of the silicon nitride film on the polysilicon. Damage to film quality.
  • each of the buffer layers 202 is only an exemplary range provided by the embodiment. In other embodiments of the present invention, the layers in the buffer layer 202 may also be used according to actual conditions. The thickness is made to be different from the specific setting of the above example range.
  • the specific structure of the buffer layer 202 in this embodiment is not limited to a laminated structure composed of a silicon nitride film and a silicon oxide film, and may be a single-layer film structure or a stacked structure including at least three films.
  • the material for forming the buffer layer 202 is not limited to silicon nitride and silicon oxide.
  • the buffer layer 202 may be selected according to actual conditions. In other embodiments of the present invention, the buffer layer 202 may not be provided.
  • the process of forming the gate insulating layer 204 may be, for example, a PECVD process, and is not limited thereto.
  • the gate insulating layer 204 formed may be, for example, a stacked structure of a silicon oxide film and a silicon nitride film, and the silicon oxide film is closer to the substrate than the silicon nitride film.
  • the thickness of the silicon oxide film may be, for example, 30 nm to 100 nm, and the thickness of the silicon nitride film may be, for example, 20 nm to 100 nm.
  • the gate insulating layer 204 may also be a single layer thin film structure or a stacked structure including at least three thin films.
  • the material for forming the gate insulating layer 204 may also be an insulating material other than silicon oxide and silicon nitride; and the thickness of each layer of the film constituting the gate insulating layer 204 is not limited to the above preferred range. Set according to the actual situation.
  • the metal thin film 502 is formed by, for example, PECVD, magnetron sputtering, or the like, and is not limited herein.
  • the thickness of the metal thin film 502 may be set according to actual conditions, for example, may be 200 nm to 500 nm; the forming material of the metal thin film 502 may include, for example, at least one or a combination of aluminum, copper, molybdenum, titanium, and an aluminum bismuth compound.
  • the metal film 502 may be a single-layer film structure or a laminated structure composed of a multilayer film, such as a structure in which a three-layer film of molybdenum, aluminum, and molybdenum is sequentially laminated, or a three-layer film of titanium, aluminum, and titanium is sequentially laminated. Structure and so on.
  • Step S112 forming a first photoresist layer A1 and a second photoresist layer A2 on the metal film 502 by using a semi-transmissive mask.
  • the first photoresist layer A1 covers the active layer region to be formed and the gate line region to be formed, including a first portion A11 covering the gate region to be formed and a gate line region to be formed, and a second portion located around the first portion A11 A12;
  • the second photoresist layer A2 covers the source region to be formed, the drain region to be formed, and the data line region to be formed.
  • the thickness of the first portion A11 and the second photoresist layer A2 of the first photoresist layer are both greater than the thickness of the second portion A12 of the first photoresist layer, covering the first photoresist layer to be formed in the gate line region.
  • A1 or the second photoresist layer A2 covering the area of the data line to be formed is broken at the intersection of the two, as shown in FIG.
  • the specific thickness of the first photoresist layer A1 and the second photoresist layer A2 in this step is not limited.
  • the thickness of the first portion A11 of the first photoresist layer A1 may be, for example, 1 to 3 ⁇ m
  • the thickness of the second portion A12 may be, for example, 0.5 to 1 ⁇ m
  • the thickness of the second photoresist layer A2 may be, for example, 1 to 3 ⁇ m.
  • the thickness of the first portion A11 and the second photoresist layer A2 of the first photoresist layer A1 may be the same or different.
  • the first portion A11 of the first photoresist layer A1 covers the gate region to be formed and the gate line region to be formed for forming the gate and gate lines in the subsequent step;
  • the second portion A12 of the first photoresist layer A1 Located around the first portion A11, together with the first portion A11, covers an active layer region to be formed for forming an active layer in a subsequent step;
  • the second photoresist layer A2 covers the source region to be formed, the drain region to be formed, and A data line region is to be formed for forming source, drain and data lines in subsequent steps.
  • the gate lines and the data lines are formed in the same film layer, so that the gate lines are short-circuited to the data lines, and the first photoresist layer to be formed in the gate line region is covered.
  • A1 or the second photoresist layer A2 covering the area of the data line to be formed needs to be disconnected at the intersection of the two.
  • a gate line or a data line that is disconnected at the intersection of the gate line and the data line is formed in a subsequent step.
  • Step S113 removing the exposure by using the first photoresist layer A1 and the second photoresist layer A2 as a mask
  • the metal film and the exposed metal film cover the gate insulating layer and the active material layer, forming a pattern including the active layer 203 and a pattern including the source 206, the drain 207, the gate lines, and the data lines, the gate lines Or the data line is disconnected at the intersection of the gate line and the data line, as shown in FIG.
  • the film layer not protected by the photoresist layer may be continuously etched by a dry etching process such as plasma or inductive coupling, and etched to completely remove the active material layer not protected by the photoresist.
  • a dry etching process such as plasma or inductive coupling
  • the method for removing the gate insulating layer and the active material layer covered by the exposed metal film and the exposed metal film is not limited in this embodiment, for example, the matching may be selected according to different materials of the metal film material. Craft.
  • the wet removal method may be used, for example, if the metal thin film is formed by sequentially laminating titanium, aluminum, and titanium.
  • the above removal process can be performed by inductively coupled plasma etching.
  • the source 206, the drain 207, the gate line and the data line are formed, but the gate is not formed, and a metal thin film over the gate region to be formed is formed as the gate layer 701 to be formed. Since both the source 206 and the drain 207 need to be electrically connected to the active layer 203, and the gate layer 701 to be formed at this time completely covers the active layer 203, it is necessary to remove a portion of the gate layer 701 to be formed in a subsequent step. To form a gate such that it covers only a portion of the active layer 203.
  • a pattern including a storage electrode for forming a storage capacitor with a subsequently formed pixel electrode to switch between two frames may be simultaneously formed.
  • the residual active material layer 203' shown in the drawing is the portion other than the portion where the active layer 203 is formed in the portion remaining after the active material layer 501 has passed through the above-described step S113. Since the active layer, the gate, the source, and the drain are simultaneously formed by only one patterning process, the source 206 and the substrate 201 are formed between the drain 207 and the substrate 201, respectively. There is a residual active material layer 203'.
  • Step S114 removing the second portion A12 of the first photoresist layer, as shown in FIG.
  • the second portion A12 of the first photoresist layer A1 may be removed, for example, using a plasma ashing process.
  • the first portion A11 and the second photoresist layer A2 of the first photoresist layer A1 are also removed by a certain amount, but due to the first portion A11 of the first photoresist layer A1 and The thickness of the second photoresist layer A2 is greater than the second portion A12 of the first photoresist layer A1.
  • the gate region to be formed and the gate line are still covered by the first portion A11, and the source 206, the drain 207 and the data line are still covered by the second photoresist layer A2, and only The surface of the metal thin film (to be formed with the gate layer 701) formed around the gate region is exposed.
  • Step S115 removing the metal thin film around the first portion A11 of the first photoresist layer by using the first portion A11 of the first photoresist layer and the second photoresist layer A2 as a mask to form a pattern including the gate electrode 205.
  • a portion of the gate insulating layer 204 is exposed around the gate 205 as shown in FIG.
  • a metal film ie, a gate layer 701 to be formed
  • the gate region ie, the first portion A11 of the first photoresist layer
  • a wet etching or a dry etching process may be removed.
  • the remaining metal film forms the gate 205.
  • the active layer covered by the gate insulating layer around the gate 205 is used as a region in ohmic contact with the source 206 and the drain 207.
  • the method for fabricating the array substrate can also perform the following operations: using the gate electrode 205 as a mask and surrounding the gate electrode 205.
  • the active layer 203 is doped; the base substrate is annealed to activate doped impurities. By this doping process, the conductive characteristics of the doped region (i.e., the active layer as the source/drain contact region) can be lowered, and the ohmic contact resistance can be lowered.
  • the above-described doping process or an ion implantation method may be employed, for example, the ion cloud implantation, ion doping may include H PH 2 or 3 comprising the H B 2 2 H 6, ion implantation dose may be in the 10 ⁇ 15 Between ⁇ 10 ⁇ 16ions/cm 2 , the implantation energy can be between 10 and 100 KeV.
  • the remaining photoresist layer (the first portion A11 and the second photoresist layer A2 of the first photoresist layer) may be removed.
  • the active material layer 501, the gate insulating layer 204, and the metal thin film 502 are successively formed on the base substrate.
  • a thin portion covers the active layer region to be formed around the gate region to be formed; the second photoresist layer A2 covers the source, drain and data line regions to be formed, the thickness of which is greater than that in the first photoresist layer A1
  • the thinner portion is thicker.
  • the exposed metal film and its covered gate insulating layer and active material layer are then removed to form active layer 203, source 206, drain 207, gate lines, and data lines. Thereafter, the thinner portion of the first photoresist layer A1 is removed, the metal film around the gate region is exposed, and the portion of the metal film is removed to form the gate electrode 205.
  • Step S115 realizes forming the active layer 203, the gate electrode 205, the source electrode 206, the drain electrode 207, the gate line and the data line under the same patterning process, forming a patterning process required for forming the active layer, and forming a gate electrode
  • the patterning process required for the gate line and the patterning process required to form the source, drain, and data lines are combined into one patterning process, thereby simplifying the fabrication method of the array substrate and improving the difficulty of multiple pattern alignment.
  • the large problem caused by the alignment deviation improves the yield of the array substrate.
  • Step S12 forming a passivation layer 301 on the base substrate, patterning the passivation layer 301 by a second patterning process, forming a source contact hole 302 exposing a portion of the source 206 and a portion of the active layer 203, and exposing the exposed portion
  • the drain 207 is in contact with the drain contact hole 303 of the partial active layer 203 and the cross-bridge structure contact hole exposing the partially broken gate line or data line, as shown in FIG.
  • step S12 may include the following steps S121 to S123, for example.
  • Step S121 forming a passivation layer 301 on the base substrate as shown in FIG.
  • the process of forming the passivation layer 301 may include, for example, first depositing a hydrogen-containing passivation layer material on a side of the pattern including the gate electrode 205, the source electrode 206, the drain electrode 207, the gate line, and the data line away from the substrate substrate 201. Then, an annealing process such as rapid thermal annealing or heat treatment furnace annealing is performed to cause hydrogen to enter the inside of the active layer 203, repair its internal body defects, and enter the interface between the active layer 203 and other film layers to repair interface defects, thereby improving TFT.
  • an annealing process such as rapid thermal annealing or heat treatment furnace annealing is performed to cause hydrogen to enter the inside of the active layer 203, repair its internal body defects, and enter the interface between the active layer 203 and other film layers to repair interface defects, thereby improving TFT.
  • the material of the passivation layer 301 may be, for example, a hydrogen-containing silicon nitride film, and the thickness may be, for example, 200 nm to 500 nm.
  • Step S122 forming a third photoresist layer A3 and a fourth photoresist layer A4 on the passivation layer 301, the third photoresist layer A3 covering the gate electrode 205, the source electrode 206, the gate line and the data line,
  • the fourth photoresist layer A4 covers the drain 207, and the thickness of the third photoresist layer A3 is greater than the thickness of the fourth photoresist layer A4, as shown in FIG.
  • a semi-transmissive mask having a pattern of source contact holes to be formed and a pattern of drain contact holes to be formed may be employed in this step, such as a halftone mask or a gray mask or the like.
  • a photoresist layer of different thickness is formed on the passivation layer 301 by using different characteristics of light transmittance of a specific region on the transflective mask: the thickness of the third photoresist layer A3 is greater than that of the fourth photoresist layer The thickness of A4.
  • the thickness of the third photoresist layer A3 may be, for example, 1 ⁇ m to 3 ⁇ m, and the thickness of the fourth photoresist layer A4 may be, for example, 0.5 ⁇ m to 1 ⁇ m.
  • Step S123 using the third photoresist layer A3 and the fourth photoresist layer A4 as a mask, removing the exposed passivation layer, forming a source contact hole 302 exposing a portion of the source 206 and a portion of the active layer 203, A portion of the drain 207 is exposed to the drain contact hole 303 of the portion of the active layer 203 and a cross-bridge structure contact hole exposing the partially broken gate line or data line, as shown in FIG.
  • etching of the source contact hole, the drain contact hole, and the cross-bridge structure contact hole may be performed by a dry etching process.
  • the exposed passivation layer 301 is etched; when etched to the surface of the film layer where the source 206, the drain 207, the gate line and the data line are located, the source is different due to different etching rates for different materials.
  • the selection ratio of the formation material (usually metal) of the electrode 206, the drain 207, the gate line and the data line with respect to the etching of the passivation layer material is extremely small, and thus the source 206, the drain 207, the gate line and the data
  • the wire material is not removed or only removed by a very small amount, and the source 206, the drain 207, the gate line and the data line are in the film layer to be formed in the source contact hole region to be formed, and the drain contact hole is to be formed.
  • the region, the passivation layer material to be formed in the contact hole region of the bridge structure is etched away, thereby forming a stepped structure at the source 206 and the drain 207, and part of the surface is exposed and disconnected at the same time
  • the gate line or the data line is partially exposed, and is formed across the bridge structure contact hole; during the continuous etching down, it is not covered by the source 206 and the drain 207 and is in the source contact hole region to be formed and the drain is to be formed.
  • the material of the gate insulating layer 204 in the region of the contact hole is removed, straight Exposing the surface of the active layer 203, the etching ends, source contact hole 302 and the drain contact hole 303 is formed.
  • the dry etching process used may be, for example, an etching process such as inductively coupled plasma etching.
  • the exposed passivation layer is removed, and the gate insulating layer around the gate electrode 205 covered by the exposed passivation layer is also removed.
  • Step S13 forming a transparent conductive film on the base substrate, and removing a portion of the transparent conductive film by a film peeling process to form a source contact portion 401 electrically connecting the source 206 and the active layer 203 in the source contact hole.
  • a drain contact portion 402 electrically connecting the drain electrode 207 and the active layer 203 is formed in the contact hole, and a pixel electrode 403 electrically connected to the drain contact portion 402 is formed on the passivation layer 301 over the drain electrode 207.
  • a cross-bridge structure of gate lines or data lines that are electrically disconnected is formed on the passivation layer in and above the structure contact hole, as shown in FIG.
  • the above step S13 may include, for example, the following steps S131 to S133.
  • Step S131 removing the fourth photoresist layer A4, as shown in FIG.
  • the fourth photoresist layer A4 can be removed, for example, by an ashing process such as plasma ashing. Since the thickness of the third photoresist layer A3 is larger than that of the fourth photoresist layer A4, although the third photoresist layer A3 is partially removed during the photoresist layer removal process, a certain thickness remains.
  • the cover is over the gate 205, the source 206, the gate lines, and the data lines. The remaining third photoresist layer A3 acts as a release layer in the subsequent step.
  • Step S132 A transparent conductive film 1401 is formed on the base substrate as shown in FIG.
  • the transparent conductive film 1401 is formed by, for example, magnetron sputtering, chemical vapor deposition, or the like.
  • the thickness, the forming material, and the specific structure of the transparent conductive film 1401 can be selected according to actual needs. This embodiment is not limited thereto, and the thickness thereof may be, for example, 20 nm to 150 nm, and the forming material may be, for example, ITO (Indium Tin Oxide). a combination of one or more of indium tin), IZO (Indium Zinc Oxide), ZTO (zinc oxide tin), Ag, Al, Au, etc., and the specific structure may be, for example, a single layer film structure or a plurality of layers. A composite structure composed of a film.
  • the transparent conductive film 1401 is, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or ZTO (Zinc Oxide).
  • An oxide transparent conductive film such as tin) has a thickness of, for example, 20 nm to 100 nm; and if the fabricated array substrate is applied to a top emission AMOLED display device, the transparent conductive film 1401 is, for example, an ITO film, an Ag (silver) film, and an ITO film.
  • the composite film formed, or a composite film composed of an IZO film and an Ag film, or another composite film, the thickness of the ITO film in the transparent conductive film 1401 may be, for example, 10 nm to 50 nm, and the film thickness of Ag may be, for example, 20 nm to 100 nm.
  • Step S133 peeling off the third photoresist layer A3 to remove the transparent conductive film overlying the third photoresist layer A3, and forming the source of the electrical connection source 206 and the active layer 203 in the source contact hole 302.
  • the contact portion 401 is formed in the drain contact hole 303 to electrically connect the drain 207 and the drain contact portion 402 of the active layer 203, and the passivation layer 301 over the drain 207 is electrically connected to the drain contact portion 402.
  • the pixel electrode 403 forms a bridge structure of a gate line or a data line which is electrically disconnected on the passivation layer in and over the contact hole of the bridge structure, as shown in FIG.
  • the base substrate on which the transparent conductive film 1401 is formed may be placed in a stripping machine, the residual third photoresist layer A3 may be removed using a photoresist stripping solution, and the third photoresist layer may be simultaneously removed by a film stripping process.
  • the transparent conductive film covered on A3, the source contact hole 302, the drain contact hole 303, and the transparent conductive film in the region where the pixel electrode is to be formed are retained.
  • the transparent conductive film in the source contact hole 302 is electrically connected to the source 206 and the active layer 203 as a source contact portion 401
  • the transparent conductive film in the drain contact hole 303 is electrically connected to the drain 207 as a drain contact portion 402.
  • Source layer 203 is electrically connected to the source 206 and the active layer 203 as a source contact portion 401
  • the transparent conductive film in the drain contact hole 303 is electrically connected to the drain 207 as a drain contact portion 402.
  • a transparent conductive film over the passivation layer 301 in the pixel electrode region to be formed adjacent to the drain 207 is electrically connected as a pixel electrode 403 to the drain electrode 207.
  • the pixel electrode 403 can form a storage capacitor with the storage electrode for maintaining the display of the previous frame during the switching of the adjacent two frames.
  • the gate lines and the data lines are formed under the same photolithography step as the gate 205, the source 206, and the drain 207, and the data lines or gates are intersected at the data lines and the gate lines.
  • the pole line needs to be disconnected.
  • the gate lines are continuous and the data lines are disconnected from the gate lines, as shown in FIG. 16, after the passivation layer 301 is deposited, it is necessary to make a cross-bridge structure contact hole at the break, and then take a cross.
  • the bridge structure 1602 electrically connects the disconnected data lines 1601, thereby achieving electrical isolation between the data lines 1601 and the gate lines 1603.
  • the cross-bridge structure contact hole 1602a required to be electrically connected to the disconnected data line 1601 is formed simultaneously with the source contact hole 302 and the drain contact hole 303, and is filled in the cross-bridge structure contact hole, and the electrical connection is broken.
  • the cross-bridge structure 1602 is formed by a partially transparent conductive film 1401.
  • the transparent conductive film material is filled in the contact hole of the bridge structure while forming the transparent conductive film 1401, and the bridge is peeled off while peeling off the third photoresist layer A3.
  • a transparent conductive film material that needs to be stripped around the structure 1602 forms a bridge structure 1602 of the data line 1601 that is electrically disconnected.
  • step S12 step S121 to step S123
  • step S13 steps S131 to S133
  • a photoresist layer having different thicknesses is formed by using a semi-transmissive mask, and etching is performed to form a source.
  • the upper, thicker photoresist layer and the transparent conductive film covered thereon form the pixel electrode 403, and realize the electrical connection between the source 206 and the drain 207 and the active layer 203, thereby
  • the formation of the source contact hole and the drain contact hole in the method of fabricating the array substrate and the formation of the contact hole of the pixel electrode are combined into two, simplifying the fabrication steps of the array substrate and improving the production efficiency; Moreover, since the number of times of the patterning process is reduced, the problem of alignment deviation caused by multiple patterning can be avoided to a certain extent, and the yield of the product is improved.
  • the method for fabricating the array substrate may further include the step of forming a pixel defining layer on the substrate.
  • step S13 depositing a pixel defining layer material on the substrate substrate subjected to step S13, using a patterning worker A photoresist mask having a pixel defining layer pattern is formed, and etching is performed to remove the pixel defining layer material outside the pixel defining layer to form a pixel defining layer.
  • the material for forming the pixel defining layer may be, for example, a material such as acryl, and the thickness thereof is, for example, 1 ⁇ m to 4 ⁇ m.
  • the completed array substrate may be annealed, for example, using a rapid thermal annealing furnace or a heat treatment furnace to stabilize the characteristics of the TFT.
  • the manufacturing method provided in this embodiment can be applied to the fabrication of the LTPS TFT array substrate, but this does not limit the application range of the fabrication method provided by the embodiment, and the core idea of the present invention remains unchanged.
  • the fabrication method provided in the present embodiment can also be applied to the fabrication of an amorphous silicon TFT array substrate, an HTPS TFT array substrate, an oxide TFT array substrate, an organic TFT array substrate, and the like.
  • the active layer, the gate, the source, the drain, the gate line, and the data line are simultaneously formed by only one patterning process, and the gate and the source and drain are omitted.
  • Inter-layer insulating layer, the active layer is formed in the method of fabricating the array substrate shown in FIG. 1, the gate and gate lines are formed, and the patterning process required to form the source and drain electrodes and the data line is merged into one time. .
  • the source contact hole and the drain contact hole having the stepped structure at the bottom are formed only by one patterning process, and the contact hole of the bridge structure is formed at the same time, and the transparent conductive film is deposited at one time, combined with the film peeling process,
  • the electrical connection between the source and the drain and the active layer, and the electrical connection of the broken gate line or the data line are realized, thereby making the source contact hole in the method of fabricating the array substrate shown in FIG.
  • the two patterning processes required for the formation of the drain contact hole and the formation of the pixel electrode contact hole are combined into one.
  • the manufacturing method provided by the embodiment can reduce the 8-9 patterning processes required to be performed in the method for fabricating the array substrate shown in FIG. 1 to 3 times, thereby simplifying the manufacturing steps of the array substrate and improving the production efficiency; Moreover, since the number of times of the patterning process is reduced, the alignment deviation caused by multiple high-precision alignment of multiple lithography can be effectively improved, and the yield of the product is improved.
  • the present embodiment provides an array substrate, as shown in FIG. 17, the array substrate provided in this embodiment includes: an active layer 203 on the substrate substrate 201; a gate insulating layer 204 covering the active layer 203; a gate 205, a source 206, a drain 207, a gate line and a data line on the gate insulating layer 204 and located in the same film layer, between the source 206 and the substrate 201, the drain 207 and the substrate Substrate 201 A residual active material layer 203' is formed between, respectively, the gate line or the data line is disconnected at the intersection of the gate line and the data line; covering the gate 205, the source 206, the drain 207, the gate line, and the data a passivation layer 301 of the line; a source contact hole, a drain contact hole and a bridge structure contact hole located inside the passivation layer 301 and the gate insulating layer 204, the source contact hole exposing a part of the source 206 and a part of the active
  • the positional relationship of the active layer 203, the gate insulating layer 204, the gate electrode 205, the source electrode 206, the drain electrode 207, the gate line, the data line, and the passivation layer 301 can be, for example, as shown in FIG. 17, that is, the active layer 203
  • the gate insulating layer 204 is located on a side of the active layer 203 facing away from the substrate 201, and the gate 205, the source 206, the drain 207, the gate lines, and the data lines are located on the gate insulating layer 204.
  • the passivation layer 301 is located on the side of the gate electrode 205, the source 206, the drain 207, the gate lines, and the data lines facing away from the substrate 201.
  • the gate electrode 205, the source 206, the drain 207, the gate line and the data line of the array substrate provided in this embodiment are located in the same film layer, so there is no overlap between the gate 205 and the source 206 and the drain 207.
  • the array substrate shown in FIG. 1 has a gate and a source and a drain in different layers, a gate and a source
  • the overlap between the drains results in the generation of parasitic capacitance, which in turn affects the electrical performance of the device.
  • the array substrate in the embodiment has less parasitic capacitance and better electrical performance.
  • the above structure omits the interlayer insulating layer between the gate and the source and the drain with respect to the array substrate shown in FIG. 1, which reduces the use amount of the material to some extent and reduces the production cost.
  • the array substrate in this embodiment can adopt fewer times of composition.
  • the process is formed. Therefore, the array substrate provided in this embodiment has the advantages of simple manufacturing method and high production efficiency.
  • the substrate can be fabricated by a fewer number of patterning processes, and the number of patternings can reduce the problem of misalignment. Therefore, the array substrate provided in this embodiment has a high yield.
  • 203' shown in the drawing is a portion other than the portion where the active layer 203 is formed in the portion remaining after the active material layer 501 is etched.
  • the material for forming the active layer 203 in this embodiment is, for example, polysilicon.
  • the material of the gate electrode 205, the source electrode 206, the drain electrode 207, and the data line of the drain electrode 207 is not limited in this embodiment, and the materials of the three materials may include, for example, at least one of aluminum, copper, molybdenum, titanium, and aluminum bismuth compounds. Combination of species or several to achieve better electrical conductivity.
  • the thickness of the source contact portion 401, the drain contact portion 402, the pixel electrode 403, and the bridge structure is, for example, 20 nm to 150 nm to achieve a better conductive effect.
  • the array substrate in this embodiment can omit the fabrication of the planar layer after the passivation layer 301 is formed, thereby saving material, reducing cost, and simplifying the process.
  • the material of the passivation layer 301 in this embodiment may be, for example, the same material as the flat layer, for example, acrylic, to planarize the surface of the substrate while insulating the upper and lower layers of the flat layer.
  • the array substrate provided in this embodiment may further include, for example, a storage electrode 203a disposed in the same layer as the active layer 203. As shown in FIG. 17, the storage electrode may be formed in the same step as the active layer 203, for example, with pixels.
  • the electrodes 403 are superimposed to form a storage capacitor for maintaining the display of the previous frame when the two frames are switched.
  • the array substrate may further include a buffer layer 202 between the base substrate 201 and the active layer 203 to protect the substrate substrate 201.
  • the buffer layer 202 may include, for example, a silicon nitride film and a silicon oxide film.
  • the silicon nitride film may be close to the substrate 201 with respect to the silicon oxide film.
  • the silicon nitride film has a strong diffusion barrier property and can suppress metal ions to follow. Under the influence of the formed polysilicon film, the silicon oxide film can form an excellent interface with the subsequently formed polysilicon film, thereby preventing the defects of the silicon nitride film from impairing the quality of the polysilicon film.
  • the array substrate provided in this embodiment may further include: a pixel defining layer 1701 covering the source contact portion 401, the drain contact portion 402, and the bridge structure, the pixel defining layer 1701
  • the pixel 206 and the drain 207 are electrically insulated from each other and the film layer formed on the pixel defining layer 1701, and the pixel defining layer 1701 is formed around the pixel electrode 403, and is also used to define a pixel region.
  • the pixel defining layer 1701 may be made of the same material as the flat layer, for example, a material such as acryl may be used to planarize the surface of the substrate.
  • the array substrate provided in this embodiment may be, for example, an LTPS TFT array substrate.
  • an amorphous silicon TFT array substrate, an HTPS TFT array substrate, an oxide TFT array substrate, or an organic TFT array substrate may also be used. Etc., there is no limitation here.
  • the embodiment provides a display device, and the display device includes the array substrate of the second embodiment.
  • the display device provided in this embodiment may be, for example, an OLED (Organic Light Emitting Diode) display device, such as an AMOLED (Active Matrix Organic Light Emitting Diode) display device; (Liquid Crystal Display, liquid crystal display device), such as IPS (In-Plane Switching) type LCD.
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • IPS In-Plane Switching
  • the display device provided in this embodiment has the gate of the TFT and the source and drain electrodes in the same film layer, there is no parasitic capacitance between the gate and the source and the drain, thereby improving the performance of the display device.
  • the display device in the embodiment can be formed by using a fewer number of patterning processes, the display device has higher production efficiency; at the same time, reducing the number of patterning can improve the problem of misalignment, and thus the implementation
  • the display device in the example has a higher yield.
  • the TFT in the display device provided by the embodiment does not have an interlayer insulating layer between the gate and the pattern including the source and the drain, the use of the material is saved, thereby making the display device in the embodiment The production cost is reduced and the process steps are simplified.
  • Embodiments of the present invention provide a thin film transistor including: an active layer on a substrate; a gate insulating layer covering the active layer; and a gate insulating layer on the same film layer a gate, a source and a drain, a residual active material layer being formed between the source and the substrate, between the drain and the substrate, respectively; covering the gate, a passivation layer of the source and the drain; a source contact hole and a drain connection located inside the passivation layer and the gate insulating layer a contact hole, the source contact hole exposing a portion of the source and a portion of the active layer, the drain contact hole exposing a portion of the drain and a portion of the active layer; located in the same film layer a source contact portion and a drain contact portion, the source contact portion being located inside the source contact hole, electrically connecting the source and the active layer; and the drain contact portion being located at the drain contact Inside the hole, the drain and the active layer are electrically connected.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, comprising: sequentially forming an active material layer, a gate insulating layer, and a metal thin film on a substrate, and patterning the active material by a first patterning process a layer, the gate insulating layer and the metal thin film, forming a pattern including an active layer and a pattern including a gate, a source, and a drain, and a portion of the gate insulating layer is exposed around the gate; Forming a passivation layer on the base substrate, patterning the passivation layer by a second patterning process, forming a source contact hole exposing a portion of the source and a portion of the active layer, exposing a portion a drain and a portion of the drain contact hole of the active layer; forming a conductive film on the base substrate, removing a portion of the conductive film to form an electrical connection between the source and the source in the source contact hole A source contact portion of the active layer, in which a drain contact portion electrical

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Abstract

一种阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法，该阵列基板的制作方法包括：在衬底基板（201）上形成有源材料层（501）、栅极绝缘层（204）和金属薄膜（502），通过第一次构图工艺形成包括有源层（203）的图形和包括栅极（205）、源极（206）、漏极（207）、栅极线（1063）和数据线（1061）的图形；在衬底基板（201）上形成钝化层（301），通过第二次构图工艺形成源极接触孔（302）、漏极接触孔（303）和跨桥结构接触孔（1062a）；在衬底基板（201）上形成透明导电薄膜（1401），去除部分透明导电薄膜（1401），以形成源极接触部分（401）、漏极接触部分（402）、像素电极（403）和跨桥结构（1062）。该制作方法减少了构图工艺的使用次数。

Description

阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法 技术领域
本发明的至少一个实施例涉及一种阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法。
背景技术
有源矩阵(Active Matrix)型显示装置是利用薄膜晶体管(Thin Film Transistor，简称TFT)进行像素显示驱动的一种显示装置，具有轻薄、低功耗、低辐射、低成本等诸多优点，是目前主流的显示技术。
有源矩阵型显示装置均包括一TFT阵列基板，根据TFT有源层的形成材料的不同，TFT阵列基板可分为非晶硅(a-Si：H)、低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)、高温多晶硅(High Temperature Poly-Silicon，简称HTPS)、氧化物半导体阵列基板等多种类型。LTPS TFT阵列基板以其载流子迁移率高、可高度集成、抗干扰能力强等优点，成为目前领域内研究的热点之一。
LTPS TFT阵列基板通常包括多条沿第一方向的栅极线和多条沿第二方向的数据线，第一方向与第二方向相互垂直，以限定形成呈矩阵式排布的多个像素单元。如图1所示，每个像素单元均包括：像素电极115；位于像素电极115下层的存储电极104；位于栅极线(图中未示出)与数据线(图中未示出)交叉处的TFT，TFT与像素电极115相连，用于驱动像素电极。TFT包括有源层103、栅极106、源极110和漏极111，通常栅极106与栅极线相连，源极110与数据线相连，漏极111与像素电极115相连。
制作LTPS TFT阵列基板的方法通常包括：在衬底基板101上依次形成缓冲层102、包括有源层103和存储电极104的图形、栅极绝缘层105、包括栅极106和栅极线的图形、层间绝缘层107、源极接触孔、漏极接触孔、包括源极110、漏极111和数据线的图形、钝化层112、钝化层内的像素电极接触孔、平坦层113、平坦层113内的像素电极接触孔(与钝化层112内的像素电极接触孔是连通的)、像素电极115和像素定义层116。该方法还包括： 在形成包括有源层103和存储电极104的图形后，形成遮挡有源层103，但暴露存储电极104的光刻胶图形，以实现对存储电极104的离子掺杂，再去除该光刻胶图形的步骤。
发明内容
本发明的至少一个实施例提供一种阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法，以简化阵列基板的制作方法、提高生产效率，并提高阵列基板的良率。
本发明的至少一个实施例提供了一种阵列基板的制作方法，其包括：在衬底基板上依次形成有源材料层、栅极绝缘层和金属薄膜，通过第一次构图工艺图案化所述有源材料层、所述栅极绝缘层和所述金属薄膜，形成包括有源层的图形和包括栅极、源极、漏极、栅极线和数据线的图形，所述栅极的周围暴露出部分所述栅极绝缘层，所述栅极线或所述数据线在所述栅极线和所述数据线的交叉处断开；在衬底基板上形成钝化层，通过第二次构图工艺图案化所述钝化层，形成暴露出部分所述源极与部分所述有源层的源极接触孔、暴露出部分所述漏极与部分所述有源层的漏极接触孔和暴露出部分断开的栅极线或数据线的跨桥结构接触孔；在衬底基板上形成透明导电薄膜，去除部分所述透明导电薄膜，以在所述源极接触孔中形成电连接所述源极和所述有源层的源极接触部分，在所述漏极接触孔中形成电连接所述漏极和所述有源层的漏极接触部分，在所述漏极上方的钝化层上形成与所述漏极接触部分电连接的像素电极，在所述跨桥结构接触孔内和上方的钝化层上形成电连接断开的栅极线或数据线的跨桥结构。
本发明的至少一个实施例还提供了一种阵列基板，其包括：位于衬底基板上的有源层；覆盖所述有源层的栅极绝缘层；位于所述栅极绝缘层上且位于同一膜层的栅极、源极、漏极、栅极线和数据线，在所述源极和所述衬底基板之间、所述漏极和所述衬底基板之间分别形成有残余有源材料层，所述栅极线或所述数据线在所述栅极线和所述数据线的交叉处断开；覆盖所述栅极、所述源极、所述漏极、所述栅极线和所述数据线的钝化层；位于所述钝化层和所述栅极绝缘层内部的源极接触孔、漏极接触孔和跨桥结构接触孔，所述源极接触孔暴露出部分所述源极和部分所述有源层，所述漏极接触孔暴 露出部分所述漏极和部分所述有源层，所述跨桥结构接触孔暴露出部分断开的栅极线或数据线；位于同一膜层的源极接触部分、漏极接触部分、像素电极和跨桥结构，所述源极接触部分位于所述源极接触孔内部，电连接所述源极与所述有源层；所述漏极接触部分位于所述漏极接触孔内部，电连接所述漏极与所述有源层；所述像素电极位于所述漏极上方的钝化层上，通过所述漏极接触部分与所述漏极电连接；所述跨桥结构位于所述跨桥结构接触孔内和上方的钝化层上，电连接断开的栅极线或数据线。
本发明的至少一个实施例还提供了一种显示装置，其包括以上所述的阵列基板。
本发明的至少一个实施例还提供了一种薄膜晶体管，其包括：位于衬底基板上的有源层；覆盖所述有源层的栅极绝缘层；位于所述栅极绝缘层上且位于同一膜层的栅极、源极和漏极，在所述源极和所述衬底基板之间、所述漏极和所述衬底基板之间分别形成有残余有源材料层；覆盖所述栅极、所述源极和所述漏极的钝化层；位于所述钝化层和所述栅极绝缘层内部的源极接触孔和漏极接触孔，所述源极接触孔暴露出部分所述源极和部分所述有源层，所述漏极接触孔暴露出部分所述漏极和部分所述有源层；位于同一膜层的源极接触部分和漏极接触部分，所述源极接触部分位于所述源极接触孔内部，电连接所述源极与所述有源层；所述漏极接触部分位于所述漏极接触孔内部，电连接所述漏极与所述有源层。
本发明的至少一个实施例还提供了一种薄膜晶体管的制作方法，其包括：在衬底基板上依次形成有源材料层、栅极绝缘层和金属薄膜，通过第一次构图工艺图案化所述有源材料层、所述栅极绝缘层和所述金属薄膜，形成包括有源层的图形和包括栅极、源极、漏极的图形，所述栅极的周围暴露出部分所述栅极绝缘层；在衬底基板上形成钝化层，通过第二次构图工艺图案化所述钝化层，形成暴露出部分所述源极与部分所述有源层的源极接触孔、暴露出部分所述漏极与部分所述有源层的漏极接触孔；在衬底基板上形成导电薄膜，去除部分所述导电薄膜，以在所述源极接触孔中形成电连接所述源极和所述有源层的源极接触部分，在所述漏极接触孔中形成电连接所述漏极和所述有源层的漏极接触部分。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种TFT阵列基板的结构示意图；
图2～图4为本发明实施例一所提供的阵列基板的制作方法各步骤的示意图；
图5～图9为本发明实施例一所提供的阵列基板的制作方法中步骤S11的具体步骤的示意图；
图10～图12为本发明实施例一所提供的阵列基板的制作方法中步骤S12的具体步骤的示意图；
图13～图15为本发明实施例一所提供的阵列基板的制作方法中步骤S13的具体步骤的示意图；
图16为本发明实施例一所提供的阵列基板的制作方法中电连接断开的数据线的步骤的示意图；
图17为本发明实施例二所提供的阵列基板的基本结构图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，均属于本发明保护的范围。
本申请的发明人注意到，图1所示的阵列基板的整个制作过程至少需要8～9次构图工艺，而每次构图工艺均需经过涂胶、曝光、显影、清洗等多道工序，这就导致阵列基板的制作步骤十分繁杂，生产效率较低；另外，构图工艺过程中需要较高的对位精度，高精度的对位难度很大，对位不准会直接引起产品的良率下降。
实施例一
本发明实施例提供了一种阵列基板的制作方法，该方法包括以下步骤 S11至S13。
步骤S11：在衬底基板201上依次形成有源材料层、栅极绝缘层204和金属薄膜，通过第一次构图工艺图案化有源材料层、栅极绝缘层204和金属薄膜，形成包括有源层203的图形和包括栅极205、源极206、漏极207、栅极线(图中未示出)和数据线(图中未示出)的图形，栅极205的周围暴露出部分栅极绝缘层204，栅极线或数据线在栅极线和数据线的交叉处断开，如图2所示。
本实施例中，上述步骤S11例如可包括以下步骤S111至S115。
步骤S111：在衬底基板201上依次形成有源材料层501、栅极绝缘层204和金属薄膜502，如图5所示。
为保证产品的各项性能更优良，例如可对衬底基板201进行初始清洗，以清除生产过程中残留在衬底基板表面的杂质粒子。
所提供的衬底基板201的具体材料可根据实际情况而定。若需要制作的显示装置为非柔性的，则衬底基板201例如可选用玻璃基板；若需要制作柔性或可弯曲显示装置，则衬底基板201例如可为塑料薄膜等具有柔性或可弯曲性的材料。
本实施例中，有源层的形成材料可根据实际需要进行不同的选择，例如可选用非晶硅、多晶硅、氧化物等材料。
以有源层的形成材料为多晶硅为例，本实施例中形成有源材料层501例如可包括：在衬底基板上沉积非晶硅材料；采用晶化工艺，使非晶硅材料转化为多晶硅材料，形成有源材料层501。
例如，可首先采用溅射工艺或PECVD等淀积工艺在衬底基板的一侧上沉积非晶硅材料，所沉积的非晶硅材料的厚度例如为40nm～100nm，然后对非晶硅材料进行激光退火结晶、金属诱导结晶、固相结晶等晶化工艺，使非晶硅材料转化为多晶硅材料，形成有源材料层501。另外，在沉积完非晶硅材料之后，进行晶化工艺之前，例如可使用热处理炉对非晶硅材料进行脱氢工艺处理，以防止后续结晶过程中的氢爆；在晶化结束后，例如可采用稀释的氢氟酸溶液对所形成的有源材料层501进行清洗，以降低有源材料层501的表面粗糙度。
在形成有源材料层501后，例如可采用离子注入、离子云注入等掺杂方 法，对有源材料层501进行薄膜晶体管沟道掺杂，以调整薄膜晶体管的阈值电压，改善薄膜晶体管的开关特性。掺杂离子例如为含H2的PH3或者含H2的B2H6，离子注入剂量的范围例如为10^11～13^16ions/cm2，注入能量例如为10KeV～100KeV。
本实施例中，在形成有源材料层501之前，所述阵列基板的制作方法例如还可包括：在衬底基板201上形成缓冲层202。
例如，可采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)或其它工艺在衬底基板201上依次形成氮化硅薄膜和氧化硅薄膜，将该两层薄膜的叠层作为缓冲层202。氮化硅薄膜的厚度例如为50nm～100nm，氧化硅薄膜的厚度例如为100nm～400nm。氮化硅薄膜具有很强的扩散阻挡特性，能够抑制金属离子对后续形成的多晶硅薄膜的影响，氧化硅薄膜能够与后续形成的多晶硅薄膜形成优良的界面，从而防止氮化硅薄膜的缺陷对多晶硅薄膜质量的损害。
需要说明的是，上述缓冲层202中的各膜层的厚度仅为本实施例所提供的示例范围，在本发明的其它实施例中，还可根据实际情况对缓冲层202中的各膜层的厚度进行不同于上述示例范围的具体设定。
并且，本实施例中的缓冲层202的具体结构并不仅限于为氮化硅薄膜和氧化硅薄膜所构成的叠层结构，其还可为单层薄膜结构或包括至少三层薄膜的叠层结构，且缓冲层202的形成材料也并不仅限于氮化硅和氧化硅两种。
另外，缓冲层202可根据实际情况选择是否设置，在本发明的其它实施例中，也可不设置缓冲层202。
本步骤中，形成栅极绝缘层204所采用的工艺例如可为PECVD等工艺，在此并不限定。
所形成的栅极绝缘层204例如可为氧化硅薄膜与氮化硅薄膜所构成的叠层结构，氧化硅薄膜相对于氮化硅薄膜更靠近衬底基板。氧化硅薄膜的厚度例如可为30nm～100nm，氮化硅薄膜的厚度例如可为20nm～100nm。栅极绝缘层204还可为单层薄膜结构或者包括至少三层薄膜的叠层结构。
需要说明的是，栅极绝缘层204的形成材料还可为除氧化硅和氮化硅外的绝缘材料；并且，构成栅极绝缘层204的各层薄膜的厚度并不仅限于上述优选范围，可根据实际情况进行设定。
本步骤中，形成金属薄膜502例如可采用PECVD、磁控溅射等工艺，在此并不进行限定。
金属薄膜502的厚度可根据实际情况设定，例如可为200nm～500nm；金属薄膜502的形成材料例如可包括铝、铜、钼、钛和铝钕化合物等中的至少一种或几种的组合；金属薄膜502可为单层薄膜结构，也可为多层薄膜构成的叠层结构，如：钼、铝和钼三层薄膜依次叠层的结构，或钛、铝和钛三层薄膜依次层叠的结构等。
步骤S112：利用半透式掩膜版，在金属薄膜502上形成第一光刻胶层A1和第二光刻胶层A2。第一光刻胶层A1覆盖待形成有源层区域和待形成栅极线区域，包括覆盖待形成栅极区域与待形成栅极线区域的第一部分A11和位于第一部分A11周围的第二部分A12；第二光刻胶层A2覆盖待形成源极区域、待形成漏极区域和待形成数据线区域。第一光刻胶层的第一部分A11和第二光刻胶层A2的厚度均大于第一光刻胶层的第二部分A12的厚度，覆盖待形成栅极线区域的第一光刻胶层A1或覆盖待形成数据线区域的第二光刻胶层A2在二者交叉处断开，如图6所示。
本步骤中对第一光刻胶层A1和第二光刻胶层A2的具体厚度并不限定。第一光刻胶层A1的第一部分A11的厚度例如可为1～3μm，第二部分A12的厚度例如可为0.5～1μm，第二光刻胶层A2的厚度例如可为1～3μm。第一光刻胶层A1的第一部分A11和第二光刻胶层A2的厚度可相同，也可不同。
第一光刻胶层A1的第一部分A11覆盖待形成栅极区域与待形成栅极线区域，用于后续步骤中形成栅极与栅极线；第一光刻胶层A1的第二部分A12位于第一部分A11的周围，与第一部分A11共同覆盖待形成有源层区域，用于后续步骤中形成有源层；第二光刻胶层A2覆盖待形成源极区域、待形成漏极区域和待形成数据线区域，用于后续步骤中形成源极、漏极和数据线。
需要说明的是，由于本实施例中栅极线与数据线形成于同一膜层中，因此为避免栅极线与数据线相连而短路，覆盖待形成栅极线区域的第一光刻胶层A1或覆盖待形成数据线区域的第二光刻胶层A2需在二者交叉处断开。以在后续步骤中形成在栅极线与数据线交叉处断开的栅极线或数据线。
步骤S113：以第一光刻胶层A1和第二光刻胶层A2为掩膜，去除暴露 的金属薄膜和暴露的金属薄膜遮盖的栅极绝缘层与有源材料层，形成包括有源层203的图形和包括源极206、漏极207、栅极线和数据线的图形，栅极线或数据线在栅极线和数据线的交叉处断开，如图7所示。
本步骤中，例如可采用等离子体或电感耦合等干法刻蚀工艺对未被光刻胶层保护的膜层进行连续刻蚀，刻蚀以完全去除未被光刻胶保护的有源材料层为终点，防止由于有源材料层相连导致的晶体管特性下降。
需要说明的是，本实施例对去除暴露的金属薄膜和暴露的金属薄膜遮盖的栅极绝缘层与有源材料层所采用的工艺方法并不限定，例如可根据金属薄膜材料的不同选择相匹配的工艺。例如：若金属薄膜为钼、铝和钼三层薄膜依次叠层而成，则例如可使用湿法刻蚀方法进行上述去除工序；若金属薄膜为钛、铝和钛依次层叠而成，则例如可使用电感耦合等离子方法刻蚀进行上述去除工序。
经过步骤S113后，源极206、漏极207、栅极线和数据线形成，但是栅极并未形成，覆盖在待形成栅极区域上的金属薄膜作为待形成栅极层701。由于源极206和漏极207均需要与有源层203电连接，而此时待形成栅极层701是完全覆盖有源层203的，因此需要在后续步骤中去除部分待形成栅极层701，以形成栅极，使其仅覆盖有源层203的一部分。
本实施例中，在形成包括有源层203的图形的步骤中，例如还可同时形成包括存储电极的图形，该存储电极用于与后续形成的像素电极构成存储电容，以在两帧画面切换时，维持上一帧画面的显示。
需要说明的是，附图中所示出的残余有源材料层203′为有源材料层501经过上述步骤S113后所剩余的部分中除形成有源层203的部分外其它部分。由于本实施例仅通过一次构图工艺同时形成有源层、栅极、源极、漏极，因此，在源极206和衬底基板201之间、漏极207和衬底基板201之间分别形成有残余有源材料层203′。
步骤S114：去除第一光刻胶层的第二部分A12，如图8所示。
本步骤中，例如可使用等离子体灰化工艺去除第一光刻胶层A1的第二部分A12。在灰化去除的过程中，第一光刻胶层A1的第一部分A11和第二光刻胶层A2也会同时被去除一定的量，但是由于第一光刻胶层A1的第一部分A11和第二光刻胶层A2的厚度均大于第一光刻胶层A1的第二部分A12 的厚度，因此灰化去除过程结束后，待形成栅极区域和栅极线仍然被第一部分A11遮盖，源极206、漏极207和数据线仍然被第二光刻胶层A2覆盖，仅有待形成栅极区域周围的金属薄膜(待形成栅极层701)表面被暴露出来。
步骤S115：以第一光刻胶层的第一部分A11和第二光刻胶层A2为掩膜，去除第一光刻胶层的第一部分A11周围的金属薄膜，形成包括栅极205的图形，栅极205的周围暴露出部分栅极绝缘层204，如图9所示。
本步骤中，例如可采用湿法刻蚀或者干法刻蚀工艺对待形成栅极区域(即第一光刻胶层的第一部分A11)周围的金属薄膜(即待形成栅极层701)进行去除，剩余的金属薄膜形成栅极205。
由于源极206和漏极207会与有源层203电连接，因此栅极205周围的栅极绝缘层所覆盖的有源层被作为与源极206和漏极207进行欧姆接触的区域。基于减小欧姆接触电阻的考虑，本实施例中，在形成包括栅极205的图形之后，阵列基板的制作方法例如还可进行以下操作：以栅极205为掩膜，对栅极205周围的有源层203进行掺杂；对衬底基板进行退火，以激活掺杂的杂质。通过该掺杂过程，能够降低掺杂区域(即作为源漏接触区的有源层)的导电特性，降低欧姆接触电阻。
需要说明的是，上述掺杂过程例如可采用离子注入或者离子云注入的方法，掺杂离子可为包括H2的PH3或者包括H2的B2H6，离子注入剂量可在10^15～10^16ions/cm2之间，注入能量可在10～100KeV之间。
需要说明的是，在完成整个步骤S11后，可去除剩余的光刻胶层(第一光刻胶层的第一部分A11和第二光刻胶层A2)。
本实施例中，通过在衬底基板上连续形成有源材料层501、栅极绝缘层204和金属薄膜502。利用半透式掩膜构图工艺形成第一光刻胶层A1和第二光刻胶层A2，使第一光刻胶层A1中较厚的部分遮盖待形成栅极和栅极线区域，较薄的部分遮盖待形成栅极区域周围的待形成有源层区域；第二光刻胶层A2覆盖待形成源极、漏极和数据线区域，其厚度比第一光刻胶层A1中的较薄部分的厚度厚。然后去除暴露的金属薄膜及其覆盖的栅极绝缘层和有源材料层，形成有源层203、源极206、漏极207、栅极线和数据线。之后去除第一光刻胶层A1中的较薄部分，暴露出待形成栅极区域周围的金属薄膜，去除该部分金属薄膜形成栅极205。可见，通过上述步骤S11(步骤S111～ 步骤S115)实现了在同一次构图工艺下形成有源层203、栅极205、源极206、漏极207、栅极线和数据线，将形成有源层所需的构图工艺、形成栅极和栅极线所需的构图工艺与形成源极、漏极和数据线所需的构图工艺合并为一次构图工艺，从而简化了阵列基板的制作方法，同时改善了多次构图对位的难度较大所引起对位偏差的问题，提高了阵列基板的良率。
步骤S12：在衬底基板上形成钝化层301，通过第二次构图工艺图案化钝化层301，形成暴露出部分源极206与部分有源层203的源极接触孔302、暴露出部分漏极207与部分有源层203的漏极接触孔303和暴露出部分断开的栅极线或数据线的跨桥结构接触孔，如图3所示。
本实施例中，上述步骤S12例如可包括以下步骤S121至S123。
步骤S121：在衬底基板上形成钝化层301，如图10所示。
形成钝化层301的过程例如可包括：首先在包括栅极205、源极206、漏极207、栅极线和数据线的图形背离衬底基板201的一侧沉积含氢的钝化层材料，然后进行快速热退火或者热处理炉退火等退火工艺，使氢进入有源层203内部，修复其内部体缺陷，并进入有源层203与其它膜层的界面，修复界面缺陷，从而达到提高TFT特性的目的。
钝化层301的材料例如可为含氢的氮化硅薄膜，厚度例如可为200nm～500nm。
步骤S122：在钝化层301上形成第三光刻胶层A3和第四光刻胶层A4，第三光刻胶层A3覆盖栅极205、源极206、栅极线和数据线，第四光刻胶层A4覆盖漏极207，第三光刻胶层A3的厚度大于第四光刻胶层A4的厚度,如图11所示。
本步骤中可采用具有待形成源极接触孔图案和待形成漏极接触孔图案的半透式掩膜版，例如半色调掩膜版或灰色调掩膜版等。利用半透式掩膜版上特定区域的光透过率不同的特性，在钝化层301上形成不同厚度的光刻胶层：第三光刻胶层A3的厚度大于第四光刻胶层A4的厚度。
第三光刻胶层A3的厚度例如可为1μm～3μm，第四光刻胶层A4的厚度例如可为0.5μm～1μm。
步骤S123：以第三光刻胶层A3和第四光刻胶层A4为掩膜，去除暴露的钝化层，形成暴露出部分源极206与部分有源层203的源极接触孔302、 暴露出部分漏极207与部分有源层203的漏极接触孔303和暴露出部分断开的栅极线或数据线的跨桥结构接触孔，如图12所示。
上述步骤中，例如可利用干法刻蚀工艺进行源极接触孔、漏极接触孔和跨桥结构接触孔的刻蚀。起初，所暴露出来的钝化层301被刻蚀；当刻蚀至源极206、漏极207、栅极线和数据线所在膜层的表面时，由于对不同材料的刻蚀速率不同，源极206、漏极207、栅极线和数据线的形成材料(通常为金属)相对于钝化层材料的刻蚀的选择比极小，因此源极206、漏极207、栅极线和数据线材料并不会被去除或仅仅被去除极少的量，而源极206、漏极207、栅极线和数据线所在膜层中属于待形成源极接触孔区域、待形成漏极接触孔区域、待形成跨桥结构接触孔区域内的钝化层材料则被刻蚀掉，从而在源极206和漏极207处形成台阶状的结构，二者的部分表面被暴露出来，同时断开的栅极线或数据线被部分暴露，跨桥结构接触孔形成；继续向下刻蚀的过程中，未被源极206和漏极207遮盖且处于待形成源极接触孔区域和待形成漏极接触孔区域内的栅极绝缘层204的材料被去除，直至暴露出有源层203的表面，刻蚀结束，源极接触孔302和漏极接触孔303形成。
本步骤中，所使用的干法刻蚀工艺例如可为电感耦合等离子体刻蚀等刻蚀工艺。
需要说明的是，本步骤中在去除暴露的钝化层的同时，还去除暴露的钝化层所覆盖的、位于栅极205周围的栅极绝缘层。
步骤S13：在衬底基板上形成透明导电薄膜，通过薄膜剥离工艺去除部分透明导电薄膜，以在源极接触孔中形成电连接源极206和有源层203的源极接触部分401，在漏极接触孔中形成电连接漏极207和有源层203的漏极接触部分402，在漏极207上方的钝化层301上形成与漏极接触部分402电连接的像素电极403，在跨桥结构接触孔内和上方的钝化层上形成电连接断开的栅极线或数据线的跨桥结构，如图4所示。
上述步骤S13例如可包括以下步骤S131至S133。
步骤S131：去除第四光刻胶层A4，如图13所示。
本步骤中，例如可通过等离子体灰化等灰化工艺去除第四光刻胶层A4。由于第三光刻胶层A3的厚度大于第四光刻胶层A4，因此在光刻胶层去除过程中，第三光刻胶层A3虽然被去除了一部分，但是仍然剩余一定的厚度遮 盖在栅极205、源极206、栅极线和数据线的上方。该剩余的第三光刻胶层A3在后续步骤中会作为剥离层。
步骤S132：在衬底基板上形成透明导电薄膜1401，如图14所示。
本步骤中，形成透明导电薄膜1401例如可采用磁控溅射、化学汽相淀积等工艺。
透明导电薄膜1401的厚度、形成材料和具体结构可根据实际需要相应选择，本实施例对此并不限定，其厚度范围例如可为20nm～150nm，形成材料例如可为ITO(Indium Tin Oxide，氧化铟锡)、IZO(Indium Zinc Oxide，氧化铟锌)、ZTO(氧化锌锡)、Ag、Al、Au等中的一种或多种的组合，具体结构例如可为单层薄膜结构或多层薄膜构成的复合结构。
例如，若所制作的阵列基板应用于底发射的AMOLED显示装置，则透明导电薄膜1401例如为ITO(Indium Tin Oxide，氧化铟锡)、IZO(Indium Zinc Oxide，氧化铟锌)或ZTO(氧化锌锡)等氧化物透明导电薄膜，其厚度例如为20nm～100nm；若所制作的阵列基板应用于顶发射的AMOLED显示装置，则透明导电薄膜1401例如为ITO薄膜、Ag(银)薄膜和ITO薄膜所构成的复合薄膜，或者IZO薄膜和Ag薄膜所构成的复合薄膜，或者其它复合薄膜，透明导电薄膜1401中ITO薄膜的厚度例如可为10nm～50nm，Ag的薄膜厚度例如可为20nm～100nm。
步骤S133：剥离第三光刻胶层A3，以去除覆盖在第三光刻胶层A3上的透明导电薄膜，在源极接触孔302中形成电连接源极206和有源层203的源极接触部分401，在漏极接触孔303中形成电连接漏极207和有源层203的漏极接触部分402，在漏极207上方的钝化层301上形成与漏极接触部分402电连接的像素电极403，在跨桥结构接触孔内和上方的钝化层上形成电连接断开的栅极线或数据线的跨桥结构，如图15所示。
例如，可把形成完透明导电薄膜1401的衬底基板放入剥离机台里，使用光刻胶剥离液去除残留的第三光刻胶层A3，通过薄膜剥离工艺同时去除第三光刻胶层A3上覆盖的透明导电薄膜，源极接触孔302、漏极接触孔303及处于待形成像素电极区域内的透明导电薄膜被保留下来。源极接触孔302内的透明导电薄膜作为源极接触部分401电连接源极206与有源层203，漏极接触孔303内的透明导电薄膜作为漏极接触部分402电连接漏极207与有源层 203，与漏极207相邻的待形成像素电极区域内的钝化层301上方的透明导电薄膜作为像素电极403与漏极207电连接。例如，像素电极403可以与存储电极形成一存储电容，用于在相邻两帧画面切换过程中，维持上一帧画面的显示。
需要说明的是，本实施例中，栅极线和数据线与栅极205、源极206和漏极207在同一光刻步骤下形成，在数据线与栅极线交叉处，数据线或栅极线需断开。以栅极线连续、数据线在与栅极线交叉处断开为例，如图16所示，在沉积完钝化层301后，需要在断开处制作跨桥结构接触孔，然后采取跨桥结构1602将断开的数据线1601电连接，以此实现数据线1601与栅极线1603相互之间的电性绝缘。电连接断开的数据线1601所需制作的跨桥结构接触孔1602a与源极接触孔302和漏极接触孔303同时形成，填充于跨桥结构接触孔内、电连接断开的数据线1601的跨桥结构1602由部分透明导电薄膜1401形成，在形成透明导电薄膜1401的同时将透明导电薄膜材料填充于跨桥结构接触孔内，并在剥离第三光刻胶层A3的同时剥离跨桥结构1602周围需要剥离的透明导电薄膜材料，形成电连接断开的数据线1601的跨桥结构1602。
本实施例中，从上述步骤S12(步骤S121～步骤S123)～步骤S13(步骤S131～步骤S133)，首先通过使用半透式掩膜版形成不同厚度的光刻胶层，进行刻蚀形成源极接触孔和漏极接触孔，然后去除存在于待形成像素电极区域内的、厚度较薄的光刻胶层，之后形成透明导电薄膜，采用薄膜剥离工艺去除存在于源极206和栅极205上方的、厚度较厚的光刻胶层及其上覆盖的透明导电薄膜，形成像素电极403，且实现源极206和漏极207与有源层203的电连接，从而将图1所示的阵列基板的制作方法中的源极接触孔和漏极接触孔的形成与像素电极接触孔的形成所需进行的两次构图合二为一，简化了阵列基板的制作步骤，提高了生产效率；且由于减少了构图工艺的使用次数，因此能够在一定程度上避免多次构图造成的对位偏差问题，提高了产品的良率。
在形成完源极接触部分401、漏极接触部分402和像素电极403之后，本实施例提供的阵列基板的制作方法例如还可包括：在衬底基板上形成像素定义层的步骤。
例如，在经过步骤S13的衬底基板上沉积像素定义层材料，利用构图工 艺形成具有像素定义层图案的光刻胶掩膜，进行刻蚀，去除待形成像素定义层外的像素定义层材料，形成像素定义层。
像素定义层的形成材料例如可以采用亚克力等材料，其厚度例如为1μm～4μm。
在像素定义层制备完毕后，例如可使用快速热退火炉或热处理炉，对完成的阵列基板进行退火处理，以稳定TFT的特性。
需要说明的是，本实施例中的所提供制作方法可应用于LTPS TFT阵列基板的制作，但是这并不能对本实施例所提供的制作方法的应用范围构成限定，在本发明的核心思想不变的前提下，本实施例所提供的制作方法还能够应用于非晶硅TFT阵列基板、HTPS TFT阵列基板、氧化物TFT阵列基板、有机TFT阵列基板等的制作。
本实施例所提供的阵列基板的制作方法中，仅通过一次构图工艺同时形成有源层、栅极、源极、漏极、栅极线和数据线，省去了栅极与源漏极之间的层间绝缘层，将图1所示的阵列基板的制作方法中形成有源层、形成栅极和栅极线、与形成源漏极和数据线所需用到的构图工艺合并为一次。
并且，本实施例仅通过一次构图工艺形成底部具有台阶状结构的源极接触孔和漏极接触孔，同时形成跨桥结构接触孔，并通过一次性沉积透明导电薄膜，结合薄膜剥离工艺，在形成像素电极的同时，实现源极和漏极与有源层的电连接，断开的栅极线或数据线的电连接，从而将图1所示的阵列基板的制作方法中源极接触孔和漏极接触孔的形成与像素电极接触孔的形成所需进行的两次构图工艺合二为一。
可见，本实施例所提供的制作方法能够将图1所示的阵列基板的制作方法需要进行的8～9次构图工艺减少至3次，从而简化了阵列基板的制作步骤，提高了生产效率；且由于减少了构图工艺的使用次数，因此能够有效改善多次光刻的多次高精度对位造成的对位偏差，提高产品的良率。
实施例二
本实施例提供了一种阵列基板，如图17所示，本实施例所提供的阵列基板包括：位于衬底基板201上的有源层203；覆盖有源层203的栅极绝缘层204；位于栅极绝缘层204上且位于同一膜层的栅极205、源极206、漏极207、栅极线和数据线，在源极206和衬底基板201之间、漏极207和衬底基板201 之间分别形成有残余有源材料层203′，栅极线或数据线在栅极线和数据线的交叉处断开；覆盖栅极205、源极206、漏极207、栅极线和数据线的钝化层301；位于钝化层301和栅极绝缘层204内部的源极接触孔、漏极接触孔和跨桥结构接触孔，源极接触孔暴露出部分源极206和部分有源层203，漏极接触孔暴露出部分漏极207和部分有源层203，跨桥结构接触孔暴露出部分断开的栅极线或数据线；位于同一膜层的源极接触部分401、漏极接触部分402、像素电极403和跨桥结构，源极接触部分401位于源极接触孔内部，电连接源极206与有源层203；漏极接触部分402位于漏极接触孔内部，电连接漏极207与有源层203；像素电极403位于漏极207上方的钝化层301上，通过漏极接触部分402与漏极207电连接；跨桥结构位于跨桥结构接触孔内和上方的钝化层上，电连接断开的栅极线或数据线。
有源层203、栅极绝缘层204、栅极205、源极206、漏极207、栅极线、数据线和钝化层301的位置关系例如可如图17所示，即有源层203位于衬底基板201上，栅极绝缘层204位于有源层203背离衬底基板201的一侧，栅极205、源极206、漏极207、栅极线和数据线位于栅极绝缘层204背离衬底基板201的一侧，钝化层301位于栅极205、源极206、漏极207、栅极线和数据线背离衬底基板201的一侧。
需要说明的是，本实施例仅以图17所示出的上述各膜层的位置关系为例进行说明，在本发明的其它实施例中，上述有源层203、栅极绝缘层204、栅极205、源极206、漏极207、栅极线、数据线和钝化层301的相对位置还可以有其它的变化。
本实施例所提供的阵列基板的栅极205、源极206、漏极207、栅极线和数据线位于同一膜层中，因此栅极205与源极206和漏极207之间不存在重叠部分，即栅极205与源极206和漏极207之间没有寄生电容；而图1所示的阵列基板由于栅极与源极和漏极位于不同的膜层中，栅极与源极和漏极之间的重叠导致寄生电容的产生，进而影响器件的电性能。可见，本实施例中的阵列基板的寄生电容较小，电性能更优。且上述结构相对于图1所示的阵列基板省略了栅极与源漏极之间的层间绝缘层，在一定程度上减少了材料的使用量，降低了生产成本。
并且，由实施例一可知本实施例中的阵列基板能够采用更少次数的构图 工艺形成，因此本实施例所提供的阵列基板具有制作方法简单、生产效率高的优点。
同时，由于构图工艺需要较高的对位精度，高的对位精度使对位的难度较大，多次构图极易引起对位的偏差，造成器件的良率下降，本实施例中的阵列基板能够利用更少次数的构图工艺制作完成，减少构图次数能够改善对位不准的问题，因此本实施例所提供的阵列基板具有较高的良率。
需要说明的是，附图中所示出的203′为有源材料层501经过被刻蚀一部分后所剩余的部分中除形成有源层203的部分外其它部分。
本实施例中有源层203的形成材料例如为多晶硅。
本实施例对栅极205、源极206、漏极207栅极线和数据线的材料并不限定，三者的材料例如可包括铝、铜、钼、钛和铝钕化合物等中的至少一种或几种的组合，以达到更好的导电效果。
另外，本实施例中，源极接触部分401、漏极接触部分402、像素电极403和跨桥结构的厚度例如为20nm～150nm，以达到更好的导电效果。
相对于的阵列基板，本实施例中阵列基板可在形成完钝化层301后省略平坦层的制作，以节约材料、降低成本、简化工艺。基于该思想，本实施例中钝化层301的材料例如可选用与平坦层相同的材料，例如为亚克力，以在隔绝平坦层上下膜层的同时，平坦化衬底基板的表面。
本实施例所提供的阵列基板例如还可包括：与有源层203同层设置的存储电极203a，如图17所示，该存储电极例如可与有源层203形成于同一步骤下，与像素电极403重叠构成存储电容，用于在两帧画面切换时，维持上一帧画面的显示。
本实施例中，阵列基板例如还可包括：位于衬底基板201与有源层203之间的缓冲层202，以保护衬底基板201。缓冲层202例如可包括氮化硅薄膜和氧化硅薄膜，氮化硅薄膜例如可相对于氧化硅薄膜靠近衬底基板201，氮化硅薄膜具有很强的扩散阻挡特性，能够抑制金属离子对后续形成的多晶硅薄膜的影响，氧化硅薄膜能够与后续形成的多晶硅薄膜形成优良的界面，从而防止氮化硅薄膜的缺陷对多晶硅薄膜质量的损害。
另外，本实施例所提供的阵列基板例如还可包括：覆盖源极接触部分401、漏极接触部分402和跨桥结构的像素定义层1701，该像素定义层1701 用于保持源极206和漏极207与形成于像素定义层1701上的膜层相互电性绝缘，并且像素定义层1701形成于像素电极403的周围，还用于定义出像素区域。像素定义层1701可采用与平坦层相同的材料，例如可采用亚克力等材料，以平坦化衬底基板的表面。
本实施例所提供的阵列基板例如可为LTPS TFT阵列基板，在本发明的其它实施例中，还可为非晶硅TFT阵列基板、HTPS TFT阵列基板、氧化物TFT阵列基板或有机TFT阵列基板等，在此并不进行限定。
实施例三
基于实施例二，本实施例提供了一种显示装置，该显示装置包括实施例二所述的阵列基板。
本实施例所提供的显示装置例如可为OLED(Organic Light Emitting Diode，有机发光二极管)显示装置，如：AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)显示装置；还可为LCD(Liquid Crystal Display，液晶显示装置)，如：IPS(In-Plane Switching，平面转换)型LCD等。
由于本实施例所提供的显示装置，其TFT的栅极与源漏极处于同一膜层，因此栅极与源极和漏极之间不存在寄生电容，从而改善了显示装置的性能。
并且，由于本实施例中的显示装置，其阵列基板能够利用更少次数的构图工艺制作形成，因此显示装置生产效率更高；同时，减少构图次数能够改善对位不准的问题，因此本实施例中的显示装置具有较高的良率。
此外，由于本实施例所提供的显示装置中的TFT不存在栅极与包括源极和漏极的图形之间的层间绝缘层，节省了材料的使用，因此使得本实施例中的显示装置的生产成本降低，工艺步骤简化。
实施例四
本发明实施例提供了一种薄膜晶体管，其包括：位于衬底基板上的有源层；覆盖所述有源层的栅极绝缘层；位于所述栅极绝缘层上且位于同一膜层的栅极、源极和漏极，在所述源极和所述衬底基板之间、所述漏极和所述衬底基板之间分别形成有残余有源材料层；覆盖所述栅极、所述源极和所述漏极的钝化层；位于所述钝化层和所述栅极绝缘层内部的源极接触孔和漏极接 触孔，所述源极接触孔暴露出部分所述源极和部分所述有源层，所述漏极接触孔暴露出部分所述漏极和部分所述有源层；位于同一膜层的源极接触部分和漏极接触部分，所述源极接触部分位于所述源极接触孔内部，电连接所述源极与所述有源层；所述漏极接触部分位于所述漏极接触孔内部，电连接所述漏极与所述有源层。
本发明实施例提供了一种薄膜晶体管的制作方法，其包括：在衬底基板上依次形成有源材料层、栅极绝缘层和金属薄膜，通过第一次构图工艺图案化所述有源材料层、所述栅极绝缘层和所述金属薄膜，形成包括有源层的图形和包括栅极、源极、漏极的图形，所述栅极的周围暴露出部分所述栅极绝缘层；在衬底基板上形成钝化层，通过第二次构图工艺图案化所述钝化层，形成暴露出部分所述源极与部分所述有源层的源极接触孔、暴露出部分所述漏极与部分所述有源层的漏极接触孔；在衬底基板上形成导电薄膜，去除部分所述导电薄膜，以在所述源极接触孔中形成电连接所述源极和所述有源层的源极接触部分，在所述漏极接触孔中形成电连接所述漏极和所述有源层的漏极接触部分。在一个示例中，所述导电薄膜可以采用上述的透明导电薄膜。
本实施例的薄膜晶体管的制作方法的实施可参考上述阵列基板的相关描述，重复之处不再赘述。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2014年5月27日递交的中国专利申请第201410226377.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (21)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上依次形成有源材料层、栅极绝缘层和金属薄膜，通过第一次构图工艺图案化所述有源材料层、所述栅极绝缘层和所述金属薄膜，形成包括有源层的图形和包括栅极、源极、漏极、栅极线和数据线的图形，所述栅极的周围暴露出部分所述栅极绝缘层，所述栅极线或所述数据线在所述栅极线和所述数据线的交叉处断开；
    在衬底基板上形成钝化层，通过第二次构图工艺图案化所述钝化层，形成暴露出部分所述源极与部分所述有源层的源极接触孔、暴露出部分所述漏极与部分所述有源层的漏极接触孔和暴露出部分断开的栅极线或数据线的跨桥结构接触孔；
    在衬底基板上形成透明导电薄膜，去除部分所述透明导电薄膜，以在所述源极接触孔中形成电连接所述源极和所述有源层的源极接触部分，在所述漏极接触孔中形成电连接所述漏极和所述有源层的漏极接触部分，在所述漏极上方的钝化层上形成与所述漏极接触部分电连接的像素电极，在所述跨桥结构接触孔内和上方的钝化层上形成电连接断开的栅极线或数据线的跨桥结构。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，
    利用半透式掩膜版，在所述金属薄膜上形成第一光刻胶层和第二光刻胶层，所述第一光刻胶层覆盖待形成有源层区域和待形成栅极线区域，并包括覆盖待形成栅极区域与待形成栅极线区域的第一部分和位于所述第一部分周围的第二部分，所述第二光刻胶层覆盖待形成源极区域、待形成漏极区域和待形成数据线区域，所述第一光刻胶层的第一部分和所述第二光刻胶层的厚度均大于所述第一光刻胶层的第二部分的厚度，覆盖所述待形成栅极线区域的第一光刻胶层或覆盖所述待形成数据线区域的第二光刻胶层在二者交叉处断开；
    以所述第一光刻胶层和所述第二光刻胶层为掩膜，去除暴露的金属薄膜和所述暴露的金属薄膜遮盖的栅极绝缘层与有源材料层，形成所述包括有源层的图形和包括所述源极、所述漏极、所述栅极线和所述数据线的图形，所 述栅极线或所述数据线在所述栅极线和所述数据线的交叉处断开；
    去除所述第一光刻胶层的第二部分；
    以所述第一光刻胶层的第一部分和所述第二光刻胶层为掩膜，去除所述第一光刻胶层的第一部分周围的金属薄膜，形成包括所述栅极的图形，所述栅极的周围暴露出部分所述栅极绝缘层。
  3. 根据权利要求1或2所述的阵列基板的制作方法，在形成包括所述栅极的图形之后，还包括：
    以所述栅极为掩膜，对所述栅极周围的有源层进行掺杂；
    对衬底基板进行退火，以激活所述掺杂的杂质。
  4. 根据权利要求1-3任一所述的阵列基板的制作方法，其中，
    在所述钝化层上形成第三光刻胶层和第四光刻胶层，所述第三光刻胶层覆盖所述栅极、所述源极、所述栅极线和所述数据线，所述第四光刻胶层覆盖所述漏极，所述第三光刻胶层的厚度大于所述第四光刻胶层的厚度；
    以所述第三光刻胶层和所述第四光刻胶层为掩膜，去除暴露的钝化层，形成暴露出部分所述源极与部分所述有源层的源极接触孔、暴露出部分所述漏极与部分所述有源层的漏极接触孔和暴露出部分断开的栅极线或数据线的跨桥结构接触孔。
  5. 根据权利要求4所述的阵列基板的制作方法，其中，
    去除所述第四光刻胶层；
    在衬底基板上形成透明导电薄膜；
    剥离所述第三光刻胶层，以去除覆盖在所述第三光刻胶层上的透明导电薄膜，形成所述源极接触部分、所述漏极接触部分、所述像素电极以及所述跨桥结构。
  6. 根据权利要求1-5任一所述的阵列基板的制作方法，其中，形成所述有源材料层包括：
    在所述衬底基板上沉积非晶硅材料；
    采用晶化工艺，使所述非晶硅材料转化为多晶硅材料，形成所述有源材料层。
  7. 根据权利要求1-6任一所述的阵列基板的制作方法，其中，在形成所述包括有源层的图形的步骤中，还同时形成包括存储电极的图形，以与所述 像素电极构成存储电容。
  8. 根据权利要求1-7任一项所述的阵列基板的制作方法，在形成所述有源材料层之前，还包括：
    在所述衬底基板上形成缓冲层。
  9. 根据权利要求1-8任一项所述的阵列基板的制作方法，在形成所述源极接触部分、所述漏极接触部分和所述像素电极之后，还包括：
    在衬底基板上形成像素定义层。
  10. 一种阵列基板，包括：
    位于衬底基板上的有源层；
    覆盖所述有源层的栅极绝缘层；
    位于所述栅极绝缘层上且位于同一膜层的栅极、源极、漏极、栅极线和数据线，其中，在所述源极和所述衬底基板之间、所述漏极和所述衬底基板之间分别形成有残余有源材料层，所述栅极线或所述数据线在所述栅极线和所述数据线的交叉处断开；
    覆盖所述栅极、所述源极、所述漏极、所述栅极线和所述数据线的钝化层；
    位于所述钝化层和所述栅极绝缘层内部的源极接触孔、漏极接触孔和跨桥结构接触孔，其中，所述源极接触孔暴露出部分所述源极和部分所述有源层，所述漏极接触孔暴露出部分所述漏极和部分所述有源层，所述跨桥结构接触孔暴露出部分断开的栅极线或数据线；
    位于同一膜层的源极接触部分、漏极接触部分、像素电极和跨桥结构，其中，所述源极接触部分位于所述源极接触孔内部，电连接所述源极与所述有源层；所述漏极接触部分位于所述漏极接触孔内部，电连接所述漏极与所述有源层；所述像素电极位于所述漏极上方的钝化层上，通过所述漏极接触部分与所述漏极电连接；所述跨桥结构位于所述跨桥结构接触孔内和上方的钝化层上，电连接断开的栅极线或数据线。
  11. 根据权利要求10所述的阵列基板，其中，所述有源层的材料为多晶硅。
  12. 根据权利要求10或11所述的阵列基板，其中，所述钝化层的材料为亚克力。
  13. 根据权利要求10-12任一所述的阵列基板，其中，所述源极接触部分、所述漏极接触部分、所述像素电极和所述跨桥结构的厚度为20nm～150nm。
  14. 根据权利要求10-13任一所述的阵列基板，还包括：与所述有源层同层设置的存储电极，所述存储电极与所述像素电极构成存储电容。
  15. 根据权利要求10-14任一项所述的阵列基板，还包括：位于所述衬底基板与所述有源层之间的缓冲层。
  16. 根据权利要求10-15任一项所述的阵列基板，还包括：覆盖所述源极接触部分、所述漏极接触部分和所述跨桥结构的像素定义层。
  17. 根据权利要求16所述的阵列基板，其中，所述像素定义层的材料为亚克力。
  18. 一种显示装置，包括权利要求10-17任一项所述的阵列基板。
  19. 根据权利要求18所述的显示装置，其中，所述显示装置为液晶显示装置或有机发光二极管显示装置。
  20. 一种薄膜晶体管，包括：
    位于衬底基板上的有源层；
    覆盖所述有源层的栅极绝缘层；
    位于所述栅极绝缘层上且位于同一膜层的栅极、源极和漏极，其中，在所述源极和所述衬底基板之间、所述漏极和所述衬底基板之间分别形成有残余有源材料层；
    覆盖所述栅极、所述源极和所述漏极的钝化层；
    位于所述钝化层和所述栅极绝缘层内部的源极接触孔和漏极接触孔，其中，所述源极接触孔暴露出部分所述源极和部分所述有源层，所述漏极接触孔暴露出部分所述漏极和部分所述有源层；
    位于同一膜层的源极接触部分和漏极接触部分，其中，所述源极接触部分位于所述源极接触孔内部，电连接所述源极与所述有源层；所述漏极接触部分位于所述漏极接触孔内部，电连接所述漏极与所述有源层。
  21. 一种薄膜晶体管的制作方法，包括：
    在衬底基板上依次形成有源材料层、栅极绝缘层和金属薄膜，通过第一次构图工艺图案化所述有源材料层、所述栅极绝缘层和所述金属薄膜，形成 包括有源层的图形和包括栅极、源极、漏极的图形，所述栅极的周围暴露出部分所述栅极绝缘层；
    在衬底基板上形成钝化层，通过第二次构图工艺图案化所述钝化层，形成暴露出部分所述源极与部分所述有源层的源极接触孔、暴露出部分所述漏极与部分所述有源层的漏极接触孔；
    在衬底基板上形成导电薄膜，去除部分所述导电薄膜，以在所述源极接触孔中形成电连接所述源极和所述有源层的源极接触部分，在所述漏极接触孔中形成电连接所述漏极和所述有源层的漏极接触部分。
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