CN103178119B - 阵列基板、阵列基板制备方法以及显示装置 - Google Patents

阵列基板、阵列基板制备方法以及显示装置 Download PDF

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CN103178119B
CN103178119B CN201310097845.2A CN201310097845A CN103178119B CN 103178119 B CN103178119 B CN 103178119B CN 201310097845 A CN201310097845 A CN 201310097845A CN 103178119 B CN103178119 B CN 103178119B
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electrode
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CN103178119A (zh
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金熙哲
宋泳锡
刘圣烈
崔承镇
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/361,396 priority patent/US9070599B2/en
Priority to PCT/CN2013/086368 priority patent/WO2014153958A1/zh
Priority to EP13856064.4A priority patent/EP2991121B1/en
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Abstract

本发明涉及液晶显示技术领域，具体涉及一种阵列基板、阵列基板制备方法以及显示装置。本发明的一种阵列基板，首先在栅电极与漏电极和源电极之间形成有填充层，由于填充层增大了栅电极与漏电极以及源电极之间的距离，进而减少了栅线和源电极以及像素电极之间形成的电容；进一步的，本发明的阵列基板钝化层过孔设置在栅线之上，这样不但增加了有效透光区域，从而增大了像素的开口率，而且没有增加跳变电压，不会引起图像闪烁或者残像等产品不良；因此，本发明提高了光透过率以及分辨率，并且由于减少了背光模组能耗，节省了成本，同时提升了应用该阵列基板的显示装置的显示品质。

Description

阵列基板、阵列基板制备方法以及显示装置
技术领域
本发明涉及液晶显示技术领域，具体涉及一种阵列基板、阵列基板制备方法以及显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)由于具有画面稳定、图像逼真、消除辐射、节省空间以及节省能耗等优点，现已占据了平面显示领域的主导地位。TFT-LCD(Thin Film Transistor-LiquidCrystal Display，薄膜晶体管液晶显示器)是目前主流的液晶显示器。
液晶显示器中有一个很重要的规格是光透过率，而决定光透过率最重要的因素就是开口率。开口率简单的来说就是光线能透过的有效区域比例；液晶面板包括阵列基板和彩膜基板，其中，阵列基板平面示意图如图1中所示，其上设有栅线15’，垂直于栅线15’设有数据线16’，栅线15’和数据线16’之间限定有像素区域，像素区域内设有薄膜晶体管和像素电极12’，薄膜晶体管的栅电极2’与栅线15’连接、源电极9’与数据线16’连接、漏电极8’通过钝化层过孔11’与像素电极12’连接。当光线经由背光板发射出来时，并不是所有的光线都能穿过面板，比如给驱动芯片、信号走线、薄膜晶体管以及储存电容等区域除了可能不完全透光外，也可能经过这些地方的光线并不受到电压的控制，而无法显示正确的灰阶，所以都需利用BM(Black Matrix，黑矩阵)加以遮蔽，以免干扰到其它透光区域的正确亮度。所以有效的透光区域，就只剩下图1中A区域所显示的区域，这一块有效的透光区域与全部面积的比例就称之为开口率。只要提高开口率，便可以增加光透过率以及分辨率，而同时背光板的亮度也不用特别的高，可以节省耗电及成本。
现有技术中，为了增加开口率，在不断针对影响开口率的各个因素进行优化。但是，现有技术中钝化层过孔通常不设置在栅线区域之上，栅线和源电极以及像素电极之间形成的电容Cgs的大小为30fF-100fF，因此跳变电压ΔVp在0.5V-1.0V之间；如果将钝化层过孔设置在栅线区域之上，则可以在很大程度上增加有效透光区域，从而增大像素的开口率；但是，如果直接将钝化层过孔设置在栅线之上，栅线和源电极以及像素电极之间形成的电容Cgs的大小为200fF-500fF，则跳变电压ΔVp在2.5V-7.0V之间，由于跳变电压过大，因此会引起图像闪烁或者残像等产品不良。
发明内容
(一)要解决的技术问题
本发明的目的在于提供一种钝化层过孔设置在栅线区域之上的阵列基板，用以增加有效透光区域，进而增大像素开口率、提高光透过率、增加分辨率以及加强显示品质；进一步的，本发明还提供了该阵列基板的制备方法以及应用该阵列基板的显示装置。
(二)技术方案
本发明技术方案如下：
一种阵列基板，包括基板、形成在所述基板上的数据线以及栅线，所述数据线以及栅线限定的像素区域内设置有薄膜晶体管以及像素电极，所述薄膜晶体管包括：
与所述栅线连接的栅电极；
设置在所述栅线和栅电极上的栅绝缘层；
设置于所述栅电极对应区域的有源层；
分别设置在所述有源层两侧的漏电极和源电极；
设置在所述栅电极与漏电极和源电极之间的填充层；
设置在所述源电极、漏电极及有源层上的钝化层，所述钝化层对应于栅线的位置，开设有使所述漏电极与像素电极连接的钝化层过孔。
优选的，所述填充层厚度为
优选的，所述填充层为非导电的介质材料。
优选的，所述填充层由感光树脂发生固化反应形成。
优选的，所述沟道区域呈U型，其开口背离所述数据线。
优选的，所述栅线宽度与所述沟道区域宽度相同。
本发明还提供了一种制备上述阵列基板的方法：
一种阵列基板制备方法，包括步骤：
在所述基板上形成栅线、栅电极以及栅绝缘层；
在所述栅绝缘层形成有源层、漏电极和源电极；
在所述栅电极与漏电极和源电极之间形成填充层；
在所述源电极、漏电极及沟道区域上形成钝化层钝化层过孔；
形成通过钝化层过孔与所述漏电极连接的像素电极。
优选的，包括步骤：
S1.在所述基板上形成栅线、栅电极并在所述栅线以及栅电极上形成覆盖整个基板的栅绝缘层；
S2.在所述栅绝缘层上形成填充层；
S3.在所述栅绝缘层以及填充层上形成有源层、漏电极和源电极；
S4.在所述源电极、漏电极及沟道区域上形成钝化层；
S5.在所述钝化层位于所述栅线以及漏电极上方的位置开设钝化层过孔；
S6.形成通过钝化层过孔与所述漏电极连接的像素电极。
优选的，所述步骤S2包括：
S201.在所述栅绝缘层上涂覆一层感光树脂；
S202.通过双色调掩膜板曝光，形成对应所述填充层的感光树脂完全保留区域、对应所述沟道区域的感光树脂半保留区域以及对应栅电极接线区域的感光树脂完全去除区域；
S203.显影处理后，通过刻蚀工艺去除感光树脂完全去除区域的栅绝缘层；
S204.通过灰化工艺去除感光树脂半保留区域的感光树脂，暴露出栅绝缘层。
优选的，所述步骤S3包括：
S301.在所述在栅绝缘层以及填充层上沉积半导体层、掺杂半导体层以及源-漏金属层；
S302.在所述与源-漏金属层上涂覆一层光刻胶；
S303.通过双色调掩模板曝光，形成对应所述源电极以及漏电极区域的光刻胶完全保留区域、对应所述沟道区域的光刻胶半保留区域以及对应上述区域之外区域的光刻胶完全去除区域；
S304.显影处理后，通过第一次刻蚀工艺去除光刻胶完全去除区域的源-漏金属层、掺杂半导体层以及半导体层；
S305.通过灰化工艺去除光刻胶半保留区域的光刻胶；
S306.通过第二次刻蚀工艺去除光刻胶半保留区域的源-漏金属层以及掺杂半导体层，并去除部分厚度的半导体层；
S307.剥离剩余的光刻胶。
本发明还提供了一种包括上述任意一种阵列基板的显示装置。
(三)有益效果
本发明的一种阵列基板，首先在栅电极与漏电极和源电极之间形成有填充层，由于填充层增大了栅电极与漏电极以及源电极之间的距离，进而减少了栅线和源电极以及像素电极之间形成的电容；进一步的，本发明的阵列基板的钝化层过孔设置在栅线区域之上，这样不但增加了有效透光区域，从而增大了像素的开口率，而且没有增加跳变电压，不会引起图像闪烁或者残像等产品不良；因此，本发明提高了光透过率以及分辨率，并且由于减少了背光模组能耗，节省了成本，同时提升了应用该阵列基板的显示装置的显示品质。
附图说明
图1是现有技术中一种阵列基板的平面示意图；
图2是本发明的一种阵列基板的平面示意图；
图3是图2中阵列基板的剖面示意图；
图4是本发明的一种阵列基板制备方法流程示意图；
图5是依据图4中方法在基板上形成栅电极以及栅绝缘层后的剖面示意图；
图6是在图5中基板上涂覆感光树脂层后的剖面示意图；
图7是在图6中基板上进行显影处理后感光树脂半保留区域的剖面示意图；
图8是在图6中基板上进行显影处理后感光树脂完全去除区域的剖面示意图；
图9是在图8中基板上进行刻蚀工艺后的剖面示意图；
图10是在图7中基板上进行灰化工艺后的剖面示意图；
图11是在图10中基板上依次沉积有源层以及源-漏金属层后的剖面示意图；
图12是在图11中基板上形成有源层、源电极、漏电极以及有源层的沟道区域后的剖面示意图；
图13是在图12中基板上形成钝化层后的剖面示意图；
图14是在图13中基板上开设钝化层过孔后的剖面示意图；
图15是在图14中基板上形成像素电极后的剖面示意图；
图中：2’：栅电极；8’：漏电极；9’：源电极；11’：钝化层过孔；12’：像素电极；15’：栅线；16’：数据线；17’：沟道区域；1：基板；2：栅电极；3：栅绝缘层；4：填充层；5：半导体层；6：掺杂半导体层；7：源-漏金属层；8：漏电极；9：源电极；10：钝化层；11：钝化层过孔；12：像素电极；15：栅线；16：数据线；17：沟道区域。
具体实施方式
下面结合附图和实施例，对发明的具体实施方式做进一步描述。以下实施例仅用于说明本发明，但不用来限制本发明的范围。
需要说明的是：本发明的“上”“下”“内”“外”只是参考附图对本发明进行说明，不作为限定用语。
实施例一
如图2所示的一种阵列基板，图中所示为一个像素单元的结构；图3是图2中阵列基板的剖面图；其包括形成在基板1上的数据线16以及栅线15，数据线16以及栅线15限定了像素区域，在像素区域内形成有薄膜晶体管以及像素电极12，栅线15用于向薄膜晶体管提供开启信号，数据线16用于向像素电极12提供数据信号；薄膜晶体管包括：形成在基板1上并与栅线15连接的栅电极2；形成在栅线15以及栅电极2上并覆盖整个基板的栅绝缘层3；形成在栅绝缘层3上的有源层，形成在有源层上方的漏电极8以及与漏电极8相对并与数据线16连接的源电极9，源电极9与漏电极8通过有源层的沟道区域17实现可控制的电连接；形成在源电极9、漏电极8及沟道区域17上具有钝化层10；本发明的改进点之一是，在栅电极与漏电极和源电极之间形成有填充层；本实施例中以在栅绝缘层3与有源层4之间形成填充层为例进行说明；由于填充层4增大了栅线15与漏电极8以及源电极9之间的距离，进而减少了栅线15和源电极9以及像素电极12之间形成的电容；进一步的，在钝化层10位于栅线15上方的位置，开设有使漏电极8与像素电极12连接的钝化层过孔11；对比图1以及图2，可以发现，通过将钝化层过孔设置在栅线15之上，可以大大增加有效透光区域，从而增大了像素的开口率；增加的有效透光区域如图中B区域所示；实际应用中，以23.6英寸的全高清(full HD，1920×1080)分辨率产品为例，这样可以增大5％-10％的开口率。
填充层4的主要作用是增大增大栅绝缘层3与漏电极8以及源电极9之间的距离，进而减少栅线15和源电极9以及像素电极12之间形成的电容，因此填充层4的材料优选为非导电的介质的材料，这样不会由于加入填充层4而影响降低电容的效果；本实施例中的填充层4由感光树脂发生固化反应形成，这样除了不影响降低电容的效果之外，还降低了填充层4的形成难度。
填充层4的厚度如果过大，则会造成最终产品厚度不良，填充层4的厚度如果过小，则起不到减小跳变电压的效果；本发明中，填充层厚度为这样既不会造成产品厚度不良，由能够起到不增大跳变电压的效果；优选的，填充层厚度为
此外，本发明还通过改变沟道区域开口的朝向，进一步的增加有效透光面积；现有技术中沟道区域呈U型，其开口与数据线延伸方向平行，具体如图1中17’所示，而本实施例中沟道区域17开口背离数据线16；这样的话，相比现有技术，需要的栅线的宽度会得到减少，栅线15宽度与沟道区域17宽度相同即可实现正常功能；栅线15宽度减少则意味着会增加相应面积的有效透光区域，从而增大像素的开口率；对比图1以及图2，增大的有效透光区域如C区域所示；实际应用中，以以23.6英寸的全高清(full HD，1920×1080)分辨率产品为例，这样可以增大2％-5％的开口率。
需要说明的是：实施例一的阵列基板采用底栅型的TFT结构进行说明示意，这仅仅是实现本发明的阵列基板的一种TFT结构，实际使用中还可以采用顶栅型TFT结构或经过变形的已知TFT结构。由于不是本发明的重点，在此不做赘述。
实施例二
本发明还提供了一种制备上述阵列基板的方法，主要在基板上形成栅线、栅电极并在栅线以及栅电极上形成覆盖整个基板的栅绝缘层；在栅绝缘层形成有源层、漏电极和源电极；在栅电极与漏电极和源电极之间形成填充层；在源电极、漏电极及沟道区域上形成钝化层；在钝化层位于栅线以及漏电极上方的位置开设钝化层过孔；形成通过钝化层过孔与漏电极连接的像素电极。本实施例中以在栅电极与漏电极和源电极之间形成填充层为例进行说明。
流程图如图4所示的一种阵列基板制备方法，主要包括以下步骤：
S1.清洁基板1后，在基板1上形成栅线15、栅电极2并在栅线15以及栅电极2上形成覆盖整个基板的栅绝缘层3；该步骤主要包括：
S101.在基板1上形成栅线15以及栅电极2：采用磁控溅射或热蒸发的方法在基板1(如玻璃基板1或石英基板1)上沉积一层栅金属薄膜；栅金属薄膜可以使用Cr、W、Ti、Ta、Mo、Al、Cu等金属及其合金，也可以为由多层金属薄膜组成的复合薄膜；然后采用普通掩模板，通过构图工艺对栅金属薄膜进行刻蚀，在基板1上形成栅线15以及薄膜晶体管的栅电极2的图形；
S102.在栅线15以及栅电极2上形成覆盖整个基板的栅绝缘层3，栅绝缘层3厚度为具体如图5中所示；栅绝缘层3可以采用氧化物、氮化物或氧氮化合物等。
S2.在栅绝缘层3上形成填充层4；本实施例中以感光树脂形成填充层为例进行说明。该步骤主要包括：
S201.在栅绝缘层3上涂覆一层感光树脂，感光树脂层的厚度为具体如图6中所示；
S202.通过双色调掩膜板曝光，形成对应填充层4的感光树脂完全保留区域、对应沟道区域17的感光树脂半保留区域以及对应栅电极接线区域的感光树脂完全去除区域；
S203.显影处理后，感光树脂完全保留区域的感光树脂厚度没有变化；光刻胶完全去除区域的感光树脂被完全去除，如图8中所示；感光树脂半保留区域的感光树脂厚度变薄，如图7中所示；然后通过刻蚀工艺去除感光树脂完全去除区域的栅绝缘层3，暴露出栅电极15，形成栅电极接线区域，如图9中所示；这样可以使得栅电极和沟道区域之间的距离不变，防止栅电极的驱动电压增大；
S204.通过灰化工艺去除感光树脂半保留区域的感光树脂，暴露出栅绝缘层3，如图10中所示。
S3.在栅绝缘层3以及填充层4上形成有源层、源电极9、漏电极8以及沟道区域17，本实施例中的有源层包括半导体层5以及掺杂半导体层6；该步骤主要包括：
S301.采用PECVD(Plasma Enhanced Chemical VaporDeposition，等离子体增强化学气相沉积法)方法在栅绝缘层3以及填充层4上依次沉积半导体层5以及掺杂半导体层6；然后采用磁控溅射或热蒸发方法沉积源-漏金属层7；具体如图11中所示；源-漏金属层7可以采用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金，也可以采用由多层金属复合构成；
S302.在与源-漏金属层7上涂覆一层光刻胶；
S303.通过双色调掩模板曝光，形成对应源电极9以及漏电极8区域的光刻胶完全保留区域、对应沟道区域17的光刻胶半保留区域以及对应上述区域之外区域的光刻胶完全去除区域；
S304.显影处理后，光刻胶完全保留区域的光刻胶厚度没有变化，光刻胶完全去除区域的光刻胶被完全去除，光刻胶半保留区域的光刻胶厚度变薄；然后通过第一次刻蚀工艺去除光刻胶完全去除区域的源-漏金属层7、掺杂半导体层6以及半导体层5，形成有源层图形；
S305.通过灰化工艺去除光刻胶半保留区域的光刻胶，暴露出该区域的源-漏金属层7；
S306.通过第二次刻蚀工艺去除光刻胶半保留区域的源-漏金属层7以及掺杂半导体层6，并去除部分厚度的半导体层5，形成源电极9、漏电极8以及沟道区域17；
S307.剥离剩余的光刻胶；此时具体结构如图12中所示。
S4.在源电极9、漏电极8及沟道区域17上采用PECVD方法沉积形成钝化层10；具体如图13中所示。
S5.采用普通掩模板通过构图工艺在钝化层10位于栅线15以及漏电极8上方的位置开设钝化层过孔11；具体如图14中所示。
S6.形成通过钝化层过孔11与漏电极8连接的像素电极12：
S601.采用磁控溅射或热蒸发的方法，沉积一层透明导电薄膜，透明导电薄膜可以采用ITO(Indium Tin Oxides，铟锡氧化物)或IZO(Indium Zinc Oxide，铟锌氧化物)单层膜，也可以采用为ITO和IZO复合膜；
S602.采用普通掩模板通过构图工艺在像素区域形成像素电极12，像素电极12通过钝化层过孔11与漏电极8连接；具体如图15中所示。
需要说明的是：实施例二的阵列基板制备方法仅仅是制备本发明实施例一中所述结构阵列基板的一种实现方法，实际使用中还可以通过增加或减少构图工艺次数、选择不同的材料或材料组合改变实现方法来实现本发明。
实施例三
本发明还提供了一种包括上述任意一种阵列基板的显示装置。
本发明还提供了一种显示装置，包括实施例一所述的阵列基板；由于其像素开口率增大，因此该显示装置具有光透过率以及分辨率，并且由于减少了背光模组能耗，节省了成本，同时提升了显示品质。
上述显示装置可以是显示面板、电子纸、OLED(Organic LightEmitting Diode，有机发光二级管)面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的保护范畴。

Claims (8)

1.一种阵列基板，包括基板、形成在所述基板上的数据线以及栅线，所述数据线以及栅线限定的像素区域内设置有薄膜晶体管以及像素电极，其特征在于，所述薄膜晶体管包括：
与所述栅线连接的栅电极；
设置在所述栅线和栅电极上方的栅绝缘层；
设置于所述栅电极对应区域上方的有源层；
分别设置在所述有源层两侧的漏电极和源电极；
设置在所述栅电极与漏电极和源电极之间的填充层；
设置在所述源电极、漏电极及有源层上的钝化层，所述钝化层对应于栅线的位置，开设有使所述漏电极与像素电极连接的钝化层过孔；
所述有源层的沟道区域呈U型，其开口背离所述数据线，所述栅线宽度与所述沟道区域宽度相同。
2.根据权利要求1所述的阵列基板，其特征在于，所述填充层厚度为
3.根据权利要求1所述的阵列基板，其特征在于，所述填充层为非导电的介质材料。
4.根据权利要求3所述的阵列基板，其特征在于，所述填充层由感光树脂发生固化反应形成。
5.一种阵列基板制备方法，其特征在于，包括步骤：
S1.在所述基板上形成栅线、栅电极并在所述栅线以及栅电极上形成覆盖整个基板的栅绝缘层；
S2.在所述栅绝缘层上形成填充层；
S3.在所述栅绝缘层以及填充层上形成有源层、漏电极和源电极；
S4.在所述源电极、漏电极及有源层的沟道区域上形成钝化层；
S5.在所述钝化层位于所述栅线以及漏电极上方的位置开设钝化层过孔；
S6.形成通过钝化层过孔与所述漏电极连接的像素电极。
6.根据权利要求5所述的阵列基板制备方法，其特征在于，所述步骤S2包括：
S201.在所述栅绝缘层上涂覆一层感光树脂；
S202.通过双色调掩膜板曝光，形成对应所述填充层的感光树脂完全保留区域、对应所述沟道区域的感光树脂半保留区域以及对应栅电极接线区域的感光树脂完全去除区域；
S203.显影处理后，通过刻蚀工艺去除感光树脂完全去除区域的栅绝缘层；
S204.通过灰化工艺去除感光树脂半保留区域的感光树脂，暴露出栅绝缘层。
7.根据权利要求6所述的阵列基板制备方法，其特征在于，所述步骤S3包括：
S301.在所述栅绝缘层以及填充层上沉积半导体层、掺杂半导体层以及源-漏金属层；
S302.在所述源-漏金属层上涂覆一层光刻胶；
S303.通过双色调掩模板曝光，形成对应所述源电极以及漏电极区域的光刻胶完全保留区域、对应所述沟道区域的光刻胶半保留区域以及对应上述区域之外区域的光刻胶完全去除区域；
S304.显影处理后，通过第一次刻蚀工艺去除光刻胶完全去除区域的源-漏金属层、掺杂半导体层以及半导体层；
S305.通过灰化工艺去除光刻胶半保留区域的光刻胶；
S306.通过第二次刻蚀工艺去除光刻胶半保留区域的源-漏金属层以及掺杂半导体层，并去除部分厚度的半导体层；
S307.剥离剩余的光刻胶。
8.一种显示装置，其特征在于，包括权利要求1-4任意一项所述的阵列基板。
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