CN105140300B - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

Info

Publication number
CN105140300B
CN105140300B CN201510684583.9A CN201510684583A CN105140300B CN 105140300 B CN105140300 B CN 105140300B CN 201510684583 A CN201510684583 A CN 201510684583A CN 105140300 B CN105140300 B CN 105140300B
Authority
CN
China
Prior art keywords
film transistor
thin film
tft
electrode
stripes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510684583.9A
Other languages
English (en)
Other versions
CN105140300A (zh
Inventor
顾可可
杨妮
胡伟
苟中平
刘信
齐智坚
侯宇松
陈帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chongqing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510684583.9A priority Critical patent/CN105140300B/zh
Publication of CN105140300A publication Critical patent/CN105140300A/zh
Priority to PCT/CN2016/098090 priority patent/WO2017067338A1/zh
Priority to US15/501,797 priority patent/US10361317B2/en
Application granted granted Critical
Publication of CN105140300B publication Critical patent/CN105140300B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133345Insulating layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供了一种薄膜晶体管及其制作方法、阵列基板和显示装置,其中的薄膜晶体管包括同层设置的第一电极图形与第二电极图形;所述第一电极图形包括沿第一方向延伸的第一条状部,所述第二电极图形包括围绕所述第一条状部的第一端的弯曲部;所述第二电极图形还包括从所述弯曲部的第一端沿所述第一方向延伸的第二条状部;该薄膜晶体管的沟道的形成区域包括所述弯曲部与所述第一条状部之间所夹的区域,以及所述第二条状部与所述第一条状部之间所夹的区域。本发明可以在不增大薄膜晶体管设置面积的前提下增加沟道宽度,从而可以用于器件性能的提升或者设置面积的减小,有利于产品成本的降低和产品性能的提升。

Description

薄膜晶体管及其制作方法、阵列基板和显示装置
技术领域
本发明涉及显示技术,具体涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
现有的TFT-LCD(Thin Film Transistor-Liquid Crystal Display,薄膜晶体管-液晶显示器),主要是通过像素电极和公共电极之间产生的电场控制液晶分子的转动,来呈现所要显示的画面的。由此,像素电极上的电位与像素的灰阶值有着严格的对应关系。而像素电极的电位能否达到要求值,主要是由TFT的开启电流等性能参数决定的。相同工艺条件下,TFT的宽长比(W/L,其中的W为沟道宽度、L为沟道长度)对TFT的性能参数起很大作用。
图1是现有技术中一种薄膜晶体管的结构示意图。参见图1,该TFT的沟道即源电极13与漏电极14之间的U形区域内的有源层12,并且其形成区域位于栅电极11的设置区域内。由于工艺能力的限制,TFT的沟道长度(如图1中源电极13与漏电极14的间距)很难被减小,因此提高性能参数的方法主要是增大沟道宽度(如图1中U形的沟道的轨迹长度),比如将沟道沿任一方向整体拉长。但是,该类方式会增大TFT的大小,从而挤占一部分透光区域的面积、减小像素的开口率,影响显示效果。
发明内容
针对现有技术中的缺陷,本发明提供一种薄膜晶体管及其制作方法、阵列基板和显示装置,可以在不减小像素开口率的前提下增加薄膜晶体管的宽长比。
第一方面,本发明提供了一种薄膜晶体管,包括同层设置的第一电极图形与第二电极图形;所述第一电极图形包括沿第一方向延伸的第一条状部,所述第二电极图形包括围绕所述第一条状部的第一端的弯曲部;所述第二电极图形还包括从所述弯曲部的第一端沿所述第一方向延伸的第二条状部;该薄膜晶体管的沟道的形成区域包括所述弯曲部与所述第一条状部之间所夹的区域,以及所述第二条状部与所述第一条状部之间所夹的区域。
可选地,所述第一电极图形还包括与所述第一条状部的第二端相接的本体部。
可选地,所述第一电极图形和所述第二电极图形上覆盖有绝缘层,所述绝缘层中形成有用于连接所述本体部的过孔。
可选地,所述过孔的形状为圆形、半圆形、方形或者长方形。
可选地,所述第二条状部的一端与所述本体部的一侧边缘对齐;该薄膜晶体管的沟道的形成区域还包括所述第二条状部与所述本体部之间所夹的区域。
可选地,所述薄膜晶体管还包括有源层图形;所述薄膜晶体管的沟道的形成区域位于所述有源层图形的设置区域内。
可选地,所述薄膜晶体管还包括栅电极图形,所述栅电极图形的设置区域包含所述沟道的形成区域。
可选地,所述弯曲部的形状为U形、L形或者I形。
第二方面,本发明还提供了一种上述任意一种薄膜晶体管的制作方法,包括:
形成包括所述第一电极图形与所述第二电极图形的导电层。
第三方面,本发明还提供了一种阵列基板,包括设置在像素区域内的薄膜晶体管;所述薄膜晶体管为上述任意一种的薄膜晶体管。
第四方面,本发明还提供了一种显示装置,包括上述任意一种的阵列基板。
由上述技术方案可知,本发明通过第二电极图形中第二条状部的设置,可以在不增大薄膜晶体管设置面积的前提下增加沟道宽度,从而可以用于器件性能的提升或者设置面积的减小。在具体应用至现有的TFT-LCD中时,本发明只需要改变现有图案化工艺的图案形状即可实现,有利于产品成本的降低和产品性能的提升。
当然,实施本发明的任一产品或方法并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单的介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是现有技术中一种薄膜晶体管的结构示意图;
图2是本发明一个实施例中一种薄膜晶体管的局部结构示意图;
图3是本发明一个实施例中一种薄膜晶体管的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图2是本发明一个实施例中一种薄膜晶体管的局部结构示意图。参见图2,该薄膜晶体管包括同层设置的第一电极图形与第二电极图形。具体地,如图2所示的第一电极图形包括沿第一方向R1延伸的第一条状部21a,而第二电极图形包括围绕该第一条状部21a的第一端(在图2中具体为左端)的弯曲部22a。除此之外,第二电极图形还包括从弯曲部22a的第一端(在图2中具体为有虚线标注的一端)沿第一方向R1延伸的第二条状部22b。基于上述结构,该薄膜晶体管的沟道的形成区域既包括上述弯曲部22a与第一条状部21a之间所夹的区域A1,也包括第二条状部22b与第一条状部21a之间所夹的区域A2。可以理解的是,上述第一电极图形与上述第二电极图形分别形成该薄膜晶体管的源电极和漏电极中的一个。
需要说明的是,本发明实施例中的第一电极图形与第二电极图形是同层设置的,因此可以在一次图案化工艺中利用预先确定的导体材料来同时形成。相对于现有的漏电极与源电极的图案化工艺来说,本发明实施例可以通过改变图案形状来实现。而对于本发明实施例未述及的薄膜晶体管的其他结构,可以根据具体所选取的薄膜晶体管的类型来按照现有技术的方式进行设置,本发明对此不做限制。例如,该薄膜晶体管的沟道应位于一个主要由半导体材料形成的层结构当中,而且该层结构应当与上述第一电极图形及第二电极图形直接接触。
可以看出的是,本发明实施例通过第二电极图形中第二条状部的设置,可以在不增大薄膜晶体管设置面积的前提下增加沟道宽度,从而可以用于器件性能的提升或者设置面积的减小。在具体应用至现有的TFT-LCD中时,本发明实施例只需要改变现有图案化工艺的图案形状即可实现,有利于产品成本的降低和产品性能的提升。
作为一种更为具体的示例,图3是本发明一个实施例中一种薄膜晶体管的结构示意图。参见图3,该薄膜晶体管与图2所示的薄膜晶体管一致的是:该薄膜晶体管包括同层设置的第一电极图形与第二电极图形,其中的第一电极图形包括沿第一方向R1延伸的第一条状部21a;而第二电极图形包括围绕该第一条状部21a的第一端(在图3中具体为左端)的弯曲部22a,以及从弯曲部22a的第一端(在图3中具体为有虚线标注的一端)沿第一方向R1延伸的第二条状部22b。
而在图2所示的薄膜晶体管的结构的基础之上,本发明实施例中的薄膜晶体管还具有下述特征:
第一,该薄膜晶体管还包括有源层图形23,该薄膜晶体管的沟道的形成区域位于该有源层图形的设置区域内。可以理解的是,该有源层图形23的形成材料为半导体,而且该有源层图形23与上述第一电极图形及上述第二电极图形接触,以在第一电极图形与第二电极图形之间所夹的区域内形成该薄膜晶体管的沟道。
第二,该薄膜晶体管还包括栅电极图形24,该栅电极图形24的设置区域包含该薄膜晶体管的沟道的形成区域。根据薄膜晶体管的工作原理可以推知,薄膜晶体管的沟道的形成区域需要被薄膜晶体管的栅电极所覆盖,因此上述有源层图形23需要至少在沟道的形成区域内与栅电极图形24相互交叠。可以理解的是,为保持彼此的电绝缘,有源层图形23与栅电极图形24之间应设有附图中未示出的绝缘层(可称为“栅绝缘层”),本发明对此不做限制。
第三,第一电极图形还包括与第一条状部21a的第二端(在图3中具体为右端)相接的本体部21b。由此,本体部21b可用于形成第一电极图形的电连接。举例来说,第一电极图形和第二电极图形上可以覆盖有绝缘层,而绝缘层中可以形成有用于连接该本体部21b的过孔H1。由此,可以在此基础之上通过形成导体层来在过孔H1中形成该导体层与第一电极图形的电连接。其中,过孔H1的形状可以是圆形、半圆形、方形或者长方形,本发明对此不做限制。
第四,上述第二条状部22b的一端与上述本体部21b的一侧边缘对齐,在图3中具体为第二条状部22b的右端与上述本体部21b的右侧边缘对齐。在此基础之上,该薄膜晶体管的沟道的形成区域除了上述弯曲部22a与第一条状部21a之间所夹的区域A1,和第二条状部22b与第一条状部21a之间所夹的区域A2之外,还包括第二条状部22b与本体部21b之间所夹的区域A3。可以看出的是,区域A1、A2和A3内均覆盖有有源层图形23以及栅电极图形24,因而这些区域内的沟道都可以形成第一电极图形与第二电极图形之间的电压。
可以理解的是,虽然图3所示的薄膜晶体管同时具备了上述五方面的特征,但在本发明的其他实施方式中,可以根据应用场景的需要选取其中的任意多个特征来实现所期望的技术效果,其显然包含图2所示的薄膜晶体管所具有的特征,因此同样可以在不增大薄膜晶体管设置面积的前提下增加沟道宽度,并有利于产品成本的降低和产品性能的提升,本发明对此不做限制。
另外,在本发明的其他实施方式中,弯曲部22a的形状除了可以为U形之外,还可以是L形或者I形(均可以具有预定的弯曲程度)。也就是说,视具体应用需要的不同,上述弯曲部22a可以呈U形包围第一条状部21a的第一端,也可以呈L形部分包围第一条状部21a的第一端,或者呈I形位于第一条状部21a的一侧。由此,弯曲部22a可以通过其他方式围绕第一条状部21a,以形成其他可以在给定设置面积下比现有技术中的薄膜晶体管具有更大的沟道宽度的薄膜晶体管。
可以理解的是,上述任意一种薄膜晶体管均可以是N型晶体管或者P型晶体管,可以具有顶栅结构或者底栅结构,可以是非晶硅(a-Si)TFT、多晶硅(p-Si)TFT、单晶硅TFT、金属氧化物半导体TFT中的任意一类,本发明对此不做限制。由此,根据薄膜晶体管类型的不同,可以根据应用场景确定上述第一电极图形对应该晶体管的源电极还是漏电极。特别地,在薄膜晶体管具有源电极与漏电极对称的结构时,可以不对源电极与漏电极进行特别区分。
基于同样的发明构思,本发明实施例提供一种上述任意一种薄膜晶体管的制作方法。具体来说,该方法包括:形成包括所述第一电极图形与所述第二电极图形的导电层。可以理解的是,第一电极图形与第二电极图形是同层设置的,因此可以在一次图案化工艺中利用预先确定的导体材料来同时形成在一个导电层当中。相对于现有的漏电极与源电极的图案化工艺来说,本发明实施例可以通过改变图案形状来实现。由此,本发明实施例可以用于器件性能的提升或者设置面积的减小,有利于产品成本的降低和产品性能的提升。
需要说明的是,根据所选用的薄膜晶体管的具体类型和结构的不同,本发明实施例的方法可以包括按照现有技术中的方式形成除该导电层之外的其他结构的步骤,本发明对此不作限制。
基于同样的发明构思,本发明实施例提供一种阵列基板,该阵列基板包括设置在像素区域内的薄膜晶体管;该薄膜晶体管为上述任意一种的薄膜晶体管。举例来说,本发明实施例的阵列基板可以设置在TFT-LCD或者有源矩阵有机发光二极管(Active-MatrixOrganic Light Emitting Diode,AMOLED)显示器中,而采用上述任意一种薄膜晶体管可以用于刷新频率和像素分辨率的提升,有利于产品成本的降低和产品性能的提升。
基于同样的发明构思,本发明实施例提供一种显示装置,包括上述任意一种的阵列基板。需要说明的是,本实施例中的显示装置可以为:显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于包括上述任意一种的阵列基板,因此本发明实施例所提供的显示装置可以具有更高的刷新频率和像素分辨率,以及更低的产品成本和更高的产品性能。
在本发明的描述中需要说明的是,术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。
本发明的说明书中,说明了大量具体细节。然而,能够理解,本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中,并未详细示出公知的方法、结构和技术,以便不模糊对本说明书的理解。
类似地,应当理解,为了精简本发明公开并帮助理解各个发明方面中的一个或多个,在上面对本发明的示例性实施例的描述中,本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而,并不应将该公开的方法解释呈反映如下意图:即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说,如权利要求书所反映的那样,发明方面在于少于前面公开的单个实施例的所有特征。因此,遵循具体实施方式的权利要求书由此明确地并入该具体实施方式,其中每个权利要求本身都作为本发明的单独实施例。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制,并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中,不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中,这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围,其均应涵盖在本发明的权利要求和说明书的范围当中。

Claims (8)

1.一种薄膜晶体管,其特征在于,包括同层设置的第一电极图形与第二电极图形;所述第一电极图形包括沿第一方向延伸的第一条状部,所述第二电极图形包括围绕所述第一条状部的第一端的弯曲部;所述第二电极图形还包括从所述弯曲部的第一端沿所述第一方向延伸的第二条状部,所述第二条状部不增大所述薄膜晶体管的设置面积;该薄膜晶体管的沟道的形成区域包括所述弯曲部与所述第一条状部之间所夹的区域,以及所述第二条状部与所述第一条状部之间所夹的区域;
所述第一电极图形还包括与所述第一条状部的第二端相接的本体部;所述第二条状部的一端与所述本体部的一侧边缘对齐;该薄膜晶体管的沟道的形成区域还包括所述第二条状部与所述本体部之间所夹的区域;所述薄膜晶体管还包括有源层图形;所述薄膜晶体管的沟道的形成区域位于所述有源层图形的设置区域内。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述第一电极图形和所述第二电极图形上覆盖有绝缘层,所述绝缘层中形成有用于连接所述本体部的过孔。
3.根据权利要求2所述的薄膜晶体管,其特征在于,所述过孔的形状为圆形、半圆形或者方形。
4.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括栅电极图形,所述栅电极图形的设置区域包含所述沟道的形成区域。
5.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述弯曲部的形状为U形、L形或者I形。
6.一种如权利要求1至5中任意一种薄膜晶体管的制作方法,其特征在于,包括:
形成包括所述第一电极图形与所述第二电极图形的导电层。
7.一种阵列基板,其特征在于,包括设置在像素区域内的薄膜晶体管;所述薄膜晶体管为权利要求1至5中任意一项所述的薄膜晶体管。
8.一种显示装置,其特征在于,包括如权利要求7所述的阵列基板。
CN201510684583.9A 2015-10-20 2015-10-20 薄膜晶体管及其制作方法、阵列基板和显示装置 Active CN105140300B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510684583.9A CN105140300B (zh) 2015-10-20 2015-10-20 薄膜晶体管及其制作方法、阵列基板和显示装置
PCT/CN2016/098090 WO2017067338A1 (zh) 2015-10-20 2016-09-05 薄膜晶体管及其制作方法、阵列基板和显示装置
US15/501,797 US10361317B2 (en) 2015-10-20 2016-09-05 Thin film transistor and method for manufacturing the same, array substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510684583.9A CN105140300B (zh) 2015-10-20 2015-10-20 薄膜晶体管及其制作方法、阵列基板和显示装置

Publications (2)

Publication Number Publication Date
CN105140300A CN105140300A (zh) 2015-12-09
CN105140300B true CN105140300B (zh) 2019-01-18

Family

ID=54725587

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510684583.9A Active CN105140300B (zh) 2015-10-20 2015-10-20 薄膜晶体管及其制作方法、阵列基板和显示装置

Country Status (3)

Country Link
US (1) US10361317B2 (zh)
CN (1) CN105140300B (zh)
WO (1) WO2017067338A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140300B (zh) 2015-10-20 2019-01-18 重庆京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN107204375B (zh) * 2017-05-19 2019-11-26 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法
CN110620154A (zh) * 2019-08-22 2019-12-27 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、阵列基板、显示面板及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1479147A (zh) * 2002-08-27 2004-03-03 Lg.������Lcd��ʽ���� 液晶显示装置的矩阵衬底及其制作方法
US20040066483A1 (en) * 2002-10-04 2004-04-08 Lg.Philips Lcd Co., Ltd. Array substrate of liquid crystal display device and method of fabricating the same
CN103412449A (zh) * 2013-07-23 2013-11-27 合肥京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101257811B1 (ko) * 2006-06-30 2013-04-29 엘지디스플레이 주식회사 액정표시장치용 어레이 기판과 그 제조방법
CN101315950A (zh) 2007-05-30 2008-12-03 北京京东方光电科技有限公司 一种薄膜晶体管充电沟道结构
CN101354505B (zh) 2007-07-26 2010-09-15 北京京东方光电科技有限公司 具有螺旋交互源漏电极结构的液晶显示装置
CN102468231B (zh) 2010-11-10 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制造方法和有源显示器
KR101339001B1 (ko) * 2012-07-04 2013-12-09 엘지디스플레이 주식회사 액정표시장치용 어레이기판 및 제조방법
CN103178119B (zh) * 2013-03-25 2015-07-29 京东方科技集团股份有限公司 阵列基板、阵列基板制备方法以及显示装置
CN105140300B (zh) 2015-10-20 2019-01-18 重庆京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1479147A (zh) * 2002-08-27 2004-03-03 Lg.������Lcd��ʽ���� 液晶显示装置的矩阵衬底及其制作方法
US20040066483A1 (en) * 2002-10-04 2004-04-08 Lg.Philips Lcd Co., Ltd. Array substrate of liquid crystal display device and method of fabricating the same
CN103412449A (zh) * 2013-07-23 2013-11-27 合肥京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
US20180219104A1 (en) 2018-08-02
US10361317B2 (en) 2019-07-23
WO2017067338A1 (zh) 2017-04-27
CN105140300A (zh) 2015-12-09

Similar Documents

Publication Publication Date Title
US10553621B2 (en) Thin-film transistor structure and manufacturing method thereof, display panel and display device
US9651838B2 (en) Array substrate and manufacturing method thereof, display panel and display device
CN103728799B (zh) 具有最小边框的液晶显示装置
KR102007833B1 (ko) 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판
CN104813386B (zh) Tft基板
TW200703660A (en) TFT array panel, liquid crystal display including same, and method of manufacturing TFT array panel
JP2010032760A (ja) 表示装置
US20110109862A1 (en) Liquid crystal display device and method for manufacturing the same
CN102655156A (zh) 一种阵列基板及其制造方法
JP5551226B2 (ja) 液晶ディスプレイパネル及びその画素アレイ基板
CN105140300B (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN103165540A (zh) 阵列基板及其制作方法
CN104505391A (zh) 一种阵列基板及其制造方法和显示面板
TW201044086A (en) Pixel designs of improving the aperture ratio in an LCD
CN104091831A (zh) 一种薄膜晶体管、阵列基板和显示装置
CN109461731B (zh) 静电防护电路及制造方法、静电防护模块及液晶显示装置
CN110073496A (zh) 薄膜晶体管和显示设备
CN103346160A (zh) 阵列基板及其制作方法、显示装置
CN106154667A (zh) 一种阵列基板及其制作方法、显示装置
CN108490707B (zh) 阵列基板及显示面板
CN104701303B (zh) 一种显示装置、阵列基板及其制作方法
US9373646B2 (en) Polysilicon TFT device and manufacturing method thereof
CN103123428A (zh) Tft-lcd阵列基板及其制造方法
US20140078436A1 (en) Pixel structure for liquid crystal display, array substrate and liquid crystal display
CN109690661A (zh) 有源矩阵基板和具备有源矩阵基板的显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant