WO2016201610A1 - 金属氧化物薄膜晶体管及制备方法、显示面板和显示器 - Google Patents

金属氧化物薄膜晶体管及制备方法、显示面板和显示器 Download PDF

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WO2016201610A1
WO2016201610A1 PCT/CN2015/081486 CN2015081486W WO2016201610A1 WO 2016201610 A1 WO2016201610 A1 WO 2016201610A1 CN 2015081486 W CN2015081486 W CN 2015081486W WO 2016201610 A1 WO2016201610 A1 WO 2016201610A1
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layer
source
metal oxide
film transistor
transition
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PCT/CN2015/081486
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English (en)
French (fr)
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张盛东
邓伟
肖祥
贺鑫
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北京大学深圳研究生院
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Priority to PCT/CN2015/081486 priority Critical patent/WO2016201610A1/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present invention relates to the field of semiconductor device manufacturing, and in particular, to a metal oxide thin film transistor, a method of manufacturing the same, a display panel, and a display.
  • IGZO Indium Gallium Zinc Oxide
  • a-Si TFT LCD amorphous germanium thin film transistor liquid crystal display
  • IGZO TFT indium gallium zinc oxide thin film transistor
  • IGZO TFT devices have higher on-state current and smaller device size, making them more suitable for OLED (Organic Light Emitting Diode) and high resolution display;
  • IGZO A good amorphous film can be obtained under normal temperature sputtering conditions, which makes the uniformity of the IGZO TFT in the whole panel, and is more suitable for large-area display.
  • the IGZO TFT has a low preparation process temperature and can be used with existing The a-Si TFT production process is compatible with transparency in the visible light region, and has become an important material for next-generation display technology research.
  • a fatal weakness in IGZO TFTs is that IGZO is easily corroded in acid and alkaline environments, which makes the BCE structure of IGZO TFTs more difficult to achieve than in a-Si TFTs.
  • the IGZO TFT uses a metal oxide semiconductor to form an active layer (hereinafter referred to as an IGZO layer).
  • an IGZO layer a metal oxide semiconductor to form an active layer (hereinafter referred to as an IGZO layer).
  • the metal oxide thin film transistor IGZO TFT usually has a BCE (back channel etch structure) and an ESL (etch barrier structure). ) two.
  • ESL back channel etch structure
  • it also has an etch barrier layer on the metal oxide IGZO layer, and the etch barrier layer can protect the IGZO layer from being damaged when the source-drain electrodes are formed, but an additional requirement is needed in the fabrication of the etch-blocking IGZO TFT.
  • the photolithography process forms an etch barrier layer on the metal oxide semiconductor layer, thus increasing the manufacturing cost of the metal oxide IGZO TFT.
  • the BCE type IGZO TFT has no barrier layer on the IGZO layer, so it is less lithographic than the ESL type IGZO TFT, which can reduce equipment investment and provide production efficiency. Moreover, compared with the ESL structure, the BCE type IGZO TFT has high compatibility with the existing amorphous silicon process, and can greatly reduce the equipment cost brought about by the industrial upgrading. However, since the BCE type IGZO TFT has no barrier layer on the IGZO layer, the IGZO layer is easily damaged when the source/drain electrodes are formed, thereby impairing the performance of the metal oxide IGZO TFT, and thus the BCE type IGZO TFT is the largest in the preparation process. The difficulty is to achieve patterning of the source/drain regions without damaging the back channel.
  • BCE type IGZO TFTs Current source and drain etching of BCE type IGZO TFTs includes dry etching and wet etching. During the dry etching process, the plasma beam will bombard the IGZO back channel and cause damage. In the wet etching process, since the source/drain are generally made of metal, the acidic solution is generally used for etching, and the IGZO TFT is sensitive to the acid-base environment, so it is difficult to find the source/drain metal and IGZO. An etching solution with a higher selection ratio.
  • the technical problem to be solved by the present invention is that, in the process of preparing an IGZO TFT for the prior art, the source/drain region patterning process is highly susceptible to damage to the back channel, and a metal oxide thin film transistor and a preparation method thereof are provided to avoid drying.
  • the etching forms a damage to the channel region by the plasma beam of the source/drain process.
  • a metal oxide thin film transistor comprising:
  • the active layer is separated from the gate electrode by the gate dielectric layer, the active layer is made of a metal oxide semiconductor material, and the portion of the active layer aligned with the gate electrode forms a channel region;
  • a transition layer is further formed between the source/drain electrodes and the active layer, and the transition layer is a metal oxide conductor layer.
  • a method of fabricating a metal oxide thin film transistor comprising the steps of:
  • the source/drain electrode layer is etched by dry etching and stopped at the transition layer to form source/drain electrodes;
  • a transition layer other than the source/drain electrode shield portion is removed to expose the channel region.
  • introducing a high-conductivity metal oxide layer between the metal oxide semiconductor layer and the source-drain electrodes not only reduces the contact resistance of the source and drain, improves the switching characteristics of the device, but also avoids the dry etching. Damage to the channel.
  • the present invention can simplify the process of the thin film transistor by reducing the lithography process, save the manufacturing cost, and realize mass production.
  • FIG. 1 is a cross-sectional structural view of a preferred embodiment of a thin film transistor of the present invention
  • 3(a) to 3(d) are diagrams showing main process steps of another embodiment of a method for fabricating a thin film transistor of the present invention, wherein (a) is a schematic view of a process step of forming an active layer, a transition layer and a metal layer, (b) The schematic diagram of the process steps of the active layer patterning, (c) is a schematic diagram of the process steps of forming the source/drain electrodes, and (d) is a schematic diagram of the process steps for removing the excess portion of the transition layer.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the metal oxide thin film transistor of the present embodiment includes a gate electrode 110, a gate dielectric layer 120, an active layer 130, a transition layer 140, and source/drain electrodes 151.
  • the gate electrode 110 is formed on the substrate 100.
  • the gate electrode 110 is an opaque metal material such as chromium, molybdenum, titanium, copper, aluminum or molybdenum titanium alloy, and the thickness thereof is generally 100 to 300 nm.
  • the gate dielectric layer 120 is formed on the substrate 100 and covers the gate electrode 110.
  • the gate dielectric layer 120 is an insulating medium such as silicon nitride or silicon oxide, and has a thickness of 100 to 400 nm.
  • the active layer 130 is formed on the gate dielectric layer 120, the portion of the active layer aligned with the gate electrode forms a channel region, and the active layer 130 is isolated from the gate electrode 110 by the gate dielectric layer 120, and the active layer is metal oxide.
  • the semiconductor material which has a low carrier concentration in an unbiased state or a negative bias state, exhibits a high resistance state.
  • the active layer 130 is an amorphous or polycrystalline metal oxide semiconductor material (such as a zinc oxide-based or indium oxide-based thin film material) having a thickness of 30 to 200 nm, and the metal oxide semiconductor material Corrosion rate is slow in weakly acidic or weakly alkaline solutions, such as indium gallium zinc oxide (IGZO), tin oxide (SnO2), indium oxide (In2O3), cadmium indium oxide (Cd2InO4) and their doping systems Tin (SnO2: Sb), fluorine-doped tin oxide (SnO2: F), indium tin oxide (ITO), and the like.
  • IGZO indium gallium zinc oxide
  • SnO2 tin oxide
  • In2O3 indium oxide
  • Cd2InO4 cadmium indium oxide
  • Tin SnO2: Sb
  • F fluorine-doped tin oxide
  • ITO indium tin oxide
  • the source/drain electrodes 151 are distributed on both sides above the active layer 130 in isolation from each other, and the source/drain electrodes 151 are made of a metal material such as chromium, molybdenum, titanium, copper, aluminum or molybdenum titanium alloy, and the thickness of the gate electrode 6 is generally It is 100 to 300 nm.
  • the transition layer 140 is formed between the source/drain electrode 151 and the active layer 130, and the transition layer is a metal oxide conductor layer. In a preferred embodiment, the transition layer uses a metal oxide oxidizing rate higher than that of the active layer.
  • the material for example, the transition layer 140 is an amorphous or polycrystalline metal oxide having a high selectivity in an acidic or alkaline solution, such as AZO (zinc oxide aluminum), BZO (zinc oxide boron), zinc oxide (ZnO). Etc., the thickness is 100-400 nm; the material carrier concentration is very high, and it is a low-resistance material.
  • the transition layer 140 serves as a stop layer for etching in etching the source/drain electrodes 151. It serves to protect the channel region 131 from damage. At the same time, the transition layer 140 employs a highly conductive metal oxide material and thus also serves as a heavily doped layer in contact with the source/drain electrodes and the channel region, thereby reducing the contact resistance between the source/drain electrodes 151 and the channel region.
  • the present invention also provides a method for fabricating the above thin film transistor.
  • the method for preparing the thin film transistor according to the embodiment includes the following steps:
  • a gate electrode is formed on the front side of the substrate.
  • a metal conductive film of 100-300 nm thick is formed on the substrate 100, and the material thereof may be chromium, molybdenum, titanium or aluminum, and then photolithography and engraving.
  • the gate electrode 110 is formed by etching. In the present embodiment, the gate electrode 110 is deposited by magnetron sputtering.
  • the substrate 100 may be a high temperature resistant substrate such as a glass substrate or a non-high temperature resistant type such as a transparent plastic substrate.
  • a gate dielectric layer overlying the gate electrode 110 is formed over the substrate 100.
  • an insulating film covering the gate electrode 110 is formed as a gate dielectric layer 120 on the substrate 100 by plasma enhanced chemical vapor deposition, and has a thickness of 100 to 400 nm.
  • the gate dielectric layer 120 is made of a transparent insulating material, such as silicon nitride or silicon oxide. In order to make the deposition uniform to improve product performance and to reduce production costs, the gate dielectric layer 120 is formed by continuous deposition.
  • An active layer is formed on the gate dielectric layer 120.
  • a transparent metal oxide semiconductor film is continuously deposited on the gate dielectric layer 120 by magnetron sputtering, and the metal oxide semiconductor film is amorphous or polycrystalline.
  • a transparent metal oxide semiconductor material and the metal oxide semiconductor material has a slow etching rate in a weakly acidic or weakly alkaline solution, and specific materials such as indium gallium zinc oxide (IGZO), tin oxide (SnO 2 ), and indium oxide (In 2 O 3 ) Indium cadmium oxide (Cd2InO4) and its doping system are doped tin oxide (SnO2: Sb), fluorine-doped tin oxide (SnO2: F), indium tin oxide (ITO) and the like.
  • the sputtering gas pressure is between 0.1 and 2.5 Pa, the gas is a mixed gas of argon gas and oxygen gas, and may be pure argon gas.
  • the metal oxide semiconductor film may have a deposition thickness of 30 to 200
  • the active region pattern is formed by photolithography and etching of the metal oxide semiconductor thin film, and the intermediate portion of the active layer 130 is aligned with the gate electrode 110 to form the channel region 131.
  • the photoresist used is a positive photoresist with higher contrast.
  • a transition layer is formed on the gate dielectric layer and the active layer 130.
  • a metal oxide film having a high conductance (conductivity of more than 10 -4 S/m) is continuously deposited on the metal oxide semiconductor film by magnetron sputtering.
  • the metal oxide film constituting the transition layer 140 has a thickness of 10 to 20 nm and is formed by continuous deposition by magnetron sputtering using a transparent amorphous or polycrystalline metal oxide material, wherein the sputtering gas pressure is 0.1 to 0.1. Between 2.5Pa, the reaction gas is a mixture of argon and oxygen. Thought pure argon.
  • the metal oxide material used in the transition layer 140 has a high selectivity in an acidic or alkaline solution, the corrosion rate is greater than the metal oxide of the active layer 130, and the metal oxide material selected for the transition layer 140 should also be high conductance.
  • the transparent material for example, AZO (zinc oxide aluminum), BZO (zinc oxide boron), zinc oxide (ZnO), or the like is used.
  • a metal layer is deposited on the metal oxide film by magnetron sputtering as the source/drain electrode layer 150 having a thickness of 100 to 300 nm and a source/drain electrode layer 150.
  • the metal film is selected from the group consisting of chromium, molybdenum, titanium or aluminum.
  • the transition layer and the metal layer can be continuously formed on the gate dielectric layer and the active layer 130.
  • a photoresist is coated on the surface of the metal thin film of the source/drain electrode layer 150 and exposed and developed (not shown) to expose regions other than the source/drain electrodes, and then dried.
  • the metal thin film is etched to form the source/drain electrodes 151.
  • the transition layer 140 since the transition layer 140 is located between the metal thin film layer and the active layer, the transition layer 140 serves as a stop layer for dry etching in the process of forming the source/drain electrodes 151 by the photolithographic metal thin film layer, blocking The contact of the plasma beam with the channel region 131 effectively prevents damage to the channel region 131 by dry etching.
  • the transition layer 140 also serves as a blocking layer for the process step, and the protection channel region 131 is not damaged during the process of preparing the source/drain electrodes.
  • the source/drain electrode 151 is used as a mask, and the transition layer 140 is uncovered by etching with etching solution.
  • the region removal that is, removing the excess portion of the transition layer 140 from the corresponding portion of the source/drain electrode region 151, exposes the channel region 131 covered under the transition layer 140.
  • the ratio of the two is selected in the etching solution.
  • the corrosive liquid preferentially corrodes the transition layer.
  • the etching liquid is cleaned in time to avoid damage to the channel region 131.
  • the metal oxide material constituting the transition layer 140 and the metal oxide semiconductor material constituting the active layer 130 have a poor corrosion rate to the acid-base etching solution, the selection range of the etching liquid is large, and the excess portion can be removed.
  • transition layer 140 It is easier for the transition layer 140 to not corrode the channel region 131. Thus, after the source/drain electrodes 151 are prepared, it is easier to remove the excess transition layer 140, which not only protects the channel region 131 from damage, but also increases the difficulty of the entire process.
  • a passivation layer and a contact hole are formed on the surface of the thin film transistor.
  • a passivation covering the source/drain electrodes 151 and the gate dielectric layer 120 is deposited on the surface of the thin film transistor by plasma enhanced chemical vapor deposition or magnetron sputtering.
  • the passivation layer is made of a silicon nitride layer or a material such as silicon dioxide or aluminum oxide, and has a thickness of 100 to 300 nm.
  • the passivation layer is subjected to photolithography and etching treatment to form contact holes of the gate electrode 110 and the source/drain electrodes 151.
  • a layer of transparent conductive film is then formed, photolithographically and etched to form pixel electrodes and interconnected.
  • the contact between the source/drain electrodes and the metal oxide semiconductor channel region is relatively good, it is not necessary to add an ohmic contact layer like the organic semiconductor thin film transistor to lower the source/drain electrodes and the channel region.
  • an increase is made between the active layer and the source/drain electrode layer during the preparation of the thin film transistor.
  • the transition layer when the source/drain electrodes are formed, the transition layer functions to protect the channel region.
  • the portion of the transition layer exposing the source/drain electrodes is removed to expose the channel region, leaving The portion between the source/drain electrodes and the active layer corresponds to a heavily doped region, further reducing the contact resistance between the source/drain electrodes and the active layer.
  • the source and drain electrodes function as a natural mask. In this way, the cost of separately making a mask is saved, and the process steps are simplified.
  • the metal oxide layer with high conductance in the channel region is removed by etching without causing similar etching damage to the back channel.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the channel region is formed after the source and drain electrodes and the transition layer are etched.
  • the process steps for preparing the gate electrode 110 and the gate dielectric layer 120 are the same as those of the previous embodiment, and can be seen in FIGS. 2(a) to (b) and their corresponding descriptions.
  • a gate dielectric layer 120, a metal oxide semiconductor active layer 130, a metal oxide transition layer 140, and a metal source/drain electrode layer 150 are continuously formed on the gate electrode 110.
  • a transparent metal oxide semiconductor film is continuously deposited as a channel layer 130 by magnetron sputtering on the gate dielectric layer 120, and the channel layer 130 is made of an amorphous or polycrystalline transparent metal oxide semiconductor material.
  • a thin film material such as zinc oxide or indium oxide
  • the metal oxide semiconductor material has a slower rate of corrosion in a weakly acidic or weakly alkaline solution, such as indium gallium zinc oxide (IGZO), tin oxide (SnO 2 ), oxidation Indium (In2O3), cadmium indium oxide (Cd2InO4) and doping systems thereof are doped tin oxide (SnO2: Sb), fluorine-doped tin oxide (SnO2: F), indium tin oxide (ITO), and the like.
  • the thickness can be 30 to 200 nm. It has a low carrier concentration in the unbiased state or the negative bias state, exhibiting a high resistance state.
  • the metal oxide semiconductor material is continuously deposited by magnetron sputtering to form a trench
  • the channel layer 130 has a sputtering gas pressure of 0.1 to 2.5 Pa, and the reaction gas is a mixed gas of argon gas and oxygen gas, and may be pure argon gas.
  • a metal oxide film having a high conductance (conductivity greater than 10-4 S/m) and a metal film are successively deposited on the metal oxide semiconductor film by magnetron sputtering as the transition layer 140 and Source/drain electrode layer 150.
  • the transition layer 140 metal oxide film has a thickness of 10 to 20 nanometers and is formed by continuous deposition by a magnetron sputtering method using a transparent amorphous or polycrystalline metal oxide material, wherein the sputtering gas pressure is 0.1. Between -2.5 Pa, the reaction gas is a mixed gas of argon gas and oxygen gas, and may be pure argon gas.
  • the source/drain electrode layer metal film is formed by one of chromium, molybdenum, titanium or aluminum, and is formed by continuous deposition by magnetron sputtering, and has a thickness of 100 to 300 nm.
  • the metal oxide material used in the transition layer 140 has a high etching rate in an acidic or alkaline solution, and the etching rate is higher than that of the metal film of the active layer 130, and the transition layer 140 is opposite to the active layer 130 in the etching solution.
  • the transition layer 140 is made of a material such as AZO (zinc oxide aluminum), BZO (zinc oxide boron), or zinc oxide (ZnO).
  • Form an active area pattern As shown in FIG. 3(b), a portion of the metal layer corresponding to the last formed active layer pattern is coated with a photoresist coating and exposed and developed, and a first photoresist coating corresponding to the channel region is formed.
  • the thickness of 152 is smaller than the thickness of the photoresist coating of the other portion of the second photoresist coating 153, and the difference in thickness is greater than or equal to the thickness of the metal layer.
  • the source/drain electrode layer 150 and the transition layer 140 are sequentially etched, the unmasked portion is removed, and etching is continued.
  • the active layer 130 patterns the active layer 130. Among them, according to the different etching objects, the corresponding etching method should be selected.
  • the photoresist coating is etched by a plasma etching process and etched until the transition layer, wherein the thinner first photoresist 152 is completely removed and the thickness is thicker.
  • the second photoresist 153 is thinned after being removed by a certain thickness, and the remaining portion is still over the source/drain electrode layer. Since the photoresist coating over the alignment channel region is thin, the metal underneath is The layers are also etched away to form source/drain electrodes.
  • the transition layer is etched by an etching solution.
  • the acid-base etching rate of the material used in the transition layer is higher than that of the active layer using the material. The corrosion rate, so the transition layer is preferentially etched away and the channel region is exposed.
  • the photoresist used is a positive photoresist with higher contrast.
  • the selection range of the etching liquid is large, and the etching liquid is selected to be larger than the BCE type IGZO TFT. Wet etching is easier.
  • the patterning of the active layer is performed after the source/drain electrode layer is formed, continuous deposition of the gate dielectric layer, the active layer, the transition layer, and the source/drain electrode layer can be realized, and the preparation is reduced.
  • the contamination in the process can further improve the performance of the device while further reducing the cost.
  • the present invention also proposes a display panel including the above thin film transistor, and a display including the display panel.
  • the thin film transistor and the preparation method thereof, the display panel and the display provided by the invention not only avoid the damage of the active layer by the photolithography process but also serve as the heavy doping of the source and drain contacts by adding the transition layer. Layer, reducing contact resistance.
  • the dry etching forms the source-drain electrode region, which reduces the number of lithography.
  • the source/drain electrode is used as a mask to etch the transition layer, which eliminates the need for a separate mask, greatly shortens the process flow of the thin film transistor, and simplifies the process steps. Save on production costs.

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Abstract

一种金属氧化物薄膜晶体管及其制备方法。薄膜晶体管的制备方法包括步骤：在有源层（130）和源/漏电极层（150）之间制备过渡层（140），以所述过渡层为刻蚀停止层，利用干法刻蚀对源/漏电极层进行刻蚀，从而形成源/漏电极（151），移除所述源/漏电极遮蔽部分以外的过渡层以露出沟道区（131）。采用该方法，通过增加过渡层既避免了沟道区的损伤，又降低了源/漏极之间的接触电阻，简化了工艺步骤，节约了制作成本。还公开了包括该薄膜晶体管的显示面板及包括该显示面板的显示器。

Description

金属氧化物薄膜晶体管及制备方法、显示面板和显示器 技术领域
本发明涉及半导体器件制造领域，尤其涉及一种金属氧化物薄膜晶体管及其制造方法、显示面板和显示器。
背景技术
随着平板显示的进一步发展，金属氧化物薄膜晶体管得到了广泛的关注，尤以IGZO(铟镓锌氧化物)TFT为代表。在传统a-Si TFT LCD(非晶矽薄膜晶体管液晶显示屏)中，a-Si TFT的迁移率一般低于1cm2/Vs，而IGZO TFT(铟镓锌氧化物薄膜晶体管)的迁移率则较高(可以达到10cm2/Vs甚至更高)，因此IGZO TFT器件具有较高的开态电流、器件尺寸能够做的更小，使其更适用于OLED(有机发光二极管)和高分辨率显示；IGZO在常温溅射条件下能够得到很好的非晶薄膜，这使得IGZO TFT在整块面板中的均一性良好，更适用于大面积显示；另外，IGZO TFT具有制备工艺温度低、能够与现有的a-Si TFT生产工艺兼容、在可见光域透明等优点，成为下一代显示技术研究的重要材料。但IGZO TFT中一个致命的弱点就是IGZO极易在酸、碱环境中被腐蚀，这使IGZO TFT的BCE结构比a-Si TFT中更难以实现。
IGZO TFT采用金属氧化物半导体制作有源层(以下简称IGZO层)，根据制造工艺的不同，金属氧化物薄膜晶体管IGZO TFT通常有BCE(背沟道刻蚀结构)和ESL(刻蚀阻挡层结构)两种。对于ESL，其在金属氧化物IGZO层上还具有刻蚀阻挡层，刻蚀阻挡层可在形成源漏电极时保护IGZO层不被破坏，但在制造刻蚀阻挡型IGZO TFT时需要一次额外的光刻工艺以在金属氧化物半导体层上形成刻蚀阻挡层，因此增加了金属氧化物IGZO TFT的制造成本。BCE型的IGZO TFT在IGZO层上没有阻挡层，因此比ESL型的IGZO TFT少了一次光刻，可以减少设备的投资，提供生产效率。并且，与ESL结构相比，BCE型IGZO TFT与现有的非晶硅工艺具有高度的兼容性，能够大大降低产业更新换代所带来的设备成本。但由于BCE型的IGZO TFT在IGZO层上没有阻挡层，在形成源漏电极时很容易对IGZO层造成破坏，从而损害了金属氧化物IGZO TFT的性能，因此BCE型IGZO TFT制备过程中最大的困难是在不损伤背沟道的前提下实现源/漏区域的图形化。
目前BCE型IGZO TFT的源漏刻蚀包括干法刻蚀和湿法腐蚀。干法刻蚀过程中，等离子束会轰击IGZO背沟道造成损伤。采用湿法腐蚀过程中，由于源/漏极一般采用金属，因此一般采用酸性溶液进行腐蚀，而IGZO TFT对酸碱环境都十分敏感，因而难以找到对源/漏金属和IGZO 具有较高选择比的腐蚀液。
可见，现有技术中，无论采用干法刻蚀还是湿法刻蚀都难以避免对背沟道造成损伤。为避免该问题，业界又转向采用ESL型IGZO TFT，但又会导致晶体管的结构以及制作工艺的复杂性提高。
发明内容
本发明要解决的技术问题在于，针对现有技术在制备IGZO TFT工艺中，实现源/漏区图形化过程极易损伤背沟道，提供一种金属氧化物薄膜晶体管及其制备方法，避免干法刻蚀形成源/漏极过程等离子束对沟道区的损伤。
根据本发明的第一方面，在一种实施例中提供一种金属氧化物薄膜晶体管，包括：
栅电极；
通过栅介质层与栅电极隔离的有源层，有源层采用金属氧化物半导体材料，所述有源层与栅电极对准的部分形成沟道区；
相互隔离的源极和漏极；
在源/漏电极与所述有源层之间还形成有过渡层，过渡层为金属氧化物导体层。
根据本发明的第二方面，在一种实施例中提供一种金属氧化物薄膜晶体管的制备方法，包括步骤：
制备有源层、过渡层和源/漏电极层，所述过渡层在有源层和源/漏电极层之间；
利用干法刻蚀对源/漏电极层进行刻蚀并停止在过渡层，从而形成源/漏电极；
移除所述源/漏电极遮蔽部分以外的过渡层以露出沟道区。
本发明实施例中，在金属氧化物半导体层和源漏电极之间引入高电导的金属氧化物层，不仅使源漏的接触电阻降低，提高器件开关特性，而且避免了干法刻蚀对背沟道的损伤。相比沟道刻蚀阻挡型器件的制作，本发明可以通过减少一次光刻过程而简化薄膜晶体管的工艺流程，节约制作成本，可实现大规模生产。
附图说明
图1是本发明薄膜晶体管较佳实施例的剖面结构图；
图2(a)～(g)依次示出了本发明的薄膜晶体管制备方法较佳实施例的主要工艺步骤，其中(a)为形成栅电极的工艺步骤示意图，(b)为形成栅介质层的工艺步骤示意图，(c)为形成沟道区的工艺步骤示意图，(d)为形成过渡层和金属层的工艺步骤示意图，(e)为形成源/漏电极的工 艺步骤示意图，(f)去除过渡层的工艺步骤示意图，(g)为钝化层的工艺步骤示意图；
图3(a)～(d)示出了本发明薄膜晶体管制备方法另一实施例的主要工艺步骤，其中，(a)为形成有源层、过渡层和金属层的工艺步骤示意图，(b)有源层图形化的工艺步骤示意图，(c)为形成源/漏电极工艺步骤示意图，(d)为去除过渡层多余部分的工艺步骤示意图。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
请参见图1，本实施例给出的金属氧化物薄膜晶体管包括栅电极110、栅介质层120、有源层130、过渡层140和源/漏电极151。
栅电极110生成于衬底100上，本实施例中，栅电极110为不透明金属材料，如铬、钼、钛、铜、铝或钼钛合金等，其厚度一般为100～300纳米。
栅介质层120生成于衬底100上并覆盖所述栅电极110，栅介质层120为氮化硅、氧化硅等绝缘介质，其厚度为100～400纳米。
有源层130生成于所述栅介质层120上，有源层与栅电极对准的部分形成沟道区，有源层130通过栅介质层120与栅电极110隔离，有源层为金属氧化物半导体材料，其在未偏置状态或负偏置状态下载流子浓度很低，呈现高电阻状态。本实施例中，有源层130为非晶或多晶的金属氧化物半导体材料(如氧化锌基或氧化铟基的薄膜材料)，其厚度为30～200纳米，并且该金属氧化物半导体材料在弱酸性或弱碱性溶液中腐蚀速率较慢，例如氧化铟镓锌(IGZO)、氧化锡(SnO2)、氧化铟(In2O3)、氧化鎘铟(Cd2InO4)及其掺杂体系即掺锑氧化锡(SnO2:Sb)、掺氟氧化锡(SnO2:F)、氧化铟锡(ITO)等。
源/漏电极151相互隔离地分布在有源层130上方的两侧，源/漏电极151采用金属材料，如铬、钼、钛、铜、铝或钼钛合金等，栅电极6的厚度一般为100～300纳米。
过渡层140生成于源/漏电极151与有源层130之间，过渡层为金属氧化物导体层，在较优的实施例中，过渡层采用酸碱腐蚀速率高于有源层的金属氧化物材料，例如，过渡层140为在酸性或碱性溶液中具有高选择比的非晶或多晶金属氧化物，如AZO(氧化锌铝)、BZO(氧化锌硼)、氧化锌(ZnO)等，厚度为100～400纳米；其材料载流子浓度很高，为低阻材料。
过渡层140在刻蚀形成源/漏电极151的过程中作为刻蚀的停止层， 起到了保护沟道区131不受损伤的作用。同时，过渡层140采用高电导的金属氧化物材料，因而也作为源/漏电极和沟道区接触的重杂层，从而降低了源/漏电极151和沟道区之间的接触电阻。
基于上述实施例的描述，本发明还给出了上述薄膜晶体管的制备方法，本实施例给出的薄膜晶体管的制备方法包括步骤：
1.在衬底正面上生成栅电极。
具体地，如图2(a)所示，在衬底100上生b成一层100～300纳米厚的金属导电薄膜，其材料可为铬、钼、钛或铝等，再通过光刻和刻蚀形成栅电极110。本实施例中栅电极110采用磁控溅射法淀积而成。衬底100可为耐高温的衬底，如玻璃衬底，也可为非耐高温型，如透明的塑料衬底。
2.在衬底100上生成一层覆盖栅电极110的栅介质层。
具体地，如图2(b)所示，在衬底100上采用等离子增强化学汽相淀积法生成一层覆盖栅电极110的绝缘薄膜作为栅介质层120，其厚度为100～400纳米。其中，栅介质层120采用透明的绝缘材料构成，例如氮化硅、氧化硅等。为了使淀积均匀从而提高产品性能，及降低生产成本，生成栅介质层120时采用连续淀积。
3.在栅介质层120上生成有源层。
具体地，如图2(c)所示，在栅介质层120上采用磁控溅射法连续淀积一层透明的金属氧化物半导体薄膜，该金属氧化物半导体薄膜采用非晶或多晶的透明金属氧化物半导体材料，且该金属氧化物半导体材料在弱酸性或弱碱性溶液中腐蚀速率较慢，具体材料例如氧化铟镓锌(IGZO)、氧化锡(SnO2)、氧化铟(In2O3)、氧化鎘铟(Cd2InO4)及其掺杂体系即掺锑氧化锡(SnO2:Sb)、掺氟氧化锡(SnO2:F)、氧化铟锡(ITO)等。溅射气压在0.1～2.5Pa之间，气体为氩气和氧气的混合气体，也可以为纯氩气，金属氧化物半导体薄膜的淀积厚度可为30～200纳米。
在形成金属氧化物半导体薄膜后，通过光刻及刻蚀金属氧化物半导体薄膜形成有源区图形，使有源层130的中间部分与栅电极110相对准形成沟道区131。其中，为使光刻生成的图形具有较高的分辨率，所用的光刻胶为对比度较高的正性光刻胶。
4.在栅介质层和有源层130上生成过渡层。
具体地，如图2(d)所示，在金属氧化物半导体薄膜上采用可磁控溅射法连续淀积一层高电导(电导率大于10-4S/m)的金属氧化物薄膜。
构成过渡层140的金属氧化物薄膜厚度为10～20纳米，采用透明的非晶或多晶的金属氧化物材料，通过可磁控溅射法连续淀积而成，其中溅射气压在0.1～2.5Pa之间，反应气体为氩气和氧气的混合气体，也可 以为纯氩气。
过渡层140采用的金属氧化物材料在酸性或碱性溶液中具有高选择比，其腐蚀速率大于有源层130的金属氧化物，并且过渡层140选用的金属氧化物材料还应是高电导的透明材料，例如采用AZO(氧化锌铝)、BZO(氧化锌硼)、氧化锌(ZnO)等。
5.在过渡层上生成金属层。
如图2(d)所示，在金属氧化物薄膜上采用可磁控溅射法淀积一层金属层作为源/漏电极层150，其厚度为100～300纳米，源/漏电极层150的金属薄膜选用铬、钼、钛或铝等其中一种。
在优选的实施例中，可在栅介质层和有源层130上连续生成过渡层和金属层。
6.制备源/漏电极。
具体地，如图2(e)所示，在源/漏电极层150的金属薄膜表面涂光刻胶并进行曝光显影(图未示出)，露出源/漏电极以外的区域，再利用干法刻蚀金属薄膜形成源/漏电极151。
在本实施例中，由于过渡层140位于金属薄膜层和有源层之间，在光刻金属薄膜层生成源/漏电极151的过程中，过渡层140作为干法刻蚀的停止层，阻挡了等离子束与沟道区131的接触，有效的防止了干法刻蚀对沟道区131的损伤。当然，若采取其他刻蚀方式形成源/漏电极151，过渡层140同样作为该工艺步骤的阻止层，起到保护沟道区131不在制备源/漏电极的过程中受到损伤。
7.除去过渡层多余部分，露出沟道区。
具体的，如图2(f)所示，在干法刻蚀源/漏电极层150去除光刻胶以前，以源/漏电极151为掩膜，采用腐蚀液腐蚀将过渡层140未被遮盖的区域去除，即，将过渡层140与源/漏电极区151相对应部分之外的多余部分去除，使覆盖在过渡层140之下的沟道区131露出。
在本实施例中，由于过渡层采用材料的酸碱腐蚀速率高于有源层采用材料的酸碱腐蚀速率，且过渡层覆盖在沟道区之上，利用两者在腐蚀液中选择比的差异，使腐蚀液优先对过渡层进行腐蚀，在腐蚀液腐蚀过渡层140完成(即露出沟道区)后，及时清理腐蚀液，避免损伤沟道区131。同时，因为构成过渡层140的金属氧化物材料与构成有源层130的金属氧化物半导体材料存在对酸碱腐蚀液的腐蚀速率差，使得腐蚀液的选取范围大，选取既能去除多余部分的过渡层140又不会对沟道区131造成损伤的腐蚀液较为容易。这样，在源/漏电极151制备完成后，再去除多余的过渡层140较为容易，既能保护沟道区131不受损伤，又不会增加整个工艺流程的难度。
8.在薄膜晶体管的表面生成钝化层和接触孔。
具体地，如图2(g)所示，在薄膜晶体管表面，用等离子增强化学汽相淀积法或磁控溅射方法淀积一层覆盖源/漏电极151及栅介质层120的钝化层160，钝化层采用氮化硅层或二氧化硅或氧化铝等材料，其厚度为100～300纳米。
进一步地，对钝化层进行光刻和刻蚀处理，形成栅电极110、源/漏电极151的接触孔。之后再生成一层透明导电薄膜，光刻和刻蚀形成像素电极并完成互连。
对于金属氧化物薄膜晶体管，由于源/漏电极和金属氧化物半导体沟道区之间接触已比较良好，不需要再像有机半导体薄膜晶体管一样增加欧姆接触层以降低源/漏电极和沟道区之间的接触电阻，在本实施例中，为了在采用背沟道刻蚀工艺中减少对沟道区的伤害，在薄膜晶体管制备过程中，在有源层和源/漏电极层之间增加了过渡层，在形成源/漏电极时，过渡层起到了保护沟道区的作用，在形成源/漏电极后，将过渡层露出源/漏电极的部分去除以将沟道区露出，留在源/漏电极和有源层之间的部分相当于重参杂区，进一步降低了源/漏电极和有源层之间的接触电阻。
在露出沟道区时，源漏电极起了天然掩膜版的作用。此种方式，节省了另外制作掩膜版的成本，简化了工艺步骤。
位于沟道区的具有高电导的金属氧化物层通过腐蚀去除，不会对背沟道产生类似刻蚀的损伤。
实施例二：
在本发明另一实施例中，上述薄膜晶体管的制备方法中，沟道区是在源漏电极和过渡层刻蚀之后形成的。其中，制备栅电极110、栅介质层120的工艺步骤与上一实施例相同，可参见图2(a)～(b)及其对应的说明。
1.首先如图3(a)所示，在栅电极110上连续生成栅介质层120、金属氧化物半导体有源层130、金属氧化物过渡层140及金属源/漏电极层150。
具体地，在栅介质层120上采用磁控溅射法连续淀积一层透明的金属氧化物半导体薄膜作为沟道层130，沟道层130采用非晶或多晶的透明金属氧化物半导体材料，如氧化锌基或氧化铟基的薄膜材料，且该金属氧化物半导体材料在弱酸性或弱碱性溶液中腐蚀速率较慢，例如氧化铟镓锌(IGZO)、氧化锡(SnO2)、氧化铟(In2O3)、氧化鎘铟(Cd2InO4)及其掺杂体系即掺锑氧化锡(SnO2:Sb)、掺氟氧化锡(SnO2:F)、氧化铟锡(ITO)等。其厚度可为30～200纳米。其在未偏置状态或负偏置状态下载流子浓度很低，呈现高电阻状态。
较佳的，采用磁控溅射法连续淀积该金属氧化物半导体材料形成沟 道层130，其溅射气压设定在0.1～2.5Pa之间，反应气体为氩气和氧气的混合气体，也可以为纯氩气。
进一步地，在金属氧化物半导体薄膜上采用可磁控溅射法连续淀积一层高电导(电导率大于10-4S/m)的金属氧化物薄膜及一层金属薄膜分别作为过渡层140及源/漏电极层150。其中，过渡层140金属氧化物薄膜的厚度为10～20纳米，采用透明的非晶或多晶的金属氧化物材料，通过可磁控溅射法连续淀积而成，其中溅射气压在0.1～2.5Pa之间，反应气体为氩气和氧气的混合气体，也可以为纯氩气。源/漏电极层金属薄膜选用铬、钼、钛或铝等其中一种，通过磁控溅射法连续淀积形成，其厚度为100～300纳米。
更进一步地，过渡层140采用的金属氧化物材料在酸性或碱性溶液中具有高腐蚀速率，其腐蚀速率大于有源层130的金属薄膜，在腐蚀液中过渡层140相对于有源层130具有较高的选择比，过渡层140采用例如AZO(氧化锌铝)、BZO(氧化锌硼)、氧化锌(ZnO)等材料。
2.形成有源区图形。如图3(b)所示，在金属层上与最后形成的有源层图形对应的部分涂布光刻胶涂层并进行曝光显影，与沟道区对应部分的第一光刻胶涂层152的厚度小于其它部分第二光刻胶涂层153的光刻胶涂层厚度，且其厚度差大于或等于金属层的厚度。
再以第一光刻胶涂层152、第二光刻胶涂层153为掩膜，依次刻蚀源/漏电极层150、过渡层140，将其未被掩盖部分移除，并继续刻蚀有源层130，使有源层130图形化。其中，根据刻蚀对象的不同，应选取相应的刻蚀方式。
3.生成源/漏电极。如图3(c)所示，采用等离子体刻蚀工艺对光刻胶涂层进行刻蚀，一直刻蚀到过渡层，其中较薄的第一光刻胶152被完全除去，而厚度较厚的第二光刻胶153被移除一定厚度后变薄，余下的部分仍覆盖在源/漏电极层上方，由于对准沟道区上方的光刻胶涂层较薄，因此其下面的金属层也被刻蚀掉，从而形成源/漏电极。
4.腐蚀过渡层。如图3(d)以第二光刻胶涂层153和源/漏电极为掩膜，采用腐蚀液腐蚀过渡层，由于过渡层采用材料的酸碱腐蚀速率高于有源层采用材料的酸碱腐蚀速率，所以过渡层被优先腐蚀掉，并使沟道区露出。
最后移除第二光刻胶涂层153，在薄膜晶体管的表面生成钝化层并制作电极及联线，该工艺步骤与前一实施例相同，具体参见图2(g)及其相对应的说明内容，这里不再赘述。
为使光刻生成的图形具有较高的分辨率，所用的光刻胶为对比度较高的正性光刻胶。在腐蚀液腐蚀过渡层140完成后，及时清理腐蚀液，这样对有源层130就不会造成化学伤害，避免了损伤沟道区131。
因为构成过渡层140的金属氧化物材料与构成有源层130的金属氧化物半导体材料存在对酸碱腐蚀液的腐蚀速率差，使得腐蚀液的选取范围大，腐蚀液的选取比BCE型IGZO TFT的湿法腐蚀较为容易。
本实施例的制备方法中，由于有源层的图形化是在源漏电极层形成之后，因此可以实现栅介质层、有源层、过渡层和源漏电极层的连续淀积，减少了制备过程中的污染，在进一步降低成本的同时，也可以提高器件的性能。
本发明还同时提出包括上述薄膜晶体管的显示面板，和包括该显示面板的显示器。
综上，本发明提出的一种薄膜晶体管及其制备方法、显示面板和显示器，通过增加过渡层既避免了光刻过程对有源层的损伤，又充当源极、漏极接触的重掺杂层，降低接触电阻。干法刻蚀形成源漏电极区，减少了光刻次数，同时，以源/漏电极为掩膜刻蚀过渡层，无需另制掩膜极大地缩短了薄膜晶体管的工艺流程，简化了工艺步骤，节约了制作成本。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (12)

  1. 一种金属氧化物薄膜晶体管，包括：
    栅电极；
    通过栅介质层与栅电极隔离的有源层，有源层采用金属氧化物半导体材料，所述有源层与栅电极对准的部分形成沟道区；
    相互隔离的源极和漏极；其特征在于：
    源/漏电极与所述有源层之间还形成有过渡层，过渡层为金属氧化物导体层。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述过渡层采用酸碱腐蚀速率高于所述有源层的金属氧化物材料。
  3. 根据权利要求2所述的薄膜晶体管，其特征在于，所述过渡层为透明金属氧化物层。
  4. 一种金属氧化物薄膜晶体管的制备方法，其特征在于，包括步骤：
    制备有源层、过渡层和源/漏电极层，所述过渡层在有源层和源/漏电极层之间；
    利用干法刻蚀对源/漏电极层进行刻蚀并停止在过渡层，从而形成源/漏电极；
    移除所述源/漏电极遮蔽部分以外的过渡层以露出沟道区。
  5. 根据权利要求4所述的薄膜晶体管的制备方法，其特征在于，所述过渡层采用材料的酸碱腐蚀速率高于所述有源层采用材料的酸碱腐蚀速率。
  6. 根据权利要求5所述的薄膜晶体管的制备方法，其特征在于，所述有源层为透明的非晶或多晶金属氧化物半导体材料，过渡层为透明的非晶或多晶金属氧化物材料。
  7. 根据权利要求5所述的薄膜晶体管的制备方法，其特征在于，移除所述源/漏电极遮蔽部分以外的过渡层以露出沟道区包括：
    在去除源/漏电极的光刻胶之前，以刻蚀出来的源/漏电极为掩膜，采用腐蚀液腐蚀所述过渡层，使沟道区露出。
  8. 根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，在对过渡层腐蚀完后及时清理腐蚀液。
  9. 根据权利要求4-8中任一项所述的薄膜晶体管的制备方法，其 特征在于，还包括：
    在衬底上生成栅电极；
    在衬底上生成覆盖所述栅电极的栅介质层；
    制备有源层、过渡层和源/漏电极层包括：
    在所述栅介质层上生成一金属氧化物半导体层，经处理成有源层，有源层的中间部分与栅电极对准；
    在所述有源层上生成金属氧化物导电层作为过渡层；
    在所述过渡层上生成金属层作为源/漏电极层；
    利用干法刻蚀对源/漏电极层进行刻蚀包括：在金属层上涂布光刻胶层并进行曝光显影，露出源漏电极以外的区域，然后采用干法刻蚀露出源漏电极以外金属，直至刻蚀到过渡层时停止，从而形成源/漏电极。
  10. 根据权利要求4-8中任一项所述的薄膜晶体管的制备方法，其特征在于，还包括：
    在衬底上生成栅电极；
    在衬底上生成覆盖所述栅电极的栅介质层；
    制备有源层、过渡层和源/漏电极层包括：
    在栅介质层上连续生成一金属氧化物半导体层、一金属氧化物导电层和一金属层；
    在金属层上与有源层图形对应的部分涂布光刻胶涂层并进行曝光显影，与沟道区对应部分的光刻胶涂层厚度小于其它部分的光刻胶涂层厚度，且其厚度差大于或等于金属层的厚度；
    以光刻胶涂层为掩膜，依次刻蚀金属层、金属氧化物导电层和金属氧化物半导体层，从而形成源/漏电极层、过渡层和有源层图形；
    利用干法刻蚀对源/漏电极层进行刻蚀包括：在形成源/漏电极层、过渡层和有源层图形后采用干法刻蚀涂布有光刻胶涂层的金属层，直至刻蚀到过渡层时停止，从而形成源/漏电极。
  11. 一种显示面板，其特征在于包括如权利要求1-3中任一项所述的薄膜晶体管。
  12. 一种显示器，其特征在于包括如权利要求11所述的显示面板。
PCT/CN2015/081486 2015-06-15 2015-06-15 金属氧化物薄膜晶体管及制备方法、显示面板和显示器 WO2016201610A1 (zh)

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