WO2019205333A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2019205333A1
WO2019205333A1 PCT/CN2018/098025 CN2018098025W WO2019205333A1 WO 2019205333 A1 WO2019205333 A1 WO 2019205333A1 CN 2018098025 W CN2018098025 W CN 2018098025W WO 2019205333 A1 WO2019205333 A1 WO 2019205333A1
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WIPO (PCT)
Prior art keywords
layer
insulating layer
transparent electrode
interlayer insulating
array substrate
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PCT/CN2018/098025
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English (en)
French (fr)
Inventor
刘广辉
张鑫
颜源
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/086,041 priority Critical patent/US10896921B2/en
Publication of WO2019205333A1 publication Critical patent/WO2019205333A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • Low-temperature polysilicon (LTPS) display technology in LCD has high carrier mobility, which enables transistors in LCDs to achieve higher switching current ratios.
  • LTPS Low-temperature polysilicon
  • each can be reduced by The size of the thin film transistor of the pixel, increase the light transmission area of each pixel, increase the panel aperture ratio, improve the panel brightness and high resolution, reduce the panel power, and thus obtain a better visual experience.
  • in-cell touch structure Inserts a film layer with touch function into the array process of normal display. In order to meet the functions of display and touch, each layer needs to complete the mask and etch to form a certain pattern.
  • the introduction of the in-cell touch array substrate requires a 12-mask process for preparation, which increases the use of the exposure machine in the array process, thereby increasing the complexity of the array process, resulting in a reduction in the overall capacity of the array substrate, in order to reduce manufacturing costs.
  • the industry has invented nine mask processes for the preparation of array substrates.
  • Figure 1 shows a flow chart of nine mask processes, but this still does not meet the increasing demand for array substrates. Therefore, there is a need for an array substrate capable of reducing the production cost and cycle of the array substrate and a method of fabricating the same.
  • the reticle process required in the preparation process of the existing array substrate leads to a problem that the production time of the array substrate is long and the production cost is high.
  • a method for fabricating an array substrate comprises:
  • Step S10 providing a substrate, and preparing a buffer layer above the substrate
  • Step S20 preparing a polysilicon layer above the buffer layer, the polysilicon layer includes a source-drain doping region and an intermediate channel region at both ends, and a gate insulating layer and a gate are prepared on a surface of the polysilicon layer.
  • the gate is disposed on a surface of the gate insulating layer;
  • Step S30 preparing an interlayer insulating layer over the buffer layer, the interlayer insulating layer covering a surface of the buffer layer, the polysilicon layer, the gate insulating layer, and the gate;
  • Step S40 preparing a planarization layer on the surface of the interlayer insulating layer, exposing, etching, and developing the interlayer insulating layer and the planarization layer to form a first via hole and a second via hole by using a first mask.
  • the first via hole and the second via hole both penetrate the inter-insulating layer, and the gate insulating layer is in contact with the polysilicon layer;
  • Step S50 sequentially preparing a transparent electrode layer and a metal layer over the interlayer insulating layer, patterning the transparent electrode layer and the metal layer using a second mask to form a patterned first transparent electrode layer, source and drain Extreme traces and touch lines;
  • Step S60 preparing a passivation layer on the surface of the source and drain traces and the touch line, and preparing a patterned second transparent electrode layer on the surface of the passivation layer, the touch line and the The second transparent electrode layer is electrically connected.
  • the step S50 specifically includes:
  • Step S501 sequentially depositing the transparent electrode layer and the metal layer over the interlayer insulating layer, and coating a photoresist layer on a surface of the metal layer;
  • Step S502 exposing the photoresist layer by using a second mask, and then etching the photoresist layer to obtain a photoresist pattern; etching the transparent electrode layer by using a first etching process to obtain transparency An electrode pattern; etching the metal layer by a second etching process to obtain a first metal pattern, the first metal pattern comprising a target metal pattern and a metal pattern to be separated;
  • Step S503 removing the photoresist corresponding to the upper portion of the metal pattern to be removed by an ashing process, and removing the metal pattern to be removed by using the second etching process;
  • Step S504 peeling off the remaining photoresist of the photoresist layer to form the first transparent electrode layer, the source and drain traces, and the touch line.
  • the first etching process is a dry etching and the second etching process is a wet etching.
  • the target metal pattern includes the source and drain traces and the touch line.
  • the step S40 specifically includes: preparing a planarization layer on the surface of the interlayer insulating layer, exposing, etching, and developing the interlayer insulating layer and the planarization layer by using a first mask Forming a first via and a second via, and subsequently etching away the remaining planarization layer pattern; wherein the planarization layer is used as a photoresist layer of the interlayer insulating layer, the first via and the The second vias are sequentially in contact with the inter-insulating layer, and the gate insulating layer is in contact with the polysilicon layer, wherein the first via is connected to the source doping region, and the second via is The drain doped regions are connected.
  • the step S40 specifically includes: preparing a planarization layer on the surface of the interlayer insulating layer, coating a photoresist layer on the surface of the planarization layer, and insulating the interlayer by using a first mask
  • the layer and the planarization layer are exposed, etched, and developed to form a first via and a second via, and then etch away the remaining photoresist layer pattern; wherein the planarization layer and the interlayer insulating layer share a common In the reticle process, the first via and the second via sequentially pass through the interlayer insulating layer, and the gate insulating layer is in contact with the polysilicon layer, wherein the first via and the source A pole doped region is connected, and the second via is connected to the drain doping region.
  • an array substrate comprising:
  • the buffer layer being formed above the substrate
  • the polysilicon layer being formed over the buffer layer, the polysilicon layer comprising source and drain doping regions at both ends and an intermediate channel region;
  • a gate insulating layer being formed over the polysilicon layer
  • the gate being formed on a surface of the gate insulating layer
  • the source drain doped region is electrically connected, a metal layer is formed on the first transparent electrode layer, an active drain trace and a touch line are formed in the metal layer, and the source drain trace is The source and drain doping regions are electrically connected, and the touch line is electrically connected to the second transparent electrode layer.
  • the array substrate further includes a planarization layer formed on a surface of the interlayer insulating layer.
  • the first transparent electrode layer is patterned to form a pixel electrode
  • the second transparent electrode layer is patterned to form a common electrode
  • a method for fabricating an array substrate including:
  • Step S10 providing a substrate, and preparing a buffer layer above the substrate
  • Step S20 preparing a polysilicon layer above the buffer layer, the polysilicon layer includes a source-drain doping region and an intermediate channel region at both ends, and a gate insulating layer and a gate are prepared on a surface of the polysilicon layer.
  • the gate is disposed on a surface of the gate insulating layer;
  • Step S30 preparing an interlayer insulating layer over the buffer layer, the interlayer insulating layer covering a surface of the buffer layer, the polysilicon layer, the gate insulating layer, and the gate;
  • Step S40 preparing a planarization layer on the surface of the interlayer insulating layer, exposing, etching, and developing the interlayer insulating layer and the planarization layer to form a first via hole and a second via hole by using a first mask.
  • the first via hole and the second via hole both penetrate the inter-insulating layer, and the gate insulating layer is in contact with the polysilicon layer;
  • Step S50 sequentially preparing a transparent electrode layer and a metal layer over the interlayer insulating layer, patterning the transparent electrode layer and the metal layer using a second mask to form a patterned first transparent electrode layer, source and drain Extreme traces and touch lines;
  • Step S60 preparing a passivation layer on the surface of the source and drain traces and the touch line, and preparing a patterned second transparent electrode layer on the surface of the passivation layer, the touch line and the Second transparent electrode layer electrical connection
  • the first reticle is a common reticle
  • the second reticle is a halftone reticle
  • the first transparent electrode layer is patterned to form a pixel electrode
  • the second transparent electrode layer is patterned to form Common electrode.
  • the step S50 specifically includes:
  • Step S501 sequentially depositing the transparent electrode layer and the metal layer over the interlayer insulating layer, and coating a photoresist layer on a surface of the metal layer;
  • Step S502 exposing the photoresist layer by using a second mask, and then etching the photoresist layer to obtain a photoresist pattern; etching the transparent electrode layer by using a first etching process to obtain transparency An electrode pattern; etching the metal layer by a second etching process to obtain a first metal pattern, the first metal pattern comprising a target metal pattern and a metal pattern to be separated;
  • Step S503 removing the photoresist corresponding to the upper portion of the metal pattern to be removed by an ashing process, and removing the metal pattern to be removed by using the second etching process;
  • Step S504 peeling off the remaining photoresist of the photoresist layer to form the first transparent electrode layer, the source and drain traces, and the touch line.
  • the first etching process is a dry etching and the second etching process is a wet etching.
  • the target metal pattern includes the source and drain traces and the touch line.
  • the step S40 specifically includes: preparing a planarization layer on the surface of the interlayer insulating layer, exposing, etching, and developing the interlayer insulating layer and the planarization layer by using a first mask Forming a first via and a second via, and subsequently etching away the remaining planarization layer pattern; wherein the planarization layer is used as a photoresist layer of the interlayer insulating layer, the first via and the The second vias are sequentially in contact with the inter-insulating layer, and the gate insulating layer is in contact with the polysilicon layer, wherein the first via is connected to the source doping region, and the second via is The drain doped regions are connected.
  • the step S40 specifically includes: preparing a planarization layer on the surface of the interlayer insulating layer, coating a photoresist layer on the surface of the planarization layer, and insulating the interlayer by using a first mask
  • the layer and the planarization layer are exposed, etched, and developed to form a first via and a second via, and then etch away the remaining photoresist layer pattern; wherein the planarization layer and the interlayer insulating layer share a common In the reticle process, the first via and the second via sequentially pass through the interlayer insulating layer, and the gate insulating layer is in contact with the polysilicon layer, wherein the first via and the source A pole doped region is connected, and the second via is connected to the drain doping region.
  • An advantage of the present invention is to provide an array substrate and a manufacturing method thereof, which are prepared by sharing a flat mask layer and an interlayer insulating layer by a mask process, and the source and drain electrodes are made by exchanging positions of the pixel electrode and the common electrode.
  • the electrode and the touch line share a mask process, and a 7-pass lithography process is proposed to prepare the substrate with the embedded touch array, thereby shortening the production cycle of the array substrate and saving the manufacturing cost.
  • FIG. 1 is a schematic flow chart of a process of 9 masks in a method for fabricating an array substrate in the prior art
  • FIG. 2 is a schematic flow chart of a process of 7 masks in a method for fabricating an array substrate according to an embodiment of the invention
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • step S50 is a schematic flow chart of a main process in step S50 of fabricating an array substrate according to an embodiment of the present invention
  • 5a-5f are schematic structural views of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIGS. 6a-6d are schematic structural diagrams of the step S50 in the embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the invention provides a method for fabricating an array substrate in the method for fabricating an existing array substrate, which requires a large number of mask processes in the preparation process of the existing array substrate, resulting in a longer production time of the array substrate and a higher production cost.
  • This embodiment can improve the defect.
  • FIG. 2 is a schematic flow chart of a process of fabricating an array substrate in a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIGS. 5a-5f are diagrams showing an array substrate according to an embodiment of the present invention. Schematic diagram of the manufacturing method
  • the present invention provides a method for fabricating an array substrate.
  • the method for fabricating the array substrate includes:
  • step S10 providing a substrate 11, and preparing a buffer layer 13 above the substrate 11;
  • step S10 further includes preparing a light shielding layer over the substrate 11, and the buffer layer 13 covers the light shielding layer 12.
  • the material of the light shielding layer 12 is molybdenum (Mo), and the material of the buffer layer is at least one of silicon nitride and silicon oxide.
  • a polysilicon layer 14 is prepared over the buffer layer 13, and the polysilicon layer 14 includes a source doping region 141a, a drain doping region 141b, and an intermediate channel region at both ends.
  • a gate insulating layer 15 and a gate electrode 16 are formed on the surface of the polysilicon layer 14, and the gate electrode 16 is disposed on a surface of the gate insulating layer 15;
  • the source doped region 141a includes a source heavily doped region and a source lightly doped region
  • the drain doped region 141b includes a drain heavily doped region and a drain light doped region.
  • the gate insulating layer 15 is made of silicon oxide and silicon nitride, and the gate is made of molybdenum (Mo).
  • step S30 an interlayer insulating layer 17 is formed over the buffer layer 13, and the interlayer insulating layer 17 covers the buffer layer 13, the polysilicon layer 14, the gate insulating layer 15 and The surface of the gate 16.
  • the material for preparing the interlayer insulating layer 17 is at least one of silicon oxide and silicon nitride.
  • a planarization layer (labeled) is prepared on the surface of the interlayer insulating layer 17, and the interlayer insulating layer 17 and the planarization layer are exposed and etched by using a first mask.
  • Developing to form a first via 18a and a second via 18b, the first via 18a and the second via 18b sequentially extending through the planarization layer, the interlayer insulating layer 17, and the gate insulating Layer 15 is in contact with the polysilicon layer 14, and then the remaining planarization layer pattern is etched away, wherein the first via 18a is connected to the source doping region 141a, and the second via 18b is The drain doping regions 141a are connected.
  • the first reticle may be a common reticle.
  • the preparation of the interlayer insulating layer 17 and the planarization layer in the prior art requires two reticle processes, but is planarized in the embodiment of the present invention.
  • the layer is used as a photoresist layer of the interlayer insulating layer 17, and the planarization layer is etched away after exposure, etching, and development, so that the preparation of the interlayer insulating layer 17 can be completed by only one mask process, in the middle of the embodiment of the present invention.
  • the insulating layer 17 has the dual function of insulation and planarization, thereby saving a mask process relative to the prior art.
  • the planarization layer may also be retained, during the preparation of the interlayer insulating layer 17 and the planarization layer, since the first via 18a and the second via 18b are in the interlayer insulating layer 17 and planarized
  • the layers have the same pattern, so they can be prepared by only one mask process, which can save a mask process as compared with the prior art.
  • the next major A method of fabricating an array substrate without a planarization layer will be described.
  • a transparent electrode layer 19a and a metal layer 20a are sequentially prepared on the surface of the interlayer insulating layer 17, and the transparent electrode layer 19a and the metal layer 20a are exposed and etched using a second mask. And developing to form the pixel electrode 19, the source and drain traces, and the touch line 20 (the source and drain traces and the touch line are all labeled with 20).
  • FIG. 4 a schematic flowchart of the main process of the step S50 is shown in FIG. 4, and a schematic structural flow of the step S50 is shown in FIGS. 6a-6d.
  • step S50 The specific steps of the step S50 include:
  • step S501 the transparent electrode layer 19a and the metal layer 20a are sequentially deposited on the surface of the interlayer insulating layer 17, and a photoresist layer is coated on the surface of the metal layer 20a;
  • Step S502 exposing the photoresist layer by using a second mask, and then etching the photoresist layer to obtain the photoresist pattern 21a; etching the transparent electrode layer 19a by using a first etching process to Obtaining a transparent electrode pattern 19; etching the metal layer 20a by a second etching process to obtain a first metal pattern 20b, the first metal pattern 20b comprising a target metal pattern and a metal pattern to be separated (not shown);
  • step S503 the photoresist corresponding to the metal pattern to be removed is removed by an ashing process, and the metal pattern to be removed is removed by the second etching process, and the remaining photoresist is removed. Marked with 21;
  • step S504 the remaining photoresist 21 of the photoresist layer is etched away to form the first transparent electrode layer 19, the source and drain traces 20, and the touch line 20.
  • the first transparent electrode layer 19 is patterned to form a pixel electrode
  • the second transparent electrode layer 23 is patterned to form a common electrode.
  • the present invention interchanges the positions of the pixel electrode and the common electrode in the array substrate, so that the pixel electrode with the pattern is disposed under the entire common electrode, and the pixel electrode and the source can be further
  • the drain trace 20 and the touch line 20 are fabricated in the same mask process, thereby omitting a mask process.
  • the first etching process is dry etching
  • the second etching process is wet etching
  • the source and drain traces 20 and the touch line 20 are prepared in the same mask process, the second mask is a halftone mask.
  • a passivation layer 22 is prepared on the surface of the source drain trace 20 and the touch line 20, and a common electrode 23 is prepared on the surface of the passivation layer.
  • a method for fabricating an array substrate includes:
  • Step S10 providing a substrate, and preparing a buffer layer above the substrate
  • Step S20 preparing a polysilicon layer above the buffer layer, the polysilicon layer includes a source-drain doping region and an intermediate channel region at both ends, and a gate insulating layer and a gate are prepared on a surface of the polysilicon layer.
  • the gate is disposed on a surface of the gate insulating layer;
  • Step S30 preparing an interlayer insulating layer over the buffer layer, the interlayer insulating layer covering a surface of the buffer layer, the polysilicon layer, the gate insulating layer, and the gate;
  • Step S40 preparing a planarization layer on the surface of the interlayer insulating layer, coating a photoresist layer on the planarization layer, and exposing and etching the interlayer insulating layer and the planarization layer by using a first mask.
  • Step S50 sequentially preparing a transparent electrode layer and a metal layer on the surface of the planarization layer, and exposing, etching, and developing the transparent electrode layer and the metal layer using a second photomask to form a first transparent electrode layer, Source and drain traces and touch lines;
  • Step S60 preparing a passivation layer on the surface of the source and drain traces and the touch line, and preparing a second transparent electrode layer on the surface of the passivation layer.
  • step S50 specifically includes:
  • Step S501 depositing the transparent electrode layer and the metal layer on the surface of the planarization layer, and coating a photoresist layer on the surface of the metal layer;
  • Step S502 exposing the photoresist layer by using a second mask, and then etching the photoresist layer to obtain a photoresist pattern; etching the transparent electrode layer by using a first etching process to obtain transparency An electrode pattern; etching the metal layer by a second etching process to obtain a first metal pattern, the first metal pattern comprising a target metal pattern and a metal pattern to be separated;
  • Step S503 removing the photoresist corresponding to the upper portion of the metal pattern to be removed by an ashing process, and removing the metal pattern to be removed by using the second etching process;
  • Step S504 etching away the remaining photoresist of the photoresist layer to form the first transparent electrode layer, the source and drain traces, and the touch line.
  • the first etching process is dry etching
  • the second etching process is wet etching
  • the target metal pattern includes the source and drain traces and the touch line.
  • the first reticle is a common reticle
  • the second reticle is a halftone reticle
  • an array substrate is further provided. As shown in FIG. 7, the array substrate includes:
  • the buffer layer 13 is formed above the substrate 11 and covers the substrate 11;
  • the polysilicon layer 14 is formed on the surface of the buffer layer 13, the polysilicon layer 14 includes a source doped region 141a, a drain doped region 141b and an intermediate channel region 142 at both ends;
  • the gate insulating layer 15 is formed above the polysilicon layer 14;
  • the transparent electrode layer 19 is electrically connected to the source/drain doping region 141.
  • the first transparent electrode layer 19 is formed with a metal layer 20, and the active drain trace 201 and the touch line are formed in the metal layer 20.
  • the source and drain traces 201 are electrically connected to the source and drain doping regions 141 , and the touch lines 202 are electrically connected to the second transparent electrode layer 23 .
  • the array substrate further includes a planarization layer (not shown) formed on a surface of the interlayer insulating layer 17.
  • the first via 18a and the second via 18b each penetrate the planarization layer, the interlayer insulating layer 17, the gate insulating layer 15, and the polysilicon layer 14. contact.
  • the first transparent electrode layer 19 is patterned to form a pixel electrode
  • the second transparent electrode layer 23 is patterned to form a common electrode.
  • the working principle of the array substrate is the same as that of the method for fabricating the array substrate.
  • the principle of the array substrate refer to the principle of the method for fabricating the array substrate, and details are not described herein.
  • the invention provides an array substrate and a manufacturing method thereof, which are prepared by sharing a flat mask layer and an interlayer insulating layer by a mask process, and the source and drain electrodes, the pixel electrode and the touch are made by exchanging positions of the pixel electrode and the common electrode.
  • the wire is shared by a photomask process, and a 7-pass photolithography process is proposed to prepare an in-cell touch array substrate, thereby shortening the production cycle of the array substrate and saving manufacturing costs.

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Abstract

一种阵列基板的制作方法，包括：提供一基板，并在该基板上依次制备缓冲层、多晶硅层、栅绝缘层、栅极、间绝缘层、第一透明电极层、源漏极走线和触控线，其中，通过将平坦化层作为间绝缘层的光阻层以节省一道光罩制程，通过将像素电极、源漏极走线和触控线在同一光罩制程中制备又节省一道光罩工艺。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及其制作方法。
 背景技术
液晶显示器（Liquid Crystal Display，简称LCD）等平面显示装置因为具有高画质、省电、机身薄及应用范围广泛等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置的主流。
LCD中的低温多晶硅（简称LTPS）显示技术具有较高的载流子迁移率，可以使LCD中的晶体管获得更高的开关电流比，在满足要求的充电电流的条件下，可以通过缩小每个像素的薄膜晶体管的尺寸、增加每个像素透光区，提高面板开口率、改善面板亮点和高分辨率，降低面板功率，进而获得更好的视觉体验。
鉴于低温多晶硅技术的有源矩阵朝着不断缩小尺寸方向发展，随之而来的光刻技术进步导致了生产设备成本的激增。常见的导入内嵌式触控结构（In Cell Touch）是将具有触控功能的膜层穿插在正常显示的阵列制程中，为了满足显示与触控的功能同时可用，每一层都需要完成光罩、蚀刻形成一定的图案。导入内嵌式触控阵列基板需要使用12道光罩工艺进行制备，这样增加了阵列工艺中曝光机的使用，进而增加了阵列制程的复杂性，致使阵列基板整体的产能降低，为了降低制造成本，本行业内发明了9道光罩工艺进行阵列基板的制备，如图1所示为9道光罩工艺的流程图，但是这还是不能满足对阵列基板日益增加的产能的需求。因此，目前亟需一种能够降低阵列基板生产成本和周期的阵列基板及其制作方法。
 技术问题
现有阵列基板制备过程中所需光罩制程较多导致阵列基板的生产时间较长，生产成本较高的问题。
 技术解决方案
为实现上述目的，本发明提供的技术方案如下：
根据本发明的一个方面，提供了一种阵列基板的制作方法，所述阵列基板的制作方法包括：
步骤S10、提供一基板，并在所述基板上方制备缓冲层；
步骤S20、在所述缓冲层的上方制备多晶硅层，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区，在所述多晶硅层的表面制备栅绝缘层和栅极，所述栅极设置在所述栅绝缘层的表面；
步骤S30、在所述缓冲层的上方制备间绝缘层，所述间绝缘层覆盖在所述缓冲层、所述多晶硅层、所述栅绝缘层和所述栅极的表面；
步骤S40、在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，所述第一过孔和所述第二过孔均贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触；
步骤S50、在所述间绝缘层上方依次制备透明电极层和金属层，使用第二光罩图案化所述透明电极层和所述金属层，以形成图案化的第一透明电极层、源漏极走线和触控线；
步骤S60、在所述源漏极走线和所述触控线的表面制备钝化层，并在所述钝化层的表面制备图案化的第二透明电极层，所述触控线与所述第二透明电极层电连接。
根据本发明一优选实施例，所述步骤S50具体包括：
步骤S501、在所述间绝缘层上方依次沉积所述透明电极层和所述金属层，在所述金属层表面涂布光阻层；
步骤S502、采用第二光罩对所述光阻层进行曝光，进而对所述光阻层进行蚀刻，以获取光阻图案；采用第一蚀刻工艺对所述透明电极层进行蚀刻，以获得透明电极图案；采用第二蚀刻工艺对所述金属层进行蚀刻，以获得第一金属图案，所述第一金属图案包括目标金属图案和待离金属图案；
步骤S503、通过灰化工艺，除掉所述待离金属图案上方所对应的光阻，采用所述第二蚀刻工艺除掉所述待离金属图案；
步骤S504、剥离所述光阻层剩余的光阻，以形成所述第一透明电极层、所述源漏极走线和所述触控线。
根据本发明一优选实施例，所述第一蚀刻工艺为干性蚀刻，所述第二蚀刻工艺为湿性蚀刻。
根据本发明一优选实施例，所述目标金属图案包括所述源漏极走线和所述触控线。
根据本发明一优选实施例，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的平坦化层图案；其中，所述平坦化层作为所述间绝缘层的光阻层使用，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
根据本发明一优选实施例，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，在所述平坦化层表面涂布光阻层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的光阻层图案；其中，所述平坦化层和所述间绝缘层共用一道光罩工艺，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
根据本发明的另一个方面，还提供了一种阵列基板，所述阵列基板包括：
基板；
缓冲层，所述缓冲层形成在所述基板的上方；
多晶硅层，所述多晶硅层形成在所述缓冲层的上方，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区；
栅绝缘层，所述栅绝缘层形成在所述多晶硅层的上方；
栅极，所述栅极形成在所述栅绝缘层的表面；
图案化的第一透明电极层和图案化的第二电极层，以及位于所述第一透明电极层和所述第二透明电极层之间的钝化层，所述第一透明电极层与所述源漏极掺杂区电连接，所述第一透明电极层上形成有金属层，所述金属层中形成有源漏极走线和触控线，所述源漏极走线与所述源漏极掺杂区电连接，所述触控线与所述第二透明电极层电连接。
根据本发明一优选实施例，所述阵列基板还包括平坦化层，所述平坦化层形成在于所述间绝缘层的表面。
根据本发明一优选实施例，所述第一透明电极层经图案化形成像素电极，所述第二透明电极层经过图案化形成公共电极。
根据本发明的又一个方面，提供了一种阵列基板的制作方法，包括：
步骤S10、提供一基板，并在所述基板上方制备缓冲层；
步骤S20、在所述缓冲层的上方制备多晶硅层，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区，在所述多晶硅层的表面制备栅绝缘层和栅极，所述栅极设置在所述栅绝缘层的表面；
步骤S30、在所述缓冲层的上方制备间绝缘层，所述间绝缘层覆盖在所述缓冲层、所述多晶硅层、所述栅绝缘层和所述栅极的表面；
步骤S40、在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，所述第一过孔和所述第二过孔均贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触；
步骤S50、在所述间绝缘层上方依次制备透明电极层和金属层，使用第二光罩图案化所述透明电极层和所述金属层，以形成图案化的第一透明电极层、源漏极走线和触控线；
步骤S60、在所述源漏极走线和所述触控线的表面制备钝化层，并在所述钝化层的表面制备图案化的第二透明电极层，所述触控线与所述第二透明电极层电连接
其中，所述第一光罩为普通光罩，所述第二光罩为半色调光罩，所述第一透明电极层经过图案化形成像素电极，所述第二透明电极层经过图案化形成公共电极。
根据本发明一优选实施例，所述步骤S50具体包括：
步骤S501、在所述间绝缘层上方依次沉积所述透明电极层和所述金属层，在所述金属层表面涂布光阻层；
步骤S502、采用第二光罩对所述光阻层进行曝光，进而对所述光阻层进行蚀刻，以获取光阻图案；采用第一蚀刻工艺对所述透明电极层进行蚀刻，以获得透明电极图案；采用第二蚀刻工艺对所述金属层进行蚀刻，以获得第一金属图案，所述第一金属图案包括目标金属图案和待离金属图案；
步骤S503、通过灰化工艺，除掉所述待离金属图案上方所对应的光阻，采用所述第二蚀刻工艺除掉所述待离金属图案；
步骤S504、剥离所述光阻层剩余的光阻，以形成所述第一透明电极层、所述源漏极走线和所述触控线。
根据本发明一优选实施例，所述第一蚀刻工艺为干性蚀刻，所述第二蚀刻工艺为湿性蚀刻。
根据本发明一优选实施例，所述目标金属图案包括所述源漏极走线和所述触控线。
根据本发明一优选实施例，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的平坦化层图案；其中，所述平坦化层作为所述间绝缘层的光阻层使用，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
根据本发明一优选实施例，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，在所述平坦化层表面涂布光阻层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的光阻层图案；其中，所述平坦化层和所述间绝缘层共用一道光罩工艺，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
 有益效果
本发明的优点在于，提供了一种阵列基板及其制作方法，通过将平坦化层和间绝缘层共用一道光罩制程制备，通过将像素电极和公共电极位置交换位置，使源漏极、像素电极和触控线共用一道光罩制程制备，进而提出了一种7道光刻工艺技术制备具有内嵌式触控阵列基板，进而缩短了阵列基板的生产周期，节约了制作成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中阵列基板的制作方法中9道光罩制程的流程示意图；
图2为本发明实施例中阵列基板的制作方法中7道光罩制程的流程示意图；
图3为本发明实施例中阵列基板的制作方法的流程示意图；
图4为本发明实施例中阵列基板的制作方法步骤S50中主要工艺的流程示意图；
图5a-5f为本发明实施例中阵列基板的制作方法的结构示意图；
图6a-6d为本发明实施例中步骤S50的结构流程示意图;
图7为本发明实施例中阵列基板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有阵列基板的制作方法中现有阵列基板制备过程中所需光罩制程较多导致阵列基板的生产时间较长，生产成本较高的问题，提出了一种阵列基板的制作方法，本实施例能够改善该缺陷。
下面结合附图和具体实施例对本发明做进一步的说明：
图2为本发明实施例中阵列基板的制作方法中7道光罩制程的流程示意图；图3为本发明实施例中阵列基板的制作方法的流程示意图图5a-5f为本发明实施例中阵列基板的制作方法的结构示意图；
如图2、图3和图5a-5f所示，本发明提供了一种阵列基板的制作方法为实施例1，所述阵列基板的制作方法包括：
如图5a所示，步骤S10、提供一基板11，并在所述基板11上方制备缓冲层13；
在一实施例中，步骤S10还包括在基板11上方制备遮光层，所述缓冲层13覆盖遮光层12。
具体的，遮光层12的材料为钼（Mo）,所述缓冲层的材料为氮化硅和氧化硅中的至少一者。
如图5b所示，步骤S20、在所述缓冲层13的上方制备多晶硅层14，所述多晶硅层14包括位于两端的源极掺杂区141a、漏极掺杂区141b和中间的沟道区142，在所述多晶硅层14的表面制备栅绝缘层15和栅极16，所述栅极16设置在所述栅绝缘层15的表面；
具体的,所述源极掺杂区141a包括源极重掺杂区和源极轻掺杂区，所述漏极掺杂区141b包括漏极重掺杂区和漏极轻掺杂区。
所述栅绝缘层15的制备材料为氧化硅和氮化硅，所述栅极的制备材料为钼（Mo）。
如图5c所示，步骤S30、在所述缓冲层13的上方制备间绝缘层17，所述间绝缘层17覆盖在所述缓冲层13、所述多晶硅层14、所述栅绝缘层15和所述栅极16的表面。
所述间绝缘层17的制备材料为氧化硅和氮化硅中的至少一者。
如图5d所示，步骤S40、在所述间绝缘层17表面制备平坦化层（为标出），采用第一光罩对所述间绝缘层17和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔18a和第二过孔18b，所述第一过孔18a和所述第二过孔18b均依次贯穿所述平坦化层、所述间绝缘层17、所述栅绝缘层15与所述多晶硅层14接触，随后蚀刻掉剩余的平坦化层图案，其中，所述第一过孔18a与所述源极掺杂区141a连接，所述第二过孔18b与所述漏极掺杂区141a连接。
需要解释的是，所述第一光罩可以为普通光罩，现有技术中的间绝缘层17和平坦化层的制备需要采用两道光罩工艺，但是在本发明实施例中通过将平坦化层作为间绝缘层17的光阻层使用，在通过曝光、蚀刻、显影后将平坦化层蚀刻掉，使得仅通过一道光罩工艺便可以完成间绝缘层17的制备，在本发明实施例中间绝缘层17有绝缘和平坦化的双重作用，进而相对于现有工艺节省了一道光罩制程。
在另一实施例中，也可以将平坦化层保留，在进行间绝缘层17和平坦化层的制备过程中，由于第一过孔18a和第二过孔18b在间绝缘层17和平坦化层的图案相同，因此可以仅采用一道光罩工艺进行制备，进而相对现有工艺同样可以节省一道光罩制程，但是由于在本实施例中需要添加的光阻层进行制备，因此接下来主要对无平坦化层的阵列基板的制作方法进行介绍。
如图5e所示，步骤S50、在所述间绝缘层17表面依次制备透明电极层19a和金属层20a，使用第二光罩对所述透明电极层19a和所述金属层20a进行曝光、蚀刻、显影，以形成像素电极19、源漏极走线和触控线20(源漏极走线和触控线均用20进行标注)。
进一步，所述步骤S50的主要工艺的流程示意图如4所示，所述步骤S50的结构流程示意图如图6a-6d所示。
所述步骤S50的具体步骤包括：
如图6a和6b所示，步骤S501、在所述间绝缘层17表面依次沉积所述透明电极层19a和所述金属层20a，在所述金属层20a表面涂布光阻层；
步骤S502、采用第二光罩对所述光阻层进行曝光，进而对所述光阻层进行蚀刻，以获取光阻图案21a；采用第一蚀刻工艺对所述透明电极层19a进行蚀刻，以获得透明电极图案19；采用第二蚀刻工艺对所述金属层20a进行蚀刻，以获得第一金属图案20b，所述第一金属图案20b包括目标金属图案和待离金属图案(未标明)；
如图6c所示，步骤S503、通过灰化工艺，除掉所述待离金属图案上方所对应的光阻，采用所述第二蚀刻工艺除掉所述待离金属图案，剩下的光阻用21标注；
如图6d所示，步骤S504、蚀刻掉所述光阻层剩余的光阻21，以形成所述第一透明电极层19、所述源漏极走线20和所述触控线20。
具体的，所述第一透明电极层19经过图案化形成像素电极，所述第二透明电极层23经过图案化形成公共电极。
相较于现有工艺，本发明在步骤S50中，将阵列基板中像素电极和公共电极的位置互换，使得具有图案的像素电极设置在整块公共电极的下方，进而可将像素电极、源漏极走线20和触控线20在同一光罩制程中制备，从而又省略了一道光罩制程。
其中，所述第一蚀刻工艺为干性蚀刻，所述第二蚀刻工艺为湿性蚀刻。
进一步的，为了实现像素电极、源漏极走线20和触控线20在同一光罩制程中制备，所述第二光罩为半色调光罩。
如图5f所示，步骤S60、在所述源漏极走线20和所述触控线20的表面制备钝化层22，并在所述钝化层的表面制备公共电极23。
根据本发明另一实施例，还提供了一种阵列基板的制作方法为实施例2，所述阵列基板的制作方法包括：
步骤S10、提供一基板，并在所述基板上方制备缓冲层；
步骤S20、在所述缓冲层的上方制备多晶硅层，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区，在所述多晶硅层的表面制备栅绝缘层和栅极，所述栅极设置在所述栅绝缘层的表面；
步骤S30、在所述缓冲层的上方制备间绝缘层，所述间绝缘层覆盖在所述缓冲层、所述多晶硅层、所述栅绝缘层和所述栅极的表面；
步骤S40、在所述间绝缘层表面制备平坦化层，在所述平坦化层上涂布光阻层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，所述第一过孔和所述第二过孔均依次贯穿所述平坦化层、所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，随后蚀刻掉剩余的光阻层图案，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接；
步骤S50、在所述平坦化层表面依次制备透明电极层和金属层，使用第二光罩对所述透明电极层和所述金属层进行曝光、蚀刻、显影，以形成第一透明电极层、源漏极走线和触控线；
步骤S60、在所述源漏极走线和所述触控线的表面制备钝化层，并在所述钝化层的表面制备第二透明电极层。
进一步的，所述步骤S50具体包括：
步骤S501、在所述平坦化层表面依次沉积所述透明电极层和所述金属层，在所述金属层表面涂布光阻层；
步骤S502、采用第二光罩对所述光阻层进行曝光，进而对所述光阻层进行蚀刻，以获取光阻图案；采用第一蚀刻工艺对所述透明电极层进行蚀刻，以获得透明电极图案；采用第二蚀刻工艺对所述金属层进行蚀刻，以获得第一金属图案，所述第一金属图案包括目标金属图案和待离金属图案；
步骤S503、通过灰化工艺，除掉所述待离金属图案上方所对应的光阻，采用所述第二蚀刻工艺除掉所述待离金属图案；
步骤S504、蚀刻掉所述光阻层剩余的光阻，以形成所述第一透明电极层、所述源漏极走线和所述触控线。
优选的，所述第一蚀刻工艺为干性蚀刻，所述第二蚀刻工艺为湿性蚀刻。
优选的，所述目标金属图案包括所述源漏极走线和所述触控线。
其中，所述第一光罩为普通光罩，所述第二光罩为半色调光罩。
根据本发明的又一个方面，还提供了一种阵列基板，如图7所示，所述阵列基板包括：
基板11；
金属层12，所述金属层12形成在所述基板11的上方；
缓冲层13，所述缓冲层13形成在所述基板11的上方并覆盖所述基板11；
多晶硅层14，所述多晶硅层14形成在所述缓冲层13的表面，所述多晶硅层14包括位于两端的源极掺杂区141a、漏极掺杂区141b和中间的沟道区142；
栅绝缘层15，所述栅绝缘层15形成在所述多晶硅层14的上方；
栅极16，所述栅极16形成在所述栅绝缘层15的上方；
图案化的第一透明电极层19和图案化的第二电极层23，以及位于所述第一透明电极层19和所述第二透明电极层23之间的钝化层22，所述第一透明电极层19与所述源漏极掺杂区141电连接，所述第一透明电极层19上形成有金属层20，所述金属层20中形成有源漏极走线201和触控线202，所述源漏极走线201与所述源漏极掺杂区141电连接，所述触控线202与所述第二透明电极层23电连接。
根据本发明一优选实施例，所述阵列基板还包括平坦化层（未标出），所述平坦化层形成在于所述间绝缘层17的表面。
根据本发明一优选实施例，所述第一过孔18a和所述第二过孔18b均贯穿所述平坦化层、所述间绝缘层17、所述栅绝缘层15与所述多晶硅层14接触。
优选的，所述第一透明电极层19经图案化形成像素电极，所述第二透明电极层23经过图案化形成公共电极。
上述阵列基板的工作原理与所述阵列基板的制作方法原理相同，所述阵列基板的原理请参考阵列基板的制作方法的原理，具体在此不作赘述。
本发明提供了一种阵列基板及其制作方法，通过将平坦化层和间绝缘层共用一道光罩制程制备，通过将像素电极和公共电极位置交换位置，使源漏极、像素电极和触控线共用一道光罩制程制备，进而提出了一种7道光刻工艺技术制备具有内嵌式触控阵列基板，进而缩短了阵列基板的生产周期，节约了制作成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种阵列基板的制作方法，其包括：
    步骤S10、提供一基板，并在所述基板上方制备缓冲层；
    步骤S20、在所述缓冲层的上方制备多晶硅层，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区，在所述多晶硅层的表面制备栅绝缘层和栅极，所述栅极设置在所述栅绝缘层的表面；
    步骤S30、在所述缓冲层的上方制备间绝缘层，所述间绝缘层覆盖在所述缓冲层、所述多晶硅层、所述栅绝缘层和所述栅极的表面；
    步骤S40、在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，所述第一过孔和所述第二过孔均贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触；
    步骤S50、在所述间绝缘层上方依次制备透明电极层和金属层，使用第二光罩图案化所述透明电极层和所述金属层，以形成图案化的第一透明电极层、源漏极走线和触控线；
    步骤S60、在所述源漏极走线和所述触控线的表面制备钝化层，并在所述钝化层的表面制备图案化的第二透明电极层，所述触控线与所述第二透明电极层电连接。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，所述步骤S50具体包括：
    步骤S501、在所述间绝缘层上方依次沉积所述透明电极层和所述金属层，在所述金属层表面涂布光阻层；
    步骤S502、采用第二光罩对所述光阻层进行曝光，进而对所述光阻层进行蚀刻，以获取光阻图案；采用第一蚀刻工艺对所述透明电极层进行蚀刻，以获得透明电极图案；采用第二蚀刻工艺对所述金属层进行蚀刻，以获得第一金属图案，所述第一金属图案包括目标金属图案和待离金属图案；
    步骤S503、通过灰化工艺，除掉所述待离金属图案上方所对应的光阻，采用所述第二蚀刻工艺除掉所述待离金属图案；
    步骤S504、剥离所述光阻层剩余的光阻，以形成所述第一透明电极层、所述源漏极走线和所述触控线。
  3. 根据权利要求2所述的阵列基板的制作方法，其中，所述第一蚀刻工艺为干性蚀刻，所述第二蚀刻工艺为湿性蚀刻。
  4. 根据权利要求2所述的阵列基板的制作方法，其中，所述目标金属图案包括所述源漏极走线和所述触控线。
  5. 根据权利要求2所述的阵列基板的制作方法，其中，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的平坦化层图案；其中，所述平坦化层作为所述间绝缘层的光阻层使用，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
  6. 根据权利要求2所述的阵列基板的制作方法，其中，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，在所述平坦化层表面涂布光阻层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的光阻层图案；其中，所述平坦化层和所述间绝缘层共用一道光罩工艺，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
  7. 一种阵列基板的制作方法，其包括：
    步骤S10、提供一基板，并在所述基板上方制备缓冲层；
    步骤S20、在所述缓冲层的上方制备多晶硅层，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区，在所述多晶硅层的表面制备栅绝缘层和栅极，所述栅极设置在所述栅绝缘层的表面；
    步骤S30、在所述缓冲层的上方制备间绝缘层，所述间绝缘层覆盖在所述缓冲层、所述多晶硅层、所述栅绝缘层和所述栅极的表面；
    步骤S40、在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，所述第一过孔和所述第二过孔均贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触；
    步骤S50、在所述间绝缘层上方依次制备透明电极层和金属层，使用第二光罩图案化所述透明电极层和所述金属层，以形成图案化的第一透明电极层、源漏极走线和触控线；
    步骤S60、在所述源漏极走线和所述触控线的表面制备钝化层，并在所述钝化层的表面制备图案化的第二透明电极层，所述触控线与所述第二透明电极层电连接;
    其中，所述第一光罩为普通光罩，所述第二光罩为半色调光罩，所述第一透明电极层经过图案化形成像素电极，所述第二透明电极层经过图案化形成公共电极。
  8. 根据权利要求7所述的阵列基板的制作方法，其中，所述步骤S50具体包括：
    步骤S501、在所述间绝缘层上方依次沉积所述透明电极层和所述金属层，在所述金属层表面涂布光阻层；
    步骤S502、采用第二光罩对所述光阻层进行曝光，进而对所述光阻层进行蚀刻，以获取光阻图案；采用第一蚀刻工艺对所述透明电极层进行蚀刻，以获得透明电极图案；采用第二蚀刻工艺对所述金属层进行蚀刻，以获得第一金属图案，所述第一金属图案包括目标金属图案和待离金属图案；
    步骤S503、通过灰化工艺，除掉所述待离金属图案上方所对应的光阻，采用所述第二蚀刻工艺除掉所述待离金属图案；
    步骤S504、剥离所述光阻层剩余的光阻，以形成所述第一透明电极层、所述源漏极走线和所述触控线。
  9. 根据权利要求8所述的阵列基板的制作方法，其中，所述第一蚀刻工艺为干性蚀刻，所述第二蚀刻工艺为湿性蚀刻。
  10. 根据权利要求8所述的阵列基板的制作方法，其中，所述目标金属图案包括所述源漏极走线和所述触控线。
  11. 根据权利要求8所述的阵列基板的制作方法，其中，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的平坦化层图案；其中，所述平坦化层作为所述间绝缘层的光阻层使用，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
  12. 根据权利要求8所述的阵列基板的制作方法，其中，所述步骤S40具体包括：在所述间绝缘层表面制备平坦化层，在所述平坦化层表面涂布光阻层，采用第一光罩对所述间绝缘层和所述平坦化层进行曝光、蚀刻、显影以形成第一过孔和第二过孔，随后蚀掉剩余的光阻层图案；其中，所述平坦化层和所述间绝缘层共用一道光罩工艺，所述第一过孔和所述第二过孔均依次贯穿所述间绝缘层、所述栅绝缘层与所述多晶硅层接触，其中，所述第一过孔与所述源极掺杂区连接，所述第二过孔与所述漏极掺杂区连接。
  13. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    缓冲层，所述缓冲层形成在所述基板的上方；
    多晶硅层，所述多晶硅层形成在所述缓冲层的上方，所述多晶硅层包括位于两端的源漏极掺杂区和中间的沟道区；
    栅绝缘层，所述栅绝缘层形成在所述多晶硅层的上方；
    栅极，所述栅极形成在所述栅绝缘层的表面；
    图案化的第一透明电极层和图案化的第二电极层，以及位于所述第一透明电极层和所述第二透明电极层之间的钝化层，所述第一透明电极层与所述源漏极掺杂区电连接，所述第一透明电极层上形成有金属层，所述金属层中形成有源漏极走线和触控线，所述源漏极走线与所述源漏极掺杂区电连接，所述触控线与所述第二透明电极层电连接。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括平坦化层，所述平坦化层形成在于所述间绝缘层的表面。
  15. 根据权利要求14所述的阵列基板，其中，所述第一透明电极层经图案化形成像素电极，所述第二透明电极层经过图案化形成公共电极。
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CN110600381A (zh) * 2019-08-26 2019-12-20 深圳市华星光电半导体显示技术有限公司 阵列基板和阵列基板的制备方法
CN110854139B (zh) * 2019-11-26 2023-03-28 武汉华星光电技术有限公司 一种tft阵列基板、其制备方法及其显示面板
CN111063660A (zh) * 2019-12-10 2020-04-24 深圳市华星光电半导体显示技术有限公司 Oled背板的制作方法及其oled背板结构
CN111129033B (zh) * 2019-12-19 2024-01-19 武汉华星光电技术有限公司 阵列基板及其制备方法
CN113050825B (zh) * 2021-03-09 2024-03-12 昆山龙腾光电股份有限公司 触摸屏的制备方法及触摸屏

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8597427B2 (en) * 2001-11-07 2013-12-03 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
CN103681690A (zh) * 2012-09-06 2014-03-26 三星显示有限公司 薄膜晶体管基底及其制造方法
CN105336684A (zh) * 2015-10-22 2016-02-17 京东方科技集团股份有限公司 多晶硅阵列基板的制作方法、多晶硅阵列基板及显示面板
CN106601778A (zh) * 2016-12-29 2017-04-26 深圳市华星光电技术有限公司 Oled背板及其制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646966B (zh) * 2013-12-02 2016-08-31 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法、显示装置
CN104078423A (zh) * 2014-06-24 2014-10-01 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
CN106876330A (zh) * 2017-02-28 2017-06-20 上海中航光电子有限公司 一种阵列基板及其制备方法、显示面板及显示装置
CN207051870U (zh) * 2017-05-27 2018-02-27 信利光电股份有限公司 一种触摸屏以及电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8597427B2 (en) * 2001-11-07 2013-12-03 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
CN103681690A (zh) * 2012-09-06 2014-03-26 三星显示有限公司 薄膜晶体管基底及其制造方法
CN105336684A (zh) * 2015-10-22 2016-02-17 京东方科技集团股份有限公司 多晶硅阵列基板的制作方法、多晶硅阵列基板及显示面板
CN106601778A (zh) * 2016-12-29 2017-04-26 深圳市华星光电技术有限公司 Oled背板及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114281206A (zh) * 2021-12-14 2022-04-05 武汉华星光电半导体显示技术有限公司 显示面板与移动终端
CN115132656A (zh) * 2022-07-05 2022-09-30 福建华佳彩有限公司 一种避免触控金属层开孔过刻的阵列基板的制造方法

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