JP5788259B2 - 薄膜トランジスタ表示板の製造方法 - Google Patents
薄膜トランジスタ表示板の製造方法 Download PDFInfo
- Publication number
- JP5788259B2 JP5788259B2 JP2011166953A JP2011166953A JP5788259B2 JP 5788259 B2 JP5788259 B2 JP 5788259B2 JP 2011166953 A JP2011166953 A JP 2011166953A JP 2011166953 A JP2011166953 A JP 2011166953A JP 5788259 B2 JP5788259 B2 JP 5788259B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- layer
- data metal
- etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 45
- 239000010409 thin film Substances 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 101
- 239000002184 metal Substances 0.000 claims description 101
- 239000010408 film Substances 0.000 claims description 72
- 238000005530 etching Methods 0.000 claims description 55
- 239000004065 semiconductor Substances 0.000 claims description 52
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- 230000001681 protective effect Effects 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000004380 ashing Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 description 8
- 238000000635 electron micrograph Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- -1 nitric acid 2 wt% Chemical class 0.000 description 2
- RILZRCJGXSFXNE-UHFFFAOYSA-N 2-[4-(trifluoromethoxy)phenyl]ethanol Chemical compound OCCC1=CC=C(OC(F)(F)F)C=C1 RILZRCJGXSFXNE-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 159000000021 acetate salts Chemical class 0.000 description 1
- BFNBIHQBYMNNAN-UHFFFAOYSA-N ammonium sulfate Chemical compound N.N.OS(O)(=O)=O BFNBIHQBYMNNAN-UHFFFAOYSA-N 0.000 description 1
- 229910052921 ammonium sulfate Inorganic materials 0.000 description 1
- 235000011130 ammonium sulphate Nutrition 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Liquid Crystal (AREA)
Description
51 第2感光膜パターン
110 基板
121 ゲート線
154 半導体層
171 データ線
173 ソース電極
175 ドレイン電極
Claims (21)
- 絶縁基板の上にゲート電極を含むゲート線を形成する段階と、
前記ゲート線の上にゲート絶縁膜を形成する段階と、
前記ゲート絶縁膜の上に第1非晶質シリコン層、第2非晶質シリコン層、下部データ金属層、及び上部データ金属層を順次に形成する段階と、
前記上部データ金属層の上に第1部分と第1部分より厚い第2部分とを有する第1感光膜パターンを形成する段階と、
前記第1感光膜パターンをマスクとして前記上部データ金属層及び前記下部データ金属層をエッチングして、第1下部データ金属パターン及び側壁が突出した突出部を含む第1上部データ金属パターンを形成する第1エッチング段階と、
前記第1感光膜パターンをマスクとして前記第1非晶質シリコン層及び前記第2非晶質シリコン層をエッチングして、それぞれ第1非晶質シリコン層パターン及び第2非晶質シリコン層パターンを形成する第2エッチング段階と、
前記第1感光膜パターンをアッシングして第2感光膜パターンを形成する段階と、
前記第2感光膜パターンをマスクとして第1上部データ金属パターンをエッチングして、第2上部データ金属パターンを形成する第3エッチング段階と、
前記第2感光膜パターンをマスクとして前記第1下部データ金属パターン、前記第1非晶質シリコン層パターン、及び前記第2非晶質シリコン層パターンをエッチングして、半導体、オーミックコンタクト層、ソース電極を含むデータ線、及びドレイン電極を形成する第4エッチング段階と、
前記データ線、前記ドレイン電極、及び前記ゲート絶縁膜の上に保護膜を形成する段階と、
前記保護膜の上に前記ドレイン電極と接続する画素電極を形成する段階とを含む薄膜トランジスタ表示板の製造方法。 - 前記第1上部データ金属パターン及び前記第1下部データ金属パターンは、前記第1感光膜パターンに対してアンダーカットが形成される、請求項1に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターン及び前記第1下部データ金属パターンの側壁は、前記第1感光膜パターンの側壁の内側に位置する、請求項2に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの突出部は、テーパ状になっている上部と、逆テーパ状になっている下部とを含む、請求項3に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの突出部の下部の終端と前記第1下部データ金属パターンの側壁とが一致する、請求項4に記載の薄膜トランジスタ表示板の製造方法。
- 前記上部データ金属層は銅または銅合金で形成され、前記下部データ金属層はチタニウムまたはチタニウム合金で形成される、請求項5に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1エッチング段階及び前記第3エッチング段階はウェットエッチング工程を実施し、前記第2エッチング段階及び前記第4エッチング段階はドライエッチング工程を実施する、請求項6に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの突出部の下部の終端と前記第2感光膜パターンの側壁の位置が同一である、請求項7に記載の薄膜トランジスタ表示板の製造方法。
- 前記上部データ金属層は銅または銅合金で形成され、前記下部データ金属層はチタニウムまたはチタニウム合金で形成される、請求項1に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1エッチング段階及び前記第3エッチング段階はウェットエッチング工程を実施し、前記第2エッチング段階及び前記第4エッチング段階はドライエッチング工程を実施する、請求項9に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの突出部の下部の終端と前記第2感光膜パターンの側壁の位置が同一である、請求項10に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1エッチング段階及び前記第3エッチング段階はウェットエッチング工程を実施し、前記第2エッチング段階及び前記第4エッチング段階はドライエッチング工程を実施する、請求項1に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの側壁の突出部の終端と前記第2感光膜パターンの側壁の位置が同一である、請求項12に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの突出部は、テーパ状になっている上部と、逆テーパ状になっている下部とを含む、請求項1に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1上部データ金属パターンの突出部の下部の終端と前記第1下部データ金属パターンの側壁とが一致する、請求項14に記載の薄膜トランジスタ表示板の製造方法。
- 前記第1下部データ金属パターンの側壁はテーパ状になっており、前記第1上部データ金属パターンの突出部の終端の内側に位置する、請求項1に記載の薄膜トランジスタ表示板の製造方法。
- 基板の上に第1半導体層、第2半導体層、下部導電層、及び上部導電層を順次に形成する段階と、
前記上部導電層の上に第1部分と第1部分より厚い第2部分とを有する第1感光膜パターンを形成する段階と、
前記第1感光膜パターンをマスクとして前記下部導電層及び前記上部導電層をエッチングして、第1下部導電パターン及び側壁が突出した突出部を含む第1上部導電パターンを形成する第1エッチング段階と、
前記第1感光膜パターンをマスクとして前記第1半導体層及び前記第2半導体層をエッチングして、第1半導体層パターン及び第2半導体層パターンを形成する第2エッチング段階と、
前記第1感光膜パターンから第2感光膜パターンを形成する段階と、
前記第2感光膜パターンをマスクとして前記第1上部導電パターンをエッチングして、第2上部導電パターンを形成する第3エッチング段階と、
前記第2感光膜パターンをマスクとして前記第1下部導電パターン、前記第1半導体層パターン、及び前記第2半導体層パターンをエッチングする第4エッチング段階とを含む薄膜トランジスタ表示板の製造方法。 - 前記第4エッチング段階は、データ線、前記データ線から延びたソース電極、ドレイン電極、半導体、前記ソース電極、及び前記ドレイン電極と前記半導体との間に位置したオーミックコンタクト層を形成する、請求項17に記載の薄膜トランジスタ表示板の製造方法。
- 前記データ線及び前記ドレイン電極の上に保護膜を形成する段階と、
前記保護膜の上に前記ドレイン電極と接続する画素電極を形成する段階とをさらに含む、請求項18に記載の薄膜トランジスタ表示板の製造方法。 - 前記第1半導体層及び前記第2半導体層は非晶質シリコンを含む、請求項19に記載の薄膜トランジスタ表示板の製造方法。
- 前記第2感光膜パターンを形成する段階は、前記第1感光膜をアッシングする段階を含む、請求項20に記載の薄膜トランジスタ表示板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100119744A KR101750430B1 (ko) | 2010-11-29 | 2010-11-29 | 박막 트랜지스터 표시판의 제조 방법 |
KR10-2010-0119744 | 2010-11-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012119659A JP2012119659A (ja) | 2012-06-21 |
JP5788259B2 true JP5788259B2 (ja) | 2015-09-30 |
Family
ID=46092285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011166953A Active JP5788259B2 (ja) | 2010-11-29 | 2011-07-29 | 薄膜トランジスタ表示板の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8557621B2 (ja) |
JP (1) | JP5788259B2 (ja) |
KR (1) | KR101750430B1 (ja) |
CN (1) | CN102479702B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102956505B (zh) * | 2012-11-19 | 2015-06-17 | 深圳市华星光电技术有限公司 | 开关管的制作方法、阵列基板的制作方法 |
KR102050438B1 (ko) * | 2012-11-29 | 2020-01-09 | 엘지디스플레이 주식회사 | 산화물 박막 트랜지스터의 제조 방법 |
CN103730413B (zh) * | 2013-12-31 | 2016-08-17 | 合肥京东方光电科技有限公司 | 一种阵列基板的制备方法以及阵列基板、显示装置 |
KR102070148B1 (ko) * | 2018-10-24 | 2020-01-29 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 제조 방법 |
KR102596354B1 (ko) * | 2018-11-05 | 2023-10-31 | 삼성디스플레이 주식회사 | 액정 표시 장치 및 그 제조 방법 |
CN111129038A (zh) * | 2019-12-26 | 2020-05-08 | Tcl华星光电技术有限公司 | Tft阵列基板及其制作方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5198694A (en) * | 1990-10-05 | 1993-03-30 | General Electric Company | Thin film transistor structure with improved source/drain contacts |
JP2001324725A (ja) * | 2000-05-12 | 2001-11-22 | Hitachi Ltd | 液晶表示装置およびその製造方法 |
KR100415617B1 (ko) * | 2001-12-06 | 2004-01-24 | 엘지.필립스 엘시디 주식회사 | 에천트와 이를 이용한 금속배선 제조방법 및박막트랜지스터의 제조방법 |
JP3672256B2 (ja) * | 2002-08-08 | 2005-07-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | エッチング液、薄膜トランジスタ・アレイ基板、薄膜トランジスタ・アレイ基板の製造方法および表示装置 |
DE60336441D1 (de) * | 2002-09-02 | 2011-05-05 | Samsung Electronics Co Ltd | Kontaktstruktur für eine Halbleitervorrichtung, dünnschichtige Transistoranordnung mit einer solchen Kontaktstruktur und dessen Herstellungsmethode |
KR100905472B1 (ko) * | 2002-12-17 | 2009-07-02 | 삼성전자주식회사 | 박막 트랜지스터 어레이 기판 및 이를 포함하는 액정 표시장치 |
US20040224241A1 (en) * | 2003-02-03 | 2004-11-11 | Samsung Electronics Co., Ltd. | Thin film transistor array panel, manufacturing method thereof, and mask therefor |
KR101090249B1 (ko) * | 2004-10-06 | 2011-12-06 | 삼성전자주식회사 | 박막 트랜지스터 표시판의 제조 방법 |
KR20070075808A (ko) * | 2006-01-16 | 2007-07-24 | 삼성전자주식회사 | 표시 기판의 제조 방법 및 이를 이용하여 제조한 표시 기판 |
KR101235106B1 (ko) * | 2006-06-30 | 2013-02-20 | 엘지디스플레이 주식회사 | 액정표시장치용 어레이 기판과 그 제조방법 |
JP5250832B2 (ja) * | 2007-07-09 | 2013-07-31 | ゴールドチャームリミテッド | アクティブマトリクス駆動表示装置 |
KR20090096226A (ko) * | 2008-03-07 | 2009-09-10 | 삼성전자주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
KR101602252B1 (ko) * | 2008-06-27 | 2016-03-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 박막 트랜지스터, 반도체장치 및 전자기기 |
KR20110067765A (ko) * | 2009-12-15 | 2011-06-22 | 삼성전자주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
-
2010
- 2010-11-29 KR KR1020100119744A patent/KR101750430B1/ko active IP Right Grant
-
2011
- 2011-06-10 US US13/157,806 patent/US8557621B2/en active Active
- 2011-07-28 CN CN201110214106.8A patent/CN102479702B/zh active Active
- 2011-07-29 JP JP2011166953A patent/JP5788259B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
KR20120058109A (ko) | 2012-06-07 |
CN102479702A (zh) | 2012-05-30 |
US20120135555A1 (en) | 2012-05-31 |
KR101750430B1 (ko) | 2017-06-26 |
CN102479702B (zh) | 2016-03-02 |
US8557621B2 (en) | 2013-10-15 |
JP2012119659A (ja) | 2012-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4958764B2 (ja) | 液晶表示装置用アレイ基板の製造方法 | |
JP5788259B2 (ja) | 薄膜トランジスタ表示板の製造方法 | |
CN109509707B (zh) | 显示面板、阵列基板、薄膜晶体管及其制造方法 | |
CN106847704B (zh) | 对金属层表面粗糙化处理的方法、薄膜晶体管及制作方法 | |
JP2009124152A (ja) | アレイ基板及びこれの製造方法 | |
WO2017008497A1 (zh) | 氧化物薄膜晶体管的制备方法 | |
US10121901B2 (en) | Pixel structure with isolator and method for fabricating the same | |
JP5063936B2 (ja) | Tftアレイ基板の製造方法 | |
CN109494257B (zh) | 一种薄膜晶体管及其制造方法、阵列基板、显示装置 | |
JP4630420B2 (ja) | パターン形成方法 | |
WO2017140058A1 (zh) | 阵列基板及其制作方法、显示面板及显示装置 | |
US8586453B2 (en) | Methods for fabricating thin film pattern and array substrate | |
WO2015143818A1 (zh) | 阵列基板及其制造方法、显示装置 | |
CN105679775B (zh) | 一种阵列基板及其制作方法、显示面板和显示装置 | |
TWI459477B (zh) | 畫素結構及其製作方法 | |
US20200161143A1 (en) | Thin film transistor substrate, liquid crystal display panel having the same and method of manufacturing the same | |
US10497724B2 (en) | Manufacturing method of a thin film transistor and manufacturing method of an array substrate | |
CN107247376B (zh) | Tft基板的制作方法及液晶显示装置的制作方法 | |
US11637127B2 (en) | Display substrate and method for forming the same and display device | |
JP2004318076A (ja) | 横方向電場駆動液晶ディスプレイの製造方法 | |
KR100663288B1 (ko) | 박막 트랜지스터 액정표시장치의 제조방법 | |
US11469258B2 (en) | Display panel and display device | |
KR20120064998A (ko) | 기판 평탄화 방법 | |
KR101291896B1 (ko) | 표시장치용 박막트랜지스터 제조방법 | |
WO2024087174A1 (zh) | 薄膜晶体管装置及其制造方法、复合型刻蚀液及阵列基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20121213 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130325 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140527 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150120 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150122 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150304 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150630 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150729 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5788259 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |