WO2014012320A1 - 薄膜晶体管及其制作方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板、显示装置 Download PDF

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Publication number
WO2014012320A1
WO2014012320A1 PCT/CN2012/085988 CN2012085988W WO2014012320A1 WO 2014012320 A1 WO2014012320 A1 WO 2014012320A1 CN 2012085988 W CN2012085988 W CN 2012085988W WO 2014012320 A1 WO2014012320 A1 WO 2014012320A1
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Prior art keywords
layer
insulating layer
active layer
thin film
substrate
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PCT/CN2012/085988
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English (en)
French (fr)
Inventor
刘政
龙春平
任章淳
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京东方科技集团股份有限公司
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Priority to US14/124,104 priority Critical patent/US20150171224A1/en
Publication of WO2014012320A1 publication Critical patent/WO2014012320A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • the present invention relates to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • a thin film transistor is fabricated by sequentially depositing an active layer 12 , a gate insulating layer 13 , a gate electrode 14 , and an interlayer insulating layer 17 on a substrate 10 .
  • vias 16 ie, portions of the etched gate insulating layer 13 and the interlayer insulating layer 17
  • the via 16 functions to connect the active layer 12 to an external circuit by filling the via 16 with a conductive electrode material.
  • the inventors have found that at present, the gate insulating layer and the interlayer insulating layer cannot be completely uniform in thickness, and the dry etching process cannot achieve complete uniform etching, so that when the via is etched, there is The area is just etched onto the active layer, and some areas will etch away part of the active layer or leave part of the insulating layer. This inevitably results in the contact resistance of the active layer and the conductive electrode material. Uniform, even partial regions, have relatively large contact resistance, which affects the switching characteristics of display devices using thin film transistors, and the more prominent the problem is when the substrate area is larger. Summary of the invention
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, an array substrate, and a display device capable of not destroying an active layer when a via etch process forms a via hole over a source region or a drain region.
  • the present invention provides a thin film transistor including a substrate, an active layer disposed on the substrate,
  • the gate insulating layer, the gate electrode and the interlayer insulating layer further include:
  • a conductive etch barrier layer disposed on the active layer; a position of the conductive etch barrier layer corresponding to a source region and a drain region of the active layer, at a source of the active layer A via is formed over the region and the drain region, and the via does not exceed an edge of the conductive etch barrier.
  • the active layer, the gate insulating layer, the gate electrode and the interlayer insulating layer disposed on the substrate include:
  • the active layer disposed on the substrate
  • the gate insulating layer disposed on the active layer and the substrate;
  • the gate disposed on the gate insulating layer
  • the interlayer insulating layer disposed on the gate and the gate insulating layer.
  • the conductive etch barrier layer is disposed between the active layer and the gate insulating layer.
  • the thin film transistor further includes:
  • a buffer layer disposed between the substrate and the active layer.
  • the active layer, the gate insulating layer, the gate electrode and the interlayer insulating layer disposed on the substrate include:
  • the gate disposed on the substrate
  • the gate insulating layer disposed on the gate and the substrate;
  • the active layer disposed on the gate insulating layer
  • the interlayer insulating layer disposed on the active layer and the gate insulating layer.
  • the conductive etch barrier layer is disposed between the active layer and the interlayer insulating layer.
  • the conductive etch stop layer has a thickness in the range of 1500 angstroms to 3000 angstroms.
  • the present invention also provides an array substrate comprising an array of thin film transistors having any of the features described above.
  • the present invention also provides a display device comprising the above array substrate.
  • the present invention also provides a method of fabricating a thin film transistor, comprising: forming an active layer, a gate insulating layer, a gate, and an interlayer insulating layer on a substrate, and after forming the active layer, further comprising:
  • a conductive etch barrier layer on the active layer, the conductive etch barrier layer corresponding to a source region and a drain region of the active layer;
  • the method further includes:
  • Forming a conductive etch barrier layer on the active layer including:
  • the conductive etch barrier layer is formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition PECVD, low pressure chemical vapor deposition LPCVD, atmospheric pressure chemical vapor deposition APCVD or electron cyclotron resonance chemical vapor deposition ECR-CVD.
  • FIG. 1 is a schematic structural view of a prior art thin film transistor
  • FIG. 2 is a schematic view showing the structure of a thin film transistor provided by the present invention.
  • FIG. 3 is a schematic view showing another structure of a thin film transistor according to the present invention.
  • FIG. 4 is a schematic view showing a structure of a thin film transistor in a process of fabricating a thin film transistor according to the present invention
  • FIG. 5 is a schematic diagram 2 showing a structure of a thin film transistor in a process of fabricating a thin film transistor according to the present invention
  • FIG. 6 is a schematic view 3 of a thin film transistor structure in the process of fabricating a thin film transistor according to the present invention.
  • FIG. 7 is a schematic view showing a structure of a thin film transistor in a process of fabricating a thin film transistor according to the present invention.
  • FIG. 8 is a schematic diagram 5 showing a structure of a thin film transistor in a process of fabricating a thin film transistor according to the present invention.
  • FIG. 9 is a first schematic view showing the structure of another thin film transistor in the process of fabricating a thin film transistor according to the present invention.
  • FIG. 10 is a second schematic diagram showing another structure of a thin film transistor in a thin film transistor manufacturing process according to the present invention.
  • FIG. 11 is a third schematic diagram showing another structure of a thin film transistor in the process of fabricating a thin film transistor according to the present invention.
  • the thin film transistor provided by the embodiment of the invention includes a substrate, an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer disposed on the substrate, and further comprising:
  • a conductive etch barrier layer disposed on the active layer; a position of the conductive etch barrier layer corresponding to a source region and a drain region of the active layer, at a source of the active layer A via is formed over the region and the drain region, and the via does not exceed an edge of the conductive etch barrier.
  • the active layer, the gate insulating layer, the gate, and the interlayer insulating layer disposed on the substrate include:
  • the active layer disposed on the substrate
  • the gate insulating layer disposed on the active layer and the substrate;
  • the gate disposed on the gate insulating layer
  • the interlayer insulating layer disposed on the gate and the gate insulating layer.
  • the structure of a thin film transistor 1 provided by an embodiment of the present invention may include: a substrate 10, which is easy to generate metal impurities in a high temperature processing process due to a high content of metal impurities such as aluminum, barium, and sodium in the alkali glass.
  • the material of the substrate 10 may be an alkali-free glass; for example, a buffer layer 11 may be disposed on the substrate 10 for blocking diffusion of impurities contained in the substrate 10. Entering the active layer 12 to prevent influence on characteristics such as threshold voltage and leakage current of the TFT element;
  • the above-mentioned via hole does not exceed the edge of the conductive etch barrier layer, that is, the edge of the shadow projected by the via hole on the conductive etch barrier layer does not exceed the edge of the conductive etch barrier layer, in general,
  • the shape of the hole is a cylindrical shape, but the embodiment of the present invention does not limit the shape of the conductive etch barrier layer, that is, the conductive etch barrier layer may be circular or polygonal, so that the via hole does not exceed the conductive etch.
  • the edge of the barrier layer is sufficient.
  • the via hole slightly exceeds the edge of the conductive etch barrier layer, because the etching gas is not easy to control when etching the via hole, so the adaptability can be changed according to the process requirements.
  • the conductive etch stop layer can cover the source region and the drain region of the active layer as much as possible, but does not exceed the corresponding regions of the source region and the drain region, because the contact area is larger, the contact resistance is higher. Small, the better the conductivity.
  • a gate insulating layer 13 disposed on the buffer layer 11, the active layer 12, and the conductive etch barrier layer 15; a gate electrode 14 disposed on the gate insulating layer 13, the gate electrode 14 being located Above the source layer 12;
  • An interlayer insulating layer 17 is disposed on the gate electrode 14 and the gate insulating layer 13.
  • the material of the buffer layer 11 is silicon oxide and/or silicon nitride.
  • the buffer layer 11 has a thickness in the range of 500 angstroms to 4,000 angstroms.
  • the active layer, the gate insulating layer, the gate, and the interlayer insulating layer disposed on the substrate include:
  • the gate disposed on the substrate
  • the gate insulating layer disposed on the gate and the substrate;
  • the active layer disposed on the gate insulating layer
  • the interlayer insulating layer disposed on the active layer and the gate insulating layer.
  • the structure of another thin film transistor 1 provided by the embodiment of the present invention may include:
  • the substrate 10 has a high content of metal impurities such as aluminum, bismuth and sodium in the alkali glass, and the metal impurities are easily diffused in the high-temperature treatment process. Therefore, the material of the substrate 10 may be an alkali-free glass; Upper gate 14;
  • a gate insulating layer 13 disposed on the substrate 10 and the gate electrode 14;
  • An active layer 12 disposed on the gate insulating layer 13 is disposed above the gate electrode 14.
  • the active layer 12 provides a source region 120, a drain region 121, and a channel region. 122; ;
  • a conductive etch barrier layer 15 disposed on the active layer 12, the conductive etch barrier layer 15 corresponding to the source region 120 and the drain region 121 of the active layer 12, active A via hole 16 is formed over the source region 120 and the drain region 121 of the layer 12, and the via hole 16 does not exceed the edge of the conductive etch barrier layer 15;
  • An interlayer insulating layer 17 is disposed on the active layer 12, the gate insulating layer 13, and the conductive etch barrier layer 15.
  • the two thin film transistors provided in FIG. 2 and FIG. 3 differ only in that the thin film transistor of FIG. 2 is a "top gate” structure, that is, an active layer is disposed between the substrate and the gate insulating layer, and the gate electrode Formed on the gate insulating layer, the thin film transistor of FIG. 3 is a "bottom gate” structure, that is, a gate insulating layer covers the gate electrode, and an active layer is disposed on the gate insulating layer. That is to say, the method for adding a conductive etch barrier layer on the active layer proposed in the embodiment of the present invention can be applied to a thin film transistor of a "top gate” structure or a thin film transistor of a "bottom gate” structure. .
  • the active layer has a thickness in the range of 500 angstroms to 1000 angstroms.
  • the conductive etch stop layer has a thickness in the range of 1000 angstroms to 7000 angstroms, for example, the conductive etch barrier layer has a thickness in the range of 1500 angstroms to 3000 angstroms.
  • the alkali-free glass refers to a glass which can reduce shrinkage generated during heat treatment without significantly increasing the strain point.
  • the alkali-free glass is characterized by a gradient Aan-st (ppmTC) of the equilibrium density curve from a temperature range near the annealing point (Tan) to a strain point (Tst) and an average linear expansion coefficient ⁇ 50 of 50 to 350 °C.
  • the ratio of 350 ( lO-6/°C ) ( Aan-st/a50-350 ) is greater than or equal to 0 and less than 3.64.
  • the thin film transistor of the present invention includes a substrate, an active layer disposed on the substrate, a gate insulating layer, a gate electrode, and an interlayer insulating layer, further comprising a conductive etch barrier layer disposed on the active layer, wherein The position of the conductive etch barrier layer corresponds to the source and drain regions of the active layer.
  • the via etch process forms a via hole over the source region and the drain region, the via hole does not exceed the conductive etch barrier layer. the edge of.
  • the via etching process is used to engrave the corresponding region above the source and the drain of the active layer.
  • the etching gas is difficult to etch the conductive etch barrier layer, and the via hole does not damage the active layer, thereby avoiding the prior art.
  • the active layer is etched away or not etched to the active layer, resulting in a non-uniform contact resistance between the active layer and the conductive electrode material.
  • the embodiment of the invention provides a method for fabricating a thin film transistor, comprising: forming an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer on a substrate, and after forming the active layer, further comprising:
  • a conductive etch barrier layer on the active layer, the conductive etch barrier layer corresponding to a source region and a drain region of the active layer;
  • the method further includes:
  • a via hole is formed over the source region and the drain region of the active layer by a via etching process, the via hole not exceeding an edge of the conductive etch barrier layer.
  • the active layer, the gate insulating layer, the gate electrode and the interlayer insulating layer are formed on the substrate, including:
  • the interlayer insulating layer is formed on the gate and the gate insulating layer.
  • the manufacturing method of the thin film transistor includes:
  • the substrate may be an alkali-free glass, because the alkali metal has high content of metal impurities such as aluminum, bismuth and sodium, and it is easy to diffuse metal impurities in the high-temperature treatment process.
  • metal impurities such as aluminum, bismuth and sodium
  • a buffer layer 11 is formed by a plasma enhanced chemical vapor deposition (PECVD) method to block diffusion of impurities contained in the substrate 10 into an active source. In the layer, it is prevented from affecting characteristics such as a threshold voltage and a leakage current of the TFT element.
  • the method of forming the buffer layer 11 on the substrate 10 may further include Low Pressure Chemical Vapor Deposition (LPCVD) and Atmospheric Pressure Chemical Vapor Deposition (Atmospheric Pressure Chemical Vapor Deposition, APCVD), Electron Cyclotron Resonance-Chemical Vapor Deposition (ECR-CVD) or sputtering.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • APCVD Atmospheric Pressure Chemical Vapor Deposition
  • ECR-CVD Electron Cyclotron Resonance-Chemical Vapor Deposition
  • the material of the buffer layer 11 is silicon oxide and/or silicon nitride, that is, the buffer layer 11 may be a single layer of silicon oxide, silicon nitride or a laminate of the two.
  • the thickness of the buffer layer 11 may be 300 angstroms to 10,000 angstroms, for example, the thickness of the buffer layer 11 is in the range of 500 angstroms to 4000 angstroms, and the temperature of the deposition buffer layer 11 is not more than 600 ° C. That is, the deposition temperature is 600 ° C or lower.
  • the buffer layer 11 may not be provided.
  • a buffer layer 11 is disposed on the substrate 10 for blocking diffusion of impurities contained in the substrate 10 into the active layer 12 to prevent threshold voltage and leakage of the TFT element. Characteristics such as current have an effect.
  • a method of forming an active layer on a buffer layer may include:
  • an amorphous silicon film is deposited on the buffer layer 11 by PECVD, LPCVD or sputtering, and the amorphous silicon film is patterned to form the active layer 12, specifically, in the buffer layer 11.
  • a deposition is performed thereon, and a mask is formed by a photolithography process, and then a pattern is formed by a dry etching process to form the active layer 12 at a deposition temperature of not more than 600 °C. It is also possible to use PECVD on the buffer layer 11,
  • a microcrystalline silicon film or the like is deposited by LPCVD or a sputtering method, and a microcrystalline silicon film or the like is patterned to form an active layer 12.
  • a conductive etch stop layer is formed on the source 120 and the drain 121 of the active layer 12.
  • the method of forming the conductive etch stop layer 15 may include depositing a conductive material on the source region 120 and the drain region 121 of the active layer 12 by sputtering to form a conductive etch barrier layer 15, the conductive material. It may be a metal, a metal alloy or a conductive metal oxide, for example, molybdenum, molybdenum alloy or indium gallium oxide (IGZO).
  • the thickness of the conductive etch barrier layer 15 may range from 1000 angstroms to 7000 angstroms, for example, The thickness of the conductive etch barrier layer 15 may range from 1500 angstroms to 3,000 angstroms Inside.
  • Depositing the conductive material to form the conductive etch stop layer 15 may also include methods such as thermal evaporation, PECVD, LPCVD, APCVD, or ECR-CVD.
  • a gate insulating layer and a gate on the active layer, the buffer layer, and the conductive etch barrier layer.
  • a gate insulating layer 13 is formed on the active layer 12, the buffer layer 11, and the conductive etch barrier layer 15 by PECVD, LPCVD, APCVD, or ECR-CVD, etc., using sputtering, heat.
  • PECVD, LPCVD, APCVD, ECR-CVD, etc. deposit a gate film on the gate insulating layer 13, and use a wet etching or dry etching method to form a mask by photolithography to form a gate.
  • Extreme 14 deposit a gate insulating layer and a gate on the active layer, the buffer layer, and the conductive etch barrier layer.
  • the thickness of the gate insulating layer 13 may be in the range of 300 angstroms to 3000 angstroms, and a suitable thickness may be selected according to specific process requirements, which is not limited by the present invention.
  • the material of the gate insulating layer 13 may be a single layer of silicon oxide, silicon nitride or a combination of the two, and the temperature of the deposited gate insulating layer 13 may be below 600 ° C; the material of the gate 14 may be made of metal or metal alloy. It is composed of a conductive material such as molybdenum or molybdenum alloy or doped polysilicon.
  • the thickness of the gate electrode 14 may range from 1000 angstroms to 8000 angstroms. For example, the thickness of the gate electrode 14 may range from 2500 angstroms to 4,000 angstroms.
  • an interlayer insulating layer 17 may be formed on the gate electrode 14 and the gate insulating layer 13 by a method such as PECVD, LPCVD, APCVD, or ECR-CVD at a deposition temperature of 600 ° C or less.
  • the interlayer insulating layer 17 may be composed of a single layer of silicon oxide or a laminate of silicon oxide and silicon nitride.
  • the via hole does not exceed an edge of the conductive etch barrier layer.
  • a via process may be selected on the corresponding conductive etch barrier layer on the source region and the drain region, which is more advantageous for controlling the size and depth of the via.
  • a photoresist is coated on the interlayer insulating layer 17 as a mask, wherein the thickness of the photoresist may be in the range of 10,000 angstroms to 20,000 angstroms, and dry etching is performed in the source region. 120, a via hole 16 is formed above the drain region 121, wherein the dry etching may be performed by plasma etching, reactive ion etching, inductively coupled plasma etching, etc., and the etching gas may be selected from fluorine and chlorine. Such as CF 4 , CHF 3 , SF 6 , CC1 2 F 2 , etc. or a mixture of these gases and 0 2 .
  • the etching rate of the etching gas to the conductive etching barrier layer 15 is very slow (the etching amount is negligible), so that when the via etching is performed, When the etching process forms the via hole 16 over the source region 120 and the drain region 121, the via hole 16 does not exceed
  • electrically etching the barrier layer 15 it is possible to avoid the occurrence of the portion of the active layer 12 being etched away or the portion of the gate insulating layer remaining due to the unevenness of the gate insulating layer 13 and/or the interlayer insulating layer 17.
  • the active layer, the gate insulating layer, the gate electrode and the interlayer insulating layer are formed on the substrate, including:
  • the interlayer insulating layer is formed on the active layer and the gate insulating layer.
  • the manufacturing method of the thin film transistor includes:
  • the substrate may be an alkali-free glass, because the alkali metal has high content of metal impurities such as aluminum, bismuth and sodium, and it is easy to diffuse metal impurities in the high-temperature treatment process.
  • metal impurities such as aluminum, bismuth and sodium
  • a thin film transistor having a "bottom gate” structure is formed.
  • a gate electrode 14 is formed on the substrate 10, and a gate insulating layer 13 is formed on the substrate 10 and the gate electrode 14, and a gate insulating layer 13 and a gate are formed.
  • the method of the pole 14 is similar to the method of forming the gate insulating layer 13 and the gate electrode 14 in the thin film transistor of the "top gate” structure, and will not be described herein.
  • the method of forming the active layer 12 in the thin film transistor in which the "top gate” structure is formed is as shown in the figure.
  • an active layer 12 is formed on the gate insulating layer 13.
  • a conductive etch stop layer 15 is formed on the source region 120 and the drain region 121 of the active layer 12, and details are not described herein.
  • an interlayer insulating layer 17 may be formed on the active layer 12 and the conductive etch barrier layer 15 at a deposition temperature of 600 ° C or lower by a method such as PECVD, LPCVD, APCVD, or ECR-CVD.
  • the interlayer insulating layer 17 may be composed of a single layer of silicon oxide or a laminate of silicon oxide and silicon nitride. S206, using a via etching process to form a via hole above the source region and the drain region.
  • the via hole does not exceed an edge of the conductive etch barrier layer.
  • a via process may be selected on the corresponding conductive etch barrier layer on the source region and the drain region, which is more advantageous for controlling the size and depth of the via.
  • a photoresist is coated on the interlayer insulating layer 17 as a mask, wherein the thickness of the photoresist may be in the range of 10,000 angstroms to 20,000 angstroms, and dry etching is performed in the source region. 120, a via hole 16 is formed above the drain region 121, wherein the dry etching may be performed by plasma etching, reactive ion etching, inductively coupled plasma etching, etc., and the etching gas may be selected from fluorine and chlorine. Such as CF 4 , CHF 3 , SF 6 , CC1 2 F 2 , etc. or a mixture of these gases and 0 2 .
  • the etching gas etches the conductive etch barrier layer 15 very slowly (the etching amount is negligible), so that when the via etching When the via 16 is formed over the source region 120 and the drain region 121, the via 16 does not exceed the conductive etch barrier layer 15 to avoid the occurrence of unevenness of the interlayer insulating layer 17, resulting in the active layer 12. A portion that is etched away, or a portion of the interlayer insulating layer remains.
  • the method for fabricating a thin film transistor comprises: forming an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer on a substrate, and forming a conductive etching barrier layer on the active layer, the conductive etching barrier layer The position corresponds to the source region and the drain region of the active layer.
  • the via etching process forms a via hole over the source region and the drain region, the via hole does not exceed the edge of the conductive etch barrier layer.
  • the via etch process is used to correspond to the source region and the drain region of the active layer.
  • the region etches the via hole ie, etches the gate insulating layer and a portion of the interlayer insulating layer
  • the embodiment of the present invention provides an array substrate including an array of thin film transistors having any of the features described in the above embodiments.
  • the thin film transistors are identical to the above embodiments, and are not described herein again.
  • Embodiments of the present invention provide a display device having an array substrate of any of the features described in the above embodiments.
  • the display device may be a liquid crystal display device, including a color film substrate disposed in parallel And the array substrate provided in the above embodiment, and the liquid crystal filled between the color filter substrate and the array substrate; the display device may also be an OLED display device, including the array substrate proposed in the above embodiment, and evaporating An organic light-emitting material and a package cover on the array substrate.
  • the liquid crystal display device provided by the embodiment of the present invention may be a product having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer, and the invention is not limited.
  • a thin film transistor comprising a substrate, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer disposed on the substrate, further comprising:
  • a conductive etch barrier layer disposed on the active layer; a position of the conductive etch barrier layer corresponding to a source region and a drain region of the active layer, at a source of the active layer A via is formed over the region and the drain region, and the via does not exceed an edge of the conductive etch barrier.
  • the active layer disposed on the substrate
  • the gate insulating layer disposed on the active layer and the substrate;
  • the gate disposed on the gate insulating layer
  • the interlayer insulating layer disposed on the gate and the gate insulating layer.
  • the thin film transistor according to any one of (1) to (4), wherein the active layer, the gate insulating layer, the gate electrode, and the interlayer insulating layer disposed on the substrate include:
  • the gate disposed on the substrate
  • the gate insulating layer disposed on the gate and the substrate;
  • the active layer disposed on the gate insulating layer
  • the interlayer insulating layer disposed on the active layer and the gate insulating layer.
  • a display device comprising the array substrate according to (8).
  • (10) a method of fabricating a thin film transistor, comprising: forming an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer on a substrate, wherein
  • the method further includes:
  • a conductive etch barrier layer on the active layer, the conductive etch barrier layer corresponding to a source region and a drain region of the active layer;
  • the method further includes:
  • a via hole is formed over the source region and the drain region of the active layer by a via etching process, the via hole not exceeding an edge of the conductive etch barrier layer.
  • the conductive etch barrier layer is formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.

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Abstract

提供薄膜晶体管及其制作方法、阵列基板、显示装置，涉及显示技术领域，能够当过孔刻蚀工艺在源极区（120）、漏极区（121）上方形成过孔（16）时，不破坏有源层（12）。薄膜晶体管（1），包括基板（10）、设置于所述基板（10）上的有源层（12）、栅绝缘层（13）、栅极（14）以及层间绝缘层（17），还包括：设置于所述有源层（12）上的导电刻蚀阻挡层（15）；所述导电刻蚀阻挡层（15）的位置与所述有源层（12）的源极区（120）、漏极区（121）相对应，在所述有源层（12）的源极区（120）、漏极区（121）上方形成有过孔（16），且该过孔（16）不超过所述导电刻蚀阻挡层（15）的边缘。

Description

薄膜晶体管及其制作方法、 阵列基板、 显示装置 技术领域
本发明涉及薄膜晶体管及其制作方法、 阵列基板、 显示装置。 背景技术
随着科技的不断进步，用户对液晶显示设备的需求日益增加， TFT-LCD ( Thin Film Transistor-Liquid Crystal Display, 薄膜晶体管液晶显示器）也成 为了手机、 平板电脑等产品中使用的主流显示器。 此外， 随着显示设备的普 及， 用户对高色彩质量、 高对比度、 高可视角度、 高响应速度以及低功耗的 需求越来越普遍， OLED ( Organic Light-Emitting Diode, 有机发光二极管） 显示器也开始逐渐进入用户的视野。
如图 1所示，现有技术中，薄膜晶体管的一种制作方法为在基板 10上依 次沉积有源层 12、栅绝缘层 13、栅极 14以及层间绝缘层 17之后， 釆用过孔 刻蚀工艺，在有源层 12的源极 120、漏极 121上方的对应区域刻蚀出过孔 16 (即刻蚀栅绝缘层 13、 层间绝缘层 17的部分区域）。 其中， 过孔 16的作用 是,通过在过孔 16中填充导电电极材料来实现有源层 12与外界电路的连接。
但是， 发明人发现， 目前栅绝缘层、 层间绝缘层都无法做到厚度完全均 匀， 而且干法刻蚀工艺也无法做到完全均匀性的刻蚀， 从而在刻蚀过孔时， 存在有的区域刚好刻蚀至有源层之上， 有的区域会将有源层刻蚀掉一部分或 者残留部分绝缘层的现象， 这必然导致的结果是， 有源层与导电电极材料的 接触电阻不均匀， 甚至部分区域的接触电阻相当大， 这影响到了使用薄膜晶 体管的显示器件的开关特性， 并且， 当基板面积越大时， 这种问题越突出。 发明内容
本发明的实施例提供一种薄膜晶体管及其制作方法、 阵列基板、 显示装 置， 能够当过孔刻蚀工艺在源极区、 漏极区上方形成过孔时， 不破坏有源层。
本发明的实施例釆用如下技术方案：
本发明提供一种薄膜晶体管， 包括基板， 设置于所述基板上的有源层、 栅绝缘层、 栅极以及层间绝缘层， 还包括：
设置于所述有源层上的导电刻蚀阻挡层； 所述导电刻蚀阻挡层的位置与 所述有源层的源极区、 漏极区相对应， 在所述有源层的源极区、 漏极区上方 形成有过孔， 且该过孔不超过所述导电刻蚀阻挡层的边缘。
所述设置于所述基板上的有源层、 栅绝缘层、 栅极以及层间绝缘层， 包 括：
设置于所述基板上的所述有源层；
设置于所述有源层和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述栅极；
设置于所述栅极和栅绝缘层上的所述层间绝缘层。
所述导电刻蚀阻挡层设置于所述有源层与所述栅绝缘层之间。
薄膜晶体管还包括：
设置于所述基板与所述有源层之间的緩冲层。
所述设置于所述基板上的有源层、 栅绝缘层、 栅极以及层间绝缘层， 包 括：
设置于所述基板上的所述栅极；
设置于所述栅极和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述有源层；
设置于所述有源层和栅绝缘层上的所述层间绝缘层。
所述导电刻蚀阻挡层设置于所述有源层与所述层间绝缘层之间。
所述导电刻蚀阻挡层的厚度在 1500埃至 3000埃的范围内。
本发明还提供一种阵列基板， 包括阵列形成的具有上述任意特征的薄膜 晶体管。
本发明还提供一种显示装置， 包括上述的阵列基板。
本发明还提供一种薄膜晶体管的制作方法， 包括在基板上形成有源层、 栅绝缘层、 栅极以及层间绝缘层， 在形成所述有源层后， 还包括：
在所述有源层上形成导电刻蚀阻挡层 , 所述导电刻蚀阻挡层的位置与所 述有源层的源极区、 漏极区相对应；
在形成所述层间绝缘层后， 还包括：
利用过孔刻蚀工艺在所述有源层的源极区、 漏极区上方形成过孔， 所述 过孔不超过所述导电刻蚀阻挡层的边缘。
所述在所述有源层上形成导电刻蚀阻挡层， 包括：
釆用溅射、 热蒸发、 等离子体增强化学气相沉积 PECVD、 低压化学气 相沉积 LPCVD、大气压化学气相沉积 APCVD或电子回旋谐振化学气相沉积 ECR-CVD法形成所述导电刻蚀阻挡层。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的薄膜晶体管结构示意图；
图 2为本发明提供的一种薄膜晶体管结构的示意图；
图 3为本发明提供的另一种薄膜晶体管结构的示意图；
图 4为本发明提供的薄膜晶体管制作过程中的一种薄膜晶体管结构的示 意图一；
图 5为本发明提供的薄膜晶体管制作过程中的一种薄膜晶体管结构的示 意图二；
图 6为本发明提供的薄膜晶体管制作过程中的一种薄膜晶体管结构的示 意图三；
图 7为本发明提供的薄膜晶体管制作过程中的一种薄膜晶体管结构的示 意图四；
图 8为本发明提供的薄膜晶体管制作过程中的一种薄膜晶体管结构的示 意图五；
图 9为本发明提供的薄膜晶体管制作过程中的另一种薄膜晶体管结构的 示意图一；
图 10 为本发明提供的薄膜晶体管制作过程中的另一种薄膜晶体管结构 的示意图二；
图 11 为本发明提供的薄膜晶体管制作过程中的另一种薄膜晶体管结构 的示意图三；
图 12 为本发明提供的薄膜晶体管制作过程中的另一种薄膜晶体管结构 的示意图四。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
需要说明的是： 本发明的 "上" "下"只是参考附图对本发明进行说明， 不作为限定用语。
本发明实施例提供的薄膜晶体管， 包括基板， 设置于所述基板上的有源 层、 栅绝缘层、 栅极以及层间绝缘层， 还包括：
设置于所述有源层上的导电刻蚀阻挡层； 所述导电刻蚀阻挡层的位置与 所述有源层的源极区、 漏极区相对应， 在所述有源层的源极区、 漏极区上方 形成有过孔， 且该过孔不超过所述导电刻蚀阻挡层的边缘。
示例性的， 所述设置于所述基板上的有源层、 栅绝缘层、 栅极以及层间 绝缘层， 包括：
设置于所述基板上的所述有源层；
设置于所述有源层和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述栅极；
设置于所述栅极和栅绝缘层上的所述层间绝缘层。
进而， 所述导电刻蚀阻挡层设置于所述有源层与所述栅绝缘层之间。 如图 2所示， 本发明实施例提供的一种薄膜晶体管 1的结构可以包括： 基板 10, 由于碱玻璃中铝、 钡和钠等金属杂质含量较高， 容易在高温处 理工艺中发生金属杂质的扩散， 因此所述基板 10的材料可以为无碱玻璃； 例如， 可以在所述基板 10上设置緩冲层 11 , 所述緩冲层 11用于阻挡所 述基板 10中所含的杂质扩散进入有源层 12中，防止对 TFT元件的阔值电压 和漏电流等特性产生影响；
设置于所述緩冲层 11上的有源层 12, 所述有源层 12提供源极区 120、 漏极区 121和沟道区 122; 设置于所述有源层 12上的导电刻蚀阻挡层 15, 所述导电刻蚀阻挡层 15 的位置与所述有源层 12的源极区 120、 漏极区 121相对应， 在有源层 12的 源极区 120、漏极区 121上方形成有过孔 16,且该过孔 16不超过导电刻蚀阻 挡层 15的边缘；
可以理解的是， 上述的过孔不超过导电刻蚀阻挡层的边缘是指， 过孔投 影在导电刻蚀阻挡层上的阴影的边缘不超过导电刻蚀阻挡层的边缘， 一般而 言， 过孔的形状为圓柱形， 但本发明实施例并不对导电刻蚀阻挡层的形状进 行限制， 即导电刻蚀阻挡层可以是圓形， 也可以是多边形， 故只要保证过孔 不超过导电刻蚀阻挡层的边缘即可。
需要指出的是， 在实际应用中， 若过孔稍微超出导电刻蚀阻挡层的边缘 也是允许的， 因为在刻蚀过孔时， 刻蚀气体不易掌控， 故根据工艺需求也可 作适应性改变。 制， 但是， 导电刻蚀阻挡层可以尽可能多地覆盖有源层的源极区和漏极区， 但不超过源极区和漏极区的对应区域， 因为接触面积越大， 接触电阻越小， 导电性能就越好。
设置于所述緩冲层 11、有源层 12和导电刻蚀阻挡层 15上的栅绝缘层 13; 设置于所述栅绝缘层 13上的栅极 14, 所述栅极 14位于所述有源层 12 的上方；
设置于所述栅极 14和栅绝缘层 13上的层间绝缘层 17。
例如， 所述緩冲层 11的材料为氧化硅和 /或氮化硅。
例如， 所述緩冲层 11的厚度在 500埃至 4000埃的范围内。
示例性的， 所述设置于所述基板上的有源层、 栅绝缘层、 栅极以及层间 绝缘层， 包括：
设置于所述基板上的所述栅极；
设置于所述栅极和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述有源层；
设置于所述有源层和栅绝缘层上的所述层间绝缘层。
进而 , 所述导电刻蚀阻挡层设置于所述有源层与所述层间绝缘层之间。 如图 3所示，本发明实施例提供的另一种薄膜晶体管 1的结构可以包括： 基板 10, 由于碱玻璃中铝、 钡和钠等金属杂质含量较高， 容易在高温处 理工艺中发生金属杂质的扩散， 因此所述基板 10的材料可以为无碱玻璃； 设置于所述基板 10上的栅极 14;
设置于所述基板 10和栅极 14上的栅绝缘层 13;
设置于所述栅绝缘层 13上的有源层 12,所述有源层 12位于所述栅极 14 的上方， 所述有源层 12提供源极区 120、 漏极区 121和沟道区 122; ；
设置于所述有源层 12上的导电刻蚀阻挡层 15, 所述导电刻蚀阻挡层 15 的位置与所述有源层 12的源极区 120、 漏极区 121相对应， 在有源层 12的 源极区 120、漏极区 121上方形成有过孔 16,且该过孔 16不超过导电刻蚀阻 挡层 15的边缘；
设置于所述有源层 12、栅绝缘层 13和导电刻蚀阻挡层 15上的层间绝缘 层 17。
需要说明的是， 图 2和图 3提供的两种薄膜晶体管的区别仅在于， 图 2 的薄膜晶体管为 "顶栅" 结构， 即有源层设置于基板与栅绝缘层之间， 且栅 极形成于栅绝缘层上， 图 3的薄膜晶体管为 "底栅" 结构， 即栅绝缘层覆盖 栅极， 且有源层设置于栅绝缘层上。 也就是说， 本发明实施例所提出的在有 源层上增设导电刻蚀阻挡层的方法， 既可以适用于 "顶栅" 结构的薄膜晶体 管， 也可以适用于 "底栅" 结构的薄膜晶体管。
例如， 所述有源层的厚度在 500埃至 1000埃的范围内。
例如，所述导电刻蚀阻挡层的厚度在 1000埃至 7000埃的范围内，例如， 所述导电刻蚀阻挡层的厚度在 1500埃至 3000埃的范围内。
需要补充的是， 无碱玻璃是指， 在不明显提高应变点的前提下能够减少 加热处理时产生的收缩的玻璃。 无碱玻璃的特征在于， 从退火点 （Tan ) 附 近至应变点（ Tst )附近的温度范围内的平衡密度曲线的梯度 Aan-st ( ppmTC) 与 50 ~ 350 °C的平均线膨胀系数 α50-350 ( lO-6/°C )的比值（ Aan-st/a50-350 ) 大于或等于 0且小于 3.64。
本发明提供的薄膜晶体管， 薄膜晶体管包括基板， 设置于基板上的有源 层、 栅绝缘层、 栅极以及层间绝缘层， 还包括设置于有源层上的导电刻蚀阻 挡层， 其中， 导电刻蚀阻挡层的位置与有源层的源极、 漏极区相对应， 当过 孔刻蚀工艺在源极区、 漏极区上方形成过孔时， 过孔不超过导电刻蚀阻挡层 的边缘。 通过该方案， 由于在有源层的源极区、 漏极区上增设了导电刻蚀阻 挡层， 因此釆用过孔刻蚀工艺， 在有源层的源极、 漏极上方的对应区域刻蚀 过孔时（即刻蚀栅绝缘层、 层间绝缘层的部分区域） ， 刻蚀气体很难刻蚀该 导电刻蚀阻挡层， 进而过孔不会破坏有源层， 避免了现有技术中有源层被刻 蚀掉或者未刻蚀到有源层， 而导致有源层与导电电极材料间的接触电阻不均 匀的现象。
本发明实施例提供一种薄膜晶体管的制作方法， 包括在基板上形成有源 层、 栅绝缘层、 栅极以及层间绝缘层， 在形成所述有源层后， 还包括：
在所述有源层上形成导电刻蚀阻挡层 , 所述导电刻蚀阻挡层的位置与所 述有源层的源极区、 漏极区相对应；
在形成所述层间绝缘层后， 还包括：
利用过孔刻蚀工艺在所述有源层的源极区、 漏极区上方形成过孔， 所述 过孔不超过所述导电刻蚀阻挡层的边缘。
与上述实施例中 "顶栅" 结构的薄膜晶体管相对应， 示例性的， 所述在 基板上形成有源层、 栅绝缘层、 栅极以及层间绝缘层， 包括：
在所述基板上形成所述有源层；
在所述有源层和基板上形成所述栅绝缘层；
在所述栅绝缘层上形成所述栅极；
在所述栅极和栅绝缘层上形成所述层间绝缘层。
薄膜晶体管的制作方法包括：
5101、 提供基板。
需要补充的是， 基板可以为无碱玻璃， 这是由于碱玻璃中铝、 钡和钠等 金属杂质含量较高， 容易在高温处理工艺中发生金属杂质的扩散。
5102、 在基板上形成緩冲层。
如图 4所示，在经过预先清洗的基板 10上， 以等离子体增强化学气相沉 积 ( Plasma Enhanced Chemical Vapor Deposition, PECVD )方法形成緩冲层 11以阻挡基板 10中所含的杂质扩散进入有源层中， 防止对 TFT元件的阔值 电压和漏电流等特性产生影响。 在基板 10上形成緩冲层 11的方法还可以包 括低压化学气相沉积（Low Pressure Chemical Vapor Deposition, LPCVD ) 、 大气压化学气相沉积 ( Atmospheric Pressure Chemical Vapor Deposition , APCVD ) 、 电子回旋谐振化学气相沉积 （Electron Cyclotron Resonance -Chemical Vapor Deposition, ECR-CVD )或者溅射等。
需要补充的是， 緩冲层 11的材料为氧化硅和 /或氮化硅， 即緩冲层 11可 以为单层的氧化硅、 氮化硅或者二者的叠层。
进一步地， 緩冲层 11的厚度可为 300埃至 10000埃， 例如， 緩冲层 11 的厚度在 500埃至 4000埃的范围内， 并且， 沉积緩冲层 11 的温度不大于 600 °C , 即沉积温度在 600 °C或更低温度下。
需要说明的， 可以不设置緩冲层 11。 例如， 在所述基板 10上设置緩冲 层 11 ,所述緩冲层 11用于阻挡所述基板 10中所含的杂质扩散进入有源层 12 中， 防止对 TFT元件的阔值电压和漏电流等特性产生影响。
5103、 在緩冲层上形成有源层。
示例性的， 在緩冲层上形成有源层的方法可以包括：
如图 5所示， 在緩冲层 11上釆用 PECVD、 LPCVD或者溅射方法沉积 非晶硅薄膜， 并对非晶硅薄膜进行构图， 形成有源层 12, 具体地， 在緩冲层 11之上沉积， 并以光刻工艺形成掩模， 继而釆用干法刻蚀工艺形成图形， 以 形成有源层 12,沉积温度不大于 600 °C。也可以在緩冲层 11上釆用 PECVD、
LPCVD 或者溅射方法沉积微晶硅薄膜等， 并对微晶硅薄膜等进行构图， 形 成有源层 12。
需要补充的是， 在半导体制造中， 许多芯片工艺步骤釆用光刻技术， 用 于这些步骤的图形 "底片" 称为掩模， 掩模的作用是： 在硅片上选定的区域 中对一个不透明的图形模板遮盖， 继而下面的腐蚀或扩散将只影响选定的区 域以外的区域。
5104、 在有源层上形成导电刻蚀阻挡层， 导电刻蚀阻挡层的位置与有源 层的源极区、 漏极区相对应。
如图 6所示， 在有源层 12的源极 120、 漏极 121上形成导电刻蚀阻挡层
15。 形成导电刻蚀阻挡层 15的方法可以包括， 在有源层 12的源极区 120、 漏极区 121上， 釆用溅射法沉积导电材料， 以形成导电刻蚀阻挡层 15, 该导 电材料可以为金属、 金属合金或导电的金属氧化物， 例如， 钼、 钼合金或铟 镓辞氧化物（ IGZO ) , 导电刻蚀阻挡层 15的厚度可以在 1000埃至 7000埃 的范围内，例如，导电刻蚀阻挡层 15的厚度可以在 1500埃至 3000埃的范围 内。 沉积导电材料以形成导电刻蚀阻挡层 15还可以包括热蒸发、 PECVD、 LPCVD、 APCVD或 ECR-CVD等方法。
S105、 在有源层、 緩冲层和导电刻蚀阻挡层上形成栅绝缘层和栅极。 如图 7所示， 釆用 PECVD、 LPCVD、 APCVD或 ECR-CVD等方法， 在 有源层 12、 緩冲层 11和导电刻蚀阻挡层 15上形成栅绝缘层 13, 釆用溅射、 热蒸发或 PECVD、 LPCVD、 APCVD、 ECR-CVD等方法在栅绝缘层 13上沉 积栅极薄膜， 釆用湿法刻蚀或干法刻蚀的方法， 以光刻工艺形成掩模进行构 图， 形成栅极 14。 其中， 栅绝缘层 13的厚度可以在 300埃至 3000埃的范围 内， 还可以根据具体工艺需要选择合适的厚度， 本发明不做限制。 栅绝缘层 13的材料可以釆用单层的氧化硅、氮化硅或者二者的叠层，沉积栅绝缘层 13 的温度可以在 600 °C以下； 栅极 14的材料可以由金属、 金属合金 (例如钼、 钼合金等）或掺杂的多晶硅等导电材料构成。 栅极 14的厚度可以在 1000埃 至 8000埃的范围内， 例如， 栅极 14的厚度可以在 2500埃至 4000埃的范围 内。
S106、 在栅极和栅绝缘层上形成层间绝缘层。
如图 8所示，可以釆用 PECVD、 LPCVD、 APCVD或 ECR-CVD等方法， 在 600 °C以下的沉积温度， 在栅极 14和栅绝缘层 13上形成层间绝缘层 17 , 其中，层间绝缘层 17可以由单层的氧化硅,或者氧化硅和氮化硅的叠层组成。
S107、 釆用过孔刻蚀工艺， 在源极区、 漏极区上方形成过孔。
其中， 所述过孔不超过所述导电刻蚀阻挡层的边缘。
例如， 可以选择在源极区、 漏极区上对应的导电刻蚀阻挡层上进行过孔 工艺， 更有利于控制过孔的大小、 深度等。
如图 2所示，在层间绝缘层 17上涂覆光刻胶作为掩模， 其中， 光刻胶的 厚度可以在 10000埃至 20000埃的范围内， 釆用干法刻蚀在源极区 120、 漏 极区 121上方形成过孔 16, 其中， 干法刻蚀可选用等离子刻蚀、 反应离子刻 蚀、电感耦合等离子体刻蚀等方法，刻蚀气体可选择含氟、氯的气体，如 CF4、 CHF3、 SF6、 CC12F2等或者这些气体与 02的混合气体。
由图 2可知， 由于在有源层 12增设了导电刻蚀阻挡层 15, 刻蚀气体对 导电刻蚀阻挡层 15的刻蚀速度非常緩慢 (刻蚀量可以忽略不计），使得当过 孔刻蚀工艺在源极区 120、 漏极区 121上方形成过孔 16时， 过孔 16不超过 导电刻蚀阻挡层 15, 即可以避免发生因为栅绝缘层 13和 /或层间绝缘层 17 的不均匀， 而导致有源层 12被刻蚀掉部分， 或残留部分栅绝缘层的情况。
至此， 制作成了如图 2所示的具有 "顶栅" 结构的薄膜晶体管。
与上述实施例中 "底栅" 结构的薄膜晶体管相对应， 示例性的， 所述在 基板上形成有源层、 栅绝缘层、 栅极以及层间绝缘层， 包括：
在所述基板上形成所述栅极；
在所述栅极和基板上形成所述栅绝缘层；
在所述栅绝缘层上形成所述有源层；
在所述有源层和栅绝缘层上形成所述层间绝缘层。
薄膜晶体管的制作方法包括：
5201、 提供基板。
需要补充的是， 基板可以为无碱玻璃， 这是由于碱玻璃中铝、 钡和钠等 金属杂质含量较高， 容易在高温处理工艺中发生金属杂质的扩散。
5202、 在基板上形成栅极和栅绝缘层。
如图 9所示， 制作具有 "底栅" 结构的薄膜晶体管， 首先需要在基板 10 上形成栅极 14, 以及在基板 10和栅极 14上形成栅绝缘层 13 ,形成栅绝缘层 13、 栅极 14的方法与制作 "顶栅" 结构的薄膜晶体管中形成栅绝缘层 13、 栅极 14的方法类似， 此处不再赘述。
5203、 在栅绝缘层上形成有源层。
与制作 "顶栅" 结构的薄膜晶体管中形成有源层 12 的方法相同， 如图
10所示， 在栅绝缘层 13上形成有源层 12。
5204、 在有源层上形成导电刻蚀阻挡层， 导电刻蚀阻挡层的位置与有源 层的源极、 漏极区相对应。
与步骤 S104相同， 如图 11所示， 在有源层 12的源极区 120、 漏极区 121上形成导电刻蚀阻挡层 15, 此处不再赘述。
S205、 在有源层和导电刻蚀阻挡层上形成层间绝缘层。
如图 12所示， 可以釆用 PECVD、 LPCVD、 APCVD或 ECR-CVD等方 法， 在 600°C以下的沉积温度， 在有源层 12和导电刻蚀阻挡层 15上形成层 间绝缘层 17, 其中， 层间绝缘层 17可以由单层的氧化硅， 或者氧化硅和氮 化硅的叠层组成。 S206、 釆用过孔刻蚀工艺， 在源极区、 漏极区上方形成过孔。
其中， 所述过孔不超过所述导电刻蚀阻挡层的边缘。
例如， 可以选择在源极区、 漏极区上对应的导电刻蚀阻挡层上进行过孔 工艺， 更有利于控制过孔的大小、 深度等。
如图 3所示，在层间绝缘层 17上涂覆光刻胶作为掩模， 其中， 光刻胶的 厚度可以在 10000埃至 20000埃的范围内， 釆用干法刻蚀在源极区 120、 漏 极区 121上方形成过孔 16, 其中， 干法刻蚀可选用等离子刻蚀、 反应离子刻 蚀、电感耦合等离子体刻蚀等方法，刻蚀气体可选择含氟、氯的气体，如 CF4、 CHF3、 SF6、 CC12F2等或者这些气体与 02的混合气体。
由图 3可知， 由于在有源层 12增设了导电刻蚀阻挡层 15, 刻蚀气体对 导电刻蚀阻挡层 15刻蚀速度非常緩慢 (刻蚀量可以忽略不计），使得当过孔 刻蚀工艺在源极区 120、 漏极区 121上方形成过孔 16时， 过孔 16不超过导 电刻蚀阻挡层 15, 即可以避免发生因为层间绝缘层 17的不均匀， 而导致有 源层 12被刻蚀掉部分， 或残留部分层间绝缘层的情况。
至此， 制作成了如图 3所示的具有 "底栅" 结构的薄膜晶体管。
本发明提供的薄膜晶体管的制作方法， 通过在基板上形成有源层、 栅绝 缘层、 栅极以及层间绝缘层， 以及在有源层上形成导电刻蚀阻挡层， 导电刻 蚀阻挡层的位置与有源层的源极区、 漏极区相对应， 当过孔刻蚀工艺在源极 区、 漏极区上方形成过孔时， 过孔不超过导电刻蚀阻挡层的边缘， 以制成薄 膜晶体管。 通过该方案， 由于在有源层的源极区、 漏极区上增设了导电刻蚀 阻挡层， 因此釆用过孔刻蚀工艺， 在有源层的源极区、 漏极区上方的对应区 域刻蚀过孔时（即刻蚀栅绝缘层、 层间绝缘层的部分区域） ， 刻蚀气体很难 刻蚀该导电刻蚀阻挡层， 进而过孔不会破坏有源层， 避免了现有技术中有源 层被刻蚀掉一部分或者未刻蚀到有源层， 而导致有源层与导电电极材料间的 接触电阻不均匀的现象。
本发明实施例提供一种阵列基板， 包括阵列形成的具有上述实施例所描 述的任意特征的薄膜晶体管， 该薄膜晶体管与上述实施例完全相同， 此处不 再赘述。
本发明实施例提供一种显示装置， 具有上述实施例所描述的任意特征的 阵列基板。 该显示装置可以为液晶显示装置， 包括相对平行设置的彩膜基板 和上述实施例所提出的阵列基板， 以及填充于所述彩膜基板和阵列基板之间 的液晶； 该显示装置也可以为 OLED显示装置， 包括上述实施例所提出的阵 列基板， 以及蒸镀于该阵列基板之上的有机发光材料及封装盖板。
本发明实施例提供的液晶显示装置， 所述液晶显示装置可以为液晶显示 器、 液晶电视、 数码相框、 手机、 平板电脑等具有显示功能的产品， 本发明 不做限制。
( 1 )一种薄膜晶体管， 包括基板， 设置于所述基板上的有源层、栅绝缘 层、 栅极以及层间绝缘层， 还包括：
设置于所述有源层上的导电刻蚀阻挡层； 所述导电刻蚀阻挡层的位置与 所述有源层的源极区、 漏极区相对应， 在所述有源层的源极区、 漏极区上方 形成有过孔， 且该过孔不超过所述导电刻蚀阻挡层的边缘。
( 2 )根据（1 )所述的薄膜晶体管， 其中， 所述设置于所述基板上的有 源层、 栅绝缘层、 栅极以及层间绝缘层， 包括：
设置于所述基板上的所述有源层；
设置于所述有源层和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述栅极；
设置于所述栅极和栅绝缘层上的所述层间绝缘层。
( 3 )根据（ 1 )或（ 2 )所述的薄膜晶体管， 其中 , 所述导电刻蚀阻挡层 设置于所述有源层与所述栅绝缘层之间。
( 4 )根据（1 )至（3 ) 中任一项所述的薄膜晶体管， 还包括： 设置于所述基板与所述有源层之间的緩冲层。
( 5 )根据（ 1 )至（ 4 )中任一项所述的薄膜晶体管， 其中， 所述设置于 所述基板上的有源层、 栅绝缘层、 栅极以及层间绝缘层， 包括：
设置于所述基板上的所述栅极；
设置于所述栅极和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述有源层；
设置于所述有源层和栅绝缘层上的所述层间绝缘层。
( 6 )根据（ 1 )至（ 5 )中任一项所述的薄膜晶体管， 其中， 所述导电刻 蚀阻挡层设置于所述有源层与所述层间绝缘层之间。 ( 7 )根据（ 1 )至（ 6 )中任一项所述的薄膜晶体管， 其中， 所述导电刻 蚀阻挡层的厚度在 1500埃至 3000埃的范围内。
( 8 )一种阵列基板， 其中 , 包括如（ 1 )至（ 7 )中任一项所述的薄膜晶 体管形成的阵列。
( 9 )一种显示装置， 包括如（8 )所述的阵列基板。
( 10 )—种薄膜晶体管的制作方法， 包括在基板上形成有源层、 栅绝缘 层、 栅极以及层间绝缘层， 其中，
在形成所述有源层后， 还包括：
在所述有源层上形成导电刻蚀阻挡层 , 所述导电刻蚀阻挡层的位置与所 述有源层的源极区、 漏极区相对应；
在形成所述层间绝缘层后， 还包括：
利用过孔刻蚀工艺在所述有源层的源极区、 漏极区上方形成过孔， 所述 过孔不超过所述导电刻蚀阻挡层的边缘。
( 11 )根据（10 )所述的薄膜晶体管的制作方法， 其中， 所述在所述有 源层上形成导电刻蚀阻挡层， 包括：
釆用溅射、 热蒸发、 等离子体增强化学气相沉积、 低压化学气相沉积、 大气压化学气相沉积或电子回旋谐振化学气相沉积法形成所述导电刻蚀阻挡 层。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种薄膜晶体管， 包括基板，设置于所述基板上的有源层、栅绝缘层、 栅极以及层间绝缘层， 还包括：
设置于所述有源层上的导电刻蚀阻挡层； 所述导电刻蚀阻挡层的位置与 所述有源层的源极区、 漏极区相对应， 在所述有源层的源极区、 漏极区上方 形成有过孔， 且该过孔不超过所述导电刻蚀阻挡层的边缘。
2、根据权利要求 1所述的薄膜晶体管， 其中， 所述设置于所述基板上的 有源层、 栅绝缘层、 栅极以及层间绝缘层， 包括：
设置于所述基板上的所述有源层；
设置于所述有源层和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述栅极；
设置于所述栅极和栅绝缘层上的所述层间绝缘层。
3、根据权利要求 1或 2所述的薄膜晶体管， 其中， 所述导电刻蚀阻挡层 设置于所述有源层与所述栅绝缘层之间。
4、 根据权利要求 1至 3中任一项所述的薄膜晶体管， 还包括： 设置于所述基板与所述有源层之间的緩冲层。
5、根据权利要求 1至 4中任一项所述的薄膜晶体管， 其中， 所述设置于 所述基板上的有源层、 栅绝缘层、 栅极以及层间绝缘层， 包括：
设置于所述基板上的所述栅极；
设置于所述栅极和基板上的所述栅绝缘层；
设置于所述栅绝缘层上的所述有源层；
设置于所述有源层和栅绝缘层上的所述层间绝缘层。
6、根据权利要求 1至 5中任一项所述的薄膜晶体管， 其中， 所述导电刻 蚀阻挡层设置于所述有源层与所述层间绝缘层之间。
7、根据权利要求 1至 6中任一项所述的薄膜晶体管， 其中， 所述导电刻 蚀阻挡层的厚度在 1500埃至 3000埃的范围内。
8、 一种阵列基板， 其中， 包括如权利要求 1至 7中任一项所述的薄膜晶 体管形成的阵列。
9、 一种显示装置， 包括如权利要求 8所述的阵列基板。
10、 一种薄膜晶体管的制作方法， 包括在基板上形成有源层、栅绝缘层、 栅极以及层间绝缘层， 其中，
在形成所述有源层后， 还包括：
在所述有源层上形成导电刻蚀阻挡层 , 所述导电刻蚀阻挡层的位置与所 述有源层的源极区、 漏极区相对应；
在形成所述层间绝缘层后， 还包括：
利用过孔刻蚀工艺在所述有源层的源极区、 漏极区上方形成过孔， 所述 过孔不超过所述导电刻蚀阻挡层的边缘。
11、根据权利要求 10所述的薄膜晶体管的制作方法， 其中， 所述在所述 有源层上形成导电刻蚀阻挡层， 包括：
釆用溅射、 热蒸发、 等离子体增强化学气相沉积、 低压化学气相沉积、 大气压化学气相沉积或电子回旋谐振化学气相沉积法形成所述导电刻蚀阻挡 层。
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