WO2020228421A1 - 阵列基板、其制备方法及显示面板 - Google Patents

阵列基板、其制备方法及显示面板 Download PDF

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WO2020228421A1
WO2020228421A1 PCT/CN2020/081172 CN2020081172W WO2020228421A1 WO 2020228421 A1 WO2020228421 A1 WO 2020228421A1 CN 2020081172 W CN2020081172 W CN 2020081172W WO 2020228421 A1 WO2020228421 A1 WO 2020228421A1
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pattern
active layer
silicon
forming
catalyst particles
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PCT/CN2020/081172
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English (en)
French (fr)
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袁广才
董学
关峰
高宇鹏
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京东方科技集团股份有限公司
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Priority to US17/047,912 priority Critical patent/US11715744B2/en
Publication of WO2020228421A1 publication Critical patent/WO2020228421A1/zh
Priority to US18/208,529 priority patent/US20230352496A1/en

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, in particular to an array substrate, a preparation method thereof, and a display panel.
  • Silicon-based nanowires are a new type of silicon-based semiconductor material developed in recent years, with a one-dimensional scale structure and more excellent semiconductor characteristics.
  • the use of silicon-based nanowires as the thin film transistor channel can achieve higher mobility and more stable characteristics.
  • Silicon-based nanowires are used as channel materials for thin film transistors, and the uniformity and controllability of their dimensions are particularly important. In order to meet the uniformity requirements of display devices, how to obtain silicon-based nanowire thin film transistors with uniform and controllable scales has become a hot research topic.
  • An embodiment of the present disclosure provides a method for preparing an array substrate, including: forming a first thin film transistor and a second thin film transistor on a base substrate; forming the first thin film transistor includes: forming a first gate on the base substrate The pattern of the electrode, the pattern of the first active layer, the pattern of the first source electrode and the first drain electrode; forming the second thin film transistor includes: forming a pattern of a second gate electrode, a pattern of a second active layer on a base substrate The pattern of the layer, the pattern of the second source electrode and the second drain electrode;
  • the material of the first active layer is different from the material of the second active layer
  • Forming the pattern of the first active layer specifically includes:
  • At least one pattern of catalyst particles is formed on at least one side of the guide structure; the catalyst particles and silicon have a eutectic point;
  • the catalyst particles are removed, and the amorphous silicon film and the silicon-based nanowires in the first preset area are retained to form the pattern of the first active layer, and the catalyst particles are located in the first preset area. Set outside the area.
  • the material of the second active layer is a low-temperature polysilicon material, a carbon nanotube material, or an oxide semiconductor material.
  • the pattern of the first gate electrode and the pattern of the second gate electrode are formed by one patterning process
  • the pattern of the first source electrode, the pattern of the first drain electrode, the pattern of the second source electrode, and the pattern of the second drain electrode are simultaneously formed by one patterning process.
  • the material of the second active layer is a low-temperature polysilicon material
  • the pattern of the second active layer is formed, specifically:
  • the low-temperature polysilicon film in the second predetermined area is retained to form the pattern of the second active layer.
  • any one of the multiple guide structures extends in the first direction, and the multiple guide structures are perpendicular to The cross section in the first direction includes an uneven structure, and each recess of the uneven structure has one catalyst particle formed in it.
  • any one of the multiple guide structures extends in the first direction, and the multiple guide structures are perpendicular to The cross section in the first direction is a stepped structure including at least one step, and one catalyst particle is formed on each step of the stepped structure.
  • the pattern of the first active layer is formed after the pattern of the first gate electrode is formed;
  • the formation of the guiding structure specifically includes:
  • the first gate insulating layer is patterned to form the guiding structure.
  • the pattern of the first active layer is formed after the pattern of the first gate electrode is formed;
  • the formation of the guiding structure specifically includes:
  • a first gate insulating layer is formed, and the pattern of the first gate electrode covers the first gate electrode.
  • the first gate insulating layer on the electrode constitutes the guiding structure.
  • the pattern of the first active layer is formed before the pattern of the first gate electrode is formed;
  • the forming of the guiding structure specifically includes: forming a dielectric layer on the base substrate, and patterning the dielectric layer to form the plurality of guiding structures.
  • the material of the catalyst particles includes indium, tin, nickel or indium oxide.
  • the particle diameter of the catalyst particles is 5 nm-10 ⁇ m.
  • forming the pattern of the catalyst particles specifically includes:
  • the catalyst film layer is etched to form the pattern of the catalyst particles.
  • forming the pattern of the catalyst particles specifically includes:
  • Plasma bombardment is performed on the catalyst wire to form a pattern of the catalyst particles.
  • the temperature range of the eutectic point of the catalyst particles and silicon is 200°C to 1000°C;
  • the annealing temperature is 200°C-600°C.
  • an embodiment of the present disclosure also provides an array substrate, which is prepared by using any of the above-mentioned preparation methods provided in the embodiments of the present disclosure; the array substrate includes:
  • a first thin film transistor located on a base substrate.
  • the first thin film transistor includes: a first gate electrode, a first active layer, a first source electrode, and a first drain electrode; At least one guiding structure extending along a first direction, the material of the first active layer includes silicon-based nanowires, and the extending direction of the silicon-based nanowires is the same as the extending direction of the guiding structure;
  • the length of the guide structure along the first direction is greater than the length of the silicon-based nanowire along the first direction.
  • connection direction of the first source electrode and the first drain electrode is the same as the extension direction of the silicon-based nanowire.
  • the material of the second active layer is a low-temperature polysilicon material, a carbon nanotube material, or an oxide semiconductor material.
  • an embodiment of the present disclosure also provides a display panel, including the above-mentioned array substrate provided by the embodiment of the present disclosure.
  • FIG. 1 is a flowchart of some steps in the preparation method provided by the embodiments of the disclosure.
  • 2a is a schematic structural diagram of multiple guiding structures provided by an embodiment of the disclosure.
  • 2b is a schematic structural diagram of multiple guiding structures provided by an embodiment of the disclosure.
  • Figure 3a is a schematic cross-sectional view of the multiple guide structures shown in Figure 2a along the AA' direction;
  • Fig. 3b is another schematic cross-sectional view of the multiple guiding structures shown in Fig. 2b along the AA' direction;
  • 4a to 4d are schematic diagrams of the structures provided by the embodiments of the present disclosure after performing various steps when preparing catalyst particles;
  • 5a to 5c are structural schematic diagrams after performing various steps when preparing catalyst particles according to embodiments of the disclosure.
  • 6a to 6h are schematic diagrams of the structures after performing various steps when preparing an array substrate according to an embodiment of the disclosure
  • FIG. 7 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic structural diagram of a guiding structure provided by an embodiment of the disclosure.
  • 9a to 9i are schematic structural diagrams after performing various steps when preparing an array substrate according to an embodiment of the disclosure.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • FIG. 11a is a schematic structural diagram of a first thin film transistor in an array substrate provided by an embodiment of the disclosure.
  • Fig. 11b is a schematic cross-sectional view of the first thin film transistor shown in Fig. 11a along the CC' direction.
  • An embodiment of the present disclosure provides a method for preparing an array substrate, including: forming a first thin film transistor and a second thin film transistor on a base substrate; wherein forming the first thin film transistor includes: forming a first gate electrode on the base substrate The pattern of the first active layer, the pattern of the first source electrode and the first drain electrode; forming the second thin film transistor includes: forming the pattern of the second gate electrode and the pattern of the second active layer on the base substrate , The pattern of the second source electrode and the second drain electrode;
  • the material of the first active layer is different from the material of the second active layer
  • the pattern of forming the first active layer specifically includes:
  • the catalyst particles are removed, and the amorphous silicon film and the silicon-based nanowires in the first predetermined area are retained to form a pattern of the first active layer, wherein the catalyst particles are located outside the first predetermined area.
  • the manufacturing method of the array substrate provided by the embodiment of the present disclosure includes: forming a first thin film transistor and a second thin film transistor on a base substrate.
  • the catalyst particles and silicon have a eutectic point, and the Gibbs free energy of amorphous silicon is greater than the Gibbs free energy of crystalline silicon (silicon-based nanowires) as the driving force.
  • the molten catalyst particles absorb amorphous silicon to form a supersaturated silicon eutectic, so that silicon nucleates and grows into silicon-based nanowires.
  • the amorphous silicon film grows linearly along the guiding structure under the action of the catalyst particles, thereby obtaining high-density, high-uniformity silicon-based nanowires.
  • the width of silicon-based nanowires can also be controlled by controlling the size of the catalyst particles and the thickness of the amorphous silicon film.
  • the first active layer and the second active layer are made of different materials, so that different thin film transistors have different advantages, so as to increase the practical range of the array substrate.
  • the size of the first thin film transistor can be made relatively small, so it is applied in the frame area of the panel
  • the first thin film transistor can obtain a smaller frame size; when the first thin film transistor is used in the switching transistor, a faster switching speed and a higher refresh frequency can be obtained; when the first thin film transistor is applied to the large backplane
  • the transistor is sized, it can avoid the device characteristics drifting caused by the heating of the semiconductor layer.
  • the material of the second active layer may be any one or more of low-temperature polysilicon materials, carbon nanotube materials, or oxide semiconductor materials.
  • low-temperature polysilicon has higher mobility and stability, but in large-size panels, uniformity is more difficult to control.
  • Carbon nanotubes also have higher mobility and can achieve flexible display.
  • the mobility of oxide semiconductor materials is relatively low, but large-size panels can ensure good uniformity, low leakage current, transparency and simple manufacturing process. Therefore, the material of the second active layer can be selected according to actual requirements.
  • the second active layer is used in conjunction with the first active layer to meet different circuit requirements, such as adjusting the sub-threshold swing SS of the thin film transistor, the off-state current Ioff of the thin film transistor, and the mobility of the thin film transistor.
  • the film layers with the same function are prepared in the same layer as possible.
  • the pattern of the first gate electrode and the pattern of the second gate electrode are formed by one patterning process
  • the pattern of the first source electrode, the pattern of the first drain electrode, the pattern of the second source electrode, and the pattern of the second drain electrode are simultaneously formed by one patterning process.
  • the first active layer and the second active layer can be prepared by using the same layer of amorphous silicon film.
  • the material of the second active layer is a low-temperature polysilicon material
  • the pattern of the second active layer and the pattern of the first active layer are formed simultaneously through a patterning process, specifically:
  • the catalyst particles are removed and the low-temperature polysilicon film is patterned.
  • the silicon-based nanowires and the low-temperature polysilicon film in the first preset area are retained to form the pattern of the first active layer, and the low-temperature polysilicon film in the second preset area is retained to form the second active layer.
  • Source layer graphics are generated.
  • the first predetermined area is a region for forming the first active layer
  • the second predetermined area is a region for forming the second active layer
  • the more guide structures the more silicon-based nanowires are formed. Therefore, the formation of multiple guide structures can ensure that there are multiple silicon-based nanowires in the first active layer. Nanowires, thereby improving the mobility of the first thin film transistor.
  • a plurality of guide structures 01 are formed, and any one of the plurality of guide structures 01 extends along the first direction X, as shown in FIG. 2a;
  • the material of each guide structure can be the same.
  • 3a is a schematic cross-sectional view of the plurality of guiding structures shown in FIG. 2a along the AA' direction. As shown in FIG. 3a, the cross-section of the plurality of guiding structures 01 perpendicular to the first direction includes at least one concave-convex structure.
  • the surface of all the convex parts of, and the surface of all the concave parts are almost the same height; in each concave part of the concave-convex structure, a catalyst particle 021 is formed, and the cross-sectional dimension of the catalyst particle 021 perpendicular to the first direction X is not larger than the concave part.
  • the section size is not larger than the concave part.
  • a guiding structure with an integrated structure can also be directly formed, and the top surface of the guiding structure extending in the first direction includes a concave-convex structure as shown in FIG. 3a.
  • a plurality of guide structures 01 are formed, and any one of the plurality of guide structures 01 extends along the first direction X, as shown in FIG. 2b;
  • the material of the multiple guiding structures may be the same.
  • 3b is a schematic cross-sectional view of the multiple guiding structures shown in FIG. 2b along the AA' direction. As shown in FIG.
  • the cross-section of the guiding structure 01 perpendicular to the first direction is a stepped structure including at least one step, and the stepped structure
  • a catalyst particle 021 is formed on each step of the catalyst particle 021, and the cross-sectional size of the catalyst particle 021 perpendicular to the first direction X is not greater than the cross-sectional size of the step where it is located.
  • a guiding structure with an integrated structure can also be directly formed, and the top surface of the guiding structure extending in the first direction includes at least one stepped structure as shown in FIG. 3b.
  • the cross section of the guide structure 01 perpendicular to the first direction includes a concave-convex structure or a stepped structure including at least one step, which can realize the multi-level distribution of silicon-based nanowires, thereby enhancing the groove
  • the channel width can also solve the heat dissipation problem.
  • the cross-sections of the multiple guiding structures perpendicular to the first direction may include a concave-convex structure and a stepped structure at the same time, which is not limited herein.
  • multiple guiding structures can be produced in stages, such as forming multiple strip-shaped structures respectively; if the materials of multiple guiding structures are the same, they can finally form an integrated structure; multiple guiding structures can also be produced at one time After the film process, patterning is performed to form an integral molding.
  • the side surface of each guide structure extending along the first direction may also be a flat surface.
  • the angle between the side surface and the bottom surface is preferably greater than or equal to 60° This can ensure that the subsequent amorphous silicon film can cover the catalyst particles located on the side of the guide structure to ensure the normal growth of the silicon-based nanowires.
  • the pattern of the first active layer is formed after the pattern of the first gate electrode is formed;
  • Form multiple guiding structures including:
  • the first gate insulating layer is patterned to form a guiding structure.
  • the first gate insulating layer by patterning the first gate insulating layer to form a guide structure, it is possible to avoid an increase in the thickness of the array substrate due to a separate increase in the film layer for preparing the guide structure.
  • the pattern of the first active layer is formed after the pattern of the first gate electrode is formed;
  • Form multiple guiding structures including:
  • the pattern of the first gate electrode is formed, and before the pattern of the first active layer is formed, a first gate insulating layer is formed, the pattern of the first gate electrode and the first gate insulating layer covering the first gate electrode Layers constitute a guiding structure.
  • the surface of the first gate electrode is patterned to form a plurality of guiding structures, and the first gate insulating layer covering the first gate electrode has a corresponding shape due to the guiding structure of the first gate electrode. structure.
  • the first gate insulating layer is multiplexed as the gate insulating layer of the second thin film transistor.
  • the pattern of the first active layer is formed before the pattern of the first gate electrode is formed;
  • Forming multiple guiding structures specifically includes: forming a dielectric layer on a base substrate, and patterning the dielectric layer to form multiple guiding structures.
  • the dielectric layer may be formed by a deposition method, which is not limited herein.
  • the material of the dielectric layer may be aluminum oxide (AlOx), silicon oxide (SiOx), silicon nitride (SiNx), etc., which are not limited herein.
  • the dielectric layer may be the buffer layer of the array substrate, of course, the buffer layer may also be formed on the base substrate before forming the dielectric layer, which is not limited.
  • the material of the catalyst particles includes indium, tin, nickel or indium oxide, which is not limited herein.
  • the particle size of the catalyst particles can be controlled between 5 nm and 10 ⁇ m, such as 5 nm, 10 nm, 50 nm, 100 nm, 500 nm, 1 ⁇ m, 10 ⁇ m, etc., which are not limited herein.
  • forming the pattern of the catalyst particles specifically includes:
  • a catalyst film layer 02 is formed on the base substrate 10 on which the guiding structure 01 is formed, as shown in FIG. 4a;
  • An embossed glue 03 is formed on the catalyst film layer 02, as shown in Figure 4b;
  • the catalyst film layer 02 is etched to form a pattern of catalyst particles 021, as shown in FIG. 4d.
  • forming the pattern of the catalyst particles specifically includes:
  • a catalyst film layer 02 is formed on the base substrate 10 on which the guiding structure 01 is formed, as shown in FIG. 4a;
  • An embossed glue 03 is formed on the catalyst film layer 02, as shown in Figure 4b;
  • the catalyst film layer 02 is etched to form the pattern of the catalyst line 022, as shown in FIG. 5b;
  • Plasma bombardment is performed on the catalyst wire to form a pattern of catalyst particles 021, as shown in Figs. 5c and 4d, wherein Fig. 4d is a cross-sectional view of Fig. 5c along the B-B' direction.
  • the nano-imprinting process is used to form the pattern of the catalyst particles, which can realize the high-definition of the pattern, ensure the uniformity and controllability of the catalyst particles, and ensure the uniform growth of the silicon-based nanowires.
  • the line width of the catalyst line is controlled between 50 nm and 1000 nm, such as 50 nm, 100 nm, 500 nm, 1000 nm, etc., which are not limited herein.
  • the particle size of the catalyst particles is determined according to the required line width of the silicon-based nanowires. Generally, the particle size of the catalyst particles is close to the line width of the silicon-based nanowires.
  • a photolithography process can also be used to form a pattern of catalyst particles. Therefore, optionally, in the preparation method provided in the embodiment of the present disclosure, forming the pattern of the catalyst particles specifically includes:
  • the catalyst film layer is etched to form a pattern of catalyst particles.
  • the catalyst particles are formed at one end of the guiding structure along the extending direction thereof, so that the silicon-based nanowires can be guaranteed to grow from one end of the guiding structure to the other end.
  • the guiding structure may be linear or curved along its extending direction, which is not limited herein.
  • the structure of the first thin film transistor formed may be a bottom gate structure or a top gate structure; similarly, the structure of the second thin film transistor may be It is a bottom gate structure or a top gate structure, which is not limited here.
  • the structures of the first thin film transistor and the second thin film transistor formed are both bottom-gate structures or both top-gate structures. Films with the same material and the same function can be formed by one patterning process.
  • the first thin film transistor and the second thin film transistor as both bottom-gate transistors as an example, some embodiments provided in the present disclosure specifically include the following steps:
  • Step 1 As shown in FIG. 6a, the patterns of the first gate electrode 11 and the second gate electrode 21 are formed on the base substrate 10 by one patterning process.
  • the material of the gate electrode may be metals or alloys such as molybdenum (Mo), aluminum (Al), copper (Cu), nickel (Ti), etc., and the thickness may be controlled between 50 nm and 5000 nm, which is not limited herein.
  • Step 2 As shown in FIG. 6b, a gate insulating layer 30 is formed.
  • the material of the gate insulating layer is a dielectric material, and the thickness can be controlled between 50 nm and 5000 nm, which is not limited herein.
  • Step 3 As shown in FIG. 6c, a pattern of the guiding structure 01 is formed in the gate insulating layer 30.
  • the number of guiding structures may be one or more, which is not limited here.
  • each guide structure extends in the first direction
  • the side surface of the guide structure extending in the first direction may include a stepped structure, or a plane with an angle greater than or equal to 60 degrees with the bottom surface, or the guide
  • the surface of the structure extending in the first direction may include an uneven structure, which is not limited herein.
  • Step 4 As shown in FIG. 6d, a pattern of catalyst particles 021 is formed on at least one side of the guiding structure 01.
  • an imprinting glue can be formed on the catalyst film layer, and the nano-imprinting process can be performed on the imprinting glue to form the pattern of the imprinting glue particles; the pattern of the imprinting glue particles is used as the mask pattern to perform the process on the catalyst film. Etch to form a pattern of catalyst particles. Or perform a nano-imprint process on the imprinting glue to form the pattern of the imprinted glue line, and use the pattern of the imprinted glue line as the mask pattern to etch the catalyst film to form the pattern of the catalyst line, and plasma the catalyst line The bombardment forms a pattern of catalyst particles.
  • a photolithography process can also be used to form the pattern of the catalyst particles.
  • the particle size of the catalyst particles can be controlled between 5 nm and 10 ⁇ 1, such as 5 nm, 10 nm, 50 nm, 100 nm, 500 nm, 1 ⁇ 0, 10 ⁇ 0, etc., which are not limited herein.
  • the material of the catalyst particles includes indium, tin, nickel or indium oxide, which is not limited herein.
  • Step 5 As shown in FIG. 6e, an amorphous silicon film 40 covering the catalyst particles 021 and the guiding structure 01 is formed; and the amorphous silicon film 40 is annealed so that the amorphous silicon starts from the catalyst particles 021 along the extending direction of the guiding structure 01
  • the silicon-based nanowire 41 is grown and formed.
  • a plasma-enhanced chemical vapor deposition (PECVD) method is used to deposit an amorphous silicon film of 5 nm to 5000 nm, and the thickness of the amorphous silicon film can be controlled between 10 nm and 1000 nm, which is not limited here.
  • PECVD plasma-enhanced chemical vapor deposition
  • the temperature range of the eutectic point between the catalyst particles and silicon can be 200°C to 1000°C, and the annealing temperature can be controlled between 200°C and 600°C, which is not limited here. Further, the annealing temperature can be controlled between 250°C and 450°C.
  • Step 6 As shown in FIG. 6f, the catalyst particles 021 are removed, and the amorphous silicon film (not shown in the figure) and the silicon-based nanowires 41 in the first predetermined area are retained to form the pattern of the first active layer 12 .
  • Step 7 As shown in FIG. 6g, a pattern of the second active layer 22 is formed.
  • the material of the second active layer is a carbon nanotube material, which can be formed by spin coating and patterned etching processes, and the thickness of the material of the second active layer is controlled between 1 nm and 1000 nm.
  • the material of the second active layer is an oxide semiconductor material, which can be formed by deposition and patterning etching processes.
  • Step 8 As shown in FIG. 6h, the patterns of the first source electrode 13, the first drain electrode 14, the second source electrode 23, and the second drain electrode 24 are formed by one patterning process.
  • the material of the source electrode and the drain electrode may be metals or alloys such as molybdenum (MO), aluminum (Al), copper (Cu), nickel (Ti), etc., which are not limited herein.
  • MO molybdenum
  • Al aluminum
  • Cu copper
  • Ti nickel
  • the first source electrode 13 and the first drain electrode 14 are connected to the first active layer 12 through a via hole penetrating the etching barrier layer 50, and the second source electrode 23 and the second drain electrode 24 are connected to the first active layer 12 by penetrating the etching barrier layer 50.
  • the hole is connected to the second active layer 22.
  • the material of the etch stop layer is a dielectric material, such as silicon nitride (SiNX), silicon oxide (SiOx), aluminum oxide (AllOx), etc., and the thickness can be controlled between 50nm and 5000nm. limited.
  • step 7 is before step 5 and step 6.
  • the material of the second active layer is low-temperature polysilicon, after step 5 and before step 8, it includes:
  • Step 6' performing excimer laser annealing treatment on the amorphous silicon film formed with silicon-based nanowires to convert the amorphous silicon film into a low-temperature polysilicon film;
  • Step 7' removing the catalyst particles, and patterning the low-temperature polysilicon film, retaining the silicon-based nanowires and the low-temperature polysilicon film in the first preset area to form the pattern of the first active layer, and retaining the low-temperature polysilicon film in the second preset area A pattern of the second active layer is formed.
  • the patterns of the first active layer and the second active layer can be formed by one patterning process.
  • a gray-tone mask or a half-tone mask can be formed by one patterning process.
  • it can also be formed by two patterning processes, which is not limited here.
  • the guiding structure 01 may also be composed of the first gate electrode 11 and the gate insulating layer 30. That is, in step 1, the pattern of the first gate electrode 11 is prepared to be similar to the pattern of the guide structure 01, and in step 2, a gate insulating layer 30 is formed on the first gate electrode 11 so that the gate insulating layer 30 has the same The corresponding pattern of the gate electrode 11 can save the process of patterning the gate insulating layer 30 in step 3.
  • the first thin film transistor and the second thin film transistor as both top-gate transistors as an example, some embodiments provided by the present disclosure specifically include the following steps:
  • Step 01 Form a pattern of the guiding structure 01.
  • Fig. 9a the dashed rectangular frame indicates the concave portion of the guide structure 01
  • Fig. 9b is a schematic cross-sectional view of Fig. 9a along the BB' direction.
  • the guide structure adopts dielectric materials, such as SiOx, SiNx, Al2O3, etc., and the thickness is controlled between 20 nm and 5000 nm, which is not limited here.
  • Step 02 as shown in FIGS. 9a and 9b, a pattern of catalyst particles 021 is formed on at least one side of the guiding structure 01, specifically, a pattern of catalyst particles 021 is formed on the concave portion or step portion of the guiding structure 01.
  • Step 03. As shown in FIG. 9c, an amorphous silicon film 40 covering the catalyst particles 021 and the guiding structure 01 is formed; the amorphous silicon film 40 is annealed so that the amorphous silicon starts from the catalyst particles 021 along the extending direction of the guiding structure 01 The silicon-based nanowire 41 is grown and formed.
  • Step 04. As shown in FIG. 9d, the catalyst particles 021 are removed, and the amorphous silicon film (not shown in the figure) and the silicon-based nanowires 41 in the first predetermined area are retained to form the pattern of the first active layer 12 .
  • Step 05 As shown in FIG. 9e, a pattern of the second active layer 22 is formed.
  • Step 06 As shown in FIG. 9f, a gate insulating layer 30 is formed.
  • Step 07 As shown in FIG. 9g, patterns of the first gate electrode 11 and the second gate electrode 12 are formed.
  • Step 08 As shown in FIG. 9h, a pattern of the etch stop layer 50 is formed.
  • Step 08 patterns of the first source electrode 13, the first drain electrode 14, the second source electrode 23, and the second drain electrode 24 are formed by one patterning process.
  • the first source electrode 13 and the first drain electrode 14 are connected to the first active layer 12 through a via hole that penetrates the etching stop layer 50 and the gate insulating layer 30, and the second source electrode 23 and the second drain electrode 24 are etched through
  • the etch stop layer 50 and the gate insulating layer 30 are connected to the second active layer 22 via via via holes.
  • a buffer layer may be formed before forming the guiding structure to isolate impurities in the base substrate.
  • the patterning treatment of the buffer layer can also be used to form a guiding structure.
  • the buffer layer is formed of silicon nitride (SiNX) or silicon oxide (SiOx), the thickness is controlled between 10nm and 1000nm, and then the patterning process Form a guiding structure.
  • the buffer layer can isolate impurities in the base substrate, and can save a separate film layer used to make the guiding structure.
  • the manufacturing process of the top gate thin film transistor and the bottom gate thin film transistor is only a change in the order of the film layers. Therefore, the preparation of each film layer in the top gate thin film transistor can refer to the bottom gate type Preparation of films with the same function in thin film transistors.
  • the above-mentioned array substrate when the above-mentioned array substrate is applied to a display panel, after forming the first thin film transistor and the second thin film transistor, as shown in FIG. 10, it further includes forming a planarization layer 60 and an electrode layer on the base substrate 10. 70 etc., not limited here.
  • the present disclosure is not limited to the above-mentioned structures. It is also suitable for the first thin film transistor to be a bottom gate transistor and the second thin film transistor to be a top gate transistor, or the first thin film transistor is a top gate transistor, and the first thin film transistor is a top gate transistor.
  • the second thin film transistor is a TFT structure such as a bottom-gate transistor, which can be understood by those skilled in the art without knowledge creation, and will not be repeated here.
  • the embodiments of the present disclosure also provide an array substrate, which is prepared by using any of the foregoing preparation methods provided in the embodiments of the present disclosure; wherein, as shown in FIG. 6h, FIG. 7 and FIG. 9i, the array substrate It includes a first thin film transistor and a second thin film transistor on a base substrate 10; the first thin film transistor includes: a first gate electrode 11, a first active layer 12, a first source electrode 13 and a first drain electrode 14; The two thin film transistors include: a second gate electrode 21, a second active layer 22, a second source electrode 23, and a second drain electrode 24;
  • the material of the first active layer 12 includes silicon-based nanowires, and the extending direction of the silicon-based nanowires Same as the extension direction of the guide structure 01;
  • the material of the second active layer 22 is different from the material of the first active layer 12.
  • the material of the second active layer may be a low-temperature polysilicon material, a carbon nanotube material, or an oxide semiconductor material.
  • the length of the guiding structure 01 along the first direction X is greater than the length of the silicon-based nanowire along the first direction X, and the guiding structure 01 is along the first direction X.
  • the extending direction of the silicon-based nanowire 41 is the same as the extending direction of the guiding structure 01, which is the connection direction of the first source electrode 13 and the first drain electrode 14.
  • 11a and 11b are only for explaining the positional relationship of the silicon-based nanowire 41 in the first thin film transistor.
  • the implementation of the array substrate can refer to the implementation of the aforementioned preparation method, and the repetition will not be repeated.
  • embodiments of the present disclosure also provide a display panel, including the above-mentioned array substrate provided by the embodiments of the present disclosure.
  • the display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the display device reference may be made to the above-mentioned embodiment of the array substrate, and the repetition is not repeated here.
  • the first thin film transistor may be located in the frame area of the display panel, so that the width of the frame can be reduced.
  • An array substrate, a preparation method thereof, and a display panel provided by embodiments of the present disclosure include: forming a first thin film transistor and a second thin film transistor on a base substrate.
  • the catalyst particles and silicon When forming the active layer of the first thin film transistor, the catalyst particles and silicon have a eutectic point, and the Gibbs free energy of amorphous silicon is greater than the Gibbs free energy of crystalline silicon (silicon-based nanowires) as the driving force.
  • the molten catalyst particles absorb amorphous silicon to form a supersaturated silicon eutectic, so that silicon nucleates and grows into silicon-based nanowires.
  • the amorphous silicon film grows linearly along the guiding structure under the action of the catalyst particles, thereby obtaining high-density, high-uniformity silicon-based nanowires.
  • the width of silicon-based nanowires can also be controlled by controlling the size of the catalyst particles and the thickness of the amorphous silicon film.
  • the preparation of silicon-based nanowire thin film transistors with uniform and controllable dimensions can be realized.
  • the first active layer and the second active layer are made of different materials, so that different thin film transistors have different advantages, so as to increase the practical range of the array substrate.

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Abstract

一种阵列基板、其制备方法及显示面板，包括：在衬底基板（10）上形成第一薄膜晶体管和第二薄膜晶体管。在形成第一薄膜晶体管的有源层（12）时，利用催化剂颗粒（021）与硅具有共熔点、以非晶硅的吉布斯自由能大于结晶硅(硅基纳米线)的吉布斯自由能为驱动力、通过熔融的催化剂颗粒（021）吸收非晶硅形成过饱和硅共熔体，使硅成核生长成为硅基纳米线（41）。并且硅基纳米线（41）在生长过程中，非晶硅薄膜（40）在催化剂颗粒（021）的作用下沿着导向结构（01）线性生长，从而获得高密度、高均一性的硅基纳米线（41）。另外，通过对催化剂颗粒（021）的尺寸以及非晶硅薄膜（40）的厚度进行控制还可以实现对硅基纳米线（41）的宽度进行控制，从而实现尺度均一可控的硅基纳米线薄膜晶体管的制备。

Description

阵列基板、其制备方法及显示面板
相关申请的交叉引用
本公开要求在2019年05月13日提交中国专利局、申请号为201910392488.X、申请名称为“一种阵列基板、其制备方法及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤指一种阵列基板、其制备方法及显示面板。
背景技术
硅基纳米线为近年来开发的新型硅基半导体材料，具有一维的尺度结构，更加优异的半导体特性。采用硅基纳米线作为薄膜晶体管沟道可以获得更高的迁移率以及更加稳定的特性。
硅基纳米线作为薄膜晶体管沟道材料，其尺度的均一性、可控性尤为重要。为满足显示器件的均一性需求，如何获得尺度均一可控的硅基纳米线薄膜晶体管已成为人们研究的热点。
发明内容
本公开实施例提供的一种阵列基板的制备方法，包括：在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管；形成所述第一薄膜晶体管包括：在衬底基板上形成第一栅电极的图形、第一有源层的图形、第一源电极和第一漏电极的图形；形成所述第二薄膜晶体管包括：在衬底基板上形成第二栅电极的图形、第二有源层的图形、第二源电极和第二漏电极的图形；
所述第一有源层的材料与所述第二有源层的材料不相同；
形成所述第一有源层的图形，具体包括：
形成导向结构；
在所述导向结构至少一侧形成至少一个催化剂颗粒的图形；所述催化剂颗粒与硅具有共熔点；
形成覆盖所述催化剂颗粒和所述导向结构的非晶硅薄膜；
对所述非晶硅薄膜进行退火，使非晶硅由所述催化剂颗粒开始沿所述导向结构的延伸方向生长形成硅基纳米线；
去除所述催化剂颗粒，并保留第一预设区域内的所述非晶硅薄膜和所述硅基纳米线，形成所述第一有源层的图形，所述催化剂颗粒位于所述第一预设区域外。
可选地，在本公开实施例提供的制备方法中，所述第二有源层的材料为低温多晶硅材料、碳纳米管材料或者氧化物半导体材料。
可选地，在本公开实施例提供的制备方法中，所述第一栅电极的图形与所述第二栅电极的图形通过一次构图工艺形成；
所述第一源电极的图形、所述第一漏电极的图形、所述第二源电极的图形和所述第二漏电极的图形通过一次构图工艺同时形成。
可选地，在本公开实施例提供的制备方法中，所述第二有源层的材料为低温多晶硅材料；
在形成所述第一有源层的图形的同时形成所述第二有源层的图形，具体为：
在对所述非晶硅薄膜进行退火之后，对形成有所述硅基纳米线的非晶硅薄膜进行准分子激光退火处理，使所述非晶硅薄膜转换为低温多晶硅薄膜；
去除所述催化剂颗粒，并对所述低温多晶硅薄膜进行构图时，保留第二预设区域的低温多晶硅薄膜形成第二有源层的图形。
可选地，在本公开实施例提供的制备方法中，形成的所述导向结构为多个，所述多个导向结构中的任一个均沿第一方向延伸，所述多个导向结构垂直于所述第一方向的截面包括凹凸结构，且所述凹凸结构的每一凹部内形成有一个所述催化剂颗粒。
可选地，在本公开实施例提供的制备方法中，形成的所述导向结构为多个，所述多个导向结构中的任一个均沿第一方向延伸，所述多个导向结构垂直于所述第一方向的截面为包括至少一个台阶的阶梯结构，且所述阶梯结构的每一台阶上形成有一个所述催化剂颗粒。
可选地，在本公开实施例提供的制备方法中，在形成所述第一栅电极的图形之后形成所述第一有源层的图形；
所述形成导向结构，具体包括：
在形成所述第一栅电极的图形之后，且在形成所述第一有源层的图形之前，形成第一栅极绝缘层；
对所述第一栅极绝缘层进行构图，形成所述导向结构。
可选地，在本公开实施例提供的制备方法中，在形成所第一述栅电极的图形之后形成所述第一有源层的图形；
所述形成导向结构，具体包括：
形成垂直于所述第一方向的截面包括凹凸结构的第一栅电极的图形，或者，形成垂直于所述第一方向的截面包括至少一个台阶的阶梯结构的第一栅电极的图形；
在形成所述第一栅电极的图形之后，且在形成所述第一有源层的图形之前，形成第一栅极绝缘层，所述第一栅电极的图形和覆盖于所述第一栅电极上的所述第一栅极绝缘层构成所述导向结构。
可选地，在本公开实施例提供的制备方法中，在形成所述第一栅电极的图形之前形成所述第一有源层的图形；
所述形成导向结构，具体包括：在所述衬底基板上形成介电层，对所述介电层进行构图，形成所述多个导向结构。
可选地，在本公开实施例提供的制备方法中，所述催化剂颗粒的材料包括铟、锡、镍或氧化铟。
可选地，在本公开实施例提供的制备方法中，所述催化剂颗粒的粒径为5nm～10μm。
可选地，在本公开实施例提供的制备方法中，形成所述催化剂颗粒的图形，具体包括：
在形成有所述导向结构的衬底基板上形成所述催化剂膜层；
在所述催化剂膜层上形成压印胶；
对所述压印胶进行纳米压印工艺，形成压印胶颗粒的图形；
以所述压印胶颗粒的图形为掩膜图形，对所述催化剂膜层进行刻蚀，形成所述催化剂颗粒的图形。
可选地，在本公开实施例提供的制备方法中，形成所述催化剂颗粒的图形，具体包括：
在形成有所述导向结构的衬底基板上形成所述催化剂膜层；
在所述催化剂膜层上形成压印胶；
对所述压印胶进行纳米压印工艺，形成压印胶线的图形；其中所述压印胶线的延伸方向与所述导向结构的延伸方向垂直；
以所述压印胶线的图形为掩膜图形，对所述催化剂膜层进行刻蚀，形成催化剂线的图形；
对所述催化剂线进行等离子体轰击，形成所述催化剂颗粒的图形。
可选地，在本公开实施例提供的制备方法中，所述催化剂颗粒与硅的共熔点的温度范围在200℃～1000℃；
对所述非晶硅薄膜进行退火时，退火温度为200℃-600℃。
相应地，本公开实施例还提供一种阵列基板，所述阵列基板采用本公开实施例提供的上述任一种制备方法制备；所述阵列基板包括：
位于衬底基板上的第一薄膜晶体管，所述第一薄膜晶体管包括：第一栅电极、第一有源层、第一源电极和第一漏电极；所述第一有源层下方设置有至少一个沿第一方向延伸的导向结构，所述第一有源层的材料包括硅基纳米线，所述硅基纳米线的延伸方向与所述导向结构的延伸方向相同；
位于所述衬底基板上的第二薄膜晶体管；所述第二薄膜晶体管包括：第二栅电极、第二有源层、第二源电极和第二漏电极，所述第二有源层的材料 与所述第一有源层的材料不相同。
可选地，在本公开实施例提供的阵列基板中，所述导向结构沿所述第一方向的长度大于所述硅基纳米线沿所述第一方向的长度。
可选地，在本公开实施例提供的阵列基板中，所述第一源电极和所述第一漏电极的连线方向与所述硅基纳米线的延伸方向相同。
可选地，在本公开实施例提供的阵列基板中，所述第二有源层的材料为低温多晶硅材料、碳纳米管材料或者氧化物半导体材料。
相应地，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述阵列基板。
附图说明
图1为本公开实施例提供的制备方法中的部分步骤流程图；
图2a为本公开实施例提供的多个导向结构的结构示意图；
图2b为本公开实施例提供的多个导向结构的结构示意图；
图3a为图2a所示的多个导向结构沿AA’方向的一种截面示意图；
图3b为图2b所示的多个导向结构沿AA’方向的另一种截面示意图；
图4a至图4d为本公开实施例提供的在制备催化剂颗粒时执行各步骤后的结构示意图；
图5a至图5c为本公开实施例提供的在制备催化剂颗粒时执行各步骤后的结构示意图；
图6a至图6h为本公开实施例提供的在制备阵列基板时执行各步骤后的结构示意图；
图7为本公开实施例提供的阵列基板的结构示意图；
图8为本公开实施例提供的导向结构的一种结构示意图；
图9a至图9i为本公开实施例提供的在制备阵列基板时执行各步骤后的结构示意图；
图10为本公开实施例提供的阵列基板的结构示意图；
图11a为本公开实施例提供的阵列基板中第一薄膜晶体管的结构示意图；
图11b为图11a所示的第一薄膜晶体管沿CC’方向的截面示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种阵列基板的制备方法，包括：在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管；其中形成第一薄膜晶体管包括：在衬底基板上形成第一栅电极的图形、第一有源层的图形、第一源电极和第一漏电极的图形；形成第二薄膜晶体管包括：在衬底基板上形成第二栅电极的图形、第二有源层的图形、第二源电极和第二漏电极的图形；
第一有源层的材料与第二有源层的材料不相同；
形成第一有源层的图形，如图1所示，具体包括：
S101、形成导向结构；
S102、在导向结构的至少一侧形成至少一个催化剂颗粒的图形；其中，催化剂颗粒与硅具有共熔点；
S103、形成覆盖催化剂颗粒和导向结构的非晶硅薄膜；
S104、对非晶硅薄膜进行退火，使非晶硅由催化剂颗粒开始沿导向结构的延伸方向生长形成硅基纳米线；
S105、去除催化剂颗粒，并保留第一预设区域内的非晶硅薄膜和硅基纳米线，形成第一有源层的图形，其中，催化剂颗粒位于第一预设区域外。
本公开实施例的提供的阵列基板的制备方法，包括：在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管。在形成第一薄膜晶体管的有源层时，利 用催化剂颗粒与硅具有共熔点、以非晶硅的吉布斯自由能大于结晶硅(硅基纳米线)的吉布斯自由能为驱动力、通过熔融的催化剂颗粒吸收非晶硅形成过饱和硅共熔体，使硅成核生长成为硅基纳米线。并且硅基纳米线在生长过程中，非晶硅薄膜在催化剂颗粒的作用下沿着导向结构线性生长，从而获得高密度、高均一性的硅基纳米线。另外，通过对催化剂颗粒的尺寸以及非晶硅薄膜的厚度进行控制还可以实现对硅基纳米线的宽度进行控制。从而实现尺度均一可控的硅基纳米线薄膜晶体管的制备。
另外，第一有源层和第二有源层采用不同的材料进行制作，使不同薄膜晶体管发挥不同的优势，以增加阵列基板的实用范围。
在具体实施时，由于硅基纳米线与多晶硅相比具有更加优异的半导体特性与更小的尺寸维度，因此，第一薄膜晶体管的尺寸可以做的相对较小，因此，在面板的边框区域应用第一薄膜晶体管，可以获得更小的边框尺寸；在开关晶体管中应用第一薄膜晶体管，可以获得更快的开关速度，获得更高的刷新频率；当第一薄膜晶体管应用于背板中的大尺寸晶体管时，可以避免半导体层发热导致器件特性漂移。
可选地，在本公开实施例提供的制备方法中，第二有源层的材料可以为低温多晶硅材料、碳纳米管材料或者氧化物半导体材料中的任意一种或者多种。
在具体实施时，低温多晶硅具有较高的迁移率与稳定性，但是在大尺寸面板中，均匀性比较难控制。碳纳米管同样具有较高的迁移率，并且可以实现柔性显示。氧化物半导体材料的迁移率相对低一点，但是大尺寸面板中可以保证均一性好、漏电流低、透明以及制作工艺简单。因此，第二有源层的材料可以根据实际需求进行选择。第二有源层与第一有源层配合使用，满足不同的电路需求，如调控薄膜晶体管的亚阈值摆幅SS，薄膜晶体管的关态电流Ioff，薄膜晶体管的迁移率等。
在具体实施时，为了简化制作工艺和节约生产成本，第一薄膜晶体管和第二薄膜晶体管中，具有相同功能的膜层尽可能的同层进行制备。
可选地，在本公开实施例提供的制备方法中，第一栅电极的图形与第二栅电极的图形通过一次构图工艺形成；
第一源电极的图形、第一漏电极的图形、第二源电极的图形和第二漏电极的图形通过一次构图工艺同时形成。
在具体实施时，在本公开实施例提供的上述制备方法中，当第二有源层的材料为低温多晶硅材料时，为了简化工艺步骤以及降低成本，第一有源层和第二有源层可以采用同一层非晶硅薄膜进行制备。
具体地，在本公开实施例提供的制备方法中，第二有源层的材料为低温多晶硅材料；
第二有源层的图形和第一有源层的图形通过一次构图工艺同时形成，具体为：
在对非晶硅薄膜进行退火之后，对形成有硅基纳米线的非晶硅薄膜进行准分子激光退火处理，使非晶硅薄膜转换为低温多晶硅薄膜；
去除催化剂颗粒，并对低温多晶硅薄膜进行构图，保留第一预设区域的硅基纳米线和低温多晶硅薄膜形成第一有源层的图形，保留第二预设区域的低温多晶硅薄膜形成第二有源层的图形。
需要说明的是，在本公开实施例提供的制备方法中，第一预设区域为用于形成第一有源层的区域，第二预设区域为用于形成第二有源层的区域。
具体地，在本公开实施例提供的制备方法中，导向结构越多，意味着形成的硅基纳米线越多，因此，形成多个导向结构可以保证第一有源层中有多条硅基纳米线，从而提升第一薄膜晶体管的迁移率。
可选地，在本公开实施例提供的制备方法中，形成多个导向结构01，多个导向结构中的任一个导向结构01均沿第一方向X延伸，如图2a所示；所述多个导向结构的材料可以相同。图3a为图2a所示的多个导向结构沿AA’方向的一种截面示意图，如图3a所示，多个导向结构01垂直于第一方向的截面包括至少一个凹凸结构，所有凹凸结构中的所有凸部的表面几乎等高，所有凹部的表面几乎等高；在凹凸结构的每一凹部内形成有一个催化剂颗粒 021，催化剂颗粒021在垂直于第一方向X的截面尺寸不大于所在凹部的截面尺寸。
可以理解的是，也可以直接形成具有一体结构的导向结构，该导向结构沿第一方向延伸的顶面包括如图3a所示的凹凸结构。
可选地，在本公开实施例提供的制备方法中，形成多个导向结构01，多个导向结构中的任一个导向结构01均沿第一方向X延伸，如图2b所示，；所述多个导向结构的材料可以相同。图3b为图2b所示的多个导向结构沿AA’方向的一种截面示意图，如图3b所示，导向结构01垂直于第一方向的截面为包括至少一个台阶的阶梯结构，且阶梯结构的每一台阶上形成有一个催化剂颗粒021，催化剂颗粒021在垂直于第一方向X的截面尺寸不大于所在台阶的截面尺寸。可以理解的是，也可以直接形成具有一体结构的导向结构，该导向结构沿第一方向延伸的顶面包括如图3b所示的至少一个台阶的阶梯结构。
在具体实施时，如图3a和图3b所示，导向结构01垂直于第一方向的截面包括凹凸结构或包括至少一个台阶的阶梯结构，可以实现硅基纳米线的多层次分布，从而提升沟道宽度的同时可以解决散热问题。
当然，在具体实施时，多个导向结构垂直于第一方向的截面可以同时包括凹凸结构和阶梯结构，在此不作限定。
可以理解的是，多个导向结构可以通过分次制作，如分别形成多个条状结构；如果多个导向结构的材质相同，其还可以最终形成一体结构；多个导向结构也可以通过一次成膜工艺后进行图案化构成一体成型。
需要说明的是，在本公开实施例提供的制备方法中，每个导向结构沿第一方向延伸的侧面也可以是一个平面，在具体实施时，侧面与底面的夹角优选大于或等于60°，这样可以保证后续非晶硅薄膜能够覆盖位于导向结构侧面的催化剂颗粒，以保证硅基纳米线的正常生长。
可选地，在本公开实施例提供的制备方法中，在形成第一栅电极的图形之后形成第一有源层的图形；
形成多个导向结构，具体包括：
形成第一栅电极的图形之后，在形成第一有源层的图形之前，形成第一栅极绝缘层；
对第一栅极绝缘层进行构图，形成导向结构。
在具体实施时，通过对第一栅极绝缘层进行构图，形成导向结构，可以避免由于单独增加用于制备导向结构的膜层而导致的阵列基板的厚度增加。
可选地，在本公开实施例提供的制备方法中，在形成所第一述栅电极的图形之后形成第一有源层的图形；
形成多个导向结构，具体包括：
形成垂直于第一方向的截面包括凹凸结构的第一栅电极的图形，或者，形成垂直于第一方向的截面包括至少一个台阶的阶梯结构的第一栅电极的图形；
在形成第一栅电极的图形之后，且在形成第一有源层的图形之前，形成第一栅极绝缘层，第一栅电极的图形和覆盖于第一栅电极上的第一栅极绝缘层构成导向结构。
在具体实施时，将第一栅电极的表面图案化以构成多个导向结构，覆盖于第一栅电极上的第一栅极绝缘层由于第一栅电极具有导向结构的形貌而具有相应的结构。而通过将第一栅电极的图形构成导向结构，可以避免由于单独增加用于制备导向结构的膜层而导致的阵列基板的厚度增加，并且还不用增加构图工艺，仅是将现有栅电极的图形作了改变。
在具体实施时，在本公开实施例提供的制备方法中，第一栅极绝缘层复用为第二薄膜晶体管的栅极绝缘层。
可选地，在本公开实施例提供的制备方法中，在形成第一栅电极的图形之前形成第一有源层的图形；
形成多个导向结构，具体包括：在衬底基板上形成介电层，对介电层进行构图，形成多个导向结构。
在具体实施时，在本公开实施例提供的制备方法中，介电层可以通过沉 积的方法形成，在此不作限定。
在具体实施时，介电层的材料可以为氧化铝(AlOx)，氧化硅(SiOx)，氮化硅(SiNx)等，在此不作限定。
进一步地，在具体实施时，介电层可以是阵列基板的缓冲层，当然也可以在形成介电层之前，先在衬底基板上形成缓冲层，在不作限定。
可选地，在本公开实施例提供的制备方法中，催化剂颗粒的材料包括铟、锡、镍或氧化铟，在此不作限定。
可选地，在本公开实施例提供的制备方法中，催化剂颗粒的粒径可以控制在5nm～10μm之间，例如5nm、10nm、50nm、100nm、500nm、1μm、10μm等，在此不作限定。
可选地，在本公开实施例提供的制备方法中，形成催化剂颗粒的图形，具体包括：
在形成有导向结构01的衬底基板10上形成催化剂膜层02，如图4a所示；
在催化剂膜层02上形成压印胶03，如图4b所示；
对压印胶03进行纳米压印工艺，形成压印胶颗粒031的图形，如图4c所示；
以压印胶颗粒031的图形为掩膜图形，对催化剂膜层02进行刻蚀，形成催化剂颗粒021的图形，如图4d所示。
或者，可选地，在本公开实施例提供的制备方法中，形成催化剂颗粒的图形，具体包括：
在形成有导向结构01的衬底基板10上形成催化剂膜层02，如图4a所示；
在催化剂膜层02上形成压印胶03，如图4b所示；
对压印胶03进行纳米压印工艺，形成压印胶线032的图形；其中压印胶线032的延伸方向与导向结构01的延伸方向垂直，如图5a所示；
以压印胶线032的图形为掩膜图形，对催化剂膜层02进行刻蚀，形成催化剂线022的图形，如图5b所示；
对催化剂线进行等离子体轰击，形成催化剂颗粒021的图形，如图5c和 图4d所示，其中图4d为图5c沿B-B’方向的截面图。
在具体实施时，采用纳米压印工艺形成催化剂颗粒的图形，可以实现图形的高精细化，保证催化剂颗粒的均一和可控，以保证硅基纳米线的均匀生长。
可选地，在本公开实施例提供的制备方法中，催化剂线的线宽控制在50nm～1000nm之间，例如50nm、100nm、500nm、1000nm等，在此不作限定。
在具体实施时，催化剂颗粒的粒径根据需要的硅基纳米线的线宽确定，一般催化剂颗粒的粒径接近硅基纳米线的线宽。
当然在，具体实施时，也可以采用光刻工艺形成催化剂颗粒的图形。因此，可选地，在本公开实施例提供的制备方法中，形成催化剂颗粒的图形，具体包括：
在形成有导向结构的衬底基板上形成催化剂膜层；
在催化剂膜层上形成光刻胶；
对光刻胶进行曝光、显影工艺，形成光刻胶颗粒的图形；
以光刻胶颗粒的图形为掩膜图形，对催化剂膜层进行刻蚀，形成催化剂颗粒的图形。
在具体实施时，在本公开实施例提供的制备方法中，催化剂颗粒形成于导向结构沿其延伸方向的一端，这样可以保证硅基纳米线从导向结构的一端开始向另一端延伸生长。
进一步地，在本公开实施例提供的制备方法中，导向结构沿其延伸方向可以是直线型的，也可以是曲线型，在此不作限定。
在具体实施时，在本公开实施例提供的制备方法中，形成的第一薄膜晶体管的结构可以为底栅型结构，也可以为顶栅型结构；同样，形成的第二薄膜晶体管的结构可以为底栅型结构，也可以为顶栅型结构，在此不作限定。为了简化工艺以及降低成本，形成的第一薄膜晶体管和第二薄膜晶体管的结构均为底栅型结构，或均为顶栅型结构。材料相同且具有相同功能的膜层可 以采用一次构图工艺来形成。
下面通过具体实施例说明本公开实施例提供的制备方法。
以第一薄膜晶体管和第二薄膜晶体管均为底栅型晶体管为例，本公开提供的一些实施例具体包括以下步骤：
步骤1、如图6a所示，通过一次构图工艺在衬底基板10上形成第一栅电极11和第二栅电极21的图形。
在具体实施时，栅电极的材料可以为钼(Mo)，铝(Al)，铜(Cu)，镍(Ti)等金属或合金，厚度可以控制在50nm～5000nm之间，在此不作限定。
步骤2、如图6b所示，形成栅极绝缘层30。
在具体实施时，栅极绝缘层的材料为介电材料，厚度可以控制在50nm～5000nm之间，在此不作限定。
步骤3、如图6c所示，在栅极绝缘层30中形成导向结构01的图形。
在具体实施时，导向结构的数量可以是一个，也可以是多个，在此不作限定。
在具体实施时，每个导向结构沿第一方向延伸，且导向结构沿第一方向延伸的侧面可以包括阶梯结构，或者为与底面的夹角为大于或等于60度角的平面，或者，导向结构沿第一方向延伸的表面可以包括凹凸结构，在此不作限定。
步骤4、如图6d所示，在导向结构01的至少一侧形成催化剂颗粒021的图形。
在具体实施时，可以在催化剂膜层上形成压印胶，对压印胶进行纳米压印工艺，形成压印胶颗粒的图形；以压印胶颗粒的图形为掩膜图形对催化剂膜层进行刻蚀，形成催化剂颗粒的图形。或者对压印胶进行纳米压印工艺，形成压印胶线的图形，以压印胶线的图形为掩膜图形对催化剂膜层进行刻蚀，形成催化剂线的图形，对催化剂线进行等离子体轰击，形成催化剂颗粒的图形。当然，也可以采用光刻工艺形成催化剂颗粒的图形。
进一步地，催化剂颗粒的粒径可以控制在5nm～10μ1之间，例如5nm、 10nm、50nm、100nm、500nm、1μ0、10μ0等，在此不作限定。催化剂颗粒的材料包括铟、锡、镍或氧化铟，在此不作限定。
步骤5、如图6e所示，形成覆盖催化剂颗粒021以及导向结构01非晶硅薄膜40；并对非晶硅薄膜40进行退火，使非晶硅由催化剂颗粒021开始沿导向结构01的延伸方向生长形成硅基纳米线41。
在具体实施时，采用等离子增强型化学气相淀积(PECVD)法沉积5nm～5000nm非晶硅薄膜，进一步非晶硅薄膜的厚度可以控制在10nm～1000nm之间，在此不作限定。
在具体实施时，催化剂颗粒与硅的共熔点的温度范围可以在200℃～1000℃，退火温度可以控制在200℃～600℃之间，在此不作限定。进一步地，退火温度可以控制在250℃～450℃之间。
步骤6、如图6f所示，去除催化剂颗粒021，并保留第一预设区域内的非晶硅薄膜(图中未视出)和硅基纳米线41，形成第一有源层12的图形。
步骤7、如图6g所示，形成第二有源层22的图形。
具体地，第二有源层的材料为碳纳米管材料，可以采用旋涂与图形化刻蚀工艺形成，第二有源层的材料的厚度控制在1nm～1000nm之间。
具体地，第二有源层的材料为氧化物半导体材料，可以采用沉积与图形化刻蚀工艺形成。
步骤8、如图6h所示，通过一次构图工艺形成第一源电极13、第一漏电极14、第二源电极23和第二漏电极24的图形。
在具体实施时，源电极和漏电极的材料可以为钼(MO)，铝(Al)，铜(Cu)，镍(Ti)等金属或合金，在此不作限定。
在上述实施例中，如图7所示，在形成第一源电极13、第一漏电极14、第二源电极23和第二漏电极24之前，还可以包括形成刻蚀阻挡层50的图形。第一源电极13和第一漏电极14通过贯穿刻蚀阻挡层50的过孔与第一有源层12连接，第二源电极23和第二漏电极24通过贯穿刻蚀阻挡层50的过孔与第二有源层22连接。
在具体实施时，刻蚀阻挡层的材料为介电材料，例如氮化硅(SiNX)，氧化硅(SiOx)，氧化铝(AllOx)等，厚度控制可以在50nm～5000nm之间，在此不作限定。
需要说明的是，在本公开实施例提供的上述制备方法中，第一有源层和第二有源层的形成顺序可以互换。即步骤7在步骤5和步骤6之前。
进一步地，在本公开实施例提供的上述制备方法中，当第二有源层的材料为低温多晶硅时，在步骤5之后，步骤8之前包括：
步骤6’、对形成有硅基纳米线的非晶硅薄膜进行准分子激光退火处理，使非晶硅薄膜转换为低温多晶硅薄膜；
步骤7’、去除催化剂颗粒，并对低温多晶硅薄膜进行构图，保留第一预设区域的硅基纳米线和低温多晶硅薄膜形成第一有源层的图形，保留第二预设区域的低温多晶硅薄膜形成第二有源层的图形。
需要说明的是，当硅基纳米线的线宽与多晶硅薄膜的厚度接近时，可以通过一次构图工艺形成第一有源层和第二有源层的图形，当硅基纳米线的线宽与多晶硅薄膜的厚度相差较多时，可以采用灰色调掩膜版或者半色调掩膜版通过一次构图工艺形成，当然，也可以通过两次构图工艺形成，在此不作限定。
进一步地，在本公开实施例提供的上述制备方法中，如图8所示，导向结构01也可以由第一栅电极11和栅极绝缘层30构成。即在步骤1中将第一栅电极11的图形制备成与导向结构01的图形相似，步骤2中在第一栅电极11上形成栅极绝缘层30，使栅极绝缘层30具有与第一栅电极11相应的图形，从而可以省去步骤3对栅极绝缘层30进行构图的工艺。
以第一薄膜晶体管和第二薄膜晶体管均为顶栅型晶体管为例，本公开提供的一些实施例具体包括以下步骤：
步骤01、形成导向结构01的图形。
需要说明的是，在图9a中，虚线矩形框示意出导向结构01的凹部部分， 图9b为图9a沿BB’方向的截面示意图。
在具体实施时，导向结构采用介电材料，如SiOx，SiNx，Al2O3等，厚度控制在20nm～5000nm之间，在此不作限定。
步骤02、如图9a和图9b所示，在导向结构01的至少一侧形成催化剂颗粒021的图形，具体地，在导向结构01的凹部部分或台阶部分，形成催化剂颗粒021的图形。
步骤03、如图9c所示，形成覆盖催化剂颗粒021以及导向结构01非晶硅薄膜40；并对非晶硅薄膜40进行退火，使非晶硅由催化剂颗粒021开始沿导向结构01的延伸方向生长形成硅基纳米线41。
步骤04、如图9d所示，去除催化剂颗粒021，并保留第一预设区域内的非晶硅薄膜(图中未视出)和硅基纳米线41，形成第一有源层12的图形。
步骤05、如图9e所示，形成第二有源层22的图形。
步骤06、如图9f所示，形成栅极绝缘层30。
步骤07、如图9g所示，形成第一栅电极11和第二栅电极12的图形。
步骤08、如图9h所示，形成蚀阻挡层50的图形。
步骤08、如图9i所示，通过一次构图工艺形成第一源电极13、第一漏电极14、第二源电极23和第二漏电极24的图形。第一源电极13和第一漏电极14通过贯穿刻蚀阻挡层50和栅极绝缘层30的过孔与第一有源层12连接，第二源电极23和第二漏电极24通过贯穿刻蚀阻挡层50的和栅极绝缘层30过孔与第二有源层22连接。
在上述实施例中，在形成导向结构之前还可以形成缓冲层，用来隔离衬底基板中杂质。
当然，在具体实施时，也可以对缓冲层图案化处理构成导向结构，例如缓冲层采用氮化硅(SiNX)或氧化硅(SiOx)形成，厚度控制在10nm～1000nm之间，然后通过构图工艺形成导向结构。这样缓冲层既可以隔离衬底基板中杂质，又可以省去单独用于制作导向结构的膜层。
在具体实施时，顶栅型薄膜晶体管和底栅型薄膜晶体管在制作工艺上仅 是膜层先后制作顺序的改变，因此，上述顶栅型薄膜晶体管中各膜层的制备可以参考上述底栅型薄膜晶体管中具有相同功能的膜层的制备。
在具体实施时，当上述阵列基板应用于显示面板时，在形成第一薄膜晶体管和第二薄膜晶体管之后，如图10所示，还包括在衬底基板10上形成平坦化层60、电极层70等，在此不作限定。
在具体实施时，本公开不限于以上所举结构，同样适合于第一薄膜晶体管为底栅型晶体管，第二薄膜晶体管为顶栅型晶体管，或者，第一薄膜晶体管为顶栅型晶体管，第二薄膜晶体管为底栅型晶体管等的TFT结构，本领域的技术人员可以在不出现知识创造的前提下了解，在此不在赘述。
基于同一发明构思，本公开实施例还提供了一种阵列基板，阵列基板采用本公开实施例提供的上述任一种制备方法制备；其中，如图6h、图7和图9i所示，阵列基板包括位于衬底基板10上的第一薄膜晶体管和第二薄膜晶体管；第一薄膜晶体管包括：第一栅电极11、第一有源层12、第一源电极13和第一漏电极14；第二薄膜晶体管包括：第二栅电极21、第二有源层22、第二源电极23和第二漏电极24；
在第一薄膜晶体管中，第一有源层12下方设置有至少一个沿第一方向延伸的导向结构01，第一有源层12的材料包括硅基纳米线，且硅基纳米线的延伸方向与导向结构01的延伸方向相同；
第二有源层22的材料与第一有源层12的材料不相同。
可选地，在本公开实施例提供的阵列基板中，第二有源层的材料可以为低温多晶硅材料、碳纳米管材料或者氧化物半导体材料。
在具体实施时，参见图11a和图11b所示，在第一薄膜晶体管中，导向结构01沿第一方向X的长度大于硅基纳米线沿第一方向X的长度，且导向结构01沿第一方向X延伸，硅基纳米线41的延伸方向与导向结构01的延伸方向相同，为第一源电极13与第一漏电极14的连线方向。图11a和图11b仅是为了说明硅基纳米线41在第一薄膜晶体管中的位置关系。
在具体实施时，由于该阵列基板解决问题的原理与前述一种阵列基板的 制备方法相似，因此该阵列基板的实施可以参见前述制备方法的实施，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述阵列基板。该显示面板可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
在具体实施时，第一薄膜晶体管可以位于显示面板的边框区域，这样可以减小边框的宽度。
本公开实施例提供的一种阵列基板、其制备方法及显示面板，包括：在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管。在形成第一薄膜晶体管的有源层时，利用催化剂颗粒与硅具有共熔点、以非晶硅的吉布斯自由能大于结晶硅(硅基纳米线)的吉布斯自由能为驱动力、通过熔融的催化剂颗粒吸收非晶硅形成过饱和硅共熔体，使硅成核生长成为硅基纳米线。并且硅基纳米线在生长过程中，非晶硅薄膜在催化剂颗粒的作用下沿着导向结构线性生长，从而获得高密度、高均一性的硅基纳米线。另外，通过对催化剂颗粒的尺寸以及非晶硅薄膜的厚度进行控制还可以实现对硅基纳米线的宽度进行控制。从而实现尺度均一可控的硅基纳米线薄膜晶体管的制备。另外，第一有源层和第二有源层采用不同的材料进行制作，使不同薄膜晶体管发挥不同的优势，以增加阵列基板的实用范围。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种阵列基板的制备方法，其中，包括：在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管；形成所述第一薄膜晶体管包括：在衬底基板上形成第一栅电极的图形、第一有源层的图形、第一源电极和第一漏电极的图形；形成所述第二薄膜晶体管包括：在衬底基板上形成第二栅电极的图形、第二有源层的图形、第二源电极和第二漏电极的图形；
    所述第一有源层的材料与所述第二有源层的材料不相同；
    形成所述第一有源层的图形，具体包括：
    形成导向结构；
    在所述导向结构至少一侧形成至少一个催化剂颗粒的图形；所述催化剂颗粒与硅具有共熔点；
    形成覆盖所述催化剂颗粒和所述导向结构的非晶硅薄膜；
    对所述非晶硅薄膜进行退火，使非晶硅由所述催化剂颗粒开始沿所述导向结构的延伸方向生长形成硅基纳米线；
    去除所述催化剂颗粒，并保留第一预设区域内的所述非晶硅薄膜和所述硅基纳米线，形成所述第一有源层的图形，所述催化剂颗粒位于所述第一预设区域外。
  2. 如权利要求1所述的制备方法，其中，所述第二有源层的材料为低温多晶硅材料、碳纳米管材料或者氧化物半导体材料。
  3. 如权利要求2所述的制备方法，其中，所述第一栅电极的图形与所述第二栅电极的图形通过一次构图工艺形成；
    所述第一源电极的图形、所述第一漏电极的图形、所述第二源电极的图形和所述第二漏电极的图形通过一次构图工艺同时形成。
  4. 如权利要求3所述的制备方法，其中，所述第二有源层的材料为低温多晶硅材料；
    在形成所述第一有源层的图形的同时形成所述第二有源层的图形，具体 为：
    在对所述非晶硅薄膜进行退火之后，对形成有所述硅基纳米线的非晶硅薄膜进行准分子激光退火处理，使所述非晶硅薄膜转换为低温多晶硅薄膜；
    去除所述催化剂颗粒，并对所述低温多晶硅薄膜进行构图时，保留第二预设区域的低温多晶硅薄膜形成第二有源层的图形。
  5. 如权利要求1所述的制备方法，其中，形成的所述导向结构为多个，多个导向结构中的任一个均沿第一方向延伸，所述多个导向结构垂直于所述第一方向的截面包括凹凸结构，且所述凹凸结构的每一凹部内形成有一个所述催化剂颗粒。
  6. 如权利要求1所述的制备方法，其中，形成的所述导向结构为多个，多个导向结构中的任一个均沿第一方向延伸，所述多个导向结构垂直于所述第一方向的截面为包括至少一个台阶的阶梯结构，且所述阶梯结构的每一台阶上形成有一个所述催化剂颗粒。
  7. 如权利要求5或6所述的制备方法，其中，在形成所述第一栅电极的图形之后形成所述第一有源层的图形；
    所述形成导向结构，具体包括：
    在形成所述第一栅电极的图形之后，且在形成所述第一有源层的图形之前，形成第一栅极绝缘层；
    对所述第一栅极绝缘层进行构图，形成所述导向结构。
  8. 如权利要求5或6所述的制备方法，其中，在形成所第一述栅电极的图形之后形成所述第一有源层的图形；
    所述形成导向结构，具体包括：
    形成垂直于所述第一方向的截面包括凹凸结构的第一栅电极的图形，或者，形成垂直于所述第一方向的截面包括至少一个台阶的阶梯结构的第一栅电极的图形；
    在形成所述第一栅电极的图形之后，且在形成所述第一有源层的图形之前，形成第一栅极绝缘层，所述第一栅电极的图形和覆盖于所述第一栅电极 上的所述第一栅极绝缘层构成所述导向结构。
  9. 如权利要求5或6所述的制备方法，其中，在形成所述第一栅电极的图形之前形成所述第一有源层的图形；
    所述形成导向结构，具体包括：在所述衬底基板上形成介电层，对所述介电层进行构图，形成所述多个导向结构。
  10. 如权利要求1-6任一项所述的制备方法，其中，所述催化剂颗粒的材料包括铟、锡、镍或氧化铟。
  11. 如权利要求1-6任一项所述的制备方法，其中，所述催化剂颗粒的粒径为5nm～10μm。
  12. 如权利要求1-6任一项所述的制备方法，其中，形成所述催化剂颗粒的图形，具体包括：
    在形成有所述导向结构的衬底基板上形成所述催化剂膜层；
    在所述催化剂膜层上形成压印胶；
    对所述压印胶进行纳米压印工艺，形成压印胶颗粒的图形；
    以所述压印胶颗粒的图形为掩膜图形，对所述催化剂膜层进行刻蚀，形成所述催化剂颗粒的图形。
  13. 如权利要求1-6任一项所述的制备方法，其中，形成所述催化剂颗粒的图形，具体包括：
    在形成有所述导向结构的衬底基板上形成所述催化剂膜层；
    在所述催化剂膜层上形成压印胶；
    对所述压印胶进行纳米压印工艺，形成压印胶线的图形；其中所述压印胶线的延伸方向与所述导向结构的延伸方向垂直；
    以所述压印胶线的图形为掩膜图形，对所述催化剂膜层进行刻蚀，形成催化剂线的图形；
    对所述催化剂线进行等离子体轰击，形成所述催化剂颗粒的图形。
  14. 如权利要求1-6任一项所述的制备方法，其中，所述催化剂颗粒与硅的共熔点的温度范围在200℃～1000℃；
    对所述非晶硅薄膜进行退火时，退火温度为200℃-600℃。
  15. 一种阵列基板，其中，所述阵列基板采用权利要求1-14任一项所述的制备方法制备；所述阵列基板包括：
    位于衬底基板上的第一薄膜晶体管，所述第一薄膜晶体管包括：第一栅电极、第一有源层、第一源电极和第一漏电极；所述第一有源层下方设置有至少一个沿第一方向延伸的导向结构，所述第一有源层的材料包括硅基纳米线，所述硅基纳米线的延伸方向与所述导向结构的延伸方向相同；
    位于所述衬底基板上的第二薄膜晶体管；所述第二薄膜晶体管包括：第二栅电极、第二有源层、第二源电极和第二漏电极，所述第二有源层的材料与所述第一有源层的材料不相同。
  16. 如权利要求15所述的阵列基板，其中，所述导向结构沿所述第一方向的长度大于所述硅基纳米线沿所述第一方向的长度。
  17. 如权利要求15所述的阵列基板，其中，所述第一源电极和所述第一漏电极的连线方向与所述硅基纳米线的延伸方向相同。
  18. 如权利要求14所述的阵列基板，其中，所述第二有源层的材料为低温多晶硅材料、碳纳米管材料或者氧化物半导体材料。
  19. 一种显示面板，其中，包括如权利要求15-18任一项所述的阵列基板。
PCT/CN2020/081172 2019-05-13 2020-03-25 阵列基板、其制备方法及显示面板 WO2020228421A1 (zh)

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