WO2013135075A1 - 阵列基板的制作方法、阵列基板及显示装置 - Google Patents

阵列基板的制作方法、阵列基板及显示装置 Download PDF

Info

Publication number
WO2013135075A1
WO2013135075A1 PCT/CN2012/085702 CN2012085702W WO2013135075A1 WO 2013135075 A1 WO2013135075 A1 WO 2013135075A1 CN 2012085702 W CN2012085702 W CN 2012085702W WO 2013135075 A1 WO2013135075 A1 WO 2013135075A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
film
substrate
active layer
electrode
Prior art date
Application number
PCT/CN2012/085702
Other languages
English (en)
French (fr)
Inventor
宁策
刘翔
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2013135075A1 publication Critical patent/WO2013135075A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate fabricated by the method, and a display device including the array substrate. Background technique
  • flat panel displays have gradually replaced bulky CRT displays.
  • Commonly used flat panel displays include liquid crystal displays and organic light emitting diode displays.
  • each pixel is driven by a corresponding Thin Film Transistor (TFT) in a TFT array substrate, and then combined with a peripheral driving circuit to realize image display.
  • TFT Thin Film Transistor
  • AMOLED active matrix organic light-emitting display
  • a TFT in a TFT array substrate drives a corresponding OLED pixel in an OLED panel, and then cooperates with a peripheral driving circuit to realize image display.
  • the TFT is used as a switching element, which is the key to the display of the above display, and is directly related to the development of a high performance flat panel display.
  • the TFTs which have been industrialized mainly include amorphous silicon TFTs, polycrystalline silicon TFTs, single crystal silicon TFTs, and the like, and amorphous silicon TFTs are most used for preparing array substrates in flat panel displays.
  • the array substrate using ZnO is generally completed by 4mask ⁇ 6mask, that is, four to six patterning processes.
  • the four-time patterning process includes: forming a gate electrode and a gate line by one patterning process, forming a gate insulating layer, an active layer, and a source-drain electrode by one patterning process, forming a protective layer by one patterning process, and forming a pixel by one patterning process electrode. If the number of patterning processes can be reduced, that is, if the number of times of using the mask can be reduced, the production efficiency can be improved and the production cost can be reduced. Summary of the invention
  • Embodiments of the present invention provide a method of fabricating an array substrate, the method comprising forming a gate electrode, an active layer, a source electrode, a drain electrode, and a pixel electrode, respectively, by a patterning process.
  • the source electrode, the drain electrode, and the pixel electrode are formed by one patterning process.
  • Embodiments of the present invention also provide an array substrate, which is fabricated by the above-described fabrication method.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the ZnO-based thin film transistor array substrate uses a common mask in each patterning process, so that the pattern of the source and drain electrodes and the pattern of the pixel electrode cannot be formed in one patterning process, and at least four patterns are required.
  • the process can form an array substrate.
  • a halftone or gray tone mask is used in the second patterning process so that the source and drain electrodes and the pixel electrode are formed in one patterning process.
  • the method for fabricating the array substrate according to the embodiment of the present invention can be completed by using only three patterning processes, and the number of patterning processes is further reduced, the fabrication process of the array substrate is simplified, the production efficiency is improved, and the production efficiency is shortened. Production time and production costs are reduced.
  • the active layer film is subjected to surface treatment by ion implantation, and a transparent conductive film having superior properties is formed on the surface of the active layer film.
  • the transparent conductive film deposition process is omitted, which further shortens the manufacturing time and production cost of the array substrate.
  • the source and drain electrodes and the pixel electrode are formed by the same patterning process, and the connection of the pixel electrode and the drain electrode does not require a via hole, and the connectivity is good and the electrical performance is good.
  • 1( a ) is a cross-sectional view of the array substrate after the gate film is deposited on the substrate; 1(b) is a cross-sectional view of the array substrate after the first patterning process is completed; FIG. 2(a) is an array substrate after the gate insulating film and the active layer film are deposited on the substrate shown in FIG. 1(b). Sectional view
  • Figure 2 (b) is a cross-sectional view of the array substrate after surface treatment of the active layer film shown in Figure 2 (a) to form a transparent conductive film;
  • FIG. 2(c) is a cross-sectional view of the array substrate after the source/drain metal film is deposited on the substrate shown in FIG. 2(b);
  • FIG. 2(d) is a cross-sectional view of the array substrate after the photoresist is deposited on the substrate shown in FIG. 2(c) and the photoresist is exposed and developed;
  • FIG. 2(e) is a cross-sectional view of the array substrate after the substrate shown in FIG. 2(d) is etched;
  • FIG. 2(f) is the array substrate after the ashing process is completed on the substrate shown in FIG. 2(e)
  • Figure 2 (g) is a cross-sectional view of the array substrate after the substrate shown in Figure 2 (f) is etched;
  • Figure 2 (h) is the stripping of the photoresist on the substrate shown in Figure 2 (g) a cross-sectional view of the subsequent array substrate;
  • Figure 3 (a) is a plan view showing the planar structure of the array substrate after the third patterning process is completed;
  • Figure 3 (b) is a cross-sectional view taken along line A-A of Figure 3 (a).
  • a method of fabricating an array substrate includes separately forming a gate electrode 1, an active layer 3, a source electrode 5a, a drain electrode 5b, and a pixel electrode 4 by a patterning process, wherein the source electrode 5a, the drain electrode 5b, and The pixel electrode 4 is formed by one patterning process.
  • This embodiment uses a three-time patterning process based on slit lithography, in which the source electrode 5a, the drain electrode 5b, and the pixel electrode 4 can be formed by one patterning process.
  • the principle of slit lithography is to cover A slit of a specific size is set on the stencil, and optical diffraction is performed by the slit to control the transmittance of light, thereby selectively controlling the thickness of the photoresist.
  • the photoresist is preferably formed by spin coating.
  • the gate electrode 1 and the gate line 9 are formed on the substrate by the first patterning process as shown in FIGS. 1(a) and 1(b).
  • a gate film ⁇ is deposited on the substrate, and then a layer of photoresist is applied thereon.
  • the photoresist is exposed and developed using a mask.
  • the photoresist remaining region corresponds to a region where the gate electrode 1 and the gate line 9 are to be formed.
  • the exposed gate film is etched away and the remaining photoresist is stripped by a lift-off process to form the gate electrode 1 and the gate line 9 (see FIG. 5 for the gate line 9).
  • the thickness of the gate film 1 may range from 200 nm to 400 nm.
  • the gate film 1 may be made of metal or ITO (Indium Tin Oxide), preferably made of a single layer film of Mo, Al or Cu, or formed of AlNd alloy and Mo. Made of two layers of film.
  • the gate film ⁇ can be formed by sputtering.
  • a gate insulating layer 2, an active layer 3, a pixel electrode 4, a source electrode 5a, a drain electrode 5b, and a data line 8 are formed on the substrate of the step slO1 by a second patterning process.
  • the gate insulating layer 2, the active layer 3, the pixel electrode 4, the source electrode 5a, the drain electrode 5b, and the data line 8 are formed in a patterning process by a multi-step etching process.
  • step sl02 includes the following steps:
  • PECVD plasma enhanced chemical vapor deposition
  • the shooting method is made of A1 2 0 3 or A1N (aluminum nitride).
  • the active layer film 3' has a thickness ranging from 1000 A to 1500 A, and is formed by magnetron sputtering and using ZnO.
  • step S102-2 As shown in Fig. 2(b), a transparent conductive film 4 is formed on the substrate on which step S102-1 is completed.
  • the transparent conductive film 4' has a thickness of 400 A to 600 A, preferably 50 ⁇ .
  • the transparent conductive film 4 is formed by surface treatment of the active layer film 3 formed in the step s102 -1 by ion implantation, and the surface of the active layer film 3 is formed into a transparent conductive film 4 , and said The transparent conductive film 4' is completely covered and uniformly formed on the surface of the active layer film 3'.
  • the ion implantation is: doping of In, Sn, Al, B or Ga on the surface of the active layer film 3 made of ZnO.
  • a source/drain metal film 5 is deposited on the substrate of step sl02-2.
  • the source/drain metal thin film 5' has a thickness ranging from 200 nm to 300 nm, and is formed by a magnetron sputtering method and a single layer film of Cu, Mo, Al, AlNd alloy or Ti.
  • the photoresist is exposed and developed with a halftone mask or a gray tone mask.
  • the halftone mask or the gray tone mask is provided with a non-transmissive region, a partially transmissive region, and a transmissive region. If the photoresist 7 is a positive glue, the non-transmissive region, the partially transmissive region, and the transmissive region on the gray tone or halftone mask after the exposure and development of the photoresist will respectively form a photoresist completely.
  • the photoresist 7 is a negative glue, the non-transmissive region, the partially transmissive region, and the transmissive region on the gray tone or halftone mask after the photoresist is exposed and developed, respectively, corresponding to the complete formation of the photoresist.
  • the photoresist of the photoresist completely remaining region NP is completely retained, which corresponds to a region where the source electrode 5a, the drain electrode 5b, and the data line 8 are to be formed.
  • the photoresist portion retaining region HP has a thickness thinner than the photoresist of the photoresist completely remaining region P, which corresponds to a region where the pixel electrode 4 is to be formed.
  • the photoresist of the photoresist completely removed region WP is completely removed, which corresponds to a region where the active layer 3 and the TFT channel are to be formed.
  • the principle of forming the photoresist partial retention region HP is: exposing the region using a partially transmissive region with a slit on the gray tone or halftone mask, whether the photoresist 7 is positively or negatively Glue, the diffraction effect and interference effect of the slit will make the intensity of light reaching the photoresist in the region at the time of exposure weaker than the intensity of light reaching the photoresist in the transmission region, so the photoresist in the partially transmissive region is not as good as The photoresist in the transmissive region is sufficiently exposed such that the thickness of the photoresist of the photoresist portion remaining region HP is thinner than the thickness of the photoresist of the photoresist completely remaining region NP.
  • the substrate of the step S02-5 is etched to form a gate insulating layer 2, an active layer 3, a source electrode 5a, a drain electrode 5b, a data line 8, and a TFT. Channel.
  • the source/drain metal film 5 and the transparent conductive film 4 are formed of different materials, in order to obtain a better etching effect, it is preferable to perform etching on the substrate in which the step S102-5 is completed twice.
  • the exposed source/drain metal film 5 is etched by a first etching process, and the exposed transparent conductive film 4 and a portion of the active layer film 3 are etched away by a second etching process.
  • the substrate on which the step S102-7 is completed is subjected to ashing treatment, and the photoresist of the photoresist portion remaining region HP is removed.
  • step S102-9 As shown in Fig. 2(g), the substrate on which step S102-8 is completed is etched to form the pixel electrode 4.
  • the remaining photoresist i.e., the remaining photoresist of the photoresist completely remaining region NP
  • the remaining photoresist stripping process As shown in Fig. 2(h), the remaining photoresist (i.e., the remaining photoresist of the photoresist completely remaining region NP) is stripped by a photoresist stripping process.
  • the protective layer 6 is formed by the third patterning process on the substrate on which step sl02 is completed. As shown in Figs. 3(a) and 3(b), a protective film is deposited on the substrate on which step sl02 is completed, and then a layer of photoresist is applied thereon. The photoresist is exposed and developed with a mask. For example, the photoresist retention region corresponds to a region where the protective layer 6 is to be formed. The exposed protective film is etched and the remaining photoresist is peeled off to form a protective layer 6. For example, in this step, peripheral metal lead vias can be formed simultaneously and the active layer 3 can be patterned into islands.
  • the protective layer film has a thickness ranging from 250 nm to 300 nm, and is formed by plasma enhanced chemical vapor deposition and using SiN x or SiO x , or by magnetron sputtering and using A1. 2 0 3 or AIN made.
  • the array substrate includes a substrate, a gate line 9, a data line 8, and a pixel region defined by the intersection of the gate line 9 and the data line 8 with each other.
  • the pixel region includes a thin film transistor and a pixel electrode. The thin film transistor is formed at the intersection of the gate line 9 and the data line 8.
  • the thin film transistor includes: a gate electrode 1 formed on a substrate, the gate electrode 1 being connected to the gate line 9; a gate insulating layer 2 covering the gate electrode 1 and extending to an exposed region of the substrate; The active layer 3 on the gate insulating layer 2; the source electrode 5a and the drain electrode 5b formed on the active layer 3, and a TFT channel is provided between the source electrode 5a and the drain electrode 5b.
  • a transparent conductive film for forming the pixel electrode 4 is interposed between the source electrode 5a and the active layer 3.
  • the source electrode 5a is connected to the data line 8.
  • the pixel electrode 4 is formed on the active layer 3, and one end of the pixel electrode 4 is interposed between the active layer 3 and the drain electrode 5b to connect the pixel electrode 4 and the drain electrode 5b.
  • the array substrate further includes a protective layer 6 covering the source electrode 5a and the drain electrode 5b and extending to the exposed pixel electrode 4 and the active layer 3 on.
  • the layers constituting the array substrate and the layers formed in the method for fabricating the array substrate have the same material and thickness.
  • the embodiment also provides a display device, and the display device includes the above array substrate.
  • the display device is, for example, a liquid crystal display, an organic light emitting display, or the like.
  • the active layer film 3, made of In 2 0 3 the transparent conductive film 4, used for ion implantation of Zn or Sn doped on the surface of the active layer film made of In 2 0 3 The method is formed on the surface of the active layer film.
  • the source-drain electrode is the same material as the pixel electrode, that is, the active layer film is surface-treated by ion implantation, and the surface of the active layer film is sequentially formed into a transparent conductive film and a source/drain metal film. . Since the source and drain electrodes are the same as the material for the pixel electrode, when etching the gate insulating layer 2, the active layer 3, the source electrode 5a, the drain electrode 5b, the data line 8, and the TFT channel, only one etching is used. Just fine.
  • This embodiment also provides an array substrate prepared by the above manufacturing method.
  • the embodiment also provides a display device, and the display device includes the above array substrate.
  • the display device is, for example, a liquid crystal display, an organic light emitting display, or the like.
  • the fabrication method of the array substrate can be completed by using only three patterning processes, and the number of patterning processes is further reduced and the fabrication process of the array substrate is simplified compared with the conventional technology.
  • the active layer film is surface-treated by ion implantation to form a transparent conductive film having superior performance on the surface of the active layer film, thereby eliminating the transparent conductive film deposition process, and further The manufacturing time and production cost of the array substrate are shortened.
  • the source, the drain electrode and the pixel electrode are formed by the same patterning process, and the connection of the pixel electrode and the drain electrode does not require a via hole, and the connectivity is good and the electrical performance is good.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

提供一种阵列基板的制作方法、阵列基板以及显示装置。该阵列基板的制作方法包括通过构图工艺分别形成栅电极（1）、有源层（3）、源电极（5a）、漏电极（5b）以及像素电极（4）。源电极（5a）、漏电极（5b）和像素电极（4）通过一次构图工艺形成。

Description

阵列基板的制作方法、 阵列基板及显示装置 技术领域
本发明的实施例涉及一种阵列基板的制作方法、 釆用该方法制成的阵列 基板、 以及包括该阵列基板的显示装置。 背景技术
目前，平板显示器已逐渐取代了笨重的 CRT显示器。常用的平板显示器 包括液晶显示器和有机发光二极管显示器。
在液晶显示器中， 每一像素点由 TFT 阵列基板中的对应的薄膜晶体管 ( Thin Film Transistor: 简称 TFT )来驱动 , 再配合外围驱动电路， 实现图像 显示。 在有源矩阵驱动式有机发光显示器 （Active Matrix Organic Light Emission Display, 简称 AMOLED )中， TFT阵列基板中的 TFT驱动 OLED 面板中对应的 OLED像素， 再配合外围驱动电路， 实现图像显示。 在上述显 示器中， TFT用作开关元件， 是上述显示器实现显示的关键， 直接关系到高 性能平板显示器的发展。
已实现产业化的 TFT主要有非晶硅 TFT、 多晶硅 TFT、 单晶硅 TFT等， 而用于制备平板显示器中的阵列基板使用最多的是非晶硅 TFT。
目前， 出现了 ZnO TFT。 ZnO材料价格低廉、 原料充足、 对环境人体均 无害且制备简单。 理论研究表明， II ~ VI族的宽带隙半导体材料在常态下为 六方纤辞矿晶体结构， 熔点高、 热稳定性好、 介电常数低、 光电耦合系数大， 室温下禁带宽度 E=3.37eV, 激子束 60meV。 此外， ZnO还具有高的击穿强 度和饱和飘移速度， 比 si、 GaAs、 CdS、 GaN等大部分半导体材料的抗辐照 能力更强。 基于这些优点， ZnO TFT具有取代 TFT-LCD中常规非晶硅 TFT 的趋势。
目前， 釆用 ZnO的阵列基板一般釆用 4mask~6mask, 即四次〜六次构图 工艺完成。 所述四次构图工艺包括： 通过一次构图工艺形成栅电极与栅线、 通过一次构图工艺形成栅绝缘层、 有源层以及源漏电极、 通过一次构图工艺 形成保护层、 通过一次构图工艺形成像素电极。 如果能够减少构图工艺的数量， 即如果能够减少掩模板的使用次数， 则 可以提高生产效率， 降低生产成本。 发明内容
本发明的实施例提供一种阵列基板的制作方法， 该方法包括通过构图工 艺分别形成栅电极、 有源层、 源电极、 漏电极以及像素电极。 源电极、 漏电 极和像素电极通过一次构图工艺形成。
本发明的实施例还提供一种阵列基板， 所述阵列基板釆用上述制作方法 制成。
本发明的实施例还提供一种显示装置，所述显示装置包括上述阵列基板。 传统技术中， ZnO基薄膜晶体管阵列基板在各次构图工艺中都釆用普通 掩模板， 使得源、 漏电极的图形与像素电极的图形无法在一次构图工艺中形 成， 也使得至少需要四次构图工艺才能形成阵列基板。 然而， 根据本发明的 实施例， 在第二次构图工艺中釆用半色调或灰色调掩模板， 使得源、 漏电极 与像素电极在一次构图工艺中形成。 因此本发明实施例所述阵列基板的制作 方法只需釆用三次构图工艺即可完成， 与传统技术相比进一步减少了构图工 艺次数、 简化了阵列基板的制作工艺， 提高了生产效率、 缩短了制作时间、 降低了生产成本。
传统技术一般釆用沉积的方式形成透明导电薄膜。 然而， 根据本发明的 实施例， 釆用离子注入的方法对有源层薄膜进行表面处理， 在所述有源层薄 膜的表面形成性能更优越的透明导电薄膜。 因而， 省去了透明导电薄膜沉积 工艺， 进一步缩短了阵列基板的制造时间和生产成本。
根据本发明的实施例， 源、漏电极和像素电极釆用同一次构图工艺形成， 像素电极和漏电极的连接无需过孔， 连接性好， 电学性能好。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1 ( a )为在基板上沉积了栅极薄膜之后的阵列基板的截面图； 图 1 (b)为完成第一次构图工艺之后的阵列基板的截面图； 图 2 (a)为在图 1 (b)所示基板上沉积了栅绝缘薄膜、 有源层薄膜之后 的阵列基板的截面图；
图 2 (b)为对图 2 (a)所示的有源层薄膜进行表面处理形成透明导电薄 膜之后的阵列基板的截面图；
图 2 (c)为在图 2 (b)所示基板上沉积了源漏金属薄膜之后的阵列基板 的截面图；
图 2 (d)为在图 2 (c)所示基板上沉积了光刻胶并对所述光刻胶进行曝 光、 显影之后的阵列基板的截面图；
图 2 (e)为对图 2 (d)所示基板完成刻蚀之后的阵列基板的截面图； 图 2(f)为对图 2(e)所示基板完成灰化处理之后的阵列基板的截面图； 图 2 (g)为对图 2 (f)所示基板完成刻蚀之后的阵列基板的截面图； 图 2 (h)为将图 2 (g)所示基板上的光刻胶剥离之后的阵列基板的截面 图；
图 3 (a)为完成第三次构图工艺之后的阵列基板的平面结构示意图； 以 及
图 3 (b)为图 3 (a) 的 A-A向截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
根据本发明的实施例， 阵列基板的制作方法包括通过构图工艺分别形成 栅电极 1、 有源层 3、 源电极 5a、 漏电极 5b以及像素电极 4, 其中所述源电 极 5a、 漏电极 5b和像素电极 4通过一次构图工艺形成。
实施例 1
本实施例釆用基于狭缝光刻技术的三次构图工艺， 其中源电极 5a、 漏电 极 5b和像素电极 4可以通过一次构图工艺形成。狭缝光刻技术的原理是在掩 模板上设置特定尺寸的狭缝， 利用狭缝产生光学衍射以控制光的透过率， 从 而有选择地控制光刻胶的厚度。 所述光刻胶优选釆用旋涂的方法形成。
根据本实施例的阵列基板的制作方法可以包括如下步骤：
slOl. 在基板上通过第一次构图工艺形成栅电极 1与栅线 9, 如图 1 ( a ) 和 1 ( b )所示。
首先在基板上沉积栅极薄膜 Γ , 然后在其上涂敷一层光刻胶。 釆用掩模 板对所述光刻胶进行曝光、 显影。 例如， 光刻胶保留区域对应于要形成栅电 极 1与栅线 9的区域。 刻蚀去除暴露出来的栅极薄膜并通过剥离工艺将剩余 的光刻胶剥离， 从而形成栅电极 1与栅线 9 (栅线 9可以参见图 5 ) 。
所述栅极薄膜 1，的厚度范围可以为 200nm-400nm。所述栅极薄膜 1，可以 釆用金属或 ITO ( Indium Tin Oxide, 铟锡氧化物）制成， 优选釆用 Mo、 A1 或 Cu的单层膜制成， 或者釆用 AlNd合金与 Mo形成的双层膜制成。 所述栅 极薄膜 Γ可以釆用溅射的方法形成。
sl02. 在完成步骤 slOl的基板上通过第二次构图工艺形成栅绝缘层 2、 有源层 3、 像素电极 4、 源电极 5a、 漏电极 5b以及数据线 8。
本步骤中， 所述栅绝缘层 2、 有源层 3、 像素电极 4、 源电极 5a、 漏电极 5b以及数据线 8是釆用多步刻蚀工艺在一次构图工艺中形成的。
例如， 所述步骤 sl02包括如下步骤：
S102-1. 如图 2 ( a )所示， 在完成步骤 slOl的基板上依次沉积栅绝缘薄 膜 2'及有源层薄膜 3'。
所述栅绝缘薄膜 2'的厚度范围为 300nm-400nm,其釆用等离子增强化学 气相沉积法 ( PECVD, Plasma Enhanced Chemical Vapor Deposition )并釆用 81^或 SiOx制成， 或者釆用磁控溅射法并釆用 A1203或 A1N (氮化铝 )制成。 所述有源层薄膜 3'的厚度范围为 1000A-1500A, 其釆用磁控溅射法并釆用 ZnO制成。
S102-2. 如图 2 ( b )所示， 在完成步骤 S102-1的基板上形成透明导电薄 膜 4，。
所述透明导电薄膜 4'的厚度为 400A-600A, 优选为 50θΑ。 所述透明导 电薄膜 4，的形成方法为：釆用离子注入的方法对步骤 sl02-l形成的有源层薄 膜 3，进行表面处理， 使所述有源层薄膜 3，表面形成透明导电薄膜 4，， 且所述 透明导电薄膜 4'完全覆盖并均勾地形成在有源层薄膜 3'的表面上。优选所述 离子注入为： 在 ZnO制成的有源层薄膜 3，的表面掺杂 In、 Sn、 Al、 B或 Ga。
sl02-3. 如图 2 ( c )所示， 在完成步骤 sl02-2的基板上沉积源漏金属薄 膜 5，。
所述源漏金属薄膜 5'的厚度范围为 200nm-300nm,其釆用磁控溅射法并 釆用 Cu、 Mo、 Al、 AlNd合金或 Ti的单层膜制成。
S102-4. 在完成步骤 S102-3的基板上涂敷一层光刻胶 7。
S102-5. 如图 2 ( d )所示， 釆用半色调掩模板或灰色调掩模板对所述光 刻胶进行曝光、显影。所述半色调掩模板或灰色调掩模板上设有非透射区域、 部分透射区域以及透射区域。 若所述光刻胶 7为正性胶， 则在光刻胶曝光、 显影之后所述灰色调或半色调掩模板上的非透射区域、 部分透射区域以及透 射区域将分别对应形成光刻胶完全保留区域 NP、光刻胶部分保留区域 HP以 及光刻胶完全去除区域 WP。 若所述光刻胶 7为负性胶， 则在光刻胶曝光、 显影之后所述灰色调或半色调掩模板上的非透射区域、 部分透射区域以及透 射区域将分别对应形成光刻胶完全去除区域 WP、 光刻胶部分保留区域 HP 以及光刻胶完全保留区域 NP。所述光刻胶完全保留区域 NP的光刻胶被全部 保留， 其对应于要形成源电极 5a、 漏电极 5b以及数据线 8的区域。 所述光 刻胶部分保留区域 HP的光刻胶的厚度比光刻胶完全保留区域 P的光刻胶 的厚度薄， 其对应于要形成像素电极 4 的区域。 所述光刻胶完全去除区域 WP的光刻胶被全部去除， 其对应于要形成有源层 3及 TFT沟道的区域。
形成光刻胶部分保留区域 HP的原理是： 利用灰色调或半色调掩模板上 带有狭缝的部分透射区域对该区域进行曝光， 不论所述光刻胶 7为正性胶或 是负性胶， 所述狭缝的衍射效应与干涉效应将使得曝光时到达该区域光刻胶 的光的强度比到达透射区域光刻胶的光的强度弱， 因此所述部分透射区域的 光刻胶不如透射区域的光刻胶曝光充分， 使得光刻胶部分保留区域 HP的光 刻胶的厚度比光刻胶完全保留区域 NP的光刻胶的厚度薄。
S102-6. 如图 2 ( e )所示， 对完成步骤 sl 02-5的基板进行刻蚀， 形成栅 绝缘层 2、 有源层 3、 源电极 5a、 漏电极 5b、 数据线 8以及 TFT沟道。
这里， 由于源漏金属薄膜 5，与透明导电薄膜 4，由不同的材料形成， 所以 为了获得更好的刻蚀效果，优选对完成步骤 S102-5的基板进行两次刻蚀以形 成上述图形。例如，通过第一次刻蚀工艺刻蚀掉暴露出来的源漏金属薄膜 5，， 且通过第二次刻蚀工艺刻蚀掉暴露出来的透明导电薄膜 4，和部分有源层薄膜 3，。
S102-8. 如图 2 ( f)所示， 对完成步骤 S102-7的基板进行灰化处理， 灰 化掉所述光刻胶部分保留区域 HP的光刻胶。
S102-9. 如图 2 ( g )所示， 对完成步骤 S102-8的基板进行刻蚀， 形成像 素电极 4。
S102-10. 如图 2 ( h )所示， 通过光刻胶剥离工艺将剩余的光刻胶（即， 光刻胶完全保留区域 NP的剩余光刻胶）剥离。
sl03. 在完成步骤 sl02的基板上通过第三次构图工艺形成保护层 6。 如图 3 ( a )和 3 ( b )所示， 在完成步骤 sl02的基板上沉积保护层薄膜， 然后在其上涂敷一层光刻胶。 釆用掩模板对所述光刻胶进行曝光、 显影。 例 如， 所述光刻胶保留区域对应于要形成保护层 6的区域。 对暴露出来的保护 层薄膜进行刻蚀并将剩余的光刻胶剥离， 从而形成保护层 6。 例如， 在该步 骤中， 可以同时形成外围金属引线过孔并将有源层 3图案化为岛状。
本实施例中， 所述保护层薄膜的厚度范围为 250nm-300nm, 其釆用等离 子增强化学气相沉积法并釆用 SiNx或 SiOx制成， 或者釆用磁控溅射法并釆 用 A1203或 AIN制成。
本实施例同时提供一种釆用上述制作方法制成的阵列基板。 如图 3 ( a ) 和 3 ( b )所示， 该阵列基板包括基板、 栅线 9、 数据线 8、 以及由栅线 9与 数据线 8彼此交叉限定的像素区域。 像素区域包括薄膜晶体管和像素电极。 所述薄膜晶体管形成在栅线 9与数据线 8的所述交叉处。 所述薄膜晶体管包 括： 形成在基板上的栅电极 1 , 所述栅电极 1与栅线 9相连接； 覆盖在栅电 极 1上并延伸至所述基板的暴露区域上的栅绝缘层 2; 覆盖在栅绝缘层 2上 的有源层 3; 形成在有源层 3上的源电极 5a与漏电极 5b, 所述源电极 5a与 漏电极 5b之间设置有 TFT沟道。在源电极 5a和有源层 3之间插设有用于形 成像素电极 4的透明导电膜。源电极 5a与数据线 8相连接。像素电极 4形成 在有源层 3上，且像素电极 4的一端插设在有源层 3与漏电极 5b之间以使得 像素电极 4与漏电极 5b相连接。 此外， 所述阵列基板还包括保护层 6, 该保 护层 6覆盖源电极 5a与漏电极 5b,并延伸至暴露出的像素电极 4及有源层 3 上。
组成所述阵列基板的各层与上述阵列基板的制作方法中所形成的各层的 材料、 厚度均相同。
本实施例同时还提供一种显示装置， 所述显示装置包括上述阵列基板。 该显示装置例如为液晶显示器、 有机发光显示器等等。
实施例 2
本实施例所述阵列基板的制作方法与实施例 1所述的制作方法的区别在 于：
1 )所述有源层薄膜 3，釆用 In203制成，所述透明导电薄膜 4，釆用在 In203 制成的有源层薄膜表面掺杂 Zn或 Sn等的离子注入方式形成于有源层薄膜的 表面。
2 )所述源漏电极与像素电极釆用的材料相同， 即釆用离子注入的方法对 有源层薄膜进行表面处理， 使所述有源层薄膜表面依次形成透明导电薄膜与 源漏金属薄膜。 由于源漏电极与像素电极釆用的材料相同， 在刻蚀形成栅绝 缘层 2、 有源层 3、 源电极 5a、 漏电极 5b、 数据线 8以及 TFT沟道时， 只釆 用一次刻蚀即可。
本实施例同时提供一种釆用上述制作方法制成的阵列基板。
本实施例同时还提供一种显示装置， 所述显示装置包括上述阵列基板。 该显示装置例如为液晶显示器、 有机发光显示器等等。
除了上述两点区别外， 本实施例的其他特征与实施例 1相同， 在此不再 赘述。
根据本发明的实施例， 阵列基板的制作方法只需釆用三次构图工艺即可 完成， 与传统技术相比进一步减少了构图工艺次数、 简化了阵列基板的制作 工艺。 此外， 本发明实施例釆用离子注入的方法对有源层薄膜进行表面处理 以在所述有源层薄膜的表面形成性能更优越的透明导电薄膜， 因而省去了透 明导电薄膜沉积工艺， 进一步缩短了阵列基板的制造时间和生产成本。 源、 漏电极和像素电极釆用同一次构图工艺形成， 像素电极和漏电极的连接无需 过孔， 连接性好， 电学性能好。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种阵列基板的制作方法，其中该方法包括通过构图工艺分别形成栅 电极（1 )、 有源层（3)、 源电极（5a)、 漏电极（5b)以及像素电极（4)； 其中所述源电极（5a)、 漏电极（5b)和像素电极（4)通过一次构图工 艺形成。
2.根据权利要求 1所述的制作方法，其中所述制作方法还包括有形成栅 线（9) 、 栅绝缘层（2) 、 数据线（8) 以及保护层（6) 的步骤；
所述制作方法为：
1 )在基板上形成栅电极（ 1 )与栅线（ 9 ) ；
2)完成步骤 1 )的基板上依次形成栅绝缘层（2) 、 有源层（3) 、 源电 极（5a) 、 漏电极（5b) 、 数据线（8) 以及像素电极（4) ；
3)在完成步骤 2) 的基板上形成保护层（6) 。
3. 根据权利要求 2所述的制作方法， 其中所述步骤 2 )为：
21 )在完成步骤 1 ) 的所述基板上依次形成栅绝缘薄膜及有源层薄膜；
22)在完成步骤 21 ) 的基板上依次形成透明导电薄膜及源漏金属薄膜；
23)在完成步骤 22)的基板上形成一层光刻胶， 釆用半色调掩模板或灰 色调掩模板对所述光刻胶进行曝光、 显影后， 所述基板上形成光刻胶完全保 留区域、 光刻胶部分保留区域以及光刻胶完全去除区域， 所述光刻胶完全保 留区域对应于要形成源电极（5a) 、 漏电极（5b) 以及数据线（8) 的区域， 所述光刻胶部分保留区域对应于要形成像素电极（ 4 )的区域， 所述光刻胶完 全去除区域对应于要形成有源层（3) 以及 TFT沟道的区域；
24 )对完成步骤 23 )的基板进行刻蚀，形成栅绝缘层（ 2 )、有源层（ 3 )、 源电极（ 5a ) 、 漏电极（ 5b ) 、 数据线（ 8 ) 以及 TFT沟道；
25 )对完成步骤 24 )的基板进行灰化处理， 灰化掉所述光刻胶部分保留 区域的光刻胶， 然后对所述基板再次进行刻蚀， 形成像素电极（4) 。
4. 根据权利要求 3所述的制作方法， 其中所述步骤 22) 包括： 所述透明导电薄膜与源漏金属薄膜釆用相同的材料制成， 其形成方法包 括： 釆用离子注入的方法对步骤 21 )形成的有源层薄膜进行表面处理， 使所 述有源层薄膜表面形成透明导电薄膜及源漏金属薄膜； 或者， 所述透明导电薄膜与源漏金属薄膜釆用不同的材料制成， 其形成 方法为： 釆用离子注入的方法对步骤 21 )形成的有源层薄膜进行表面处理， 使所述有源层薄膜表面形成透明导电薄膜， 在所述透明导电薄膜上形成源漏 金属薄膜。
5. 根据权利要求 4所述的制作方法， 其中所述有源层薄膜釆用 ZnO或
In203制成； 所述离子注入包括在 ZnO制成的有源层薄膜表面掺杂 In、 Sn、 Al、 B或 Ga, 或者在 ln203制成的有源层薄膜表面掺杂 Zn或 Sn。
6. 根据权利要求 3-5之一所述的制作方法， 其中所述有源层薄膜的厚度 范围为 1000A-1500A; 所述透明导电薄膜的厚度范围为 400A-600A。
7. 根据权利要求 2所述的制作方法， 其中所述步骤 1 )包括： 在基板上 形成栅极薄膜， 然后在其上形成一层光刻胶， 釆用掩模板对所述光刻胶进行 曝光、 显影， 对暴露出来的栅极薄膜进行刻蚀， 将剩余的所述光刻胶剥离， 形成栅电极（ 1 )与栅线（9 ) 。
8. 根据权利要求 2所述的制作方法， 其中所述步骤 3 )包括： 在完成步 骤 2 ) 的基板上形成保护层薄膜， 然后在其上形成一层光刻胶， 釆用掩模板 对所述光刻胶进行曝光、 显影， 对暴露出来的保护层薄膜进行刻蚀， 将剩余 的所述光刻胶剥离， 形成保护层 （6 ) ; 所述保护层薄膜的厚度范围为 250nm-300nm, 其釆用等离子增强化学气相沉积法并釆用 SiNx或 SiOx制成， 或者釆用磁控溅射法并釆用 A1203或 AIN制成。
9. 一种釆用权利要求 1-8任一所述的制作方法制成的阵列基板。
10. 一种显示装置， 其中包括权利要求 9所述的阵列基板。
PCT/CN2012/085702 2012-03-16 2012-11-30 阵列基板的制作方法、阵列基板及显示装置 WO2013135075A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210071825.3A CN102651343B (zh) 2012-03-16 2012-03-16 一种阵列基板的制作方法、阵列基板及显示装置
CN201210071825.3 2012-03-16

Publications (1)

Publication Number Publication Date
WO2013135075A1 true WO2013135075A1 (zh) 2013-09-19

Family

ID=46693315

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/085702 WO2013135075A1 (zh) 2012-03-16 2012-11-30 阵列基板的制作方法、阵列基板及显示装置

Country Status (2)

Country Link
CN (1) CN102651343B (zh)
WO (1) WO2013135075A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102651343B (zh) * 2012-03-16 2014-12-24 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN103123910B (zh) * 2012-10-31 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103500730B (zh) 2013-10-17 2016-08-17 北京京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置
CN103700663B (zh) * 2013-12-12 2016-09-07 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103700707B (zh) 2013-12-18 2018-12-11 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示装置
CN103745955B (zh) 2014-01-03 2017-01-25 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN104992947B (zh) * 2015-06-03 2018-01-12 合肥鑫晟光电科技有限公司 一种氧化物半导体tft阵列基板及其制备方法
CN106129071B (zh) * 2016-09-13 2018-12-25 京东方科技集团股份有限公司 一种阵列基板的制作方法及相应装置
CN106298807A (zh) * 2016-09-19 2017-01-04 昆山龙腾光电有限公司 薄膜晶体管阵列基板及制作方法
CN107093583A (zh) * 2017-05-03 2017-08-25 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN109192704A (zh) * 2018-09-05 2019-01-11 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN109545750B (zh) * 2018-10-08 2020-03-27 深圳市华星光电半导体显示技术有限公司 薄膜晶体管基板的制作方法及其薄膜晶体管基板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553269A (zh) * 2003-12-03 2004-12-08 吉林北方彩晶数码电子有限公司 薄膜晶体管液晶显示器制造方法
CN101078842A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN101325210A (zh) * 2007-06-13 2008-12-17 株式会社理光 磁性传感器及其制作方法
CN101615582A (zh) * 2009-06-25 2009-12-30 浙江大学 一种合金氧化物透明薄膜晶体管的制备方法
CN101770121A (zh) * 2008-12-26 2010-07-07 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102651343A (zh) * 2012-03-16 2012-08-29 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496420B1 (ko) * 2001-03-02 2005-06-17 삼성에스디아이 주식회사 2층구조의 소오스/드레인 전극을 갖는 박막 트랜지스터 및그의 제조방법과 이를 이용한 액티브 매트릭스형 표시소자및 그의 제조방법
KR101415561B1 (ko) * 2007-06-14 2014-08-07 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그의 제조 방법
CN101656232B (zh) * 2008-08-19 2011-10-12 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553269A (zh) * 2003-12-03 2004-12-08 吉林北方彩晶数码电子有限公司 薄膜晶体管液晶显示器制造方法
CN101078842A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN101325210A (zh) * 2007-06-13 2008-12-17 株式会社理光 磁性传感器及其制作方法
CN101770121A (zh) * 2008-12-26 2010-07-07 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN101615582A (zh) * 2009-06-25 2009-12-30 浙江大学 一种合金氧化物透明薄膜晶体管的制备方法
CN102651343A (zh) * 2012-03-16 2012-08-29 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置

Also Published As

Publication number Publication date
CN102651343B (zh) 2014-12-24
CN102651343A (zh) 2012-08-29

Similar Documents

Publication Publication Date Title
WO2013135075A1 (zh) 阵列基板的制作方法、阵列基板及显示装置
JP5788703B2 (ja) 平板表示装置及びその製造方法
US10707236B2 (en) Array substrate, manufacturing method therefor and display device
JP6129206B2 (ja) Ｔｆｔアレイ基板の製造方法
US20140061632A1 (en) Thin film transistor substrate and method of manufacturing the same
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
WO2013155840A1 (zh) 阵列基板及其制造方法和显示装置
US9219085B2 (en) Thin film transistor display panel and manufacturing method thereof
CN107170759B (zh) 一种阵列基板及其制作方法、显示装置
WO2018090482A1 (zh) 阵列基板及其制备方法、显示装置
WO2014127645A1 (zh) 薄膜晶体管及其制作方法和显示器件
US9620609B2 (en) Thin film transistor display panel and method of manufacturing the same
WO2016004692A1 (zh) 阵列基板制备方法
WO2013071800A1 (zh) 显示装置、薄膜晶体管、阵列基板及其制造方法
WO2014131242A1 (zh) 薄膜晶体管阵列基板、制备方法以及显示装置
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
TW201622158A (zh) 薄膜電晶體以及其製作方法
US10699905B2 (en) Low-temperature polysilicon (LTPS), thin film transistor (TFT), and manufacturing method of array substrate
WO2020228499A1 (zh) 晶体管器件及其制造方法、显示基板、显示装置
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2014117512A1 (zh) 一种薄膜晶体管、薄膜晶体管驱动背板的制备方法及薄膜晶体管驱动背板
WO2015131443A1 (zh) 一种阵列基板及其制备方法、液晶显示面板
US20160336359A1 (en) Thin film transistor device, manufacturing method thereof, and display apparatus
WO2015143745A1 (zh) 一种阵列基板的制造方法
KR20110071641A (ko) 산화물 박막 트랜지스터의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12871357

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC - FORM 1205A (05.03.2015)

122 Ep: pct application non-entry in european phase

Ref document number: 12871357

Country of ref document: EP

Kind code of ref document: A1