WO2015131443A1 - 一种阵列基板及其制备方法、液晶显示面板 - Google Patents

一种阵列基板及其制备方法、液晶显示面板 Download PDF

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Publication number
WO2015131443A1
WO2015131443A1 PCT/CN2014/077594 CN2014077594W WO2015131443A1 WO 2015131443 A1 WO2015131443 A1 WO 2015131443A1 CN 2014077594 W CN2014077594 W CN 2014077594W WO 2015131443 A1 WO2015131443 A1 WO 2015131443A1
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layer
insulating layer
gate
patterned
array substrate
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PCT/CN2014/077594
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US14/382,963 priority Critical patent/US20160231629A1/en
Publication of WO2015131443A1 publication Critical patent/WO2015131443A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/133302—Rigid substrates, e.g. inorganic substrates

Definitions

  • the present invention relates to image display technology, and more particularly to an array substrate and a method of fabricating the same, and a liquid crystal display panel. Background technique
  • a display device using a liquid crystal display panel as a core component has been widely used in people's daily life and work.
  • the performance of the liquid crystal display panel has a significant influence on the imaging effect of the display device, such as the visual angle of view, the degree of shading, and the color.
  • a liquid crystal display panel is usually composed of an array substrate, a color filter substrate, and a liquid crystal layer.
  • the array substrate is composed of a plurality of transistors arranged in an array, and a pixel unit (pixel) corresponding to each transistor.
  • the transistor is a logic switching element that activates the operation of the pixel unit. It receives the scan signal from the scan drive circuit through the scan line, receives the data signal from the data drive circuit through the data line, and conducts under the action of the scan signal, thereby transmitting the data signal to the corresponding pixel unit.
  • the liquid crystal display panel is a passive display device, and its power consumption can be roughly divided into the following three parts: backlight power consumption, driving circuit board power consumption and panel power consumption.
  • the backlight power consumption mainly depends on the brightness and luminous efficiency of the LED lamp
  • the power consumption of the driving circuit board mainly depends on the signal frequency, the driving current and the line loss
  • the power consumption of the panel is mainly the logic power consumption, that is, the logic switch on the driving array substrate The energy required to operate the component.
  • the quality of the panel design will directly affect the power consumption of the panel.
  • the present invention provides a new array substrate with lower power consumption and a preparation method thereof, and a corresponding liquid crystal display panel.
  • the array substrate includes:
  • a patterned organic insulating layer formed on the gate insulating layer, the organic insulating layer being provided with an opening in a region corresponding to a transistor gate of the gate metal layer;
  • a patterned active layer formed on the organic insulating layer, a portion of the active layer being deposited on both sides of the opening of the organic insulating layer and inside the opening;
  • the opening of the organic insulating layer is a via hole to expose a region of the gate insulating layer corresponding to a gate of the transistor in the gate metal layer.
  • the organic insulating layer may have a thickness of 10,000 ⁇ to 30,000 ⁇ .
  • the material of the above organic insulating layer may be polyacrylic acid.
  • the array substrate may further include:
  • a patterned passivation protective layer formed on the source and drain metal layers
  • the present invention provides a liquid crystal display panel including the above array substrate.
  • the present invention also provides a method for fabricating the above array substrate, comprising the steps of: providing a glass substrate;
  • a patterned source and drain metal layer is formed on the active layer.
  • the opening of the organic insulating layer may be provided as a via hole to expose a region of the gate insulating layer corresponding to a transistor gate in the gate metal layer.
  • the above preparation method may further comprise the following steps:
  • a patterned pixel electrode layer is formed on the passivation protective layer.
  • the thickness of the organic insulating layer may be set to 10,000 ⁇ to 30,000 ⁇ .
  • the present invention provides an organic insulating layer (a photoresist having a high transmittance and a low dielectric constant) on the gate metal layer when the array substrate of the liquid crystal display panel is fabricated.
  • an organic insulating layer a photoresist having a high transmittance and a low dielectric constant
  • the organic insulating layer is thick and flat, it is also effective in preventing static electricity and avoiding the breakage of the metal line, thereby improving the production yield of the display panel and reducing the production cost.
  • the technical solution proposed by the present invention is applicable to various types of liquid crystal display panels such as PSVA. DRAWINGS
  • FIG. 1 is a cross-sectional view showing the structure of an embodiment of an array substrate of the present invention
  • FIG. 2 is a cross-sectional view showing a deposition of a gate metal layer in the process of fabricating the array substrate of FIG. 1 according to the preparation method of the present invention
  • FIG. 3 is a cross-sectional view showing deposition of a gate insulating layer during the fabrication of the array substrate of FIG. 1 in accordance with the fabrication method of the present invention
  • FIG. 4 is a cross-sectional view showing deposition of an organic insulating layer in the process of fabricating the array substrate of FIG. 1 according to the preparation method of the present invention
  • Figure 5 is a cross-sectional view showing the deposition of an active layer and a source/drain metal layer during the fabrication of the array substrate of Figure 1 in accordance with the fabrication method of the present invention
  • Figure 6 is a cross-sectional view showing the deposition of a passivation protective layer during the fabrication of the array substrate of Figure 1 in accordance with the fabrication method of the present invention.
  • the array substrate can be a low power PSVA type array substrate, including:
  • a patterned gate metal layer 120 is formed on the glass substrate 110.
  • a patterned organic insulating layer 140 formed on the gate insulating layer 130, wherein the organic insulating layer 140 is provided with an opening 141 in a region corresponding to the transistor gate 121 in the gate metal layer 120 to expose the gate insulating layer a region of layer 130 corresponding to transistor gate 121 in gate metal layer 120;
  • a patterned pixel electrode layer 180 is formed on the passivation protective layer 170.
  • FIG. 6 are specific process flows for fabricating the above-mentioned PSVA type array substrate, including the following steps:
  • a glass substrate 110 is provided.
  • a layer of metal e.g., a metal material such as molybdenum, chromium or copper
  • the thickness of the metal layer may be from 2000A to 5000A.
  • the metal layer is then patterned by a photolithography process such as exposure, development, etching, and lift-off using a mask to form a gate metal layer 120 including a plurality of transistor gates 121 and a plurality of gate metal lines 122. (See Figure 2).
  • the gate insulating layer 130 may have a thickness of 2000 ⁇ to 5000 ⁇ .
  • a high transmittance low dielectric constant organic insulating material for example, polyacrylic acid
  • the thickness of the coating layer is preferably 10,000 ⁇ to 30,000 ⁇ to increase the distance between the gate metal layer 120 and the source and drain metal layer 160, thereby reducing the metal lines between each other (for example, between the gate metal line and the drain metal line). , the capacitive reactance between the gate metal line and the source metal line).
  • the coating is then patterned by exposure, development, etc. using a mask to form an organic insulating layer 140.
  • the organic insulating layer 140 has an opening 141 in a region corresponding to the transistor gate 121 of the gate metal layer 120.
  • the opening 141 is generally a through hole for exposing the transistor in the gate insulating layer 130 and the gate metal layer 120. The area corresponding to the gate 121 (see Fig. 4).
  • the source and drain metal layer 160 is deposited on the active layer 150, a portion of the active layer 150 is deposited on both sides of the opening 141 of the organic insulating layer 140, and is directly deposited on the gate insulating layer inside the opening 141. 130 (see FIG. 5), to reduce the distance between the transistor channel 151 in the active layer 150 and the corresponding gate 121 in the gate metal layer 120, to ensure that the driving transistor operates normally.
  • a layer of insulating material e.g., silicon nitride SiNx
  • PECVD plasma enhanced chemical vapor deposition
  • the passivation protective layer 170 may have a thickness of 1000A to 6000A.
  • the passivation protective layer 170 is patterned by a photolithography process such as exposure, development, etching, and lift-off using a mask to make the passivation protective layer 170 have through holes 171, thereby exposing the source and drain.
  • a portion of the drain metal line and/or the source metal line in the epitaxial layer 160 see Figure 6).
  • a transparent conductive material such as ITO or IZO
  • the thickness may be 100 A to 1000 A.
  • a patterning process is performed by a photolithography process such as exposure, development, etching, and lift-off using a mask to form a patterned pixel electrode layer 180.
  • a portion of the pixel electrode layer 180 is deposited on both sides of the opening 171 of the passivation protection layer 170, and a drain metal line and/or a source metal directly deposited in the source/drain metal layer 160 inside the opening 171. Online (see Figure 1).
  • an organic insulating layer (a high transmittance low dielectric constant photoresist) is disposed on the gate metal layer of the array substrate to increase the gate metal layer and the source and drain metal layers.
  • the distance between the wires is reduced, and the coupling capacitance between the metal wires and the metal wires is reduced, the load on the entire array substrate is effectively reduced, the logic power consumption of the array substrate is reduced, and the service life is prolonged.
  • the organic insulating layer is thick and flat, it is also effective in preventing static electricity and avoiding the breakage of the metal wire, thereby improving the production yield of the panel and reducing the production cost.
  • array substrate and the preparation method thereof provided by the present invention are far from limited to the above embodiments, and Suitable for other types of array substrates.
  • the present invention also proposes a liquid crystal display panel including the above array substrate.

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Abstract

本发明公开了一种阵列基板及其制备方法、液晶显示面板。所述阵列基板包括玻璃基板，玻璃基板上形成有图案化的栅极金属层，栅极金属层上形成有栅极绝缘层，栅极绝缘层上形成有图案化的有机绝缘层，该有机绝缘层在其与栅极金属层中的晶体管栅极对应的区域设置有开孔，以及有机绝缘层上形成有图案化的有源层，该有源层的一部分沉积于所述有机绝缘层的开孔的两侧和开孔的内部，以及有源层上形成有图案化的源漏极金属层。本发明提出的阵列基板的负载较小，逻辑功耗较低，使用寿命较长。此外由于设置的有机绝缘层较厚且平坦，因此能够有效防止静电现象，并且避免金属线的爬坡断线。

Description

一种阵列基板及其制备方法、 液晶显示面板 技术领域
本发明涉及图像显示技术， 特别是关于一种阵列基板及其制备方法、 液晶显 示面板。 背景技术
使用液晶显示面板作为核心部件的显示装置已经广泛地应用于人们的日常 生活和工作中。 液晶显示面板的工作性能对显示装置的成像效果， 例如对可视视 角、 明暗程度和色彩等有着显著的影响。
一个液晶显示面板通常由阵列基板、 彩色滤光片基板和液晶层组成。 其中， 阵列基板是由多个以阵列形式排布的晶体管， 以及与每一个晶体管对应配置的像 素单元 （pixel) 组成。 晶体管是启动像素单元工作的逻辑开关元件。 它通过扫描 线接收来自扫描驱动电路的扫描信号， 通过数据线接收来自数据驱动电路的数据 信号， 并在扫描信号的作用下导通， 从而将数据信号传输给对应的像素单元。 像 素单元的液晶分子在数据信号的作用下发生相应的偏转， 透过一定量的光， 同时 外围的灰阶调节电路还对光的强度进行调节， 从而完成图像显示。 由此可知， 液 晶显示面板是一种被动显示器件，其功耗可以大致分为以下三个部分：背光功耗、 驱动电路板功耗和面板功耗。其中，背光功耗主要取决于 LED灯的亮度和发光效 率； 驱动电路板功耗主要取决于信号频率， 驱动电流以及线路损耗； 面板功耗主 要为逻辑功耗， 也即驱动阵列基板上逻辑开关元件工作所需的能耗。 其中， 面板 设计的好坏会直接影响面板功耗的大小。
当前随着显示技术的不断发展， 液晶显示面板的尺寸正在不断地增大， 面板 中的元件和布线的数量也在成倍增加， 如何降低面板功耗成为了液晶技术发展的 一个难题。 尤其是， 如何减少因金属线彼此间的耦合容抗所引起的面板功耗损失 是一个亟待解决的技术问题。 发明内容 为解决上述问题， 本发明提供了一种新的功耗较低的阵列基板及其制备方 法， 以及相应的液晶显示面板。
所述阵列基板， 其中包括：
玻璃基板；
形成于所述玻璃基板上的图案化的栅极金属层；
形成于所述栅极金属层上的栅极绝缘层；
形成于所述栅极绝缘层上的图案化的有机绝缘层， 所述有机绝缘层在其与所 述栅极金属层中的晶体管栅极对应的区域设置有开孔；
形成于所述有机绝缘层上的图案化的有源层， 所述有源层的一部分沉积于所 述有机绝缘层的开孔的两侧和开孔的内部；
形成于所述有源层上的图案化的源漏极金属层。
优选地， 上述阵列基板中， 所述有机绝缘层的开孔为通孔， 以暴露所述栅极 绝缘层中的与所述栅极金属层中的晶体管栅极对应的区域。
根据本发明的实施例， 上述有机绝缘层的厚度可以是 10000A〜30000A。 根据本发明的实施例， 上述有机绝缘层的材料可以是聚丙烯酸。
根据本发明的实施例， 上述阵列基板， 还可以包括：
形成于所述源漏极金属层上的图案化的钝化保护层；
形成于所述钝化保护层上的图案化的像素电极层。
此外， 本发明还提供一种包括有上述阵列基板的液晶显示面板。
此外， 本发明还提出了一种上述阵列基板的制备方法， 包括以下步骤： 提供一玻璃基板；
在玻璃基板上形成图案化的栅极金属层；
在栅极金属层上形成栅极绝缘层；
在栅极绝缘层上形成图案化的有机绝缘层， 且所述有机绝缘层在其与栅极金 属层中的晶体管栅极对应的区域设置开孔；
在有机绝缘层上形成图案化的有源层， 且使有源层的一部分沉积于有机绝缘 层的开孔的两侧和开孔的内部；
在有源层上形成图案化的源漏极金属层。
优选地， 可以将上述有机绝缘层的开孔设置为通孔， 以暴露所述栅极绝缘层 中的与所述栅极金属层中的晶体管栅极对应的区域。 根据本发明的实施例， 上述制备方法还可以包括以下步骤：
在源漏极金属层上形成图案化的钝化保护层；
在钝化保护层上形成图案化的像素电极层。
优选地， 上述制备方法中， 可以将有机绝缘层的厚度设置为 10000A〜 30000Α。
与现有技术相比， 本发明提出在制作液晶显示面板的阵列基板时， 在栅极金 属层上设置一层有机绝缘层 （一种高透过率低介电常数的光刻胶） ， 以增加栅极 金属层与源漏极金属层之间的距离， 从而降低金属线交叉处以及金属线彼此间的 耦合容抗， 进而减小整个阵列基板的负载， 降低面板的逻辑功耗， 延长使用寿命。 此外， 由于有机绝缘层较厚且平坦， 因此还能够有效防止静电现象， 并且避免金 属线的爬坡断线， 从而提高显示面板的生产良率， 降低生产成本。 本发明提出的 技术方案适用于例如 PSVA等各种类型的液晶显示面板。 附图说明
附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明 的实施例共同用于解释本发明， 并不构成对本发明的限制。 在附图中：
图 1是本发明的阵列基板的一个实施例的结构剖视图；
图 2是根据本发明的制备方法制作图 1阵列基板过程中沉积栅极金属层的剖 视图；
图 3是根据本发明的制备方法制作图 1阵列基板过程中沉积栅极绝缘层的剖 视图；
图 4是根据本发明的制备方法制作图 1阵列基板过程中沉积有机绝缘层的剖 视图；
图 5是根据本发明的制备方法制作图 1阵列基板过程中沉积有源层和源漏极 金属层的剖视图；
图 6是根据本发明的制备方法制作图 1阵列基板过程中沉积钝化保护层的剖 视图。 具体实肺式
为使本发明的目的、 技术方案和优点更加清楚， 以下结合具体实施例和附图 对本发明作进一步地详细说明。
图 1是采用本发明提出的制备方法制成的一种阵列基板的示意图。 该阵列基 板可以是低功耗的 PSVA型阵列基板， 包括：
玻璃基板 110;
形成于玻璃基板 110上的图案化的栅极金属层 120。
形成于栅极金属层 120上的栅极绝缘层 130;
形成于栅极绝缘层 130上的图案化的有机绝缘层 140， 其中有机绝缘层 140 在其与栅极金属层 120中的晶体管栅极 121对应的区域设置有开孔 141， 以暴露 栅极绝缘层 130中的与栅极金属层 120中的晶体管栅极 121对应的区域；
形成于有机绝缘层 140上的图案化的有源层 150， 其中有源层 150的一部分 沉积于有机绝缘层 140的开孔 141的两侧和开孔 141的内部；
形成于有源层 150上的图案化的源漏极金属层 160;
形成于源漏极金属层 160上的图案化的钝化保护层 170;
形成于钝化保护层 170上的图案化的像素电极层 180。
图 1〜图 6是制作上述 PSVA型阵列基板的具体工艺流程， 包括以下步骤：
1 ) 提供一玻璃基板 110。
2)采用溅射镀膜法（Sputtering) 在玻璃基板 110上沉积一层金属 （例如钼、 铬或铜等金属材料） 。 该金属层的厚度可以是 2000A〜5000A。 然后利用掩膜板 通过曝光、 显影、 刻蚀和剥离等光刻工艺对此金属层进行图案化处理， 以形成包 括多个晶体管栅极 121和多条栅极金属线 122的栅极金属层 120 (参见图 2) 。
3 ) 采用等离子增强化学气相沉积法 （PECVD) 在栅极金属层 120上沉积一 层绝缘材料（例如氮化硅） ， 作为栅极绝缘层 130， 用以保护栅极金属层 120 (参 见图 3 ) 。 该栅极绝缘层 130的厚度可以是 2000Α〜5000Α。
4) 在栅极绝缘层 130 上涂布一层高透过率低介电常数的有机绝缘材料 （例 如聚丙烯酸）。该涂层的厚度优选为 10000Α〜30000Α， 用以增加栅极金属层 120 与源漏极金属层 160之间的距离， 从而降低金属线彼此间 （例如栅极金属线与漏 极金属线之间， 栅极金属线与源极金属线之间） 的耦合容抗。 然后利用掩膜板通 过曝光、 显影等工艺对此涂层进行图案化处理， 以形成有机绝缘层 140。 该有机 绝缘层 140中在与栅极金属层 120的晶体管栅极 121对应的区域具有开孔 141。 开孔 141一般为通孔， 用以暴露栅极绝缘层 130中的与栅极金属层 120的晶体管 栅极 121对应的区域 （参见图 4) 。
5 )采用等离子增强化学气相沉积法（PECVD)在有机绝缘层 140上沉积氢 化非晶硅 a-Si:H以及用于制作漏极金属线和源极金属线的金属材料， 其厚度可以 是 1000A〜6000A。 然后利用灰阶掩膜板通过曝光、 显影、 1次 S/D湿法刻蚀、 1 次 a-Si干法刻蚀和沟道光刻胶灰化、 2次沟道 S/D湿法刻蚀、沟道 N+干刻、剥离 等构图工艺进行图案化处理， 以形成包括多个晶体管沟道的有源层 150， 以及包 括多条漏极金属线和源极金属线的源漏极金属层 160。 其中， 源漏极金属层 160 沉积在有源层 150上， 有源层 150的一部分沉积在有机绝缘层 140的开孔 141的 两侧， 以及在开孔 141的内部直接沉积在栅极绝缘层 130上 （参见图 5 ) ， 以减 小有源层 150中的晶体管沟道 151与栅极金属层 120中所对应的栅极 121之间的 距离， 确保驱动晶体管正常工作。
6) 采用等离子增强化学气相沉积法 （PECVD) 在源漏极金属层 160上沉积 一层绝缘材料 （例如氮化硅 SiNx) ， 作为钝化保护层 170， 以保护源漏极金属层 160。该钝化保护层 170的厚度可以是 1000A〜6000A。然后利用掩膜板通过曝光、 显影、 刻蚀和剥离等光刻工艺对此钝化保护层 170进行图案化处理， 以使该钝化 保护层 170中具有贯通的开孔 171， 从而暴露源漏极金属层 160中的漏极金属线 和 /或源极金属线的一部分 （参见图 6) 。
7) 采用溅射镀膜法 （Sputtering) 在钝化保护层 170上沉积一层透明导电材 料 （例如 ITO或者 IZO) ， 其厚度可以是 100 A〜1000 A。 然后利用掩膜板通过 曝光、 显影、 刻蚀和剥离等光刻工艺进行图案化处理， 以形成图案化的像素电极 层 180。 该像素电极层 180的一部分沉积在钝化保护层 170的开孔 171的两侧， 以及在开孔 171的内部直接沉积在源漏极金属层 160中的漏极金属线和 /或源极金 属线上 （参见图 1 ) 。
本发明通过上述方法， 在阵列基板的栅极金属层上设置一层有机绝缘层 （一 种高透过率低介电常数的光刻胶） ， 以增加栅极金属层与源漏极金属层之间的距 离， 从而降低金属线交叉处及金属线彼此间的耦合容抗， 有效减小整个阵列基板 的负载， 降低阵列基板逻辑功耗， 延长使用寿命。 此外， 由于有机绝缘层较厚且 平坦， 因此还能够有效防止静电现象， 并且避免金属线的爬坡断线， 从而提高面 板生产良率， 降低生产成本。
当然， 本发明提出的阵列基板及其制备方法， 远不限于上述实施例， 还可以 适用于其他类型的阵列基板。
此外， 本发明还提出了一种包括上述阵列基板的液晶显示面板。
以上所述， 仅为本发明较佳的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉该技术的人员在本发明所揭露的技术范围内， 可轻易想到的变化 或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护范围应该以权 利要求的保护范围为准。

Claims

权利要求书
1、 一种阵列基板， 其包括：
玻璃基板；
形成于所述玻璃基板上的图案化的栅极金属层；
形成于所述栅极金属层上的栅极绝缘层；
形成于所述栅极绝缘层上的图案化的有机绝缘层， 所述有机绝缘层在其与所 述栅极金属层中的晶体管栅极对应的区域设置有开孔；
形成于所述有机绝缘层上的图案化的有源层， 所述有源层的一部分沉积于所 述有机绝缘层的开孔的两侧和开孔的内部；
形成于所述有源层上的图案化的源漏极金属层。
2、 如权利要求 1所述的阵列基板， 其中：
所述有机绝缘层的开孔为通孔， 以暴露所述栅极绝缘层中的与所述栅极金属 层中的晶体管栅极对应的区域。
3、 如权利要求 1所述的阵列基板， 其中：
所述有机绝缘层的厚度为 10000A〜30000A。
4、 如权利要求 2所述的阵列基板， 其中：
所述有机绝缘层的厚度为 10000Α〜30000Α。
5、 如权利要求 1所述的阵列基板， 其中：
所述有机绝缘层的材料为聚丙烯酸。
6、 如权利要求 2所述的阵列基板， 其中：
所述有机绝缘层的材料为聚丙烯酸。
7、 如权利要求 3所述的阵列基板， 其中：
所述有机绝缘层的材料为聚丙烯酸。
8、 如权利要求 1所述的阵列基板， 其还包括：
形成于所述源漏极金属层上的图案化的钝化保护层；
形成于所述钝化保护层上的图案化的像素电极层。
9、 一种液晶显示面板， 其包括阵列基板， 所述阵列基板包括：
玻璃基板；
形成于所述玻璃基板上的图案化的栅极金属层；
形成于所述栅极金属层上的栅极绝缘层； 形成于所述栅极绝缘层上的图案化的有机绝缘层， 所述有机绝缘层在其与所 述栅极金属层中的晶体管栅极对应的区域设置有开孔；
形成于所述有机绝缘层上的图案化的有源层， 所述有源层的一部分沉积于所 述有机绝缘层的开孔的两侧和开孔的内部；
形成于所述有源层上的图案化的源漏极金属层。
10、 如权利要求 9所述的液晶显示面板， 其中：
所述阵列基板的有机绝缘层的开孔为通孔， 以暴露所述栅极绝缘层中的与所 述栅极金属层中的晶体管栅极对应的区域。
11、 如权利要求 9所述的液晶显示面板， 其中：
所述阵列基板的有机绝缘层的厚度为 10000A〜30000A。
12、 如权利要求 9所述的液晶显示面板， 其中：
所述阵列基板的有机绝缘层的材料为聚丙烯酸。
13、 如权利要求 9所述的液晶显示面板， 其中所述阵列基板还包括： 形成于所述源漏极金属层上的图案化的钝化保护层；
形成于所述钝化保护层上的图案化的像素电极层。
14、 一种阵列基板的制备方法， 包括以下步骤：
提供一玻璃基板；
在玻璃基板上形成图案化的栅极金属层；
在栅极金属层上形成栅极绝缘层；
在栅极绝缘层上形成图案化的有机绝缘层， 且所述有机绝缘层在其与栅极金 属层中的晶体管栅极对应的区域设置开孔；
在有机绝缘层上形成图案化的有源层， 且使有源层的一部分沉积于有机绝缘 层的开孔的两侧和开孔的内部；
在有源层上形成图案化的源漏极金属层。
15、 如权利要求 14所述的制备方法， 其中：
还将所述有机绝缘层的开孔设置为通孔， 以暴露所述栅极绝缘层中的与所述 栅极金属层中的晶体管栅极对应的区域。
16、 如权利要求 14所述的制备方法， 其还包括以下步骤：
在源漏极金属层上形成图案化的钝化保护层；
在钝化保护层上形成图案化的像素电极层。
17、 如权利要求 14所述的制备方法， 其中： 将有机绝缘层的厚度设置为 10000A〜30000A。
PCT/CN2014/077594 2014-03-03 2014-05-15 一种阵列基板及其制备方法、液晶显示面板 WO2015131443A1 (zh)

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