CN108346562A - 低温多晶硅、薄膜晶体管及阵列基板的制作方法 - Google Patents
低温多晶硅、薄膜晶体管及阵列基板的制作方法 Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 239000010409 thin film Substances 0.000 title abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 33
- 239000012528 membrane Substances 0.000 claims abstract description 22
- 238000005224 laser annealing Methods 0.000 claims abstract description 9
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 230000000903 blocking effect Effects 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910004205 SiNX Inorganic materials 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 239000004575 stone Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 11
- 239000010408 film Substances 0.000 abstract description 9
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 9
- 238000002425 crystallisation Methods 0.000 description 8
- 230000008025 crystallization Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004579 marble Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 that is Substances 0.000 description 1
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Abstract
本发明涉及一种低温多晶硅、薄膜晶体管及阵列基板的制作方法。该低温多晶硅制作方法包括:提供基板,在所述基板上形成缓冲层;在所述缓冲层上形成非晶硅层;在半透膜掩模板的遮挡下对所述非晶硅层进行准分子激光退火处理,使所述非晶硅层转变为多晶硅层;所述半透膜掩模板包括透光的衬底和设于所述衬底表面的图案化的半透膜。本发明还提供了相应的低温多晶硅薄膜晶体管及阵列基板的制作方法。本发明的低温多晶硅、薄膜晶体管及阵列基板的制作方法可以使得多晶硅结晶效果更好,改善多晶硅薄膜晶体管的电性能,同时又能提升多晶硅层的干法刻蚀效率,释放生产制造多晶硅的产能。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种低温多晶硅、薄膜晶体管及阵列基板的制作方法。
背景技术
薄膜晶体管(Thin Film Transistor,TFT)是目前液晶显示装置(Liquid CrystalDisplay,LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode,AMOLED)中的主要驱动元件,直接关系平板显示装置的显示性能。薄膜晶体管具有多种结构,制备相应结构的薄膜晶体管的材料也具有多种,根据有源层的材料不同,可以将薄膜晶体管分为非晶硅薄膜晶体管、多晶硅薄膜晶体管等类型。
多晶硅薄膜晶体管与非晶硅薄膜晶体管相比,具有更高的电子迁移率、更快的反应时间和更高的分辨率,目前已广泛应用于显示装置,作为驱动电路部分的开关元件。多晶硅薄膜晶体管的制作方法一般采用制作低温多晶硅(LTPS)的方法,其中通常采用化学气相沉积(CVD)形成非晶硅层,再对该非晶硅层进行结晶化处理。目前一般采用准分子激光退火(ELA)技术进行结晶化,非晶硅层被308纳米激光照射后熔化形成非晶硅液体,非晶硅液体冷却时,非晶硅液体依附晶核逐渐结晶生长而形成多晶硅层。目前的准分子激光退火主要还是整面性进行激光照射结晶,这种结晶最大的缺陷就是均一性较差,较难应用于大尺寸面板。
现有的低温多晶硅制作过程如图1所示,首先采用化学气相沉积法在玻璃基板10上形成缓冲层20,缓冲层20可以为厚度1000埃~2000埃的SiNx/SiO2双层结构或SiNx/SiNO/SiO2三层结构,然后采用化学气相沉积法在缓冲层20上形成厚度300埃~800埃的非晶硅层30,最后在室温和大气压下采用准分子激光退火设备也就是激光器40对非晶硅层30进行激光退火结晶化处理,形成多晶硅层。
发明内容
因此,本发明的目的在于提供一种低温多晶硅制作方法,提升多晶硅结晶效果。
本发明的另一目的在于提供一种低温多晶硅薄膜晶体管制作方法,提升多晶硅结晶效果。
本发明的再一目的在于提供一种低温多晶硅薄膜晶体管阵列基板制作方法,提升多晶硅结晶效果。
为实现上述目的,本发明提供了一种低温多晶硅制作方法,包括:
提供基板,在所述基板上形成缓冲层;
在所述缓冲层上形成非晶硅层;
在半透膜掩模板的遮挡下对所述非晶硅层进行准分子激光退火处理,使所述非晶硅层转变为多晶硅层;
所述半透膜掩模板包括透光的衬底和设于所述衬底表面的图案化的半透膜。
其中,所述图案化的半透膜对应于非晶硅层的非硅岛区。
其中,所述缓冲层厚度为1000埃~2000埃。
其中,所述缓冲层为SiNx/SiO2双层结构。
其中,所述缓冲层为SiNx/SiNO/SiO2三层结构。
其中,所述非晶硅层厚度为300埃~800埃。
其中,所述衬底为透光的大理石衬底。
本发明还提供了一种低温多晶硅薄膜晶体管制作方法,应用上述任一项所述的低温多晶硅制作方法制作低温多晶硅层。
本发明还提供了一种低温多晶硅薄膜晶体管阵列基板制作方法,应用上述的低温多晶硅薄膜晶体管制作方法制作低温多晶硅薄膜晶体管。
综上,本发明的低温多晶硅、薄膜晶体管及阵列基板的制作方法可以使得多晶硅结晶效果更好,改善多晶硅薄膜晶体管的电性能,同时又能提升多晶硅层的干法刻蚀效率,释放生产制造多晶硅的产能。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为现有的低温多晶硅制作过程示意图;
图2为本发明低温多晶硅制作方法一较佳实施例的低温多晶硅制作过程示意图;
图3为本发明低温多晶硅制作方法一较佳实施例制作完成的低温多晶硅结构示意图。
具体实施方式
参见图2,其为本发明低温多晶硅制作方法一较佳实施例的低温多晶硅制作过程示意图。本发明的低温多晶硅制作方法提供了一种提高多晶硅层结晶均匀性的退火方法,主要包括:
提供基板10,在所述基板10上形成缓冲层20;首先,可以采用化学气相沉积法在玻璃衬底即基板10上形成厚度为1000埃~2000埃的SiNx/SiO2双层结构或SiNx/SiNO/SiO2三层结构缓冲层。
在所述缓冲层20上形成非晶硅层30;可以采用化学气相沉积法在缓冲层20上沉积非晶硅层30,非晶硅层30厚度可以为300埃~800埃。
在半透膜掩模板50的遮挡下对所述非晶硅层30进行准分子激光退火处理,使所述非晶硅层30转变为多晶硅层;利用激光器40发出准分子激光,然后在半透膜掩模板50的遮挡下对非晶硅层30进行激光退火。
半透膜掩模板50包括透光的衬底51和设于所述衬底51表面的图案化的半透膜52。半透膜掩模板50与传统的光刻掩模板设计方法相同,衬底51可以为透光的大理石衬底,利用半透膜52进行部分吸收激光能量,进而在非晶硅层30上产生照射温度梯度。因为最终形成的多晶硅层即为薄膜晶体管的有源层,所以半透膜掩模板50上的半透膜区域与有源层的非硅岛区对应,半透膜掩模板50的非半透膜区域与有源层的硅岛区对应,也就是图案化的半透膜52对应于非晶硅层30的非硅岛区。通过采用半透膜掩模板50,可以在硅岛区进行全开激光照射,其他区域进行半透膜遮挡退火,使得非晶硅层30的硅岛区温度大于其他区域的温度。
为提升制作效果,本发明低温多晶硅制作方法还可以包括现有制程中的常用步骤,例如对非晶硅层进行去氢处理,在此不再赘述。
参见图3,其为本发明低温多晶硅制作方法一较佳实施例制作完成的低温多晶硅结构示意图,展示了图2所示的基板10及缓冲层20上的非晶硅层30经退火完成后的结构。由于硅岛区温度大于其他区域的温度,因此温度梯度使得硅岛区结晶效果更好,形成硅岛区的多晶硅31,可以改善多晶硅薄膜晶体管的电性能。同时由于非硅岛区的温度较低,结晶度较差,形成非硅岛区的多晶硅32,因此更容易进行刻蚀,可以提升多晶硅层的干法刻蚀效率,释放生产制造多晶硅的产能。
应用本发明低温多晶硅制作方法,可以相应制作多晶硅结晶效果更好的低温多晶硅薄膜晶体管及阵列基板。
综上,本发明的低温多晶硅、薄膜晶体管及阵列基板的制作方法可以使得多晶硅结晶效果更好,改善多晶硅薄膜晶体管的电性能,同时又能提升多晶硅层的干法刻蚀效率,释放生产制造多晶硅的产能。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (9)
1.一种低温多晶硅制作方法,其特征在于,包括:
提供基板,在所述基板上形成缓冲层;
在所述缓冲层上形成非晶硅层;
在半透膜掩模板的遮挡下对所述非晶硅层进行准分子激光退火处理,使所述非晶硅层转变为多晶硅层;
所述半透膜掩模板包括透光的衬底和设于所述衬底表面的图案化的半透膜。
2.如权利要求1所述的低温多晶硅制作方法,其特征在于,所述图案化的半透膜对应于非晶硅层的非硅岛区。
3.如权利要求1所述的低温多晶硅制作方法,其特征在于,所述缓冲层厚度为1000埃~2000埃。
4.如权利要求1所述的低温多晶硅制作方法,其特征在于,所述缓冲层为SiNx/SiO2双层结构。
5.如权利要求1所述的低温多晶硅制作方法,其特征在于,所述缓冲层为SiNx/SiNO/SiO2三层结构。
6.如权利要求1所述的低温多晶硅制作方法,其特征在于,所述非晶硅层厚度为300埃~800埃。
7.如权利要求1所述的低温多晶硅制作方法,其特征在于,所述衬底为透光的大理石衬底。
8.一种低温多晶硅薄膜晶体管制作方法,其特征在于,应用如权利要求1~7中任一项所述的低温多晶硅制作方法制作低温多晶硅层。
9.一种低温多晶硅薄膜晶体管阵列基板制作方法,其特征在于,应用如权利要求8所述的低温多晶硅薄膜晶体管制作方法制作低温多晶硅薄膜晶体管。
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