WO2019169885A1 - 一种阵列基板的制造方法和阵列基板 - Google Patents

一种阵列基板的制造方法和阵列基板 Download PDF

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WO2019169885A1
WO2019169885A1 PCT/CN2018/113606 CN2018113606W WO2019169885A1 WO 2019169885 A1 WO2019169885 A1 WO 2019169885A1 CN 2018113606 W CN2018113606 W CN 2018113606W WO 2019169885 A1 WO2019169885 A1 WO 2019169885A1
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Prior art keywords
layer
region
source
substrate
array substrate
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PCT/CN2018/113606
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English (en)
French (fr)
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卓恩宗
莫琼花
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/253,440 priority Critical patent/US20190280016A1/en
Publication of WO2019169885A1 publication Critical patent/WO2019169885A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the embodiments of the present application relate to active switching technologies, and in particular, to a method for fabricating an array substrate and an array substrate.
  • the active switch is a key component of the display panel and plays an important role in the performance of the display panel.
  • people require that the power consumption of the electronic device be as low as possible, and the higher the endurance, the better. Low power consumption of display panels in electronic devices is also required.
  • the active switch array substrate is disposed in the display panel.
  • the active switch of the active switch array substrate has a relatively large leakage current, and when the light is irradiated onto the active switch, photogenerated carriers are generated to further increase the leakage current of the active switch.
  • the power consumption of the display panel is large, and the stability of the active switch is poor.
  • the embodiment of the present application provides a method for fabricating an array substrate and an array substrate to reduce leakage current of an active switch on the array substrate and improve stability of the active switch.
  • the embodiment of the present application provides a method for manufacturing an array substrate, the array substrate includes a plurality of active switches, and the method for manufacturing the array substrate includes:
  • a gate electrode Forming a gate electrode, a gate insulating layer, a semiconductor layer, a source/drain electrode layer, and a photoresist layer on the substrate;
  • patterned photoresist layer As a mask, patterning the source/drain electrode layer, forming a source of the active switch in a portion covered by the first region, in the A portion covered by the two regions forms a drain of the active switch, and the semiconductor layer is patterned to form a channel region of the active switch at a portion covered by the third region.
  • the embodiment of the present application further provides an array substrate, wherein the array substrate is formed with a plurality of active switches, and the active switch is formed by the manufacturing method provided above, and the active switch includes:
  • the source and the drain are located on a side of the semiconductor layer away from the substrate;
  • the distance between the projection profile of the semiconductor layer on the substrate and the projection profile of the source or the drain on the substrate ranges from 0 to 1.5 microns;
  • the pitch of the projection profile on the substrate and the projection profile of the source or the drain on the substrate ranges from 0 to 1.0 micron.
  • the manufacturing method of the array substrate provided by the embodiment of the present invention can reduce the portion of the active switch in which the semiconductor layer exceeds the source and the drain, thereby reducing the absorption light of the semiconductor layer in the active switch, generating the probability of photogenerated carriers, and reducing the probability.
  • the leakage current of the active switch correspondingly improves the stability of the active switch, and when the active switch is applied in the display panel, the power consumption of the display panel can also be reduced.
  • FIG. 1 is a schematic structural diagram of an active switch on an array substrate provided by an example technology
  • FIG. 2 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present application
  • FIG. 3 is a schematic diagram showing the principle of a patterned photoresist layer provided in the implementation of the present application.
  • FIG. 4 is a schematic diagram showing relationship between exposure energy and retention thickness of a photoresist layer provided by an embodiment of the present application
  • FIG. 5 is a plan view of the patterned photoresist layer provided by the embodiment of the present application.
  • Figure 6 is a cross-sectional structural view along section line B to B' in the top view of Figure 5;
  • FIG. 7 is a schematic view showing a thickness retention of a third region of a photoresist layer of six different samples according to an embodiment of the present application.
  • FIG. 8 is a schematic structural view of a film layer after depositing a photoresist layer in a method for fabricating an array substrate according to an embodiment of the present application;
  • FIG. 9 is a schematic structural view of a film layer after patterning a photoresist layer in a method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 10 is a schematic structural view of a film layer after the first wet etching in the method for fabricating the array substrate according to the embodiment of the present application;
  • FIG. 11 is a schematic structural view of a film layer after the first dry etching in the method for fabricating an array substrate according to an embodiment of the present application;
  • FIG. 12 is a schematic structural view of a film layer after photoresist ashing in the method for fabricating an array substrate according to an embodiment of the present application;
  • FIG. 13 is a schematic structural view of a film layer after a second wet etching in the method for fabricating an array substrate according to an embodiment of the present application;
  • FIG. 14 is a schematic structural view of a film layer after a second dry etching in the method for fabricating an array substrate according to an embodiment of the present application;
  • 15 is a schematic view showing an etching direction of a photoresist layer of an array substrate according to an embodiment of the present application.
  • 16 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • 17 is a schematic structural diagram of an active switch on an array substrate according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present application.
  • FIG. 1 is a structural diagram of an active switch on an array substrate provided by an example technology.
  • the active switch includes a substrate 11, a gate electrode 12, a gate insulating layer 13, an active layer 14 (usually formed of an amorphous silicon material, so may also be referred to as an amorphous silicon layer 14), and a doped layer.
  • the source-drain electrodes 16 optionally include a source 161 and a drain 162, wherein the semiconductor layer of the active switch may include an active layer 14 and a doped layer 15.
  • the gate 12 and the source 161 of the active switch, the gate 12 and the drain 162 are separated by a gate insulating layer 13, so that the active switch is actually an insulated gate field effect transistor, and the active switch can be divided into N Type and P type.
  • the N-type active switch is taken as an example to explain the working principle of the active switch.
  • a positive voltage greater than the turn-on voltage of the N-type active switch is applied to the gate electrode 12
  • an electric field is generated between the gate electrode 12 and the active layer 14, and under the action of the electric field, a conductive layer is formed in the active layer 14.
  • the channel forms an on state between the source 161 and the drain 162.
  • the source 161 and the drain 162 are added.
  • the upper voltage will have carriers passing through the conductive channel; and when the gate 12 is applied with a negative voltage lower than the turn-on voltage of the N-type active switch, the electron channel will not form in the active layer 14, and the source 161 A closed state is formed between the drain 162 and the drain 162.
  • a doping layer 15 is formed between the active layer 14 and the source 161, the active layer 14 and the drain 162, and is provided to reduce the resistance of the active layer 14 and the source-drain electrodes 16 signals.
  • the edge of the amorphous silicon layer 14 formed exceeds the edge of the source/drain electrode 16, that is, the amorphous silicon tail L2 is formed, and the edge of the doped layer 15 formed exceeds the edge of the source/drain electrode 16. That is, the doped layer channel outer tail L1 and the doped layer channel inner end tail L3 are formed, and when the active switch is applied in the liquid crystal display panel, the presence of the above three types of tails, especially the amorphous silicon tail L2, may directly contact or absorb.
  • the amorphous silicon layer 14 reacts with visible light to generate a light leakage current, thereby further increasing the leakage current of the active switch, resulting in a large power consumption of the array substrate, and also causing unstable electrical performance of the active switch.
  • FIG. 2 is a method for fabricating an array substrate according to an embodiment of the present application. Schematic diagram of the process.
  • Optional includes:
  • the substrate may be a glass substrate or a flexible substrate such as polyimide (PI).
  • PI polyimide
  • the substrate material includes but is not limited to a glass substrate and a flexible substrate, and any one can be used as an array substrate. The materials of the substrate fall within the scope of protection of the present application.
  • the constituent material of the optional gate is aluminum (Al) or molybdenum (Mo)
  • the constituent material of the gate insulating layer is silicon nitride (SiN)
  • the semiconductor layer may include an active layer and a doped layer, wherein The constituent material of the active layer is amorphous silicon (a to Si), and the constituent material of the doped layer is heavily doped amorphous silicon, and optionally may include N-type amorphous silicon or P-type amorphous silicon, source and drain
  • the constituent material of the pole layer is a constituent material of a molybdenum nitride, aluminum and molybdenum nitride (MoN/Al/MoN) photoresist layer which are sequentially laminated, including a resin, a sensitizer, a solvent and an additive, wherein the sensitizer is photolithography
  • the photosensitive component in the adhesive layer undergoes a photochemical reaction to the radiant energy (especially the ultraviolet region) in the form of light
  • Photoresist can be divided into positive gel and negative gel from the application characteristics.
  • positive gel the part irradiated by ultraviolet light will be removed due to chemical changes, while the negative gel is opposite.
  • the part irradiated by ultraviolet light will be chemically affected.
  • the nature of the change is retained, and the optional glue in the embodiment is taken as an example for description.
  • the constituent materials of the film layers of the array substrate include, but are not limited to, the above examples, and the constituent materials of the film layer structure of any one of the array substrates fall within the protection scope of the present application;
  • the constituent materials of the film layer structure of any one of the array substrates fall within the protection scope of the present application.
  • the patterned photoresist layer includes a first region and a second region, and a first region and a second region.
  • the thickness of the three regions and the third region ranges from 0.2 to 0.8 ⁇ m.
  • Patterning the photoresist layer in this embodiment may include removing the thickness of the flattened photoresist layer surface by an exposure and development technique to form a patterned (embossed) photoresist layer.
  • the patterned photoresist layer includes the above three regions.
  • the thickness of the third region ranges from 0.2 to 0.8 micrometers, which ensures that the photoresist in the third region is completely etched during the subsequent etching of the photoresist, that is, the active switch corresponding to the third region. When fully exposed, the remaining thickness and lateral dimensions of the first and second regions ensure that their corresponding active switch structures are effectively covered.
  • patterning the source/drain electrode layer comprises performing at least one wet etching on the source/drain electrode layer; and patterning the semiconductor layer comprises performing at least one dry etching on the semiconductor layer.
  • the wet etching may include etching the source/drain electrode layer with a mixed solution of phosphoric acid (H 3 PO 4 ), acetic acid (CH 3 COOH), and nitric acid (HNO 3 ), and etching the semiconductor layer by vacuum plasma.
  • the etching gas may include a mixed gas of sulfur hexafluoride (SF 6 ) and chlorine (Cl 2 ) or sulfur hexafluoride (SF 6 ), oxygen (O 2 ) and helium Gas (He) mixed gas.
  • the photoresist layer is patterned by using a halftone mask process, and the illumination energy required to expose the third region ranges from 37 to 48 millijoules.
  • FIG. 3 is a schematic diagram of a schematic structure of a patterned photoresist layer provided by an embodiment of the present application.
  • the exposed sample may optionally include a photoresist layer 24, a source/drain electrode layer 23, and other functional layers 22 (which may include a semiconductor layer, a gate insulating layer, and a gate layer, which are generally summarized in FIG. 22 shows) and the substrate 21.
  • the halftone mask 25 may optionally include three regions, a first region 251 corresponding to a source formation region of the exposed sample, a second region 252 corresponding to a drain formation region of the exposed sample, and a third region 253 at the first Between the region 251 and the second region 252, a channel formation region of the sample to be exposed is corresponding. Since the transmittances of the first region 251, the second region 252, and the third region 253 of the halftone mask 25 are different, the exposure of the incident light to the photoresist layer 24 is different after passing through the halftone mask 25. Thereby forming a patterned photoresist layer 24. In FIG.
  • X represents the different positions of the exposed sample (mainly referred to as the photoresist layer 24) corresponding to the halftone mask (in nanometers or micrometers, according to the actual requirements of the active switch, Not limited herein, Y represents the exposure energy (in millijoules), and the broken line 26 represents a trend corresponding to the magnitude of the exposure energy at different positions.
  • the photoresist layer 24 corresponds to the positions of the first region 251 and the second region 252 of the halftone mask 25, and since the light transmitted through the halftone mask 25 is small, the corresponding exposure energy is small, and the photoresist layer 24 is The portion to be removed is less, and the corresponding thickness is thicker; the photoresist layer 24 corresponds to the position of the third region 253 of the halftone mask 25, since the light transmitted through the halftone mask 25 is more, the corresponding exposure When the energy is large, the photoresist layer 24 is removed more, and the thickness corresponding to the retention is thin (the remaining thickness of the photoresist layer 24 is shown by H0 in FIG. 3).
  • the photoresist layer 24 is formed to have a patterned photoresist layer 24 corresponding to different thicknesses at different locations.
  • FIG. 4 is a schematic diagram of relationship between exposure energy and retention thickness of the photoresist layer provided by the embodiment of the present application. 3 and 4, the horizontal axis is the exposure energy Dose, the unit is millijoules (mJ), and the vertical axis is the photoresist layer 24 retention thickness Thic., the unit is Amy.
  • the broken line 51 represents the correspondence relationship between the thickness of the photoresist layer 24 and the exposure energy Dose.
  • the exposure energy Dose is controlled to be in the range of 37 to 48 mJ, so that the photoresist layer 24 can have a thickness of Thic. of 2000 to 8000 angstroms, that is, 0.2 to 0.8 m.
  • the remaining thickness Thic. of the photoresist layer 24 is reduced by 0.1 ⁇ m, and the required exposure energy Dose is 1.5 millijoules;
  • the thickness of the photoresist layer 24 is in the range of 0.2 to 0.4 ⁇ m, the remaining thickness Thic. of the photoresist layer 24 is reduced by 0.1 ⁇ m, and the required exposure energy Dose is 2.5 mJ. Therefore, it is necessary to control the value of the appropriate exposure energy according to the retention target thickness of the photoresist layer 24.
  • FIG. 5 is a top view of the patterned photoresist layer provided by the embodiment of the present application.
  • FIG. 5 optionally shows a first region and a second region of the photoresist layer at 34, a third region of the photoresist layer at 33; and an optional point A1, A2, and B1. The location in which the thickness of the third region of the photoresist layer 24 is minimized is shown.
  • Fig. 6 is a schematic cross-sectional view along the section line B to B' in the top view of Fig. 5. Referring to FIG.
  • a plurality of functional layers 403 (which may include a gate, a gate insulating layer, a semiconductor layer, and a source/drain electrode layer, which are not specifically divided in FIG. 6 and are shown by 403) and a photolithography are formed on the substrate 401.
  • the first region and the second region of the photoresist layer 404 have a remaining thickness H1 of 1.8 to 2.2 micrometers.
  • the angle ⁇ between the surface of the recess of the photoresist layer 404 and the interface between the photoresist layer 404 and the multi-layer functional layer 403 ranges from 28 to 32°.
  • the first and second regions of the photoresist layer 24 have a remaining thickness H1 of 2.174 micrometers, and the third region has a minimum thickness H2 of 0.54 micrometers, and the pit surface and the photoresist layer 404 and the plurality of layers.
  • the value of the angle ⁇ between the interfaces of the functional layer 403 is 30.69°.
  • the third region of the photoresist layer retains a thickness uniformity ranging from 25% to 55%.
  • the uniformity characterizes the flatness of the thickness retained in the third region.
  • the numerical calculation method for uniformity can be as follows:
  • H max represents the maximum value of the retained thickness of the third region
  • H min represents the minimum value of the retained thickness of the third region. The smaller the value of the uniformity U%, the better the uniformity of the thickness retained in the third region of the photoresist layer.
  • FIG. 7 is a schematic diagram of the remaining thickness of the third region of the photoresist layer of the six different samples provided by the embodiments of the present application.
  • the horizontal axis represents different sample numbers
  • Sam. 1 to Sam. 6 represent six different sized samples
  • the two longitudinal axes representing the remaining thickness of the photoresist layer 24, Thic.
  • the remaining thickness of the photoresist layer 24 is in the unit of Amy Line 601 represents the average of the retained target thickness of photoresist layer 24, optionally 0.5 microns, line 602 represents the maximum retained target thickness of photoresist layer 24, optionally 0.65 microns, line 603 represents light
  • the minimum retention target thickness of the engraved layer 24 may alternatively be 0.35 micrometers;
  • the dots on the fold line 61 represent the minimum remaining thickness of the photoresist layer 24, and the optional range is 0.3 to 0.36 micrometers, and the fold line
  • the dots on 63 represent the actual maximum thickness of the photoresist layer 24, with an optional range of 0.54 to 0.69 microns, and the dots on the fold line 62 represent the average of the actual thickness of the photoresist layer 24, optionally The value ranges from 0.4 to 0.47 microns;
  • the dots on the fold line 64 represent the uniformity of the actual thickness of the photoresist layer 24, and the optional range is from 25.95% to 40.95%.
  • the manufacturing method includes two wet etchings and two dry etchings, and the wet etching and the dry etching are alternately performed.
  • the method may include: first wet etching, patterning the source/drain electrode layer, forming a metal wire structure of the source region, the drain region, and the active region; and performing a first dry etching to form a semiconductor layer (the semiconductor layer includes Source layer and doped layer) island structure, that is, patterned semiconductor layer (including active layer and doped layer); second wet etching, patterning source and drain electrode layer, forming source in source region, Forming a drain in the drain region; a second dry etching, etching the semiconductor layer (including the active layer and the doped layer), that is, etching the semiconductor layer (including the active layer and the doped layer) to form an active Switch structure.
  • the dry etch can be etched by 10%, and optionally, the etch time is 76 seconds, thereby further reducing the portion of the semiconductor layer that exceeds the source and drain.
  • the feature size loss per side of the photoresist layer 414 is 0.94 microns.
  • the manufacturing method further includes performing at least one photoresist ashing step, and the photoresist ashing step is disposed between the dry etching and the wet etching step. Specifically, after the first dry etching, a photoresist ashing step is performed before the second wet etching, and the third region photoresist is removed to expose the source and drain electrodes of the channel region. Floor.
  • FIG. 8 to FIG. 14 are formed after each step in the method for manufacturing an array substrate based on two wet etching, two dry etching, and one photoresist ashing according to an embodiment of the present application.
  • a bottom gate type active switch is formed on an array substrate, and reference numerals are used in FIGS. 8 to 14.
  • FIG. 8 is a schematic structural diagram of a film layer after depositing a photoresist layer in the method for fabricating an array substrate according to an embodiment of the present application. Referring to FIG.
  • the specific structure may include: providing a substrate 100, and sequentially forming a gate 110, a gate insulating layer 120, a semiconductor layer (including the active layer 130 and the doping layer 140), and a source/drain electrode layer on the substrate 100. And a photoresist layer 160, wherein the source/drain electrode layer 150 may include a molybdenum nitride layer 151, an aluminum layer 152, and a molybdenum nitride layer 153 which are sequentially stacked; the active layer 130 and the doped layer 140 together form a semiconductor Layer (no label is set in Figure 8).
  • FIG. 9 is a schematic structural diagram of a film layer after patterning a photoresist layer in a method of fabricating an array substrate according to an embodiment of the present application.
  • the photoresist layer 160 is patterned to form a patterned photoresist layer 160.
  • the patterned photoresist layer 160 includes a first region Z1 and a second region Z2, and is located in the first region Z1.
  • the third region Z3 between the second region Z2 and the thickness H3 of the third region Z3 ranges from 0.2 to 0.8 micrometers.
  • FIG. 10 is a schematic structural view of a film layer after the first wet etching in the method for fabricating the array substrate according to the embodiment of the present application. Referring to FIG.
  • FIG. 11 is a schematic structural diagram of a film layer after the first dry etching in the method for manufacturing the active switch according to the embodiment of the present application. Referring to FIG. 11, after the first dry etching, the semiconductor layer (including the active layer 130 and the doped layer 140) is patterned.
  • FIG. 12 is a schematic view showing the structure of a film layer after photoresist ashing in the method for fabricating an array substrate according to an embodiment of the present invention. Referring to FIG. 12, after the photoresist is ashed, the source/drain electrode layer 150 of the channel region is exposed.
  • FIG. 13 is a schematic structural view of a film layer after a second wet etching in the method for fabricating an array substrate according to an embodiment of the present invention.
  • the patterned source/drain electrode layer 150 is formed.
  • a source 15a is formed in the source region (a region corresponding to the first region Z1 of the photoresist layer 24), and a drain 15b is formed in the drain region (a region corresponding to the second region Z2 of the photoresist layer 24).
  • 14 is a schematic structural view of a film layer after a second dry etching in the method for fabricating an array substrate according to an embodiment of the present application. Referring to FIG.
  • the semiconductor layer is etched (including The source layer 130 and the doped layer 140) form an array substrate structure, especially an active switch structure on the array substrate.
  • FIG. 8 to FIG. 14 show the formation process of the active switch on the array substrate, especially the array substrate, wherein the reduced portion of the latter image relative to the previous image is removed in the corresponding step. section.
  • the active switch structure on the array substrate thus formed reduces the portion of the semiconductor layer beyond the source and the drain, that is, reduces the portion of the active layer beyond the source and the drain, and reduces the doping layer beyond the source and drain.
  • the part reduces the absorption light of the semiconductor layer in the active switch on the array substrate, generates the probability of photogenerated carriers, reduces the leakage current of the active switch, and correspondingly improves the stability of the active switch.
  • the ratio of the lateral etch rate to the longitudinal etch rate in the photoresist ashing step ranges from 1:0.9 to 1:1.5.
  • FIG. 15 is a schematic diagram of an etch direction of an array substrate photoresist layer provided by an embodiment of the present application.
  • a plurality of functional layers 413 which may include a gate, a gate insulating layer, a semiconductor layer, and a source/drain electrode layer, which are not specifically divided in FIG. 15 and are shown by 413) and a pattern are formed on the substrate 411.
  • the ratio of the etch rate in the lateral direction (S direction in FIG. 15) to the etch rate in the longitudinal direction (T direction in FIG. 15) ranges from 1:0.9 to 1:1.5.
  • the location of the H4 is a first region or a second region of the photoresist layer
  • the location of the H5 is a third region of the photoresist layer.
  • the etching gas includes sulfur hexafluoride and oxygen.
  • the etching gas when the ratio of the lateral etching rate to the longitudinal etching rate is 1:0.9, the etching gas is oxygen; when the ratio of the lateral etching rate to the longitudinal etching rate is 1:1.5, the etching gas is hexafluoride. Sulfur and oxygen, and the flow ratio of sulfur hexafluoride to oxygen ranges from 0.02 to 0.1.
  • the gas in the photoresist ashing step, in the vacuum environment, the gas generates a plasma under the action of the radio frequency power source, and the plasma high-energy bombards the surface of the photoresist layer or reacts with the surface of the photoresist layer to make the photoresist layer Ashing, that is, the photoresist layer is thinned or removed.
  • the sulfur hexafluoride gas By increasing the sulfur hexafluoride gas, the longitudinal etching rate of the photoresist layer can be accelerated, and by controlling the kind and flow rate of the gas, the ratio of the lateral etching rate to the longitudinal etching rate of the photoresist layer can be controlled to be 1: Change from 0.9 to 1:1.5.
  • the flow rate of sulfur hexafluoride is in the range of 200 to 800 sccm, and the flow rate of oxygen is in the range of 8000 to 10000 sccm, thereby controlling the ratio of the ratio of the lateral etching rate to the longitudinal etching rate of the photoresist layer.
  • the range is 1:0.9 to 1:1.5.
  • the first region of the photoresist layer after the photoresist ashing step just covers the source, and the second region just covers the drain, that is, the projection and active switching of the first region of the photoresist layer on the substrate.
  • the projection of the source on the substrate is nearly coincident, and the projection of the second region of the photoresist layer on the substrate coincides with the projection of the drain of the active switch on the substrate, thereby being subsequently dry etched.
  • a portion of the semiconductor layer (including the active layer and the doped layer) that is beyond the photoresist layer is etched away, that is, a portion of the semiconductor layer (including the active layer and the doped layer) beyond the source and the drain is engraved
  • the active switching structure on the array substrate formed by etching, thereby reducing the portion of the semiconductor layer beyond the source and the drain, that is, reducing the portion of the active layer beyond the source and the drain, and reducing the doping layer beyond the source and The portion of the drain, thereby reducing the absorption light of the semiconductor layer in the active switch, generating the probability of photo-generated carriers, reducing the leakage current of the active switch, and correspondingly improving the stability of the active switch.
  • 16 is a schematic structural diagram of an array substrate according to an embodiment of the present application. Referring to FIG. 16, a plurality of active switches 20 are formed on the array substrate 30, and the active switches are formed by the manufacturing method provided by the above embodiments. 17 is a schematic structural diagram of an active switch on an array substrate according to an embodiment of the present disclosure. Referring to FIG.
  • the active switch 20 includes: a substrate 200; a gate 210, a gate insulating layer 220, and a semiconductor layer formed on the substrate 200 (including Active layer 230 and doped layer 240), source 251 and drain 252 (source drain electrode 250); wherein the projected profile of active layer 230 on substrate 200 and source 251 or drain 252 are on substrate 200
  • the pitch of the projected contour ranges from 0 to 1.5 micrometers; the distance between the projected contour of the doped layer 240 on the substrate 200 and the projected contour of the source 251 or the drain 252 on the substrate 200 ranges from 0 to 1.0 micron.
  • the probability of photogenerated carriers is to reduce the leakage current of the active switch.
  • the smaller the pitch of the projection profile of the doped layer 240 on the substrate 200 and the projection profile of the source 251 or the drain 252 on the substrate 200 the smaller the probability that the doped layer 240 absorbs light, thereby reducing the active switching.
  • the probability of generating photo-generated carriers is to reduce the leakage current of the active switch.
  • the distance between the projection profile of the active layer 230 on the substrate 200 and the projection profile of the source 251 or the drain 252 on the substrate 200 may be 0-0.8 micrometers, and the projection profile of the doped layer 240 on the substrate 200
  • the pitch of the projection profile on the substrate 200 from the source 251 or the drain 252 may be 0 to 0.5 micrometers.
  • the distance between the projection profile of the active layer 230 on the substrate 200 and the projection profile of the source 251 or the drain 252 on the substrate 200 is 0 ⁇ m, and the projection profile and source of the doped layer 240 on the substrate 200
  • the semiconductor layer including the active layer 230 and the doping layer 240
  • the semiconductor layer does not absorb light, and no photo-generated carriers are generated in the active switch, thereby actively
  • the leakage current of the switch is 0, and the stability of the corresponding active switch is high.
  • FIG. 16 the active switch of 6 rows and 6 columns is optionally shown in FIG. 16 , but it is not limited to the array substrate in the present application, and the number and arrangement of the active switches can be designed according to the actual requirements of the array substrate.
  • FIG. 17 optionally shows that the pitch of the projection profile of the active layer 230 on the substrate 200 and the projection profile of the source 251 or the drain 252 on the substrate 200 are equal to 0; the projection of the doped layer 240 on the substrate 200 The pitch of the contour and the projected contour of source 251 or drain 252 on substrate 200 is equal to zero.
  • the array substrate provided by the embodiment of the present application includes the above-mentioned active switch, which reduces the portion of the semiconductor layer beyond the source and the drain, that is, reduces the portion of the active layer beyond the source and the drain, and reduces the doping.
  • the layer exceeds the source and drain portions, thereby reducing the absorption light of the semiconductor layer in the active switch on the array substrate, generating the probability of photogenerated carriers, reducing the leakage current of the active switch, and correspondingly improving the stability of the active switch.
  • FIG. 18 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present application.
  • the display device includes a display panel 300 and a backlight module 360 , and the display panel 300 .
  • the backlight module 360 is disposed on one side of the display panel 300, and the backlight module 360 is optionally disposed under the display panel 300 in FIG.
  • the display panel 300 includes an array substrate 310, a pixel electrode 320, an encapsulation layer 330, a liquid crystal molecular layer 340, and a common electrode 350.
  • the liquid crystal in the liquid crystal molecular layer 340 is controlled by applying an electric field between the pixel electrode 320 and the common electrode 350.
  • the molecules rotate to achieve display.
  • the active switch is electrically connected to the via electrode of the pixel electrode 270 (pixel electrode 320 in FIG. 18) through the insulating layer 260, thereby transmitting the data line signal to the corresponding pixel electrode 270 when turned on. (Pixel electrode 320 in Fig. 18), other structures of the liquid crystal display device are not specifically shown here.
  • the structure of the active switch on the array substrate reduces the portion of the semiconductor layer beyond the source and the drain, that is, reduces the portion of the active layer beyond the source and the drain, and reduces the doping layer beyond the source. a portion of the pole and the drain, thereby reducing the absorption light of the semiconductor layer in the active switch on the array substrate, generating a probability of photo-generated carriers, reducing the leakage current of the active switch, and correspondingly improving the electrical performance stability of the active switch, It also reduces the power consumption of the display panel.
  • the application range of the active switch on the array substrate includes, but is not limited to, a display panel, and any electronic device that can integrate the above active switch falls within the protection scope of the present application.

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Abstract

一种阵列基板的制造方法，包括：图案化光刻胶层（24、160）形成第一区域（251、Z1）、第二区域（252、Z2）和第三区域（253、Z3）；图案化源漏电极层（23、150）和半导体层（130、140）形成与第一区域（251、Z1）、第二区域（252、Z2）和第三区域（253、Z3）覆盖部分对应的源极（15a）、漏极（15b）和沟道区。

Description

一种阵列基板的制造方法和阵列基板 技术领域
本申请实施例涉及主动开关技术，尤其涉及一种阵列基板的制造方法和阵列基板。
背景技术
主动开关是显示面板的关键器件，对显示面板的工作性能具有十分重要的作用，而随着电子设备的快速发展，人们要求电子设备的功耗越低越好，续航能力越高越好，因此也要求电子设备中的显示面板的低功耗。
显示面板中设置有主动开关阵列基板，然而目前主动开关阵列基板的主动开关的漏电流相对较大，当光线照射到主动开关上时还会产生光生载流子，进一步增大主动开关的漏电流，导致显示面板的功耗较大，还导致主动开关的稳定性能差。
发明内容
本申请实施例提供一种阵列基板的制造方法和阵列基板，以降低阵列基板上主动开关的漏电流以及提高主动开关的稳定性。
本申请实施例提供了一种阵列基板的制造方法，该阵列基板包括多个主动开关，该阵列基板的制造方法包括：
提供一基板；
在所述基板上形成栅极、栅极绝缘层、半导体层、源漏电极层和光刻胶层；
对所述光刻胶层进行图案化，以形成图案化的光刻胶层，所述图案化的光刻胶层包括第一区域和第二区域，以及位于所述第一区域和所述第二区域之间的第三区域，所述第三区域的厚度的取值范围为0.2～0.8微米；
利用所述图案化后的光刻胶层为掩膜版，对所述源漏电极层进行图形化处理，在所述第一区域覆盖的部分形成所述主动开关的源极，在所述第二区域覆盖的部分形成所述主动开关的漏极，对所述半导体层进行图形化处理，在所述第三区域覆盖的部分形成所述主动开关的沟道区。
本申请实施例还提供了一种阵列基板，该阵列基板上形成有多个主动开关，所述主动开关采用上述提供的制造方法形成，所述主动开关包括：
基板；
形成在所述基板上的半导体层、源极和漏极；
其中，所述源极和所述漏极位于所述半导体层远离所述基板的一侧；
其中，所述半导体层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距的取值范围为0～1.5微米；所述掺杂层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距的取值范围为0～1.0微米。
本申请实施例提供的阵列基板的制造方法，可减少主动开关中半导体层超出源极和漏极的部分，从而减少了主动开关中半导体层的吸收光，产生光生载流子的几率，降低了主动开关的漏电流，相应的提高主动开关的稳定性，当该主动开关应用在显示面板中时，还能够降低显示面板的功耗。
附图说明
为了更清楚地说明本申请实施例或范例技术中的技术方案，下面将对实施例或范例技术描述中所需要使用的附图做一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是范例技术提供的一种阵列基板上主动开关的结构示意图；
图2是本申请实施例提供的一种阵列基板的制造方法的流程示意图；
图3是本申请实施里提供的一种图案化光刻胶层的原理示意图；
图4是本申请实施例提供的光刻胶层曝光能量与保留厚度的关系示意图；
图5是本申请实施例提供的图案化光刻胶层后的俯视图；
图6是图5俯视图中沿剖面线B～B’的剖面结构示意图；
图7是本申请实施例提供的6个不同样品的光刻胶层第三区域保留厚度示意图；
图8是本申请实施例提供的阵列基板的制造方法中沉积光刻胶层后的膜层结构示意图；
图9是本申请实施例提供的阵列基板的制造方法中图案化光刻胶层后的膜 层结构示意图；
图10是本申请实施例提供的阵列基板的制造方法中第一次湿法刻蚀后的膜层结构示意图；
图11是本申请实施例提供的阵列基板的制造方法中第一次干法刻蚀后的膜层结构示意图；
图12是本申请实施例提供的阵列基板的制造方法中光刻胶灰化后的膜层结构示意图；
图13是本申请实施例提供的阵列基板的制造方法中第二次湿法刻蚀后的膜层结构示意图；
图14是本申请实施例提供的阵列基板的制造方法中第二次干法刻蚀后的膜层结构示意图；
图15是本申请实施例提供的阵列基板光刻胶层刻蚀方向示意图；
图16是本申请实施例提供的一种阵列基板的结构示意图；
图17是本申请实施例提供的阵列基板上主动开关的结构示意图；
图18是本申请实施例提供的一种液晶显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，以下将参照本申请实施例中的附图，通过实施方式清楚、完整地描述本申请的技术方案，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1是范例技术提供的一种阵列基板上主动开关的结构示图。参见图1，该主动开关包括：基板11、栅极12、栅极绝缘层13、有源层14(通常采用非晶硅材料形成，所以也可以称为非晶硅层14)、掺杂层15和源漏电极16，源漏电极16可选的包括源极161和漏极162，其中，主动开关的半导体层可包括有源层14和掺杂层15。主动开关的栅极12和源极161、栅极12和漏极162之间均采用栅极绝缘层13隔离，因此主动开关实际上是一种绝缘栅型场效应管，主动开关可以分为N型和P型。
在此以N型主动开关为例，对主动开关的工作原理进行说明。当给栅极12 施加大于N型主动开关的导通电压的正电压时，栅极12和有源层14之间会产生一个电场，在这个电场的作用下，有源层14中形成了导电沟道使源极161和漏极162之间形成导通状态，在栅极12上所施加的电压越大则导通沟道越大，此时，给源极161和漏极162之间加上电压就会有载流子通过导电沟道；而给栅极12施加低于N型主动开关的导通电压的负电压时，有源层14中不会形成电子沟道，则源极161和漏极162之间形成关闭状态。掺杂层15形成在有源层14和源极161、有源层14和漏极162之间，设置为减少有源层14和源漏电极16信号的电阻。本领域的技术人员可以理解，本申请实施力提供的主动开关的衬底11、栅极12、栅极绝缘层13、有源层14、掺杂层15和源漏电极16等结构的功能与范例技术类似，在此不再赘述。
主动开关的实际制造过程中，形成的非晶硅层14的边缘超出源漏电极16的边缘，即形成了非晶硅尾巴L2，形成的掺杂层15的边缘超出源漏电极16的边缘，即形成了掺杂层沟道外尾巴L1和掺杂层沟道内尾巴L3，则主动开关应用在液晶显示面板中时，上述3种类型的尾巴，尤其是非晶硅尾巴L2的存在会直接接触或吸收到液晶显示面板的背光模组发出的可见光线。而非晶硅层14会与可见光发生反应导致产生光漏电流，由此进一步增大主动开关的漏电流，导致阵列基板的功耗较大，还导致主动开关的电性能不稳定。
为了解决这一问题，本申请实施例提供了一种阵列基板的制造方法，该阵列基板包括多个主动开关，参见图2，图2是本申请实施例提供的一种阵列基板的制造方法的流程示意图。可选的包括：
S10、提供一基板。
本实施例中可选该基板为玻璃基板或聚酰亚胺(PI)等柔性基板。本领域技术人员可以理解，阵列基板上主动开关的应用产品及应用场景不同，则选用的阵列基板的基板材料不同，显然基板材料包括但不限于玻璃基板和柔性基板，任意一种可以作为阵列基板的基板的材料均落入本申请的保护范围。
S20、在基板上形成栅极、栅极绝缘层、半导体层、源漏电极层和光刻胶层。
本实施例中可选栅极的组成材料为铝(Al)或钼(Mo)，栅极绝缘层的组成材料为氮化硅(SiN)，半导体层可包括有源层和掺杂层，其中，有源层的组成材料为非晶硅(a～Si)，掺杂层的组成材料为重掺杂非晶硅，可选的可包括N型非 晶硅或P型非晶硅，源漏电极层的组成材料为依次层叠设置的氮化钼、铝和氮化钼(MoN/Al/MoN)光刻胶层的组成材料包括树脂、感光剂、溶剂和添加剂，其中，感光剂是光刻胶层内的光敏成分，对光形式的辐射能(特别是紫外区)会发生光化学反应。光刻胶从应用特性上可分为正胶和负胶，对于正胶而言，被紫外线照射的部分会因化学性质变化而被去除掉，负胶则相反，被紫外线照射的部分会因化学性质变化而保留下来，本实施例中可选的以正胶为例进行说明。本领域技术人员可以理解，阵列基板的各膜层的组成材料包括但不限于以上示例，任意一种阵列基板的膜层结构的组成材料均落入本申请的保护范围；以及本申请中也不具体各膜层结构的制造工艺，任意一种阵列基板的膜层结构的组成材料均落入本申请的保护范围。
S30、对光刻胶层进行图案化，以形成图案化的光刻胶层，图案化的光刻胶层包括第一区域和第二区域，以及位于第一区域和第二区域之间的第三区域，第三区域的厚度的取值范围为0.2～0.8微米。
本实施例中对光刻胶层进行图案化可包括利用曝光显影技术将较平整的光刻胶层表面去掉不同的厚度，从而形成图案化(凹凸不平)的光刻胶层。按照光刻胶层的厚度不同及对应主动开关的功能区不同划分，图案化的光刻胶层包括上述三个区域。
其中，第三区域的厚度的取值范围为0.2～0.8微米，可保证后续刻蚀光刻胶的过程中，第三区域的光刻胶被完全刻蚀掉，即第三区域对应的主动开关完全裸露时，第一区域和第二区域的保留厚度和横向尺寸保证其对应的主动开关结构能被有效覆盖。
S40、利用图案化后的光刻胶层为掩膜版，对源漏电极层进行图形化处理，在第一区域覆盖的部分形成主动开关的源极，在第二区域覆盖的部分形成主动开关的漏极，对半导体层进行图形化处理，在第三区域覆盖的部分形成主动开关的沟道区。
可选的，对源漏电极层进行图形化处理包括对源漏电极层进行至少一次湿法刻蚀；对半导体层进行图形化处理包括对半导体层进行至少一次干法刻蚀。
本实施例中，湿法刻蚀可包括利用磷酸(H 3PO 4)、醋酸(CH 3COOH)和硝酸(HNO 3)的混合溶液刻蚀源漏电极层，利用真空等离子体刻蚀半导体层(包 括有源层和掺杂层)，刻蚀气体可包括六氟化硫(SF 6)和氯气(Cl 2)的混合气体或者六氟化硫(SF 6)、氧气(O 2)和氦气(He)的混合气体。
可选的，对光刻胶层进行图案化采用半色调掩膜工艺，且对应曝光第三区域所需的光照能量取值范围为37～48毫焦耳。
可选的，图3是本申请实施例提供的一种图案化光刻胶层的原理示意图。参见图3，被曝光样品可选的包括光刻胶层24、源漏电极层23、其他功能层22(可包括半导体层、栅极绝缘层和栅极层，在图3中概括性的以22示出)和基板21。半色调掩膜板25可选的可包括三个区域，第一区域251对应被曝光样品的源极形成区，第二区域252对应被曝光样品的漏极形成区，第三区域253位于第一区域251和第二区域252之间，对应被曝光样品的沟道形成区。由于半色调眼膜板25第一区域251、第二区域252和第三区域253对光的透过率不同，使入射光线透过半色调掩膜板25后对光刻胶层24的曝光程度不同，从而形成图案化的光刻胶层24。图3中，X～Y坐标系下，X代表被曝光样品(主要指光刻胶层24)对应半色调掩膜板的不同位置(单位为纳米或微米，根据主动开关的实际需求设定，在此不作限定)，Y代表曝光能量(单位为毫焦耳)，折线26代表对应于不同位置曝光能量大小变化趋势。光刻胶层24对应于半色调掩膜板25的第一区域251和第二区域252的位置，由于透过半色调掩膜板25的光较少，对应曝光能量较小，光刻胶层24被除去的部分较少，对应保留的厚度较厚；光刻胶层24对应于半色调掩膜板25的第三区域253的位置，由于透过半色调掩膜板25的光较多，对应曝光能量较大，光刻胶层24被除去的部分较多，对应保留的厚度较薄(图3中以H0示出光刻胶层24的保留厚度)。光刻胶层24对应不同位置薄厚不同，形成图案化的光刻胶层24。
可选的，图4是本申请实施例提供的光刻胶层曝光能量与保留厚度的关系示意图。结合图3和图4，横轴为曝光能量Dose，单位为毫焦耳(mJ)，纵轴为光刻胶层24保留厚度Thic.，单位为埃米
Figure PCTCN2018113606-appb-000001
折线51代表光刻胶层24保留厚度Thic.与曝光能量Dose的对应关系。控制曝光能量Dose取值在37～48毫焦耳范围内，可使光刻胶层24保留厚度Thic.为2000～8000埃米，即0.2～0.8微米。
可选的，光刻胶层24的保留厚度Thic.的取值范围为0.4～0.8微米时，光刻胶层24的保留厚度Thic.每减少0.1微米，所需曝光能量Dose为1.5毫焦耳；光 刻胶层24的保留厚度Thic.的取值范围为0.2～0.4微米时，光刻胶层24的保留厚度Thic.每减少0.1微米，所需曝光能量Dose为2.5毫焦耳。从而，需要根据光刻胶层24的保留目标厚度控制合适的曝光能量的取值。
可选的，图5是本申请实施例提供的图案化光刻胶层后的俯视图。参见图5，图5中可选的以34示出光刻胶层的第一区域和第二区域，以33示出光刻胶层的第三区域；以A1、A2和B1点可选的示出了光刻胶层24的第三区域中保留厚度最小的位置。具体的，图6是图5俯视图中沿剖面线B～B’的剖面结构示意图。参见图6，在基板401上形成多层功能层403(可包括栅极、栅极绝缘层、半导体层和源漏电极层，图6中并未具体划分，均以403示出)和光刻胶层404。结合图5和图6，以光刻胶层404的第三区域中保留厚度最小的位置(即图5中A1、A2和B1标示的位置，也即图6中H2标示的位置)为中点，向光刻胶层404的第一区域和第二区域延伸，可得到一个凹坑状的截面，如图6所示。
可选的，光刻胶层404第一区域和第二区域的保留厚度H1为1.8～2.2微米。
可选的，光刻胶层404的凹坑表面与光刻胶层404与多层功能层403的界面之间的夹角α的取值范围为28～32°。
可选的，光刻胶层24的第一区域和第二区域的保留厚度H1为2.174微米，第三区域的保留厚度最小值H2为0.54微米，凹坑表面与光刻胶层404与多层功能层403的界面之间的夹角α的值为30.69°。
可选的，光刻胶层的第三区域保留厚度均一性的取值范围为25％～55％。
其中，均一性表征了第三区域保留厚度的平整度，可选的，均一性的数值计算方式可采用下式：
Figure PCTCN2018113606-appb-000002
其中，H max代表第三区域保留厚度的最大值，H min代表第三区域保留厚度的最小值。均一性U％的值越小，表明光刻胶层第三区域保留厚度的均一性越好。
可选的，图7是本申请实施例提供的6个不同样品的光刻胶层第三区域保留厚度示意图。结合图3和图7，横轴代表不同的样品编号，Sam.1～Sam.6代表6个不同尺寸的样品，两个纵轴分别代表光刻胶层24的保留厚度Thic.和保留厚度 均一性U％，光刻胶层24的保留厚度Thic.的单位为埃米
Figure PCTCN2018113606-appb-000003
直线601代表光刻胶层24的保留目标厚度平均值，可选的可以为0.5微米，直线602代表光刻胶层24的保留目标厚度最大值，可选的可以为0.65微米，直线603代表光刻胶层24的保留目标厚度最小值，可选的可以为0.35微米；折线61上的点代表光刻胶层24的实际保留厚度最小值，可选的取值范围为0.3～0.36微米，折线63上的点代表光刻胶层24的实际保留厚度最大值，可选的取值范围为0.54～0.69微米，折线62上的点代表光刻胶层24的实际保留厚度的平均值，可选的取值范围为0.4～0.47微米；折线64上的点代表光刻胶层24的实际保留厚度的均一性，可选的取值范围为25.95％～40.95％。
可选的，制造方法包括两次湿法刻蚀和两次干法刻蚀，且湿法刻蚀和干法刻蚀交替进行。具体可包括：第一次湿法刻蚀，图形化源漏电极层，形成源区、漏区和有源区的金属导线结构；第一次干法刻蚀，形成半导体层(半导体层包括有源层和掺杂层)岛状结构，也就是图形化半导体层(包括有源层和掺杂层)；第二次湿法刻蚀，图形化源漏电极层，在源区形成源极，在漏区形成漏极；第二次干法刻蚀，刻蚀半导体层(包括有源层和掺杂层)，也就是刻蚀开半导体层(包括有源层和掺杂层)，形成主动开关结构。
可选的，干法刻蚀可过刻10％，可选的，刻蚀时间为76秒，从而进一步减少半导体层超过源极和漏极的部分。
可选的，光刻胶层414每侧的特征尺寸损失为0.94微米。
可选的，制造方法还包括执行至少一次光刻胶灰化步骤，光刻胶灰化步骤设置于干法刻蚀与湿法刻蚀步骤之间。具体可包括：在第一次干法刻蚀后，在第二次湿法刻蚀前执行一次光刻胶灰化步骤，将第三区域光刻胶去除，以露出沟道区域的源漏电极层。
可选的，图8～图14是本申请实施例提供的基于两次湿法刻蚀、两次干法刻蚀和一次光刻胶灰化的阵列基板的制造方法中每个步骤之后形成的膜层结构示意图。以在阵列基板上形成底栅型主动开关为例，附图标记在图8～图14中延用。具体的，图8是本申请实施例提供的阵列基板的制造方法中沉积光刻胶层后的膜层结构示意图。参见图8，具体结构可包括：提供基板100，并在基板100上依次形成的栅极110、栅极绝缘层120、半导体层(包括有源层130和掺杂层140)、 源漏电极层150和光刻胶层160，其中，源漏电极层150可以包括依次叠层设置的氮化钼层151、铝层152和氮化钼层153；有源层130和掺杂层140共同形成半导体层(图8中未另设置标号)。图9是本申请实施例提供的阵列基板的制造方法中图案化光刻胶层后的膜层结构示意图。参见图9，对光刻胶层160进行图案化，以形成图案化的光刻胶层160，图案化的光刻胶层160包括第一区域Z1和第二区域Z2，以及位于第一区域Z1和第二区域Z2之间的第三区域Z3，第三区域Z3的厚度H3的取值范围为0.2～0.8微米。图10是本申请实施例提供的阵列基板的制造方法中第一次湿法刻蚀后的膜层结构示意图。参见图10，第一次湿法刻蚀后，图形化源漏电极层150。图11是本申请实施例提供的主动开关的制造方法中第一次干法刻蚀后的膜层结构示意图。参见图11，第一次干法刻蚀后，图形化半导体层(包括有源层130和掺杂层140)。图12是本申请实施例提供的阵列基板的制造方法中光刻胶灰化后的膜层结构示意图，参见图12，光刻胶灰化后，露出沟道区域的源漏电极层150。图13是本申请实施例提供的阵列基板的制造方法中第二次湿法刻蚀后的膜层结构示意图，参见图13，第二次湿法刻蚀后，图形化源漏电极层150，在源区(光刻胶层24的第一区域Z1对应的区域)形成源极15a，在漏区(光刻胶层24的第二区域Z2对应的区域)形成漏极15b。图14是本申请实施例提供的阵列基板的制造方法中第二次干法刻蚀后的膜层结构示意图，参见图14，第二次干法刻蚀后，刻蚀开半导体层(包括有源层130和掺杂层140)，至此形成阵列基板结构，尤其是阵列基板上主动开关结构。需要说明的是，图8～图14示出了阵列基板，尤其是阵列基板上主动开关的形成流程，其中，后一幅图相对于前一幅图减少的部分即为对应步骤中去除掉的部分。
由此形成的阵列基板上主动开关结构减少了半导体层超出源极和漏极的部分，即减少了有源层超出源极和漏极的部分，以及减少了掺杂层超出源极和漏极的部分，从而减少了阵列基板上主动开关中半导体层的吸收光，产生光生载流子的几率，降低了主动开关的漏电流，相应的提高主动开关的稳定性。
可选的，光刻胶灰化步骤中横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1:0.9～1:1.5。
可选的，图15是本申请实施例提供的阵列基板光刻胶层刻蚀方向示意图。 参见图15，在基板411上形成多层功能层413(可包括栅极、栅极绝缘层、半导体层和源漏电极层，图15中并未具体划分，均以413示出)和图形化的光刻胶层414。在光刻胶灰化过程中，横向(图15中S方向)刻蚀速率与纵向(图15中T方向)刻蚀速率的比值的取值范围为1:0.9～1:1.5。可选的，H4所在的位置为光刻胶层的第一区域或第二区域，H5所在的位置为光刻胶层的第三区域。同时，由于光刻胶层414灰化过程中存在微岛效应，即在光刻胶层414第三区域的中间位置的厚度比第三区域的边缘位置要厚，即图15中MLE所示，由此，在灰化过程中合理控制刻蚀速率，可确保光刻胶层414的第三区域完全去除干净。
可选的，光刻胶灰化步骤中，刻蚀气体包括六氟化硫和氧气。
可选的，横向刻蚀速率与纵向刻蚀速率的比值为1:0.9时，刻蚀气体为氧气；横向刻蚀速率与纵向刻蚀速率的比值为1:1.5时，刻蚀气体为六氟化硫和氧气，且六氟化硫与氧气的流量比的取值范围为0.02～0.1。
其中，光刻胶灰化步骤中，利用真空环境中，气体在射频电源的作用下产生等离子体，该等离子体高能轰击光刻胶层表面或与光刻胶层表面反应，使光刻胶层灰化，即光刻胶层变薄或被去除。通过增加六氟化硫气体，可以加快光刻胶层的纵向刻蚀速率，以及通过控制气体的种类和流量，可控制光刻胶层横向刻蚀速率与纵向刻蚀速率的比值范围在1:0.9～1:1.5范围内变化。
可选的，六氟化硫的流量取值范围为200～800sccm，氧气的流量取值范围为8000～10000sccm，从而控制光刻胶层的横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1:0.9～1:1.5。
由此使光刻胶灰化步骤后的光刻胶层的第一区域刚好覆盖源极，第二区域刚好覆盖漏极，即光刻胶层的第一区域在衬底上的投影与主动开关的源极在衬底上的投影接近重合，光刻胶层的第二区域在衬底上的投影与主动开关的漏极在衬底上的投影接近重合，从而，在后续干法刻蚀的过程中，半导体层(包括有源层和掺杂层)超出光刻胶层的部分被刻蚀掉，即半导体层(包括有源层和掺杂层)超出源极和漏极的部分被刻蚀掉，从而形成的阵列基板上主动开关结构减少了半导体层超出源极和漏极的部分，即减少了有源层超出源极和漏极的部分，以及减少了掺杂层超出源极和漏极的部分，从而减少了主动开关中半导体层的吸收光，产生光生载流子的几率，降低了主动开关的漏电流，相应的提高主动开关的稳定性。
图16是本申请实施例提供的一种阵列基板的结构示意图，参见图16，阵列基板30上形成有多个主动开关20，主动开关采用上述实施方式提供的制造方法形成。图17是本申请实施例提供的阵列基板上主动开关的结构示意图，参见图17，主动开关20包括：基板200；形成在基板200上的栅极210、栅极绝缘层220、半导体层(包括有源层230和掺杂层240)、源极251和漏极252(源漏电极250)；其中，有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距的取值范围为0～1.5微米；掺杂层240在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距的取值范围为0～1.0微米。
其中，有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距越小，有源层230吸收光的几率越小，从而可减少主动开关产生光生载流子的几率，即降低主动开关的漏电流。同理，掺杂层240在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距越小，掺杂层240吸收光的几率越小，从而可减少主动开关产生光生载流子的几率，即降低主动开关的漏电流。
可选的，有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距可为0～0.8微米，掺杂层240在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距可为0～0.5微米。可选的，有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距为0微米，且掺杂层240在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距为0微米时，半导体层(包括有源层230和掺杂层240)不吸收光，主动开关中不产生光生载流子，从而主动开关的漏电流为0，相应的主动开关的稳定性较高。
需要说明的是，图16中可选的示出了6行6列的主动开关，但并非对本申请中阵列基板的限定，可根据阵列基板的实际需求设计主动开关的数量和排列方式。图17中可选的示出了有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距等于0；掺杂层240在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距等于0。
本申请实施例提供的阵列基板包括上述主动开关，该主动开关结构减少了半 导体层超出源极和漏极的部分，即减少了有源层超出源极和漏极的部分，以及减少了掺杂层超出源极和漏极的部分，从而减少了阵列基板上主动开关中半导体层的吸收光，产生光生载流子的几率，降低了主动开关的漏电流，相应的提高主动开关的稳定性。
本申请实施例还提供一种液晶显示装置，图18是本申请实施例提供的一种液晶显示装置的结构示意图，参见图18，该显示装置包括显示面板300和背光模组360，显示面板300包括上述提供的阵列基板310，背光模组360设置在显示面板300的一侧，图18中可选的以背光模组360设置在显示面板300的下方示出。
可选的，显示面板300包括阵列基板310、像素电极320、封装层330、液晶分子层340和公共电极350，通过在像素电极320和公共电极350之间施加电场控制液晶分子层340中的液晶分子转动，从而实现显示。需要说明的是，如图17所示主动开关通过绝缘层260与像素电极270(图18中像素电极320)过孔电连接，以此在导通时将数据线信号传输至相应的像素电极270(图18中像素电极320)，在此不再具体示出液晶显示装置的其他结构。与范例技术相比，该阵列基板上主动开关的结构减少了半导体层超出源极和漏极的部分，即减少了有源层超出源极和漏极的部分，以及减少了掺杂层超出源极和漏极的部分，从而减少了阵列基板上主动开关中半导体层的吸收光，产生光生载流子的几率，降低了主动开关的漏电流，相应的提高了主动开关的电性能稳定性，同时还能够降低显示面板的功耗。
本领域技术人员可以理解，阵列基板上主动开关的应用范围包括但不限于显示面板，任意一种可以集成上述主动开关的电子设备均落入本申请的保护范围。
注意，上述仅为本申请的可选实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整、相互结合和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。

Claims (17)

  1. 一种阵列基板的制造方法，其中，所述阵列基板包括多个主动开关，所述制造方法包括：
    提供一基板；
    在所述基板上形成栅极、栅极绝缘层、半导体层和源漏电极层和光刻胶层；
    对所述光刻胶层进行图案化，以形成图案化的光刻胶层，所述图案化的光刻胶层包括第一区域和第二区域，以及位于所述第一区域和所述第二区域之间的第三区域，所述第三区域的厚度的取值范围为0.2～0.8微米；以及，
    利用所述图案化后的光刻胶层为掩膜版，对所述源漏电极层进行图形化处理，在所述第一区域覆盖的部分形成所述主动开关的源极，在所述第二区域覆盖的部分形成所述主动开关的漏极，对所述半导体层进行图形化处理，在所述第三区域覆盖的部分形成所述主动开关的沟道区。
  2. 根据权利要求1所述的制造方法，其中，所述对光刻胶层进行图案化采用半色调掩膜工艺，且对应曝光所述第三区域所需的光照能量取值范围为37～48毫焦耳。
  3. 根据权利要求2所述的制造方法，其中：对所述源漏电极层进行图形化处理包括对所述源漏电极层进行至少一次湿法刻蚀；对所述半导体层进行图形化处理包括对所述半导体层进行至少一次干法刻蚀。
  4. 根据权利要求1所述的制造方法，其中：对所述源漏电极层进行图形化处理包括对所述源漏电极层进行至少一次湿法刻蚀；对所述半导体层进行图形化处理包括对所述半导体层进行至少一次干法刻蚀。
  5. 根据权利要求4所述的制造方法，其中，所述制造方法包括两次湿法刻蚀和两次干法刻蚀，且所述湿法刻蚀和所述干法刻蚀交替进行。
  6. 根据权利要求4所述的制造方法，其中，所述制造方法还包括执行至少一次光刻胶灰化步骤，所述光刻胶灰化步骤设置于所述湿法刻蚀与所述干法刻蚀步骤之间。
  7. 根据权利要求6所述的制造方法，其中，所述光刻胶灰化步骤中横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1:0.9～1:1.5。
  8. 根据权利要求7所述的制造方法，其中，所述光刻胶灰化步骤中，刻蚀 气体包括六氟化硫和氧气。
  9. 根据权利要求8所述的制造方法，其中，六氟化硫的流量取值范围为200～800sccm；氧气的流量取值范围为8000～10000sccm。
  10. 一种阵列基板，其中，所述阵列基板上形成有多个主动开关，其中，包括：
    基板；
    形成在所述基板上的半导体层、源极和漏极；
    其中，所述源极和所述漏极位于所述半导体层远离所述基板的一侧；
    其中，所述半导体层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距的取值范围为0～1.5微米；所述掺杂层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距的取值范围为0～1.0微米。
  11. 如权利要求10所述的阵列基板，其中，所述阵列基板制造包括：
    提供一基板；
    在所述基板上形成栅极、栅极绝缘层、半导体层和源漏电极层和光刻胶层；
    对所述光刻胶层进行图案化，以形成图案化的光刻胶层，所述图案化的光刻胶层包括第一区域和第二区域，以及位于所述第一区域和所述第二区域之间的第三区域，所述第三区域的厚度的取值范围为0.2～0.8微米；以及，
    利用所述图案化后的光刻胶层为掩膜版，对所述源漏电极层进行图形化处理，在所述第一区域覆盖的部分形成所述主动开关的源极，在所述第二区域覆盖的部分形成所述主动开关的漏极，对所述半导体层进行图形化处理，在所述第三区域覆盖的部分形成所述主动开关的沟道区。
  12. 如权利要求11所述的阵列基板，其中，所述对光刻胶层进行图案化采用半色调掩膜工艺，且对应曝光所述第三区域所需的光照能量取值范围为37～48毫焦耳。
  13. 如权利要求11所述的阵列基板，其中，对所述源漏电极层进行图形化处理包括对所述源漏电极层进行至少一次湿法刻蚀；对所述半导体层进行图形化处理包括对所述半导体层进行至少一次干法刻蚀。
  14. 如权利要求13所述的阵列基板，其中，所述制造包括两次湿法刻蚀和 两次干法刻蚀，且所述湿法刻蚀和所述干法刻蚀交替进行。
  15. 如权利要求14所述的阵列基板，其中，所述制造还包括执行至少一次光刻胶灰化步骤，所述光刻胶灰化步骤设置于所述湿法刻蚀与所述干法刻蚀步骤之间。
  16. 如权利要求15所述的阵列基板，其中，所述光刻胶灰化步骤中横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1:0.9～1:1.5。
  17. 一种阵列基板的制造方法，其中，所述阵列基板包括多个主动开关，所述制造方法包括：
    提供一基板；
    在所述基板上形成栅极、栅极绝缘层、半导体层、源漏电极层和光刻胶层；
    对所述光刻胶层进行图案化，以形成图案化的光刻胶层，所述图案化的光刻胶层包括第一区域和第二区域，以及位于所述第一区域和所述第二区域之间的第三区域，所述第三区域的厚度的取值范围为0.2～0.8微米；以及，
    利用所述图案化的光刻胶层掩膜，对所述源漏电极层进行图形化处理，在所述第一区域覆盖的部分形成所述主动开关的源极，在所述第二区域覆盖的部分形成所述主动开关的漏极，对所述半导体层进行图形化处理，在所述第三区域覆盖的部分形成所述主动开关的沟道区；
    其中，还包括执行至少一次光刻胶灰化步骤；
    所述光刻胶灰化步骤中，横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1:0.9～1:1.5，刻蚀气体包括六氟化硫和氧气；
    所述横向刻蚀速率与纵向刻蚀速率的比值为1:1.5时，六氟化硫与氧气的流量比的取值范围为0.02～0.1。
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