WO2019169740A1 - 阵列基板的制造方法和阵列基板 - Google Patents

阵列基板的制造方法和阵列基板 Download PDF

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WO2019169740A1
WO2019169740A1 PCT/CN2018/087772 CN2018087772W WO2019169740A1 WO 2019169740 A1 WO2019169740 A1 WO 2019169740A1 CN 2018087772 W CN2018087772 W CN 2018087772W WO 2019169740 A1 WO2019169740 A1 WO 2019169740A1
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layer
photoresist
etching
source
ashing
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PCT/CN2018/087772
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English (en)
French (fr)
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卓恩宗
田轶群
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/331,288 priority Critical patent/US11348947B2/en
Publication of WO2019169740A1 publication Critical patent/WO2019169740A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to display technologies, and in particular, to a method of fabricating an array substrate and an array substrate.
  • the active switch is a key component of the display panel and plays an important role in the performance of the display panel.
  • people require that the power consumption of the electronic device be as low as possible, and the higher the endurance, the better. Low power consumption of display panels in electronic devices is also required.
  • An active switch array substrate is disposed in the display panel.
  • the active switch is usually a thin film transistor, and the leakage current of the thin film transistor is relatively large.
  • photo-generated carriers are generated, which further increases the leakage current of the active switch, resulting in a large power consumption of the display panel and a poor stability of the active switch.
  • Embodiments of the present disclosure provide a method of fabricating an array substrate and an array substrate to reduce leakage current of an active switch on the array substrate and improve stability of the active switch.
  • Embodiments of the present disclosure provide a method of fabricating an array substrate, the method of fabricating the array substrate comprising: providing a substrate; forming a gate, a gate insulating layer, a semiconductor layer, a source/drain electrode layer, and a photolithography on the substrate a glue layer, wherein the semiconductor layer includes an active layer and a doped layer; the photoresist layer is patterned to form a patterned photoresist layer, wherein the patterned photoresist layer The first thickness region and the second thickness region are included, and the thickness of the first thickness region is smaller than the thickness of the second thickness region; and the source/drain electrode layer is subjected to at least one wet etching using the patterned photoresist layer Forming at least one dry etch of the semiconductor layer to form a channel region of the active switch to form a source and a drain of the active switch; in the wet etching and the dry method Performing at least one photoresist ashing between the etching steps; wherein the
  • the embodiment of the present disclosure further provides an array substrate, which can be formed by the manufacturing method provided above, the array substrate comprising: a substrate and an active switch on the substrate.
  • the active switch includes: a gate on the substrate; a gate insulating layer on the gate; a semiconductor layer on the gate insulating layer, wherein the semiconductor layer includes an active layer and is located on the active layer a doped layer, the doped layer includes a first region and a second region isolated from each other; and a source on the first region of the doped layer and a second region on the doped layer The drain.
  • a pitch of the projection layer of the active layer on the substrate and a projection profile of the source or the drain on the substrate is less than 1.2 micrometers; a projection profile of the doped layer on the substrate A pitch from a projection profile of the source or the drain on the substrate is less than 0.8 microns.
  • An embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming a gate on a substrate; forming a gate insulating layer on the gate; forming a semiconductor layer on the gate insulating layer, wherein The semiconductor layer includes an active layer and a doped layer on the active layer; a source/drain electrode layer is formed on the doped layer; a photoresist layer is formed on the source/drain electrode layer; Exposing and developing the adhesive layer to obtain a first photoresist pattern, the first photoresist pattern comprising a first thickness region and a second thickness region and a hollow region, the thickness of the first thickness region being less than the thickness of the second thickness region, Exposing the source/drain electrode layer to the hollow region; performing a first wet etching on the source/drain electrode layer with the first photoresist pattern as a first mask; and performing the first photoresist pattern on the first photoresist pattern Ashing treatment to obtain a second photoresist pattern; performing
  • a third ashing process to obtain a fourth photoresist pattern; using the fourth photoresist pattern as a fourth mask, performing a second dry etching on the doped layer to form a channel region of the transistor; and removing The fourth photoresist pattern.
  • the ratio of the lateral etch rate to the longitudinal etch rate is 1:0.9 to 1:1.5.
  • a photoresist ashing step is set in the wet etching and dry etching steps, and the ratio of the ratio of the lateral etching rate to the longitudinal etching rate is controlled.
  • the ratio of the photoresist layer covering the source/drain electrode layer is reduced from 1:0.9 to 1:1.5, and the functional layer portions not blocked by the photoresist layer are removed during the dry etching process. Therefore, the length of the semiconductor layer beyond the source and the drain becomes smaller, the leakage current of the active switch on the array substrate can be reduced, and the stability of the active switch can be improved.
  • FIG. 1 is a schematic diagram of an active switch on an array substrate provided by the related art.
  • FIG. 2 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a comparison of film layers before and after ashing of a photoresist layer in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic view showing an etching direction of a photoresist layer in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a film layer after depositing a photoresist layer in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a film layer after patterning a photoresist layer in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural view of a film layer after the first wet etching in the method for fabricating the array substrate according to the embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a film layer after a first photoresist ashing in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a film layer after the first dry etching in the method for fabricating the array substrate according to the embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of a film layer after a second photoresist ashing in the method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural view of a film layer after a second wet etching in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a film layer after a third photoresist ashing in the method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural view of a film layer after a second dry etching in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of the principle of a patterned photoresist layer provided in an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram showing relationship between exposure energy and retention thickness of a photoresist layer according to an embodiment of the present disclosure.
  • 16 is a top plan view of a patterned photoresist layer provided by an embodiment of the present disclosure.
  • Figure 17 is a cross-sectional structural view taken along line B-B' in the top view of Figure 16;
  • 18 is a schematic view showing the remaining thickness of a third region of a photoresist layer of six different samples according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic structural diagram of an active switch on an array substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present disclosure.
  • FIG. 1 is a structural diagram of an active switch on an array substrate provided by the related art.
  • the active switch includes a substrate 11, a gate electrode 12, a gate insulating layer 13, an active layer 14 (usually formed of an amorphous silicon material, so may also be referred to as an amorphous silicon layer 14), and a doped layer. 15, source 161 and drain 162.
  • the gate 12 and the source 161 of the active switch, the gate 12 and the drain 162 are separated by a gate insulating layer 13, so that the active switch is actually an insulated gate field effect transistor.
  • the active switch can be divided into N type and P type.
  • the N-type active switch is taken as an example to explain the working principle of the active switch.
  • a positive voltage greater than the threshold voltage of the N-type active switch is applied to the gate electrode 12
  • an electric field is generated between the gate electrode 12 and the active layer 14.
  • a conductive trench is formed in the active layer 14.
  • the channel forms an on state between the source 161 and the drain 162, and the larger the voltage applied to the gate 12, the larger the conduction channel.
  • the edge of the amorphous silicon layer 14 formed exceeds the edge of the source/drain electrode 16, that is, the amorphous silicon tail L2 is formed, and the edge of the doped layer 15 formed exceeds the edge of the source/drain electrode 16. That is, a doped layer channel outer tail L1 and a doped layer channel inner end tail L3 are formed.
  • the above three types of tails, especially the amorphous silicon tail L2 are illuminated by the visible light emitted by the backlight module of the liquid crystal display panel, resulting in a light leakage current, thereby further increasing the leakage current of the active switch, resulting in the work of the display panel.
  • the consumption is large, and the electrical performance of the active switch is also unstable.
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure. Exemplary includes the following steps.
  • step S10 a substrate is provided.
  • the substrate is selected to be a flexible substrate such as a glass substrate or polyimide (PI).
  • PI polyimide
  • the substrate material includes but is not limited to a glass substrate and a flexible substrate, and any one of them. Materials that can serve as substrates for the array substrate fall within the scope of the present disclosure.
  • step S20 a gate electrode, a gate insulating layer, a semiconductor layer, a source/drain electrode layer, and a photoresist layer are formed on the substrate.
  • the constituent material of the optional gate is aluminum (Al) or molybdenum (Mo)
  • the constituent material of the gate insulating layer is silicon nitride (SiN)
  • the semiconductor layer may include an active layer and a doped layer, wherein
  • the constituent material of the active layer is amorphous silicon (a-Si)
  • the constituent material of the doped layer is heavily doped amorphous silicon
  • exemplary may include N-type doped amorphous silicon or P-type doped
  • the constituent material of the amorphous silicon and the source/drain electrode layer is molybdenum nitride, aluminum, and molybdenum nitride (MoN/Al/MoN) which are laminated in this order.
  • the constituent materials of the photoresist layer include a resin, a sensitizer, a solvent, and an additive, wherein the sensitizer is a photosensitive component in the photoresist layer, and a photochemical reaction occurs when irradiated with radiant energy (for example, ultraviolet ray) in the form of light.
  • radiant energy for example, ultraviolet ray
  • Photoresists can be classified into positive and negative adhesives in terms of application characteristics. In the case of a positive gel, the portion irradiated with ultraviolet rays changes in chemical properties and can be dissolved in the developer. Negative glue, on the other hand, is exposed to ultraviolet light and will not be dissolved by the developer due to chemical changes.
  • an exemplary rubber is taken as an example for description.
  • constituent materials of the film layers of the array substrate include, but are not limited to, the above examples, and the constituent materials of the film layer structure of any one of the array substrates fall within the protection scope of the present disclosure;
  • the constituent materials of the film layer structure of any one of the array substrates fall within the protection scope of the present disclosure.
  • step S30 the photoresist layer is patterned to form a patterned photoresist layer.
  • the photoresist layer is patterned to form a patterned photoresist layer.
  • the source/drain electrode layer and the semiconductor layer covered by the photoresist layer are not etched away; the source/drain electrode layer not covered by the photoresist layer And the semiconductor layer, that is, the exposed source/drain electrode layer and the semiconductor layer are etched away.
  • step S40 using the patterned photoresist layer, the source/drain electrode layer is subjected to at least one wet etching to form a source and a drain of the active switch; and the semiconductor layer is subjected to at least one dry etching to form a channel region of the active switch; and a photoresist ashing step, the photoresist ashing step being disposed between the steps of wet etching and dry etching.
  • the ratio of the lateral etch rate to the longitudinal etch rate in the photoresist ashing step ranges from 1:0.9 to 1:1.5.
  • the wet etching may include etching the source/drain electrode layer with a mixed solution of phosphoric acid (H 3 PO 4 ), acetic acid (CH 3 COOH), and nitric acid (HNO 3 ), and etching the semiconductor layer by vacuum plasma (including The active layer and the doped layer), the etching gas may include a mixed gas of sulfur hexafluoride (SF 6 ) and chlorine (Cl 2 ), or the etching gas may include sulfur hexafluoride (SF 6 ), oxygen (O 2 ) A mixture of helium (He).
  • H 3 PO 4 mixed solution of phosphoric acid
  • CH 3 COOH acetic acid
  • HNO 3 nitric acid
  • the etching gas may include a mixed gas of sulfur hexafluoride (SF 6 ) and chlorine (Cl 2 ), or the etching gas may include sulfur hexafluoride (SF 6 ), oxygen (O 2 )
  • He A mixture of helium
  • the wet etching is isotropic, that is, the lateral etching rate is equivalent to the longitudinal etching rate, that is, the width of the lateral etching of the source and drain electrode layers is close to the depth of the longitudinal etching, so that the light
  • the pattern of the engraved layer and the pattern of the source and drain electrode layers may be deviated, that is, the metal material of the source and drain electrode layers is indented a distance compared to the photoresist layer, exemplarily 1.5 to 3 microns, and dried.
  • the etched semiconductor layer (including the active layer and the doped layer) tends to be etched in the vertical direction, so that the portion covered by the photoresist layer is hardly etched away, that is, compared to the source to be formed For the drain and drain, as well as the overlying photoresist, the semiconductor layer (including the active layer and the doped layer) hardly shrinks.
  • the photoresist layer ashing step is performed at least once, and the ratio of the ratio of the lateral etch rate to the longitudinal etch rate in the photoresist ashing step is controlled.
  • the range is from 1:0.9 to 1:1.5, which can reduce the portion of the photoresist layer beyond the source/drain electrode layer, so that the deviation of the pattern of the photoresist layer from the pattern of the source/drain electrode layer is reduced or even eliminated, thus, subsequent etching
  • the pattern of the semiconductor layer including the active layer and the doped layer
  • the portion of the semiconductor layer exceeding the source and the drain is reduced.
  • the amorphous silicon tail, the outer tail of the doped layer channel, and the tail in the doped layer channel become smaller, thereby reducing the probability that the semiconductor layer (including the active layer and the doped layer) reacts with visible light to generate a leakage current, that is, the probability is reduced.
  • the leakage current of the active switch on the array substrate stabilizes the electrical performance of the active switch.
  • FIG. 3 is a schematic diagram of a comparison of film layers before and after ashing of a photoresist layer in a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • a bottom gate type active switch is formed on the array substrate, and a gate electrode 110, a gate insulating layer 120, a semiconductor layer (including the active layer 130 and the doping layer 140), and a source are sequentially deposited on the substrate 100.
  • the drain electrode layer 150 and the photoresist layer 160 are sequentially deposited on the substrate 100.
  • the original photoresist layer 1601 represents the photoresist layer before the photoresist layer ashing step is not performed
  • W1 represents the width of the photoresist layer 160 before the photoresist ashing step is not performed
  • the A point represents no execution.
  • W2 represents the width of the photoresist layer 160 after performing the photoresist layer ashing step
  • point B represents the doping after performing the photoresist ashing step
  • W0 represents the width of source-drain electrode layer 150
  • point O represents a boundary point of source-drain electrode layer 150.
  • a photoresist ashing step is performed to reduce the original photoresist layer 1601 to the photoresist layer 160.
  • the width of the photoresist layer 160 is reduced from W1 to W2, that is, the source is leaked close to the source.
  • the trend of the width W0 of the pole layer 150 changes, and the boundary of the corresponding doping layer 140 changes from point A to point B, that is, the trend toward the point O of the boundary point close to the source/drain electrode layer 150, due to the increase in active switching leakage current.
  • the reason for the large one is that the absorption of the visible light is caused.
  • the manufacturing method of the array substrate provided by the embodiment of the present disclosure reduces the portion of the semiconductor layer (including the active layer 130 and the doping layer 140) beyond the source/drain electrode layer 150, thereby It can reduce the leakage current of the active switch on the array substrate.
  • FIG. 4 is a schematic diagram of a photoresist layer etching direction in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • a functional layer 413 which may include a gate, a gate insulating layer, a semiconductor layer, and a source/drain electrode layer, not specifically divided in FIG. 4, both shown at 413) and patterned light is formed on the substrate 411.
  • the glue layer 414 In the photoresist ashing step, the ratio of the etch rate in the lateral direction (S direction in FIG. 4) to the etch rate in the longitudinal direction (T direction in FIG. 4) ranges from 1:0.9 to 1:1.5.
  • the location where H4 is located corresponds to the source or drain region of the active switch
  • the location where H5 is located corresponds to the channel region of the active switch. Due to the micro island effect in the ashing process of the photoresist layer 414, the thickness of the photoresist layer 414 is thinner as shown by MLE in the figure, that is, in the vicinity of the position corresponding to H5 of the photoresist layer 414. Reasonable control of the etching rate during the ashing process ensures that the pattern of the photoresist layer 414 is similar to that of the source/drain electrode layer (see the source/drain electrode layer 150 in FIG. 3), and corresponds to the active switching channel region. The photoresist layer 414 is completely removed.
  • the manufacturing method includes two wet etchings and two dry etchings, and the wet etching and the dry etching are alternately performed.
  • the method may include: first wet etching, patterning the source/drain electrode layer, forming a metal wire structure of a source region, a drain region, and an active region; and performing a first dry etching to form a semiconductor layer (including an active layer) And doped layer) island structure, that is, patterned semiconductor layer (including active layer and doped layer); second wet etching, patterning source and drain electrode layer, forming source in source region, leaking The region forms a drain; the second dry etching etches the semiconductor layer (including the active layer and the doped layer), that is, etches the semiconductor layer (including the active layer and the doped layer) to form an array substrate Active switch structure.
  • the manufacturing method includes performing three photoresist ashing steps, and each photoresist ashing step is disposed between adjacent wet etching and dry etching steps.
  • the method may include performing a photoresist ashing step between each wet etching and each dry etching, that is, including a patterned photoresist layer, two wet etching, and two dry etching.
  • the overall process of performing three photoresist ashing steps is: patterned photoresist layer, first wet etching, first photoresist layer ashing, first dry etching, second time Photoresist layer ashing, second wet etch, third photoresist ashing, and second dry etch. Referring to FIG.
  • the width of the photoresist layer 160 can be reduced on the basis of the etching step adjacent thereto, and the pattern of the photoresist layer 160 and the source/drain electrode layer can be made.
  • the patterns of 150 have a small difference or the same pattern, so that the length of the semiconductor layer beyond the source/drain electrode layer 150 (the source and drain electrode layers 150 form the source and the drain after forming the active switch) can be reduced during the subsequent etching process, thereby Reduce the leakage current of the active switch on the array substrate.
  • FIGS. 5-13 illustrate each step in a method of fabricating an array substrate based on two wet etching, two dry etching, and three photoresist ashing steps provided by an embodiment of the present disclosure.
  • a bottom gate type active switch is formed on an array substrate, and reference numerals are used in FIGS. 5 to 13.
  • FIG. 5 is a schematic structural diagram of a film layer after depositing a photoresist layer in a method for fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG.
  • the specific structure may include: providing a substrate 100, and sequentially forming a gate electrode 110, a gate insulating layer 120, a semiconductor layer (including the active layer 130 and the doping layer 140), and a source/drain electrode layer on the substrate 100. 150 and a photoresist layer 160, wherein the source/drain electrode layer 150 may include a molybdenum nitride layer, an aluminum layer, and a molybdenum nitride layer which are sequentially stacked.
  • FIG. 6 is a schematic structural diagram of a film layer after patterning a photoresist layer in a method of fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG.
  • the patterned photoresist layer 160 can be divided into the exposed regions Z11, Z12, Z13, and Z14.
  • the insulating layer 120 is removed, and the other layers are completely removed.
  • the first thickness region Z21 corresponds to the channel region of the active switch;
  • the second thickness regions Z31 and Z32 correspond to the source and drain regions of the active switch;
  • the third thickness regions Z41 and Z51 correspond to the metal wire structure.
  • the patterned photoresist layer is divided into different functional regions for subsequent formation of active switches on the array substrate.
  • FIG. 7 is a schematic structural view of a film layer after the first wet etching in the method for fabricating the array substrate according to the embodiment of the present disclosure. Referring to FIG. 6 and FIG.
  • FIG. 8 is a schematic structural diagram of a film layer after a first photoresist ashing in a method of fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG. 8, the width of the photoresist layer 160 after the first photoresist ashing is narrowed relative to the width of the photoresist layer before the first photoresist ashing (see the dotted line and the contour in FIG. 8).
  • FIG. 9 is a schematic structural diagram of a film layer after the first dry etching in the method for fabricating the array substrate according to the embodiment of the present disclosure. Referring to FIG.
  • the first dry etching removes the semiconductor layer (including the active layer 130 and the doping layer 140) not covered by the photoresist layer 160 to form a semiconductor layer (including the active layer 130 and the doped layer).
  • the impurity layer 140) is an island-like structure, that is, a patterned semiconductor layer (including the active layer 130 and the doped layer 140).
  • FIG. 10 is a schematic structural view of a film layer after a second photoresist ashing in the method for fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG. 6 and FIG.
  • the photoresist corresponding to the first thickness region Z21 of the photoresist layer 160 is completely removed to expose the source/drain electrode layer 150 of the channel region, and simultaneously The other portions of the photoresist are narrowed relative to the width before the second photoresist ashing step, such that in the subsequent second wet etching step, the source/drain electrode layer 150 is opposite to the photoresist layer.
  • the amount of indentation of 160 is reduced relative to the example technique, and further, in the subsequent step of etching the semiconductor layer (including the active layer 130 and the doped layer 140), the semiconductor layer not covered by the photoresist layer 160 (including The source layer 130 and the doped layer 140) are partially etched away, that is, the portion of the semiconductor layer (including the active layer 130 and the doped layer 140) that extends beyond the source/drain electrode layer 150 is further reduced, thereby further reducing leakage current.
  • 11 is a schematic structural view of a film layer after a second wet etching in a method of fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG. 6 and FIG.
  • FIG. 12 is a schematic structural diagram of a film layer after a third photoresist ashing in the method for fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG.
  • the width of the photoresist layer 160 after the third photoresist ashing step is narrowed relative to the width of the photoresist before the third photoresist ashing step (see the dotted line and the implementation profile in FIG. 12).
  • the dashed line represents the photoresist layer 160 before the third photoresist ashing
  • the solid line represents the photoresist layer 160 after the third photoresist ashing, so that the second subsequent dry etching is performed.
  • the semiconductor layer (including the active layer 130 and the doping layer 140) not covered by the photoresist layer 160 may be etched correspondingly, so that the semiconductor layer (including the active layer 130 and the doping layer 140) is exceeded.
  • FIG. 13 is a schematic structural view of a film layer after a second dry etching in a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • the semiconductor layer including the active layer 130 and the doped layer 140
  • FIG. 5 to FIG. 13 show a process of forming an array substrate, in particular, a process of forming an active switch on the array substrate, wherein a portion of the latter image that is reduced relative to the previous image is a corresponding step. The removed part.
  • the covering of the semiconductor layer (including the active layer 130 and the doping layer 140) by the photoresist layer 160 is reduced, so that the semiconductor which can be etched away in the dry etching step
  • the layers (including the active layer 130 and the doped layer 140) are increased, that is, in the active switch on the finally formed array substrate, the portion of the semiconductor layer (including the active layer 130 and the doping layer 140) exceeding the source/drain electrode layer 150 is reduced. (The portion including the active layer 130 exceeding the source 15a and the drain 15b is reduced, and the portion of the doped layer 140 beyond the source 15a and the drain 15b is reduced), the absorption light of the semiconductor layer in the active switch is reduced and the photo-generated load is generated. The probability of the flow reduces the leakage current of the active switch and correspondingly improves the stability of the active switch.
  • the etching gas includes sulfur hexafluoride and oxygen.
  • the gas in the photoresist ashing step, in the vacuum environment, the gas generates a plasma under the action of the radio frequency power source, and the plasma high-energy bombards the surface of the photoresist layer or reacts with the surface of the photoresist layer to make the photoresist layer Ashing, that is, the photoresist layer is thinned or removed.
  • the etching gas when the ratio of the lateral etching rate to the longitudinal etching rate is 1:0.9, the etching gas is oxygen; when the ratio of the lateral etching rate to the longitudinal etching rate is 1:1.5, the etching gas is hexafluoride. Sulfur and oxygen, and the flow ratio of sulfur hexafluoride to oxygen ranges from 0.02 to 0.1.
  • the lateral etching rate is faster, and by increasing the sulfur hexafluoride gas, the longitudinal etching rate of the photoresist layer can be accelerated, thereby controlling the light by controlling the type and flow rate of the gas.
  • the ratio of the lateral etch rate to the longitudinal etch rate of the dicing layer varies from 1:0.9 to 1:1.5.
  • the flow rate of the sulfur hexafluoride is in the range of 200-800 sccm, and the flow rate of the oxygen is in the range of 8000-10000 sccm, thereby controlling the ratio of the lateral etching rate to the longitudinal etching rate of the photoresist layer 160. Values range from 1:0.9 to 1:1.5.
  • the patterned photoresist layer 160 includes a first region Z31, a second region Z32, and a third region Z21 between the first region Z31 and the second region Z32, the third region.
  • the thickness of Z21 ranges from 0.2 to 0.8 microns.
  • the portion covered by the first region Z31 may also be referred to as a source forming region of the active switch for forming a source of the active switch after the subsequent etching step; the portion covered by the second region Z32 may also be referred to as an active switch.
  • a drain formation region for forming a drain of the active switch after the subsequent etching step a portion covered by the third region Z21 may also be referred to as a channel formation region of the active switch for forming an active switch after a subsequent etching step Channel area.
  • the photoresist layer 160 is patterned by using a halftone mask process, and the illumination energy required to expose the third region Z21 ranges from 37 to 48 millijoules.
  • FIG. 14 is a schematic diagram of the principle of a patterned photoresist layer provided in the implementation of the present disclosure.
  • the exposed sample illustratively includes a photoresist layer 24, a source/drain electrode layer 23, and other functional layers 22 (which may include a semiconductor layer, a gate insulating layer, and a gate layer, as summarized in FIG. 22 shows) and the substrate 21.
  • the halftone mask 25 may illustratively include three regions, a first region 251 corresponding to a source formation region of the exposed sample, a second region 252 corresponding to a drain formation region of the exposed sample, and a third region 253 at the first Between the region 251 and the second region 252, a channel formation region of the sample to be exposed is corresponding. Since the transmittances of the first region 251, the second region 252, and the third region 253 of the halftone mask 25 are different, the exposure of the incident light to the photoresist layer 24 is different after passing through the halftone mask 25. Thereby forming a patterned photoresist layer 24.
  • X represents the different positions of the exposed sample (mainly referred to as the photoresist layer 24) corresponding to the halftone mask (in nanometers or micrometers, according to the actual needs of the active switch, here) Not limited, Y represents the exposure energy (in millijoules), and the broken line 26 represents the trend of the exposure energy corresponding to different positions.
  • the photoresist layer 24 corresponds to the positions of the first region 251 and the second region 252 of the halftone mask 25, and since the light transmitted through the halftone mask 25 is small, the corresponding exposure energy is small, and the photoresist layer 24 is The portion to be removed is less, and the corresponding thickness is thicker; the photoresist layer 24 corresponds to the position of the third region 253 of the halftone mask 25, since the light transmitted through the halftone mask 25 is more, the corresponding exposure When the energy is large, the portion where the photoresist layer 24 is removed is large, and the thickness corresponding to the retention is thin (the remaining thickness of the photoresist layer 24 is shown by H0 in FIG. 14).
  • the photoresist layer 24 is formed to have a patterned photoresist layer 24 corresponding to different thicknesses at different locations.
  • FIG. 15 is a schematic diagram of relationship between exposure energy and retention thickness of a photoresist layer provided by an embodiment of the present disclosure.
  • the horizontal axis is the exposure energy Dose
  • the unit is millijoules (mJ)
  • the vertical axis is the photoresist layer 24 retention thickness Thic.
  • the unit is Amy.
  • the broken line 31 represents the correspondence relationship between the resist thickness of the photoresist layer 24 and the exposure energy Dose.
  • the exposure energy Dose is controlled to be in the range of 37-48 mJ, so that the photoresist layer 24 can have a thickness of Thic. 2000-8000 ⁇ , that is, 0.2-0.8 ⁇ m, which ensures the subsequent etching of the photoresist.
  • the photoresist of the third region is completely etched away, that is, when the active switch corresponding to the third region is completely exposed, the remaining thickness and the lateral dimension of the first region and the second region ensure the corresponding active switch structure. Is effectively covered.
  • the required exposure energy is 1.5 millijoules for each 0.1 micron reduction in the remaining thickness of the photoresist layer.
  • the photoresist layer has a remaining thickness of less than 0.4 micrometers and greater than or equal to 0.2 micrometers, and the remaining thickness of the photoresist layer, Thic., is reduced by 0.1 micrometers, and the required exposure energy is 2.5 millijoules.
  • the dry etch is over 10%.
  • the overetch time is 76 seconds.
  • the feature size loss per side of the photoresist layer is 0.94 microns.
  • FIG. 16 is a top view of a patterned photoresist layer provided by an embodiment of the present disclosure.
  • an exemplary first and second regions of the photoresist layer are shown at 34 in FIG. 16
  • a third region of the photoresist layer is shown at 33; and the points A1, A2, and B1 are exemplified.
  • the location in which the thickness of the third region of the photoresist layer 24 is minimized is shown.
  • Fig. 17 is a schematic cross-sectional view along the line B-B' in the top view of Fig. 16. Referring to FIG.
  • a plurality of functional layers 403 (which may include a gate, a gate insulating layer, a semiconductor layer, and a source/drain electrode layer, which are not specifically divided in FIG. 17 and are shown by 403) and a photolithography are formed on the substrate 401.
  • the first thickness of the photoresist layer has a thickness of 1.8-2.2 microns and the second region of the photoresist layer has a thickness of 1.8-2.2 microns.
  • the surface of the third region of the photoresist layer forms pits, and the slope angle ⁇ of the pit surface ranges from 28 to 32°.
  • the first and second regions of the photoresist layer 24 have a remaining thickness H1 of 2.174 microns, and the third region has a remaining thickness minimum H2 of 0.54 microns.
  • the pit surface and the photoresist layer 404 are The value of the angle ⁇ between the interfaces of the multilayer functional layer 403 is 30.69°.
  • the third region of the photoresist layer retains a thickness uniformity ranging from 25% to 55%.
  • the uniformity characterizes the flatness of the thickness retained by the third region.
  • the following formula can be used:
  • Hmax represents the maximum value of the retained thickness of the third region
  • Hmin represents the minimum value of the retained thickness of the third region
  • Average represents the average value of the retained thickness of the third region. The smaller the value of the uniformity U%, the better the uniformity of the thickness retained in the third region of the photoresist layer.
  • FIG. 18 is a schematic diagram of a third region retention thickness of a photoresist layer of six different samples provided by an embodiment of the present disclosure.
  • the horizontal axis represents different sample numbers
  • Sam.1-Sam.6 represents six different sized samples
  • the two longitudinal axes represent the remaining thickness of the photoresist layer 24, Thic.
  • the remaining thickness of the photoresist layer 24 is in the unit of Amy Line 501 represents the average retention target thickness of photoresist layer 24, which may be 0.5 microns, and line 502 represents the maximum retention target thickness of photoresist layer 24, exemplarily 0.65 microns, line 503 represents light
  • the minimum retention target thickness of the engraved layer 24 may be, for example, 0.35 microns;
  • the dots on the fold line 51 represent the actual remaining thickness of the photoresist layer 24, an exemplary range of 0.3-0.36 microns, a broken line
  • the dots on 53 represent the actual maximum thickness of the photoresist layer 24, an exemplary range of 0.54-0.69 microns, and the dots on the fold line 52 represent the average of the actual thickness of the photoresist layer 24, exemplary.
  • the value ranges from 0.4 to 0.47 microns;
  • the dots on the fold line 54 represent the uniformity of the actual remaining thickness of the photoresist layer 24, with exemplary values ranging from 25.95% to 40.95%.
  • the method for fabricating the array substrate reduces the masking of the semiconductor layer (including the active layer 130 and the doped layer 140) by the photoresist layer 160 by adding a step of photoresist ashing, so that the dry method In the etching step, the semiconductor layer (including the active layer 130 and the doping layer 140) that can be etched away is increased, that is, in the finally formed active switch, the semiconductor layer (including the active layer 130 and the doping layer 140) exceeds Partial reduction of the source-drain electrode layer 150 (including a reduction in the portion of the active layer 130 beyond the source 15a and the drain 15b, and a decrease in the portion of the doped layer 140 beyond the source 15a and the drain 15b) reduces the semiconductor in the active switch
  • the probability of the layer absorbing light and generating photo-generated carriers reduces the leakage current of the active switch on the array substrate and correspondingly improves the stability of the active switch.
  • FIG. 19 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • a plurality of active switches 20 are formed on the array substrate 30, and the active switches are formed by the manufacturing method provided by the above embodiments.
  • 20 is a schematic structural diagram of an active switch on an array substrate according to an embodiment of the present disclosure. Referring to FIG.
  • the active switch 20 includes: a substrate 200; a gate 210, a gate insulating layer 220, and a semiconductor layer formed on the substrate 200 (including Active layer 230 and doped layer 240), source 251 and drain 252 (source drain electrode 250); wherein the projected profile of active layer 230 on substrate 200 and source 251 or drain 252 are on substrate 200
  • the pitch of the projected contours is less than 1.2 microns; the pitch of the projected profile of doped layer 240 on substrate 200 and the projected profile of source 251 or drain 252 on substrate 200 is less than 0.8 microns.
  • FIG. 19 exemplarily shows that the pitch of the projection profile of the active layer 230 on the substrate 200 and the projection profile of the source 251 or the drain 252 on the substrate 200 is equal to 0; the projection of the doped layer 240 on the substrate 200 The pitch of the contour and the projected contour of source 251 or drain 252 on substrate 200 is equal to zero.
  • the array substrate provided by the embodiment of the present disclosure is fabricated by the above method.
  • the photoresist layer 160 is added to the semiconductor layer (including the active layer 130 and the doping) by increasing the photoresist ashing step.
  • the covering of the layer 140 increases the number of semiconductor layers (including the active layer 130 and the doping layer 140) that can be etched away in the dry etching step, that is, the final formed active switch, the semiconductor layer (including the active layer)
  • the portion of the layer 130 and the doped layer 140) that is beyond the source/drain electrode layer 150 is reduced (including the portion of the active layer 130 that is beyond the source 15a and the drain 15b is reduced, and the portion of the doped layer 140 that extends beyond the source 15a and the drain 15b)
  • the reduction reduces the probability of absorbing light of the semiconductor layer in the active switch and generating photo-generated carriers, reduces the leakage current of the active switch on the array substrate, and correspondingly improves the stability of the active switch.
  • FIG. 21 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present disclosure.
  • the display device includes a display panel 300 and a backlight module 360.
  • the display panel 300 includes the array substrate 310 provided above.
  • the backlight module 360 is disposed on one side of the display panel 300, and is only exemplarily shown in FIG.
  • the backlight module 360 is disposed below the display panel 300.
  • the display panel 300 includes an array substrate 310, a pixel electrode 320, an encapsulation layer 330, a liquid crystal molecular layer 340, and a common electrode 350.
  • the liquid crystal in the liquid crystal molecular layer 340 is controlled by applying an electric field between the pixel electrode 320 and the common electrode 350. The molecules rotate to achieve display.
  • the active switch is electrically connected to the via electrode of the pixel electrode 270 (pixel electrode 320 in FIG. 21) through the insulating layer 260, thereby transmitting the data line signal to the corresponding pixel electrode 270 when turned on.
  • Pixel electrode 320 in Fig. 21 other structures of the liquid crystal display device are not specifically shown here.
  • the step of increasing the photoresist ashing reduces the coverage of the semiconductor layer (including the active layer 130 and the doping layer 140) by the photoresist layer 160, so that the dry In the etching step, the semiconductor layer (including the active layer 130 and the doping layer 140) that can be etched away is increased, that is, in the finally formed active switch, the semiconductor layer (including the active layer 130 and the doped layer 140)
  • the portion exceeding the source-drain electrode layer 150 is reduced (including the portion of the active layer 130 beyond the source 15a and the drain 15b is reduced, and the portion of the doped layer 140 beyond the source 15a and the drain 15b is reduced), which is reduced in the active switch
  • the probability of the semiconductor layer absorbing light and generating photo-generated carriers reduces the leakage current of the active switch and correspondingly improves the stability of the active switch.

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Abstract

一种阵列基板的制造方法和阵列基板。该方法包括：在基板（100）上形成栅极（110）、栅极绝缘层（120）、半导体层、源漏电极层（150）和光刻胶层（160）；对光刻胶层进行图案化，以形成图案化的光刻胶层；利用图案化的光刻胶层对源漏电极层进行至少一次湿法刻蚀，对半导体层进行至少一次干法刻蚀，在湿法刻蚀和干法刻蚀之间对光刻胶层进行灰化处理。灰化处理的横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5。

Description

阵列基板的制造方法和阵列基板 技术领域
本公开涉及显示技术，尤其涉及一种阵列基板的制造方法和阵列基板。
背景技术
主动开关是显示面板的关键器件，对显示面板的工作性能具有十分重要的作用，而随着电子设备的快速发展，人们要求电子设备的功耗越低越好，续航能力越高越好，因此也要求电子设备中的显示面板的低功耗。
显示面板中设置有主动开关阵列基板。目前，主动开关通常为薄膜晶体管，薄膜晶体管的漏电流相对较大。并且，当光线照射到主动开关上时还会产生光生载流子，进一步增大主动开关的漏电流，导致显示面板的功耗较大，还导致主动开关的稳定性能差。
发明内容
本公开实施例提供一种阵列基板的制造方法和阵列基板，以降低阵列基板上主动开关的漏电流以及提高主动开关的稳定性。
本公开实施例提供了一种阵列基板的制造方法，该阵列基板的制造方法包括：提供一基板；在所述基板上形成栅极、栅极绝缘层、半导体层、源漏电极层和光刻胶层，其中，所述半导体层包括有源层和掺杂层；对所述光刻胶层进行图案化，以形成图案化的光刻胶层，其中，所述图案化的光刻胶层包括第一厚度区和第二厚度区，第一厚度区的厚度小于第二厚度区的厚度；利用所述图案化的光刻胶层，对所述源漏电极层进行至少一次湿法刻蚀，以形成所述主动 开关的源极和漏极，对所述半导体层进行至少一次干法刻蚀，以形成所述主动开关的沟道区；在所述湿法刻蚀和所述干法刻蚀的步骤之间执行至少一次光刻胶灰化；其中，所述至少一次光刻胶灰化的横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5。
本公开实施例还提供了一种阵列基板，该阵列基板可以用上述提供的制造方法形成，该阵列基板包括：基板和位于基板上的主动开关。
所述主动开关包括：位于所述基板上的栅极；位于栅极上的栅极绝缘层；位于栅极绝缘层上的半导体层，其中，所述半导体层包括有源层和位于有源层上的掺杂层，所述掺杂层包括彼此隔离的第一区域和第二区域；以及位于所述掺杂层的第一区域上的源极和位于所述掺杂层的第二区域上的漏极。
所述有源层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距小于1.2微米；所述掺杂层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距小于0.8微米。
本公开实施例还提供了一种阵列基板的制造方法，其中包括：在基板上形成栅极；在所述栅极上形成栅极绝缘层；在所述栅极绝缘层上形成半导体层，其中，所述半导体层包括有源层和位于有源层上的掺杂层；在所述掺杂层上形成源漏电极层；在源漏电极层上形成光刻胶层；对所述光刻胶层进行曝光和显影得到第一光刻胶图案，所述第一光刻胶图案包括第一厚度区和第二厚度区和镂空区，第一厚度区的厚度小于第二厚度区的厚度，所述镂空区暴露所述源漏电极层；以第一光刻胶图案为第一掩模，对源漏电极层进行第一湿法刻蚀；对所述第一光刻胶图案进行第一灰化处理，得到第二光刻胶图案；以第二光刻胶图案为第二掩模，对半导体层进行第一干法刻蚀；对所述第二光刻胶图案进行第二灰化处理，得到第三光刻胶图案，其中，第一厚度区在第二灰化处理中被 去除；以第三光刻胶图案为第三掩模，对源漏电极层进行第二湿法刻蚀以形成晶体管的源极和漏极；对所述第三光刻胶图案进行第三灰化处理，得到第四光刻胶图案；以所述第四光刻胶图案为第四掩模，对掺杂层进行第二干法刻蚀以形成晶体管的沟道区；以及去除所述第四光刻胶图案。
在第一灰化处理，第二灰化处理和第三灰化处理中，横向刻蚀速率与纵向刻蚀速率的比值为1∶0.9～1∶1.5。
根据本公开实施例提供的阵列基板的制造方法，在湿法刻蚀和干法刻蚀步骤中设置光刻胶灰化步骤，并控制横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5，使得光刻胶层覆超出源漏电极层的长度变小，同时，未被光刻胶层遮挡的各功能层部分在干法刻蚀的过程中被去除掉，从而使得半导体层超出源极和漏极的长度变小，可以降低阵列基板上主动开关的漏电流以及提高主动开关的稳定性。
附图说明
为了更清楚地说明本公开实施例或范例技术中的技术方案，下面将对实施例或范例技术描述中所需要使用的附图做一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术提供的一种阵列基板上主动开关的示意图。
图2是本公开实施例提供的一种阵列基板的制造方法的流程示意图。
图3是本公开实施例提供的阵列基板的制造方法中光刻胶层灰化前后的膜层结构对比示意图。
图4是本公开实施例提供的阵列基板的制造方法中光刻胶层刻蚀方向示意 图。
图5是本公开实施例提供的阵列基板的制造方法中沉积光刻胶层后的膜层结构示意图。
图6是本公开实施例提供的阵列基板的制造方法中图案化光刻胶层后的膜层结构示意图。
图7是本公开实施例提供的阵列基板的制造方法中第一次湿法刻蚀后的膜层结构示意图。
图8是本公开实施例提供的阵列基板的制造方法中第一次光刻胶灰化后的膜层结构示意图。
图9是本公开实施例提供的阵列基板的制造方法中第一次干法刻蚀后的膜层结构示意图。
图10是本公开实施例提供的阵列基板的制造方法中第二次光刻胶灰化后的膜层结构示意图。
图11是本公开实施例提供的阵列基板的制造方法中第二次湿法刻蚀后的膜层结构示意图。
图12是本公开实施例提供的阵列基板的制造方法中第三次光刻胶灰化后的膜层结构示意图。
图13是本公开实施例提供的阵列基板的制造方法中第二次干法刻蚀后的膜层结构示意图。
图14是本公开实施里提供的一种图案化光刻胶层的原理示意图。
图15是本公开实施例提供的光刻胶层曝光能量与保留厚度的关系示意图。
图16是本公开实施例提供的图案化光刻胶层后的俯视图。
图17是图16俯视图中沿剖面线B-B’的剖面结构示意图。
图18是本公开实施例提供的6个不同样品的光刻胶层第三区域保留厚度示意图。
图19是本公开实施例提供的一种阵列基板的结构示意图。
图20是本公开实施例提供的阵列基板上主动开关的结构示意图。
图21是本公开实施例提供的一种液晶显示装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，以下将参照本公开实施例中的附图，通过实施方式清楚、完整地描述本公开的技术方案，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1是相关技术提供的一种阵列基板上主动开关的结构示图。参见图1，该主动开关包括：基板11、栅极12、栅极绝缘层13、有源层14(通常采用非晶硅材料形成，所以也可以称为非晶硅层14)、掺杂层15，源极161和漏极162。主动开关的栅极12和源极161、栅极12和漏极162之间均采用栅极绝缘层13隔离，因此主动开关实际上是一种绝缘栅型场效应管。主动开关可以分为N型和P型。
在此以N型主动开关为例，对主动开关的工作原理进行说明。当给栅极12施加大于N型主动开关的阈值电压的正电压时，栅极12和有源层14之间会产生一个电场，在这个电场的作用下，有源层14中形成了导电沟道使源极161和漏极162之间形成导通状态，在栅极12上所施加的电压越大则导通沟道越大。此时，给源极161和漏极162之间加上电压就会有载流子通过导电沟道；而给 栅极12施加低于N型主动开关的导通电压的电压时，有源层14中不会形成导电沟道，则源极161和漏极162之间形成不导通状态。掺杂层15形成在有源层14和源极161、有源层14和漏极162之间，用于减少有源层14和源极161，有源层14和漏极162之间的电阻。主动开关的实际制造过程中，形成的非晶硅层14的边缘超出源漏电极16的边缘，即形成了非晶硅尾巴L2，形成的掺杂层15的边缘超出源漏电极16的边缘，即形成了掺杂层沟道外尾巴L1和掺杂层沟道内尾巴L3。上述3种类型的尾巴，尤其是非晶硅尾巴L2会被液晶显示面板的背光模组发出的可见光线照射，导致产生光漏电流，由此进一步增大主动开关的漏电流，导致显示面板的功耗较大，还导致主动开关的电性能不稳定。
为了解决这一问题，本公开实施例提供了一种阵列基板的制造方法，该阵列基板包括多个主动开关。参见图2，图2是本公开实施例提供的一种阵列基板的制造方法的流程示意图。示例性的包括如下步骤。
在步骤S10、提供一基板。
本实施例中可选该基板为玻璃衬底或聚酰亚胺(PI)等柔性衬底。本领域技术人员可以理解，阵列基板上主动开关的应用产品及应用场景不同，则选用的阵列基板的衬底材料不同，显然衬底材料包括但不限于玻璃衬底和柔性衬底，任意一种可以作为阵列基板的衬底的材料均落入本公开的保护范围。
在步骤S20、在基板上形成栅极、栅极绝缘层、半导体层、源漏电极层和光刻胶层。
本实施例中可选栅极的组成材料为铝(A1)或钼(Mo)，栅极绝缘层的组成材料为氮化硅(SiN)，半导体层可包括有源层和掺杂层，其中，有源层的组成材料为非晶硅(a-Si)，掺杂层的组成材料为重掺杂非晶硅，示例性的可包括N型掺杂的非晶硅或P型掺杂的非晶硅，源漏电极层的组成材料为依次层叠设置 的氮化钼、铝和氮化钼(MoN/Al/MoN)。光刻胶层的组成材料包括树脂、感光剂、溶剂和添加剂，其中，感光剂是光刻胶层内的光敏成分，在受到光形式的辐射能(例如紫外线)照射时，发生光化学反应。光刻胶从应用特性上可分为正胶和负胶。对于正胶而言，被紫外线照射的部分会因化学性质发生了变化，可以溶解于显影液。负胶则相反，被紫外线照射的部分会因化学性质的变化不会被显影液溶解。本实施例中示例性的以正胶为例进行说明。本领域技术人员可以理解，阵列基板的各膜层的组成材料包括但不限于以上示例，任意一种阵列基板的膜层结构的组成材料均落入本公开的保护范围；以及本公开中也不具体各膜层结构的制造工艺，任意一种阵列基板的膜层结构的组成材料均落入本公开的保护范围。
在步骤S30、对光刻胶层进行图案化，以形成图案化的光刻胶层。
本实施例中对光刻胶层进行图案化形成图案化的光刻胶层。在后续湿法刻蚀和/或干法刻蚀的步骤中，被光刻胶层覆盖的源漏电极层和半导体层不会被刻蚀掉；未被光刻胶层覆盖的源漏电极层和半导体层，即裸露的源漏电极层和半导体层会被刻蚀掉。
在步骤S40、利用图案化的光刻胶层，对源漏电极层进行至少一次湿法刻蚀，以形成主动开关的源极和漏极；对半导体层进行至少一次干法刻蚀，以形成主动开关的沟道区；以及一次光刻胶灰化步骤，光刻胶灰化步骤设置在湿法刻蚀和干法刻蚀的步骤之间。光刻胶灰化步骤中横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5。
本实施例中，湿法刻蚀可包括利用磷酸(H 3PO 4)、醋酸(CH3COOH)和硝酸(HNO 3)的混合溶液刻蚀源漏电极层，利用真空等离子体刻蚀半导体层(包括有源层和掺杂层)，刻蚀气体可包括六氟化硫(SF 6)和氯气(Cl 2)的混合气 体，或者刻蚀气体可包括六氟化硫(SF 6)、氧气(O 2)和氦气(He)的混合气体。
因为湿法刻蚀具有各向同性的特点，即横向刻蚀速率与纵向刻蚀速率相当，也就是，源漏电极层横向刻蚀的宽度接近于其纵向刻蚀的深度，这样一来，光刻胶层图案与源漏电极层的图案就会有一定的偏差，即源漏电极层的金属材料相比于光刻胶层会缩进一段距离，示例性的为1.5～3微米，而干法刻蚀半导体层(包括有源层和掺杂层)趋向于垂直方向刻蚀，这样，被光刻胶层遮盖的部分几乎不会被刻蚀掉，亦即，相比于待形成的源极和漏极，以及覆盖的光刻胶来说，半导体层(包括有源层和掺杂层)几乎不会缩进。
本公开实施例提供的阵列基板的制造方法中，通过设置再执行至少一次光刻胶层灰化步骤，并控制光刻胶灰化步骤中横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5，可以减少光刻胶层超出源漏电极层的部分，使光刻胶层的图案与源漏电极层的图案的偏差减小甚至消除，这样，后续刻蚀过程中，由于半导体层(包括有源层和掺杂层)的图案与光刻胶层的图案相当，这样，半导体层(包括有源层和掺杂层)超出源极和漏极的部分减少，即非晶硅尾巴、掺杂层沟道外尾巴和掺杂层沟道内尾巴均变小，从而减少半导体层(包括有源层和掺杂层)与可见光反应产生漏电流的几率，即降低了阵列基板上主动开关的漏电流，使主动开关的电性能稳定。
示例性的，图3是本公开实施例提供的阵列基板的制造方法中光刻胶层灰化前后的膜层结构对比示意图。参见图3，以在阵列基板上形成底栅型主动开关为例，在基板100上依次沉积栅极110、栅极绝缘层120、半导体层(包括有源层130和掺杂层140)、源漏电极层150和光刻胶层160。其中，原光刻胶层1601代表未执行光刻胶层灰化步骤之前的光刻胶层，W1代表未执行光刻胶灰化步骤 之前的光刻胶层160的宽度，A点代表未执行光刻胶灰化步骤时对应的掺杂层140的一边界点；W2代表执行光刻胶层灰化步骤后光刻胶层160的宽度，B点代表执行光刻胶灰化步骤后掺杂层140对应的一边界点；W0代表源漏电极层150的宽度，O点代表源漏电极层150的一边界点。如图3所示，执行光刻胶灰化步骤，使原光刻胶层1601变小为光刻胶层160，光刻胶层160的宽度由W1变小为W2，即向接近于源漏电极层150的宽度W0的趋势变化，对应的掺杂层140的边界由A点变为B点，即向接近于源漏电极层150的边界点O点的趋势变化，由于主动开关漏电流增大的一方面原因是吸收可见光造成的，因此本公开实施例提供的阵列基板的制造方法减少了半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分，从而，可减少阵列基板上主动开关的漏电流。
示例性的，图4是本公开实施例提供的阵列基板的制造方法中光刻胶层刻蚀方向示意图。参见图4，在基板411上形成功能层413(可包括栅极、栅极绝缘层、半导体层和源漏电极层，图4中并未具体划分，均以413示出)和图案化的光刻胶层414。在光刻胶灰化步骤中，横向(图4中S方向)刻蚀速率与纵向(图4中T方向)刻蚀速率的比值的取值范围为1∶0.9～1∶1.5。示例性的，H4所在的位置对应主动开关的源区或漏区，H5所在的位置对应主动开关的沟道区。由于光刻胶层414灰化过程中存在微岛效应，图中MLE所示，即在光刻胶层414的H5对应的位置的邻近位置，光刻胶层414的厚度较薄，由此，在灰化过程中合理控制刻蚀速率，可确保光刻胶层414的图案与源漏电极层(参见图3中源漏电极层150)图案相近的前提下，将对应主动开关沟道区的光刻胶层414完全去除干净。
可选的，制造方法包括两次湿法刻蚀和两次干法刻蚀，且湿法刻蚀和干法 刻蚀交替进行。具体可包括：第一次湿法刻蚀，图形化源漏电极层，形成源区、漏区和有源区的金属导线结构；第一次干法刻蚀，形成半导体层(包括有源层和掺杂层)岛状结构，也就是图形化半导体层(包括有源层和掺杂层)；第二次湿法刻蚀，图形化源漏电极层，在源区形成源极，在漏区形成漏极；第二次干法刻蚀，刻蚀半导体层(包括有源层和掺杂层)，也就是刻蚀开半导体层(包括有源层和掺杂层)，形成阵列基板上主动开关结构。
可选的，制造方法包括执行三次光刻胶灰化步骤，且每次光刻胶灰化步骤设置于相邻湿法刻蚀与干法刻蚀步骤之间。具体可包括在每次湿法刻蚀和每次干法刻蚀之间执行一次光刻胶灰化步骤，即包括图案化光刻胶层、两次湿法刻蚀、两次干法刻蚀和执行三次光刻胶灰化步骤的整体流程为：图案化光刻胶层、第一次湿法刻蚀、第一次光刻胶层灰化、第一次干法刻蚀、第二次光刻胶层灰化、第二次湿法刻蚀、第三次光刻胶灰化和第二次干法刻蚀。结合图3，每次执行光刻胶灰化步骤，都可以在与之相邻的刻蚀步骤的基础上减少光刻胶层160的宽度，使光刻胶层160的图案与源漏电极层150的图案相差较小或二者图案相同，从而后续刻蚀过程中可减少半导体层超出源漏电极层150(形成主动开关后，源漏电极层150形成源极和漏极)的长度，从而降低阵列基板上主动开关的漏电流。
示例性的，图5-图13示出了本公开实施例提供的基于两次湿法刻蚀、两次干法刻蚀和三次光刻胶灰化步骤的阵列基板的制造方法中每个步骤之后形成的膜层结构示意图。以在阵列基板上形成底栅型主动开关为例，附图标记在图5-图13中延用。具体的，图5是本公开实施例提供的阵列基板的制造方法中沉积光刻胶层后的膜层结构示意图。参见图5，具体结构可包括：提供基板100，并在基板100上依次形成的栅极110、栅极绝缘层120、半导体层(包括有源层130 和掺杂层140)、源漏电极层150和光刻胶层160，其中，源漏电极层150可以包括依次叠层设置的氮化钼层、铝层和氮化钼层。图6是本公开实施例提供的阵列基板的制造方法中图案化光刻胶层后的膜层结构示意图。参见图6，图案化的光刻胶层160对应可分为裸露区Z11、Z12、Z13和Z14，对应形成的阵列基板上的主动开关中，出绝缘层120外，其它层完全被去除掉的区域；第一厚度区Z21，对应主动开关的沟道区；第二厚度区Z31和Z32，对应主动开关的源区和漏区；第三厚度区Z41和Z51，对应金属导线结构。图案化光刻胶层是为了后续形成阵列基板上的主动开关划分不同的功能区域。图7是本公开实施例提供的阵列基板的制造方法中第一次湿法刻蚀后的膜层结构示意图。结合图6和图7，光刻胶层160裸露区Z11、Z12、Z13和Z14对应的源漏电极层150被去除掉，形成源区、漏区和有源区域的金属导线结构。图8是本公开实施例提供的阵列基板的制造方法中第一次光刻胶灰化后的膜层结构示意图。参见图8，第一次光刻胶灰化后光刻胶层160的宽度相对于第一次光刻胶灰化前光刻胶层的宽度变窄(可参见图8中虚线与实现轮廓的对比，虚线代表第一次光刻胶灰化前的光刻胶层160，实线代表第一次光刻胶灰化后的光刻胶层160)，这样，后续第一次干法刻蚀步骤中，可以相应的刻蚀掉没有被光刻胶层160遮盖的半导体层(包括有源层130和掺杂层140)，使半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分变少，减少漏电流。图9是本公开实施例提供的阵列基板的制造方法中第一次干法刻蚀后的膜层结构示意图。参见图9，第一次干法刻蚀，将未被光刻胶层160遮盖的半导体层(包括有源层130和掺杂层140)去除掉，形成半导体层(包括有源层130和掺杂层140)岛状结构，即图形化半导体层(包括有源层130和掺杂层140)。图10是本公开实施例提供的阵列基板的制造方法中第二次光刻胶灰化后的膜层结构示意图。结合图6和图10， 第二次光刻胶灰化步骤中，光刻胶层160第一厚度区Z21对应的光刻胶被完全去除掉以露出沟道区域的源漏电极层150，同时，其他部分的光刻胶均相对于第二次光刻胶灰化步骤之前的宽度变窄，这样，后续第二次湿法刻蚀的步骤中，源漏电极层150相对于光刻胶层160的缩进量相对于范例技术变少，进而，在后续刻蚀半导体层(包括有源层130和掺杂层140)的步骤中，未被光刻胶层160遮盖的半导体层(包括有源层130和掺杂层140)部分被刻蚀掉，也就是，半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分进一步减少，从而进一步减少了漏电流。图11是本公开实施例提供的阵列基板的制造方法中第二次湿法刻蚀后的膜层结构示意图。结合图6和图11，第二次湿法刻蚀图形化源漏电极层150，在源区(光刻胶层160的第二厚度区Z31对应的区域)形成主动开关的源极15a，在漏区(光刻胶层第二厚度区Z32对应的区域)形成主动开关的漏极15b。图12是本公开实施例提供的阵列基板的制造方法中第三次光刻胶灰化后的膜层结构示意图。参见图12，第三次光刻胶灰化步骤之后光刻胶层160的宽度相对于第三次光刻胶灰化步骤之前光刻胶的宽度变窄(可参见图12中虚线与实现轮廓的对比，虚线代表第三次光刻胶灰化前的光刻胶层160，实线代表第三次光刻胶灰化后的光刻胶层160)，这样，后续第二次干法刻蚀步骤中，可以相应的刻蚀掉没有被光刻胶层160遮盖的半导体层(包括有源层130和掺杂层140)，使半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分进一步变少，进一步减少漏电流。图13是本公开实施例提供的阵列基板的制造方法中第二次干法刻蚀后的膜层结构示意图。参见图13，第二次干法刻蚀后，刻蚀开半导体层(包括有源层130和掺杂层140)，至此形成主动开关结构。需要说明的是，图5-图13示出了阵列基板的形成流程，尤其是阵列基板上主动开关的形成流程，其中，后一幅图相对于前一幅图减少的部分即为对 应步骤中去除掉的部分。
通过增加光刻胶灰化的步骤，减少了光刻胶层160对半导体层(包括有源层130和掺杂层140)的遮盖，使得干法刻蚀步骤中，能被刻蚀掉的半导体层(包括有源层130和掺杂层140)增多，即最终形成的阵列基板上的主动开关中，半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分减少(包括有源层130超出源极15a和漏极15b的部分减少，以及掺杂层140超出源极15a和漏极15b的部分减少)，减少了主动开关中半导体层的吸收光并产生光生载流子的几率，降低了主动开关的漏电流，相应的提高主动开关的稳定性。
可选的，光刻胶灰化步骤中，刻蚀气体包括六氟化硫和氧气。
其中，光刻胶灰化步骤中，利用真空环境中，气体在射频电源的作用下产生等离子体，该等离子体高能轰击光刻胶层表面或与光刻胶层表面反应，使光刻胶层灰化，即光刻胶层变薄或被去除。
可选的，横向刻蚀速率与纵向刻蚀速率的比值为1∶0.9时，刻蚀气体为氧气；横向刻蚀速率与纵向刻蚀速率的比值为1∶1.5时，刻蚀气体为六氟化硫和氧气，且六氟化硫与氧气的流量比的取值范围为0.02-0.1。
其中，刻蚀气体为氧气时，横向刻蚀速率较快，通过增加六氟化硫气体，可以加快光刻胶层的纵向刻蚀速率，由此，通过控制气体的种类和流量，可控制光刻胶层横向刻蚀速率与纵向刻蚀速率的比值范围在1∶0.9～1∶1.5范围内变化。
可选的，六氟化硫的流量取值范围为200-800sccm，氧气的流量取值范围为8000-10000sccm，从而控制光刻胶层160的横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5。
可选的，继续参见图6，图案化的光刻胶层160包括第一区域Z31，第二区域Z32，以及位于第一区域Z31和第二区域Z32之间的第三区域Z21，第三区 域Z21的厚度的取值范围为0.2-0.8微米。其中，第一区域Z31覆盖的部分也可称为主动开关的源极形成区，用于在后续刻蚀步骤之后形成主动开关的源极；第二区域Z32覆盖的部分也可称为主动开关的漏极形成区，用于在后续刻蚀步骤之后形成主动开关的漏极；第三区域Z21覆盖的部分也可称为主动开关的沟道形成区，用于在后续刻蚀步骤之后形成主动开关的沟道区。
可选的，对光刻胶层160进行图案化采用半色调掩膜工艺，且对应曝光第三区域Z21所需的光照能量取值范围为37-48毫焦耳。
示例性的，图14是本公开实施里提供的一种图案化光刻胶层的原理示意图。参见图14，被曝光样品示例性的包括光刻胶层24、源漏电极层23、其他功能层22(可包括半导体层、栅极绝缘层和栅极层，在图14中概括性的以22示出)和基板21。半色调掩膜板25示例性的可包括三个区域，第一区域251对应被曝光样品的源极形成区，第二区域252对应被曝光样品的漏极形成区，第三区域253位于第一区域251和第二区域252之间，对应被曝光样品的沟道形成区。由于半色调眼膜板25第一区域251、第二区域252和第三区域253对光的透过率不同，使入射光线透过半色调掩膜板25后对光刻胶层24的曝光程度不同，从而形成图案化的光刻胶层24。图14中，X-Y坐标系下，X代表被曝光样品(主要指光刻胶层24)对应半色调掩膜板的不同位置(单位为纳米或微米，根据主动开关的实际需求设定，在此不作限定)，Y代表曝光能量(单位为毫焦耳)，折线26代表对应于不同位置曝光能量大小变化趋势。光刻胶层24对应于半色调掩膜板25的第一区域251和第二区域252的位置，由于透过半色调掩膜板25的光较少，对应曝光能量较小，光刻胶层24被除去的部分较少，对应保留的厚度较厚；光刻胶层24对应于半色调掩膜板25的第三区域253的位置，由于透过半色调掩膜板25的光较多，对应曝光能量较大，光刻胶层24被除去的部分 较多，对应保留的厚度较薄(图14中以H0示出光刻胶层24的保留厚度)。光刻胶层24对应不同位置薄厚不同，形成图案化的光刻胶层24。
示例性的，图15是本公开实施例提供的光刻胶层曝光能量与保留厚度的关系示意图。结合图14和图15，横轴为曝光能量Dose，单位为毫焦耳(mJ)，纵轴为光刻胶层24保留厚度Thic.，单位为埃米
Figure PCTCN2018087772-appb-000001
折线31代表光刻胶层24保留厚度Thic.与曝光能量Dose的对应关系。控制曝光能量Dose取值在37-48毫焦耳范围内，可使光刻胶层24保留厚度Thic.为2000-8000埃米，即0.2-0.8微米，此厚度范围可保证后续刻蚀光刻胶的过程中，第三区域的光刻胶被完全刻蚀掉，即第三区域对应的主动开关完全裸露时，第一区域和第二区域的保留厚度和横向尺寸保证其对应的主动开关结构能被有效覆盖。
在一个实施例中，光刻胶层的保留厚度大于或等于0.4微米时，光刻胶层的保留厚度每减少0.1微米，所需曝光能量为1.5毫焦耳。
在一个实施例中，光刻胶层的保留厚度小于0.4微米，且大于或等于0.2微米时，光刻胶层的保留厚度Thic.每减少0.1微米，所需曝光能量为2.5毫焦耳。
在一个实施例中，干法刻蚀过刻10％。
在一个实施例中，过刻时间为76秒。
在一个实施例中，光刻胶层每侧的特征尺寸损失为0.94微米。
示例性的，图16是本公开实施例提供的图案化光刻胶层后的俯视图。参见图16，图16中示例性的以34示出光刻胶层的第一区域和第二区域，以33示出光刻胶层的第三区域；以A1、A2和B1点示例性的示出了光刻胶层24的第三区域中保留厚度最小的位置。具体的，图17是图16俯视图中沿剖面线B-B’的剖面结构示意图。参见图17，在基板401上形成多层功能层403(可包括栅极、栅极绝缘层、半导体层和源漏电极层，图17中并未具体划分，均以403示出) 和光刻胶层404。结合图16和图17，以光刻胶层404的第三区域中保留厚度最小的位置(即图16中A1、A2和B1标示的位置，也即图17中H2标示的位置)为中点，向光刻胶层404的第一区域和第二区域延伸，可得到一个凹坑状的截面，如图17所示。
在一个实施例中，光刻胶层第一区域的保留厚度为1.8-2.2微米，以及光刻胶层第二区域的保留厚度为1.8-2.2微米。
在一个实施例中，光刻胶层的第三区域表面形成凹坑，凹坑表面的倾斜角度α的取值范围为28-32°。
在一个实施例中，光刻胶层24的第一区域和第二区域的保留厚度H1为2.174微米，第三区域的保留厚度最小值H2为0.54微米，凹坑表面与光刻胶层404与多层功能层403的界面之间的夹角α的值为30.69°。
在一个实施例中，光刻胶层的第三区域保留厚度均一性的取值范围为25％-55％。
其中，均一性表征了第三区域保留厚度的平整度，示例性的，均一性的数值计算方式可采用下式：
Figure PCTCN2018087772-appb-000002
其中，Hmax代表第三区域保留厚度的最大值，Hmin代表第三区域保留厚度的最小值，Average代表第三区域保留厚度的平均值。均一性U％的值越小，表明光刻胶层第三区域保留厚度的均一性越好。
示例性的，图18是本公开实施例提供的6个不同样品的光刻胶层第三区域保留厚度示意图。结合图14和图18，横轴代表不同的样品编号，Sam.1-Sam.6代表6个不同尺寸的样品，两个纵轴分别代表光刻胶层24的保留厚度Thic.和保留厚度均一性U％，光刻胶层24的保留厚度Thic.的单位为埃米
Figure PCTCN2018087772-appb-000003
直线501 代表光刻胶层24的保留目标厚度平均值，示例性的可以为0.5微米，直线502代表光刻胶层24的保留目标厚度最大值，示例性的可以为0.65微米，直线503代表光刻胶层24的保留目标厚度最小值，示例性的可以为0.35微米；折线51上的点代表光刻胶层24的实际保留厚度最小值，示例性的取值范围为0.3-0.36微米，折线53上的点代表光刻胶层24的实际保留厚度最大值，示例性的取值范围为0.54-0.69微米，折线52上的点代表光刻胶层24的实际保留厚度的平均值，示例性的取值范围为0.4-0.47微米；折线54上的点代表光刻胶层24的实际保留厚度的均一性，示例性的取值范围为25.95％-40.95％。
本公开实施例提供的阵列基板的制造方法，通过增加光刻胶灰化的步骤，减少了光刻胶层160对半导体层(包括有源层130和掺杂层140)的遮盖，使得干法刻蚀步骤中，能被刻蚀掉的半导体层(包括有源层130和掺杂层140)增多，即最终形成的主动开关中，半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分减少(包括有源层130超出源极15a和漏极15b的部分减少，以及掺杂层140超出源极15a和漏极15b的部分减少)，减少了主动开关中半导体层的吸收光并产生光生载流子的几率，降低了阵列基板上主动开关的漏电流，相应的提高主动开关的稳定性。
图19是本公开实施例提供的一种阵列基板的结构示意图。参见图19，阵列基板30上形成有多个主动开关20，主动开关采用上述实施方式提供的制造方法形成。图20是本公开实施例提供的阵列基板上主动开关的结构示意图，参见图20，主动开关20包括：基板200；形成在基板200上的栅极210、栅极绝缘层220、半导体层(包括有源层230和掺杂层240)、源极251和漏极252(源漏电极250)；其中，有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距小于1.2微米；掺杂层240在基板200上的投影轮 廓与源极251或漏极252在基板200上的投影轮廓的间距小于0.8微米。
需要说明的是，图19中示例性的示出了6行6列的主动开关，但并非对本公开中阵列基板的限定，可根据阵列基板的实际需求设计主动开关的数量和排列方式。图20中示例性的示出了有源层230在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距等于0；掺杂层240在基板200上的投影轮廓与源极251或漏极252在基板200上的投影轮廓的间距等于0。
本公开实施例提供的阵列基板采用上述方法制成，该阵列基板的制造方法中通过增加光刻胶灰化的步骤，减少了光刻胶层160对半导体层(包括有源层130和掺杂层140)的遮盖，使得干法刻蚀步骤中，能被刻蚀掉的半导体层(包括有源层130和掺杂层140)增多，即最终形成的主动开关中，半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分减少(包括有源层130超出源极15a和漏极15b的部分减少，以及掺杂层140超出源极15a和漏极15b的部分减少)，减少了主动开关中半导体层的吸收光并产生光生载流子的几率，降低了阵列基板上主动开关的漏电流，相应的提高主动开关的稳定性。
本公开实施例还提供一种液晶显示装置，图21是本公开实施例提供的一种液晶显示装置的结构示意图。参见图21，该显示装置包括显示面板300和背光模组360，显示面板300包括上述提供的阵列基板310，背光模组360设置在显示面板300的一侧，图21中仅示例性的示出了背光模组360设置在显示面板300的下方。
示例性的，显示面板300包括阵列基板310、像素电极320、封装层330、液晶分子层340和公共电极350，通过在像素电极320和公共电极350之间施加电场控制液晶分子层340中的液晶分子转动，从而实现显示。
需要说明的是，如图20所示主动开关通过绝缘层260与像素电极270(图 21中像素电极320)过孔电连接，以此在导通时将数据线信号传输至相应的像素电极270(图21中像素电极320)，在此不再具体示出液晶显示装置的其他结构。与范例技术相比，该主动开关的制造方法中通过增加光刻胶灰化的步骤，减少了光刻胶层160对半导体层(包括有源层130和掺杂层140)的遮盖，使得干法刻蚀步骤中，能被刻蚀掉的半导体层(包括有源层130和掺杂层140)增多，即最终形成的主动开关中，半导体层(包括有源层130和掺杂层140)超出源漏电极层150的部分减少(包括有源层130超出源极15a和漏极15b的部分减少，以及掺杂层140超出源极15a和漏极15b的部分减少)，减少了主动开关中半导体层的吸收光并产生光生载流子的几率，降低了主动开关的漏电流，相应的提高主动开关的稳定性。
注意，上述仅为本公开的实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整、相互结合和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。

Claims (20)

  1. 一种阵列基板的制造方法，所述阵列基板包括主动开关，所述阵列基板的制造方法包括：
    提供一基板；
    在所述基板上形成栅极、栅极绝缘层、半导体层、源漏电极层和光刻胶层，其中，所述半导体层包括有源层和掺杂层；
    对所述光刻胶层进行图案化，以形成图案化的光刻胶层，其中，所述图案化的光刻胶层包括第一厚度区和第二厚度区，第一厚度区的厚度小于第二厚度区的厚度；
    利用所述图案化的光刻胶层，对所述源漏电极层进行至少一次湿法刻蚀，以形成所述主动开关的源极和漏极，对所述半导体层进行至少一次干法刻蚀，以形成所述主动开关的沟道区；在所述湿法刻蚀和所述干法刻蚀的步骤之间执行至少一次光刻胶灰化；
    其中，所述至少一次光刻胶灰化的横向刻蚀速率与纵向刻蚀速率的比值的取值范围为1∶0.9～1∶1.5。
  2. 根据权利要求1所述的制造方法，其中，所述至少一次湿法刻蚀包括第一次湿法刻蚀和第二次湿法刻蚀，所述至少一次干法刻蚀包括第一次干法刻蚀和第二次干法刻蚀，且第一次湿法刻蚀，第一次干法刻蚀，第二次湿法刻蚀和第二次干法刻蚀依次进行。
  3. 根据权利要求2所述的制造方法，其中，所述至少一次光刻胶灰化包括第一次光刻胶灰化，第二次光刻胶灰化和第三次光刻胶灰化，且第一次光刻胶灰化在第一次湿法刻蚀和第一次干法刻蚀之间进行，第二次光刻胶灰化在第一次干法刻蚀和第二次湿法刻蚀之间进行，第三次光刻胶灰化在第二次湿法刻蚀和第二次干法刻蚀之间进行。
  4. 根据权利要求1所述的制造方法，其中，在所述至少一次光刻胶灰化中，刻蚀气体包括六氟化硫和氧气中的至少之一。
  5. 根据权利要求4所述的制造方法，其中，所述刻蚀气体为氧气，所述横向刻蚀速率与纵向刻蚀速率的比值为1∶0.9。
  6. 根据权利要求4所述的制造方法，其中，所述刻蚀气体包括六氟化硫和氧气，且六氟化硫与氧气的流量比的取值范围为0.02-0.1，所述横向刻蚀速率与纵向刻蚀速率的比值为1∶1.5。
  7. 根据权利要求6所述的制造方法，其中，六氟化硫的流量为200-800sccm。
  8. 根据权利要求6所述的制造方法，其中，氧气的流量为8000-10000sccm。
  9. 根据权利要求1所述的制造方法，其中，所述栅极绝缘层为氮化硅层。
  10. 根据权利要求1所述的制造方法，其中，所述有源层为多晶硅层或者非晶硅层。
  11. 根据权利要求1所述的制造方法，其中，所述掺杂层为重掺杂的多晶硅层或者重掺杂的非晶硅层。
  12. 根据权利要求1所述的制造方法，其中，所述源漏电极层包括层叠的氮化钼层、铝层和氮化钼层。
  13. 根据权利要求1所述的制造方法，其中，通过所述至少一次光刻胶灰化，使得所述半导体层上的光刻胶层被部分去除，被光刻胶层覆盖更少的半导体层。
  14. 一种通过权利要求1所述的方法制造的阵列基板，包括：基板和位于基板上的主动开关，
    其中，所述主动开关包括：
    位于所述基板上的栅极；
    位于栅极上的栅极绝缘层；
    位于栅极绝缘层上的半导体层，其中，所述半导体层包括有源层和位于有源层上的掺杂层，所述掺杂层包括彼此隔离的第一区域和第二区域；以及
    位于所述掺杂层的第一区域上的源极和位于所述掺杂层的第二区域上的漏极，
    其中，所述有源层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距小于1.2微米；所述掺杂层在所述基板上的投影轮廓与所述源极或所述漏极在所述基板上的投影轮廓的间距小于0.8微米。
  15. 一种阵列基板的晶体管的制造方法，包括：
    在基板上形成栅极；
    在所述栅极上形成栅极绝缘层；
    在所述栅极绝缘层上形成半导体层，其中，所述半导体层包括有源层和位于有源层上的掺杂层；
    在所述掺杂层上形成源漏电极层；
    在源漏电极层上形成光刻胶层；
    对所述光刻胶层进行曝光和显影得到第一光刻胶图案，所述第一光刻胶图案包括第一厚度区和第二厚度区和镂空区，第一厚度区的厚度小于第二厚度区的厚度，所述镂空区暴露所述源漏电极层；
    以第一光刻胶图案为第一掩模，对源漏电极层进行第一湿法刻蚀；
    对所述第一光刻胶图案进行第一灰化处理，得到第二光刻胶图案；
    以第二光刻胶图案为第二掩模，对半导体层进行第一干法刻蚀；
    对所述第二光刻胶图案进行第二灰化处理，得到第三光刻胶图案，其中，第一厚度区在第二灰化处理中被去除；
    以第三光刻胶图案为第三掩模，对源漏电极层进行第二湿法刻蚀以形成晶体管的源极和漏极；
    对所述第三光刻胶图案进行第三灰化处理，得到第四光刻胶图案；
    以所述第四光刻胶图案为第四掩模，对掺杂层进行第二干法刻蚀以形成晶体管的沟道区；以及
    去除所述第四光刻胶图案，
    其中，在第一灰化处理，第二灰化处理和第三灰化处理中，横向刻蚀速率与纵向刻蚀速率的比值为1∶0.9～1∶1.5。
  16. 根据权利要求15所述的方法，其中，在第一灰化处理，第二灰化处理和第三灰化处理中，使用的刻蚀气体包括六氟化硫和氧气的至少之一。
  17. 根据权利要求16所述的方法，其中，所述刻蚀气体为氧气，所述横向刻蚀速率与纵向刻蚀速率的比值为1∶0.9。
  18. 根据权利要求16所述的方法，其中，所述刻蚀气体为六氟化硫和氧气的混合，且六氟化硫与氧气的流量比为0.02-0.1，所述横向刻蚀速率与纵向刻蚀速率的比值为1∶1.5。
  19. 根据权利要求18所述的方法，其中，六氟化硫的流量为200-800sccm。
  20. 根据权利要求18所述的方法，其中，氧气的流量为8000-10000sccm。
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