WO2020042258A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

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Publication number
WO2020042258A1
WO2020042258A1 PCT/CN2018/107203 CN2018107203W WO2020042258A1 WO 2020042258 A1 WO2020042258 A1 WO 2020042258A1 CN 2018107203 W CN2018107203 W CN 2018107203W WO 2020042258 A1 WO2020042258 A1 WO 2020042258A1
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Prior art keywords
layer
source
drain
electrode
display panel
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PCT/CN2018/107203
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English (en)
French (fr)
Inventor
王超
刘广辉
颜源
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武汉华星光电技术有限公司
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Priority to US16/323,523 priority Critical patent/US11521993B2/en
Publication of WO2020042258A1 publication Critical patent/WO2020042258A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to a display panel and a manufacturing method thereof, and more particularly, to a display panel capable of reducing the number of photomasks and a manufacturing method thereof.
  • liquid crystal displays Liquid Crystal Display, LCD
  • LCD liquid crystal Display
  • other flat display devices have been widely used in mobile phones, televisions, personal computers due to their advantages such as high picture quality, power saving, thin body and wide application range.
  • a liquid crystal display using low temperature polysilicon (LTPS) as an active region since the low temperature polysilicon has a higher carrier mobility, the transistor can obtain a higher switching current ratio. Therefore, under the condition of meeting the required charging current, the size of each pixel transistor can be reduced, thereby increasing the light transmission area of each pixel, so as to increase the panel aperture ratio, improve the panel highlights and high resolution, and reduce the panel power Consuming. Therefore, a low-temperature polysilicon (LTPS) liquid crystal display can obtain a better visual experience.
  • LTPS low temperature polysilicon
  • the present invention provides a display panel and a manufacturing method thereof to solve the problem that the photo mask is used too many times in the prior art, thereby increasing the manufacturing cost.
  • An object of the present invention is to provide a method for manufacturing a display panel, which reduces the number of photomasks used in manufacturing a display panel by using two gray-level mask processes, thereby reducing manufacturing costs.
  • Another object of the present invention is to provide a display panel, which uses a gate electrode as a light-shielding layer, omits a flat layer, and a bottom electrode (BITO) layer as a pixel electrode, so as to reduce the number of pixels used in manufacturing the display panel.
  • the number of photomasks reduces manufacturing costs.
  • an embodiment of the present invention provides a method for manufacturing a display panel, wherein the method for manufacturing the display panel includes the steps of: providing a substrate; forming a gate on the substrate; forming a gate An insulating layer is formed on the gate and the substrate; a polysilicon layer is formed on the gate insulating layer; a first grayscale masking process is performed on the polysilicon layer to form a polysilicon layer; A source region, a drain region, and an active region between the source region and the drain region, wherein the first grayscale mask process is selected from a half-tone photomask A group consisting of a process and a gray dimming mask process; forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer; forming a first electrode layer on the interlayer dielectric layer Up; performing a second grayscale masking process on the first electrode layer and the interlayer dielectric layer, wherein the second grayscale masking process is selected from a half-tone photomask
  • the electrical material pattern layer further includes an electrode contact layer
  • the method of manufacturing the display panel further includes a step of forming a passivation pattern layer on the source contact layer and the source contact layer. On the drain contact layer, wherein the passivation pattern layer exposes the electrode contact layer.
  • the method for manufacturing a display panel further includes a step of forming a second electrode pattern layer on the passivation pattern layer and the electrode contact layer.
  • another embodiment of the present invention provides a method for manufacturing a display panel, wherein the method for manufacturing the display panel includes the steps of: providing a substrate; forming a gate on the substrate; and forming a gate insulating layer on the substrate. Forming a polysilicon layer on the gate insulating layer on the gate and the substrate; and performing a first grayscale masking process on the polysilicon layer to form a source region of the polysilicon layer, A drain region and an active region between the source region and the drain region; forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer; forming a first An electrode layer is on the interlayer dielectric layer; and a second grayscale masking process is performed on the first electrode layer and the interlayer dielectric layer, including: patterning the first electrode layer Forming a first electrode pattern layer; and forming a source via and a drain via in the interlayer dielectric layer, wherein the source via exposes the source region and the drain via exposes Mentioned drain region.
  • the method for manufacturing a display panel further includes the steps of: forming an electrical material pattern layer on the first electrode pattern layer and the source perforation of the interlayer dielectric layer. And the drain via, wherein the electrical material pattern layer includes a source contact layer and a drain contact layer, and the source contact layer is electrically connected to the source region through the source via The drain contact layer is electrically connected to the drain region through the drain via.
  • the electrical material pattern layer further includes an electrode contact layer
  • the method for manufacturing the display panel further includes a step of forming a passivation pattern layer on the source contact layer and the source contact layer. On the drain contact layer, wherein the passivation pattern layer exposes the electrode contact layer.
  • the method for manufacturing a display panel further includes a step of forming a second electrode pattern layer on the passivation pattern layer and the electrode contact layer.
  • the first grayscale mask process and the second grayscale mask process are selected from the group consisting of a half-tone photomask process and a gray dimming mask process.
  • One ethnic group is selected from the group consisting of a half-tone photomask process and a gray dimming mask process.
  • another embodiment of the present invention provides a display panel, wherein the display panel includes: a substrate, a gate, a gate insulating layer, a polysilicon layer, an interlayer dielectric layer, and a first electrode. Pattern layer.
  • the gate is provided on the substrate.
  • the gate insulating layer is provided on the gate and the substrate.
  • the polysilicon layer is disposed on the gate insulating layer, wherein the polysilicon layer includes a source region, a drain region, and an active region disposed between the source region and the drain region. .
  • the interlayer dielectric layer is disposed on the gate insulating layer and the polysilicon layer, and the interlayer dielectric layer has a source via and a drain via, wherein the source via exposes the source A polar region and the drain via expose the drain region.
  • the first electrode pattern layer is disposed on the interlayer dielectric layer.
  • the display panel further includes an electrical material pattern layer provided on the first electrode pattern layer and the source perforations and the drains of the interlayer dielectric layer.
  • the electrical material pattern layer includes a source contact layer and a drain contact layer.
  • the source contact layer is electrically connected to the source region through the source via.
  • the drain contact layer is electrically connected to the drain region through the drain via.
  • the electrical material pattern layer further includes an electrode contact layer
  • the display panel includes a passivation pattern layer provided on the source contact layer and On the drain contact layer, wherein the passivation pattern layer exposes the electrode contact layer.
  • the display panel further includes a second electrode pattern layer disposed on the passivation pattern layer and the electrode contact layer.
  • the polysilicon layer is disposed through a first grayscale mask process, and the first electrode pattern layer and the interlayer dielectric layer are disposed through a second grayscale mask. Process settings.
  • the manufacturing method of the display panel of the embodiment of the present invention uses two gray-level mask processes to reduce the number of photomasks used in manufacturing the display panel.
  • a gate is used as a light shielding layer
  • a flat layer is omitted
  • a bottom electrode bottom An ITO (BITO) layer is used as a pixel electrode to reduce the number of photomasks used in manufacturing a display panel, thereby reducing manufacturing costs.
  • BITO bottom An ITO
  • FIG. 1 is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present invention.
  • 2A to 2K are schematic cross-sectional views of each step of a method for manufacturing a display panel according to an embodiment of the present invention.
  • 3A to 3G are schematic cross-sectional views of each step of a first grayscale mask process of a method for manufacturing a display panel according to an embodiment of the present invention.
  • 4A to 4D are schematic cross-sectional views of each step of a second grayscale mask process of a method for manufacturing a display panel according to an embodiment of the present invention.
  • the manufacturing method of the display panel in the prior art requires, for example, the following components to be sequentially manufactured through nine photomask steps, including a light shielding layer (LS layer) and a polysilicon layer ( poly crystal silicon layer; poly layer) , making a gate layer (GE layer) doped with carriers (N + & N -), an interlayer dielectric layer (ILD layer), forming the source / drain contact layer (SD layer ), Making a flat layer (PLN layer), making a bottom electrode layer (bottom ITO; BITO) as a common electrode, making a passivation layer (PV layer), and making a top electrode layer (top ITO; TITO) as pixel electrodes.
  • the manufacturing method of the display panel according to the embodiment of the present invention can reduce the number of photomasks used, so the manufacturing cost can be reduced.
  • a method 10 for manufacturing a display panel mainly includes steps 11 to 18: providing a substrate (step 11); forming a gate on the substrate (step 12); forming a gate insulating layer on the gate and the substrate (step 13); forming a polysilicon layer on the gate insulating layer (step 14); performing a first step on the polysilicon layer A gray-level mask process to form a source region, a drain region of the polysilicon layer, and an active region between the source region and the drain region (step 15); forming a An interlayer dielectric layer is on the gate insulating layer and the polysilicon layer (step 16); a first electrode layer is formed on the interlayer dielectric layer (step 17); and the first electrode is Layer and the interlayer dielectric layer are subjected to a second grayscale masking process, which includes: patterning the first electrode layer to form a first electrode pattern layer; and forming the interlayer dielectric layer in the interlayer dielectric layer.
  • the method 10 for manufacturing a display panel is firstly step 11: providing a substrate 21.
  • the substrate 11 is, for example, a base substrate and can be used to carry the gate, the gate insulation layer, the polysilicon layer, the interlayer dielectric layer, and the first electrode. Pattern layer.
  • the substrate 11 is, for example, a flexible substrate, a transparent substrate, or a flexible transparent substrate.
  • a method 10 for manufacturing a display panel according to an embodiment of the present invention is followed by step 12: forming a gate electrode 22 on the substrate 21.
  • the gate electrode 22 is formed on the substrate by, for example, a lithography etching step. In other words, a photomask process is required in this step 12.
  • the gate electrode 22 can also be used as a light shielding layer for shielding the active region of the polysilicon layer formed later.
  • step 12 is to make a bottom gate, so that the gate layer 22 can function as a light shielding layer in addition to its function as a gate, thereby reducing the number of times a photomask is used.
  • a method 10 for manufacturing a display panel according to an embodiment of the present invention is followed by step 13: forming a gate insulating layer 23 on the gate 22 and the substrate 21.
  • the gate insulating layer 23 may be deposited on the gate 22 and the substrate 21 by using materials or manufacturing methods commonly used in semiconductor processes.
  • a method 10 for manufacturing a display panel according to an embodiment of the present invention is followed by step 14: forming a polysilicon layer 24 on the gate insulating layer 23.
  • the polysilicon layer 24 is formed, for example, by first forming an amorphous silicon layer (not shown) on the gate insulating layer 23, and then performing a laser on the amorphous silicon layer. An annealing step is performed to form the amorphous silicon layer into the polysilicon layer 24.
  • a method 10 for manufacturing a display panel is followed by step 15: performing a first grayscale masking process on the polysilicon layer 24 to form the polysilicon layer 24
  • a source region 241, a drain region 242, and an active region 243 are located between the source region 241 and the drain region 242.
  • the first grayscale mask process is selected from a group consisting of a half-tone photomask process and a gray dimming mask process, for example.
  • the first gray-level mask process is, for example, used to perform a lithography etching step on the polysilicon layer 24 to form photoresist layers with different thicknesses on the polysilicon layer 24. Therefore, by using different etching parameters, the source region 241 and the drain region 242 can be exposed, and then the source region 241 and the drain region 242 can be doped with carriers.
  • FIG. 3A is a schematic diagram of the first grayscale mask process, so that when the polysilicon layer 24 is subjected to a lithographic etching process, a photoresist layer 30 with different thicknesses is formed on the polysilicon layer 24. It can be known from FIG. 3A that an exposed portion of the polysilicon layer 24 can be patterned by an etching step 301.
  • FIG. 3B is a schematic diagram of the first stripping photoresist step 302. The predetermined source region 241 and the drain region 242 are exposed through different etching parameters to facilitate heavy carrier doping 303 (as shown in FIG. 3B). 3C).
  • FIG. 3A is a schematic diagram of the first grayscale mask process, so that when the polysilicon layer 24 is subjected to a lithographic etching process, a photoresist layer 30 with different thicknesses is formed on the polysilicon layer 24. It can be known from FIG. 3A that an exposed portion of the polysilicon layer 24 can be patterned by an
  • FIG. 3D is a schematic diagram of the second stripping photoresist step 304.
  • other parts 24A and 24B of the polysilicon layer 24 may be exposed again, so as to facilitate light carrier doping 305 (see FIG. 3E). (Shown) to further improve the effect of the thin film transistor.
  • FIG. 3F is a schematic diagram of the third stripping photoresist step 306.
  • all photoresist can be removed, and the remaining portion 24C of the polysilicon layer (that is, the active region 243 is passed as an electron hole) is exposed. Channel) to facilitate carrier doping 307 to the remaining portion 24C (as shown in FIG. 3G).
  • a method 10 for manufacturing a display panel according to an embodiment of the present invention is followed by step 16: forming an interlayer dielectric layer 25 on the gate insulating layer 23 and the polysilicon layer 24 .
  • the interlayer dielectric layer 25 may be deposited on the gate insulating layer 23 and the polysilicon layer 24 through materials or manufacturing methods commonly used in semiconductor processes.
  • the interlayer dielectric layer 25 includes, for example, a multilayer material including a silicon nitride layer 251 and a silicon oxide layer 252.
  • a method 10 for manufacturing a display panel according to an embodiment of the present invention is followed by step 17: forming a first electrode layer 26 on the interlayer dielectric layer 25.
  • the material of the first electrode layer 26 is, for example, indium tin oxide (ITO), and the first electrode layer 26 can be used as a bottom electrode layer (bottom ITO; BITO).
  • the method 10 for manufacturing a display panel according to an embodiment of the present invention is finally step 18: performing a second gray scale on the first electrode layer 26 and the interlayer dielectric layer 25.
  • the mask process includes: patterning the first electrode layer 26 to form a first electrode pattern layer 261; and forming a source via 25A and a drain via 25B in the interlayer dielectric layer 25, The source via 25A exposes the source region 241 and the drain via 25B exposes the drain region 242 (step 18).
  • the second grayscale mask process is selected from a group consisting of a half-tone photomask process and a gray dimming mask process, for example.
  • the second gray-level mask process is, for example, used to perform a lithography etching step on the first electrode layer 26 and the interlayer dielectric layer 25 to form photoresists with different thicknesses. Layers on the first electrode layer 26 and the interlayer dielectric layer 25.
  • FIGS. 4A to 4D are through the second gray-level masking process, so that when a photolithography etching process is performed on the first electrode layer and the interlayer dielectric layer, photoresist layers 40 having different thicknesses are formed on the first electrode layer and the interlayer dielectric layer.
  • 4B is a schematic diagram of step 402 of first stripping the photoresist layer 40.
  • the first electrode layer 26 is patterned by step 403 with different etching parameters to form a first electrode pattern layer 261 (as shown in FIG. 4C). (Shown), wherein the first electrode pattern layer 261 can be used as a pixel electrode.
  • FIG. 4D is a schematic diagram of step 404 of stripping the photoresist layer 40 a second time, and the photoresist layer 40 can be completely removed through different etching parameters.
  • the first electrode pattern layer 261 can be formed and the interlayer dielectric layer 25 can be formed by using a photomask process (the second grayscale mask process).
  • the source through-hole 25A and the drain through-hole 25B can reduce the number of times a photomask is used.
  • the embodiment of the present invention may further include a step of forming an electrical material pattern layer 27 on the first electrode pattern layer 261 and the interlayer dielectric layer 25.
  • the electrical material pattern layer 27 includes a source contact layer 271 and a drain contact layer 272, and the source contact layer 271 passes through the source via 25A is electrically connected to the source region 241, and the drain contact layer 272 is electrically connected to the drain region 242 through the drain via 25B.
  • the electrical material pattern layer 27 is formed on the first electrode pattern layer 261 and the source vias 25A of the interlayer dielectric layer 25 with The drain via 25B is described. In other words, the formation of the electrical material pattern layer 27 requires a photomask process.
  • the electrical material pattern layer 27 further includes an electrode contact layer 273, and the method 10 for manufacturing a display panel according to an embodiment of the present invention further includes a step of forming a passivation pattern layer 28.
  • the passivation pattern layer 28 exposes the electrode contact layer 273.
  • the passivation pattern layer 28 is formed on the source contact layer 271 and the drain contact layer 272 through a lithography etching step, for example. In other words, the formation of the passivation pattern layer 28 requires a photomask process.
  • the method 10 for manufacturing a display panel according to the embodiment of the present invention may further include a step of forming a second electrode pattern layer 29 on the passivation pattern layer 28 and the electrode contact layer 273. on.
  • the material of the second electrode pattern layer 29 is, for example, indium tin oxide (ITO), and the second electrode pattern layer 29 can be used as a top electrode layer (Top ITO; TITO).
  • the second electrode pattern layer 29 is formed on the passivation pattern layer 28 and the electrode contact layer 273 through a lithography etching step, for example, and the second electrode pattern layer 29 can be used as A common electrode. In other words, the formation of the second electrode pattern layer 29 requires a photomask process.
  • the manufacturing method 10 of the display panel according to the embodiment of the present invention does not include the production of a flat layer, so the number of times a photomask is used can be reduced.
  • the manufacturing method 10 of the display panel according to the embodiment of the present invention can reduce the number of photomasks used in manufacturing the display panel by using two gray-level mask processes.
  • a bottom gate can also be manufactured, so that the gate layer can serve as a light shielding layer in addition to its function as a gate, thereby reducing the number of photomasks. frequency.
  • the method for manufacturing a display panel according to the embodiment of the present invention can also reduce the number of times of using a photomask by not making a flat layer. Therefore, compared with the manufacturing method of the display panel in the prior art (nine photomask steps), the display panel of the embodiment of the present invention can be fabricated into the upper electrode layer through six photomask steps.
  • an embodiment of the present invention further provides a display panel 20, which includes: a substrate 21, a gate 22, a gate insulating layer 23, a polysilicon layer 24, an interlayer dielectric layer 25, and a first An electrode pattern layer 261.
  • the gate electrode 22 is disposed on the substrate 21.
  • the gate insulating layer 23 is disposed on the gate 22 and the substrate 21.
  • the polysilicon layer 24 is disposed on the gate insulating layer 23, wherein the polysilicon layer 24 includes a source region 241, a drain region 242, and the source region 241 and the drain region 242. Between an active region 243.
  • the interlayer dielectric layer 25 is disposed on the gate insulating layer 23 and the polysilicon layer 24.
  • the interlayer dielectric layer 25 has a source via 25A and a drain via 25B, wherein the source The electrode via 25A exposes the source region 241 and the drain via 25B exposes the drain region 242.
  • the first electrode pattern layer 26 is disposed on the interlayer dielectric layer 25.
  • the display panel further includes an electrical material pattern layer 27 provided on the first electrode pattern layer 261 and the source perforation 25A of the interlayer dielectric layer 25.
  • the electrical material pattern layer 27 includes a source contact layer 271 and a drain contact layer 272.
  • the source contact layer 271 is electrically connected to the source region 241 through the source via 25A.
  • the drain contact layer 272 is electrically connected to the drain region 242 through the drain via 25B.
  • the electrical material pattern layer 27 further includes an electrode contact layer 273, and the display panel 20 includes a passivation pattern layer 28, and the passivation pattern layer 28 is disposed on the On the source contact layer 271 and the drain contact layer 272, the passivation pattern layer 28 exposes the electrode contact layer 273.
  • the display panel further includes a second electrode pattern layer 29 provided on the passivation pattern layer 28 and the electrode contact layer 273.
  • the polysilicon layer 24 is provided by a first gray-scale mask process, and the first electrode pattern layer 261 and the interlayer dielectric layer 25 are provided by a second gray layer. Step mask process settings.
  • the display panel 20 may be obtained by the display panel manufacturing method 10 according to the embodiment of the present invention, so related embodiments and examples are not described repeatedly.

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Abstract

一种显示面板及其制造方法（10），显示面板的制造方法（10）包含步骤：提供基板（21）；形成栅极（22）在基板（21）上；形成栅极绝缘层（23）在栅极（22）及基板（21）上；形成多晶硅层（24）在栅极绝缘层（23）上；对多晶硅层（24）进行第一灰阶掩膜工艺，以形成多晶硅层（24）的源极区（241）、漏极区（242）以及位在源极区（241）及漏极区（242）之间的有源区（243）；形成层间介电层（25）在栅极绝缘层（23）及多晶硅层（24）上；形成第一电极层（26）在层间介电层（25）上；以及对第一电极层（26）及层间介电层（25）进行第二灰阶掩膜工艺，其中包含：图案化第一电极层（26）以形成第一电极图案层（261）；及在层间介电层（25）内形成源极穿孔（25A）与漏极穿孔（25B），其中源极穿孔（25A）暴露源极区（241）及漏极穿孔（25B）暴露漏极区（242）。

Description

显示面板及其制造方法 技术领域
本发明是有关于一种显示面板及其制造方法，特别是有关于一种可减少光掩膜次数的显示面板及其制造方法。
 背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
例如，使用低温多晶硅(LTPS)作为有源区的液晶显示器，由于低温多晶硅具有较高载流子迁移率，故可使晶体管获得更高的开关电流比。因此在满足要求的充电电流条件下，每个像素晶体管的尺寸可以进行缩小化，进而增大每个像素的透光区，以提高面板开口率、改善面板亮点和高分辨率，以及降低面板功耗。因此，低温多晶硅(LTPS)液晶显示器可获得较佳的视觉体验。
然而，由于每个像素晶体管的尺寸朝向小型化的方向发展，因而使光掩膜设备成本的产生指数性的增长。
故，有必要提供一种显示面板及其制造方法，以解决现有技术所存在的问题。
 技术问题
有鉴于此，本发明提供一种显示面板及其制造方法，以解决现有技术所存在的使用光掩膜次数过多，进而增加制造成本的问题。
 技术解决方案
本发明的一目的在于提供一种显示面板的制造方法，其通过使用二个灰阶掩膜工艺，以减少制造显示面板中所使用的光掩膜次数，进而减少制造成本。
本发明的另一目的在于提供一种显示面板，其通过将栅极作为遮光层、省略平坦层、以及把下电极(bottom ITO；BITO)层作为像素电极，以减少制造显示面板中所使用的光掩膜次数，进而减少制造成本。
为达成本发明的前述目的，本发明一实施例提供一种显示面板的制造方法，其中所述显示面板的制造方法包含步骤：提供一基板；形成一栅极在所述基板上；形成一栅极绝缘层在所述栅极及所述基板上；形成一多晶硅层在所述栅极绝缘层上；对所述多晶硅层进行一第一灰阶掩膜工艺，以形成所述多晶硅层的一源极区、一漏极区以及位在所述源极区及所述漏极区之间的一有源区，其中所述第一灰阶掩膜工艺是选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群；形成一层间介电层在所述栅极绝缘层及所述多晶硅层上；形成一第一电极层在所述层间介电层上；对所述第一电极层及所述层间介电层进行一第二灰阶掩膜工艺，其中所述第二灰阶掩膜工艺是选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群，以及所述第二灰阶掩膜工艺包含：图案化所述第一电极层以形成一第一电极图案层；及在所述层间介电层内形成一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区；以及形成一电性材料图案层在所述第一电极图案层上及所述层间介电层的所述源极穿孔与所述漏极穿孔中，其中所述电性材料图案层包含一源极接触层及一漏极接触层，以及所述源极接触层通过所述源极穿孔电性连接所述源极区，所述漏极接触层通过所述漏极穿孔电性连接所述漏极区。
在本发明的一实施例中，所述电性材料图案层更包含一电极接触层，以及所述显示面板的制造方法还包含步骤：形成一钝化图案层在所述源极接触层及所述漏极接触层上，其中所述钝化图案层暴露所述电极接触层。
在本发明的一实施例中，所述显示面板的制造方法还包含步骤：形成一第二电极图案层在所述钝化图案层及所述电极接触层上。
再者，本发明另一实施例提供一种显示面板的制造方法，其中所述显示面板的制造方法包含步骤：提供一基板；形成一栅极在所述基板上；形成一栅极绝缘层在所述栅极及所述基板上；形成一多晶硅层在所述栅极绝缘层上；对所述多晶硅层进行一第一灰阶掩膜工艺，以形成所述多晶硅层的一源极区、一漏极区以及位在所述源极区及所述漏极区之间的一有源区；形成一层间介电层在所述栅极绝缘层及所述多晶硅层上；形成一第一电极层在所述层间介电层上；以及对所述第一电极层及所述层间介电层进行一第二灰阶掩膜工艺，其中包含：图案化所述第一电极层以形成一第一电极图案层；及在所述层间介电层内形成一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区。
在本发明的一实施例中，所述显示面板的制造方法还包含步骤：形成一电性材料图案层在所述第一电极图案层上及所述层间介电层的所述源极穿孔与所述漏极穿孔中，其中所述电性材料图案层包含一源极接触层及一漏极接触层，以及所述源极接触层通过所述源极穿孔电性连接所述源极区，所述漏极接触层通过所述漏极穿孔电性连接所述漏极区。
在本发明的一实施例中，所述电性材料图案层更包含一电极接触层，以及所述显示面板的制造方法还包含步骤：形成一钝化图案层在所述源极接触层及所述漏极接触层上，其中所述钝化图案层暴露所述电极接触层。
在本发明的一实施例中，所述显示面板的制造方法还包含步骤：形成一第二电极图案层在所述钝化图案层及所述电极接触层上。
在本发明的一实施例中，所述第一灰阶掩膜工艺及所述第二灰阶掩膜工艺是选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群。
再者，本发明又一实施例提供一种显示面板，其中所述显示面板包含：一基板、一栅极、一栅极绝缘层、一多晶硅层、一层间介电层及一第一电极图案层。所述栅极设在所述基板上。所述栅极绝缘层设在所述栅极及所述基板上。所述多晶硅层设在所述栅极绝缘层上，其中所述多晶硅层包含一源极区、一漏极区及设在所述源极区及所述漏极区之间的一有源区。所述层间介电层设在所述栅极绝缘层及所述多晶硅层上，所述层间介电层具有一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区。所述第一电极图案层设在所述层间介电层上。
在本发明的一实施例中，所述显示面板更包含一电性材料图案层，设在所述第一电极图案层上及所述层间介电层的所述源极穿孔与所述漏极穿孔中，其中所述电性材料图案层包含：一源极接触层及一漏极接触层。所述源极接触层通过所述源极穿孔电性连接所述源极区。所述漏极接触层通过所述漏极穿孔电性连接所述漏极区。
在本发明的一实施例中，所述电性材料图案层更包含一电极接触层，以及所述显示面板包含一钝化图案层，所述钝化图案层设在所述源极接触层及所述漏极接触层上，其中所述钝化图案层暴露所述电极接触层。
在本发明的一实施例中，所述显示面板还包含一第二电极图案层，设在所述钝化图案层及所述电极接触层上。
在本发明的一实施例中，所述多晶硅层是通过一第一灰阶掩膜工艺设置，以及所述第一电极图案层与所述层间介电层是通过一第二灰阶掩膜工艺设置。
 有益效果
与现有技术相比较，本发明实施例的显示面板的制造方法，其通过使用二个灰阶掩膜工艺，以减少制造显示面板中所使用的光掩膜次数。另外，本发明实施例的显示面板，通过将栅极作为遮光层、省略平坦层、以及把下电极(bottom ITO；BITO)层作为像素电极，以减少制造显示面板中所使用的光掩膜次数，进而减少制造成本。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
 附图说明
图1是本发明一实施例的显示面板的制造方法的流程示意图。
图2A至2K是本发明一实施例的显示面板的制造方法的各个步骤的剖面示意图。
图3A至3G是本发明一实施例的显示面板的制造方法的第一灰阶掩膜工艺的各个步骤的剖面示意图。
图4A至4D是本发明一实施例的显示面板的制造方法的第二灰阶掩膜工艺的各个步骤的剖面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
首先要说明的是，现有技术中的显示面板的制作方法，例如需要依序通过九道光掩膜步骤来制作下列各组件，包含：遮光层(light shielding layer；LS layer)、制作多晶硅层(poly crystal silicon layer；Poly layer)、制作栅极层(GE layer)与载子参杂(N +&N -)、制作层间介电层(ILD layer)、制作源/漏极接触层(SD layer)、制作平坦层(PLN layer)、制作下电极层(bottom ITO；BITO)作为公用电极、制作钝化层(PV layer)以及制作上电极层(top ITO；TITO)作为像素电极。相较于上述的显示面板的制作方法，本发明实施例的显示面板的制作方法可减少所使用的光掩膜次数，故可减少制造成本。
请参照图1及图2A至2K所示，本发明一实施例的显示面板的制造方法10主要包含步骤11至18：提供一基板(步骤11)；形成一栅极在所述基板上(步骤12)；形成一栅极绝缘层在所述栅极及所述基板上(步骤13)；形成一多晶硅层在所述栅极绝缘层上(步骤14)；对所述多晶硅层进行一第一灰阶掩膜工艺，以形成所述多晶硅层的一源极区、一漏极区以及位在所述源极区及所述漏极区之间的一有源区(步骤15)；形成一层间介电层在所述栅极绝缘层及所述多晶硅层上(步骤16)；形成一第一电极层在所述层间介电层上(步骤17)；以及对所述第一电极层及所述层间介电层进行一第二灰阶掩膜工艺，其中包含：图案化所述第一电极层以形成一第一电极图案层；及在所述层间介电层内形成一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区(步骤18)。本发明将于下文逐一详细说明实施例上述各组件的细部构造、组装关系及其运作原理。
请一并参照图1及图2A，本发明一实施例的显示面板的制造方法10首先是步骤11：提供一基板21。在本步骤11中，所述基板11例如是一衬底基板，可用于承载所述栅极、所述栅极绝缘层、所述多晶硅层、所述层间介电层及所述第一电极图案层。在一实施例中，所述基板11例如是一柔性基板、一透光基板或者一柔性透光基板。
请一并参照图1及图2B，本发明一实施例的显示面板的制造方法10接着是步骤12：形成一栅极22在所述基板21上。在本步骤12中，所述栅极22例如是通过微影蚀刻步骤以形成在所述基板上。换言之，在本步骤12中需使用一道光掩膜工艺。要提到的是，所述栅极22亦可作为遮光层，用于遮挡后续形成的所述多晶硅层的有源区。在一实施例中，步骤12是通过制作底栅极的方式，以使所述栅极层22除了作为栅极的功能之外还可作为遮光层，进而减少使用光掩膜的次数。
请一并参照图1及图2C，本发明一实施例的显示面板的制造方法10接着是步骤13：形成一栅极绝缘层23在所述栅极22及所述基板21上。在本步骤13中，例如可通过半导体工艺中常见材料或制作方法，将所述栅极绝缘层23沉积在所述所述栅极22及所述基板21上。
请一并参照图1及图2D，本发明一实施例的显示面板的制造方法10接着是步骤14：形成一多晶硅层24在所述栅极绝缘层23上。在本步骤14中，所述多晶硅层24的形成方式例如是，先在所述栅极绝缘层23上形成一非晶硅层(未绘示)，之后对所述非晶硅层进行一激光退火步骤，以使所述非晶硅层形成所述多晶硅层24。
请一并参照图1及图2E，本发明一实施例的显示面板的制造方法10接着是步骤15：对所述多晶硅层24进行一第一灰阶掩膜工艺，以形成所述多晶硅层24的一源极区241、一漏极区242以及位在所述源极区241及所述漏极区242之间的一有源区243。在本步骤15中，所述第一灰阶掩膜工艺例如选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群。在一实施例中，所述第一灰阶掩膜工艺例如是用于对所述多晶硅层24进行一微影蚀刻步骤，进而形成不同厚度的光阻层在所述多晶硅层24上。因此，可通过使用不同的蚀刻参数以暴露出所述源极区241与所述漏极区242，进而对所述源极区241与所述漏极区242进行载子掺杂。
举例而言，请参照图3A至3G。图3A是通过所述第一灰阶掩膜工艺，以使所述多晶硅层24在进行一微影蚀刻工艺时，形成不同厚度的光阻层30在所述多晶硅层24上的示意图。从图3A可知，所述多晶硅层24暴露出的部分可通过蚀刻步骤301，以图案化所述多晶硅层24。图3B是第一次剥除光阻步骤302的示意图，通过不同的蚀刻参数，以将预定的源极区241与漏极区242暴露而出，以便于进行重载子掺杂303(如图3C所示)。图3D是第二次剥除光阻步骤304的示意图，通过不同的蚀刻参数，可再暴露出所述多晶硅层24的其他部分24A及24B，以便于进行轻载子掺杂305(如图3E所示)进而提高薄膜晶体管的效果。图3F是第三次剥除光阻步骤306的示意图，通过不同的蚀刻参数，可将所有光阻去除，并且暴露出所述多晶硅层的剩余部分24C(即主动区243，作为电子电洞传递的沟道)，以便于对剩余部分24C进行载子掺杂307(如图3G所示)。
请一并参照图1及图2F，本发明一实施例的显示面板的制造方法10接着是步骤16：形成一层间介电层25在所述栅极绝缘层23及所述多晶硅层24上。在本步骤16中，例如可通过半导体工艺中常见材料或制作方法，将所述层间介电层25沉积在所述栅极绝缘层23及所述多晶硅层24上。在一实施例中，所述层间介电层25例如包含氮化硅层251及氧化硅层252的多层材料。
请一并参照图1及图2G，本发明一实施例的显示面板的制造方法10接着是步骤17：形成一第一电极层26在所述层间介电层25上。在本步骤17中，所述第一电极层26的材质例如是氧化铟锡(ITO)，并且所述第一电极层26可作为一下电极层(bottom ITO；BITO)。
请一并参照图1及图2H，本发明一实施例的显示面板的制造方法10最后是步骤18：对所述第一电极层26及所述层间介电层25进行一第二灰阶掩膜工艺，其中包含：图案化所述第一电极层26以形成一第一电极图案层261；及在所述层间介电层25内形成一源极穿孔25A与一漏极穿孔25B，其中所述源极穿孔25A暴露所述源极区241及所述漏极穿孔25B暴露所述漏极区242(步骤18)。在本步骤18中，所述第二灰阶掩膜工艺例如选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群。在一实施例中，所述第二灰阶掩膜工艺例如是用于对所述第一电极层26及所述层间介电层25进行一微影蚀刻步骤，进而形成不同厚度的光阻层在所述第一电极层26及所述层间介电层25上。
举例而言，请参照图4A至4D。图4A是通过所述第二灰阶掩膜工艺，以使所述第一电极层及所述层间介电层在进行一微影蚀刻工艺时，形成不同厚度的光阻层40在所述第一电极层26及所述层间介电层25上的示意图。从图4A可知，所述第一电极层26暴露出的部分可通过蚀刻步骤401，以形成所述源极穿孔25A与所述漏极穿孔25B。图4B是第一次剥除光阻层40的步骤402的示意图，通过不同的蚀刻参数的步骤403图案化所述第一电极层26，以形成一第一电极图案层261(如图4C所示)，其中所述第一电极图案层261可作为一像素电极。图4D是第二次剥除光阻层40的步骤404的示意图，通过不同的蚀刻参数，可将所述光阻层40全部去除。
由上可知，可在使用一次光掩膜工艺(所述第二灰阶掩膜工艺)的情况下，形成所述第一电极图案层261以及在所述层间介电层25内形成所述源极穿孔25A与所述漏极穿孔25B，故可减少使用光掩膜的次数。
在一实施例中，请参照图2I，本发明实施例还可包含步骤：形成一电性材料图案层27在所述第一电极图案层261上及所述层间介电层25的所述源极穿孔25A所述漏极穿孔25B中，其中所述电性材料图案层27包含一源极接触层271及一漏极接触层272，以及所述源极接触层271通过所述源极穿孔25A电性连接所述源极区241，所述漏极接触层272通过所述漏极穿孔25B电性连接所述漏极区242。在一范例中，所述电性材料图案层27例如是通过微影蚀刻步骤以形成在所述第一电极图案层261上及所述层间介电层25的所述源极穿孔25A与所述漏极穿孔25B中。换言之，所述电性材料图案层27的形成需使用一道光掩膜工艺。
在一实施例中，请参照图2J，所述电性材料图案层27更包含一电极接触层273，以及本发明实施例的显示面板的制造方法10还包含步骤：形成一钝化图案层28在所述源极接触层271及所述漏极接触层272上，其中所述钝化图案层28暴露所述电极接触层273。在一范例中，所述钝化图案层28例如是通过微影蚀刻步骤以形成在所述源极接触层271及所述漏极接触层272上。换言之，所述钝化图案层28的形成需使用一道光掩膜工艺。
在一实施例中，请参照图2K，本发明实施例的显示面板的制造方法10还可包含步骤：形成一第二电极图案层29在所述钝化图案层28及所述电极接触层273上。所述第二电极图案层29的材质例如是氧化铟锡(ITO)，并且所述第二电极图案层29可作为一上电极层(Top ITO；TITO)。在一范例中，所述第二电极图案层29例如是通过微影蚀刻步骤以形成在所述钝化图案层28及所述电极接触层273上，其中所述第二电极图案层29可作为一公用电极。换言之，所述第二电极图案层29的形成需使用一道光掩膜工艺。
在一实施例中，本发明实施例的显示面板的制造方法10中不包含平坦层的制作，故可减少使用光掩膜的次数。
由上可知，本发明实施例的显示面板的制造方法10可通过使用二个灰阶掩膜工艺，以减少制造显示面板时所使用的光掩膜次数。另外，本发明实施例的显示面板的制造方法还可通过制作底栅极的方式，以使所述栅极层除了作为栅极的功能之外还可作为遮光层，进而减少使用光掩膜的次数。此外，本发明实施例的显示面板的制造方法还可通过不制作平坦层，故可减少使用光掩膜的次数。因此，若是相较于现有技术中的显示面板的制作方法(九道光掩膜步骤），本发明实施例的显示面板可通过六道光掩膜步骤即可制作到上电极层。
请参照图2K，本发明实施例更提出一种显示面板20，包含：一基板21、一栅极22、一栅极绝缘层23、一多晶硅层24、一层间介电层25及一第一电极图案层261。所述栅极22设在所述基板21上。所述栅极绝缘层23设在所述栅极22及所述基板21上。所述多晶硅层24设在所述栅极绝缘层23上，其中所述多晶硅层24包含一源极区241、一漏极区242及设在所述源极区241及所述漏极区242之间的一有源区243。所述层间介电层25设在所述栅极绝缘层23及所述多晶硅层24上，所述层间介电层25具有一源极穿孔25A与一漏极穿孔25B，其中所述源极穿孔25A暴露所述源极区241及所述漏极穿孔25B暴露所述漏极区242。所述第一电极图案层26设在所述层间介电层25上。
在本发明的一实施例中，所述显示面板更包含一电性材料图案层27，设在所述第一电极图案层261上及所述层间介电层25的所述源极穿孔25A与所述漏极穿孔25B中，其中所述电性材料图案层27包含：一源极接触层271及一漏极接触层272。所述源极接触层271通过所述源极穿孔25A电性连接所述源极区241。所述漏极接触层272通过所述漏极穿孔25B电性连接所述漏极区242。
在本发明的一实施例中，所述电性材料图案层27更包含一电极接触层273，以及所述显示面板20包含一钝化图案层28，所述钝化图案层28设在所述所述源极接触层271及所述漏极接触层272上，其中所述钝化图案层28暴露所述电极接触层273。
在本发明的一实施例中，所述显示面板还包含一第二电极图案层29，设在所述钝化图案层28及所述电极接触层273上。
在本发明的一实施例中，所述多晶硅层24是通过一第一灰阶掩膜工艺设置，以及所述第一电极图案层261与所述层间介电层25是通过一第二灰阶掩膜工艺设置。
在本发明一实施例中，所述显示面板20可通过上述本发明实施例的显示面板的制造方法10来获得，故相关的实施例与范例不再重复描述。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (13)

  1. 一种显示面板的制造方法，其包含步骤：
    提供一基板；
    形成一栅极在所述基板上；
    形成一栅极绝缘层在所述栅极及所述基板上；
    形成一多晶硅层在所述栅极绝缘层上；
    对所述多晶硅层进行一第一灰阶掩膜工艺，以形成所述多晶硅层的一源极区、一漏极区以及位在所述源极区及所述漏极区之间的一有源区，其中所述第一灰阶掩膜工艺是选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群；
    形成一层间介电层在所述栅极绝缘层及所述多晶硅层上；
    形成一第一电极层在所述层间介电层上；
    对所述第一电极层及所述层间介电层进行一第二灰阶掩膜工艺，其中所述第二灰阶掩膜工艺是选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群，以及所述第二灰阶掩膜工艺包含：
    图案化所述第一电极层以形成一第一电极图案层；及
    在所述层间介电层内形成一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区；以及
    形成一电性材料图案层在所述第一电极图案层上及所述层间介电层的所述源极穿孔与所述漏极穿孔中，其中所述电性材料图案层包含一源极接触层及一漏极接触层，以及所述源极接触层通过所述源极穿孔电性连接所述源极区，所述漏极接触层通过所述漏极穿孔电性连接所述漏极区。
  2. 如权利要求1所述的显示面板的制造方法，其中所述电性材料图案层更包含一电极接触层，以及所述显示面板的制造方法还包含步骤：形成一钝化图案层在所述源极接触层及所述漏极接触层上，其中所述钝化图案层暴露所述电极接触层。
  3. 如权利要求2所述的显示面板的制造方法，还包含步骤：形成一第二电极图案层在所述钝化图案层及所述电极接触层上。
  4. 一种显示面板的制造方法，其包含步骤：
    提供一基板；
    形成一栅极在所述基板上；
    形成一栅极绝缘层在所述栅极及所述基板上；
    形成一多晶硅层在所述栅极绝缘层上；
    对所述多晶硅层进行一第一灰阶掩膜工艺，以形成所述多晶硅层的一源极区、一漏极区以及位在所述源极区及所述漏极区之间的一有源区；
    形成一层间介电层在所述栅极绝缘层及所述多晶硅层上；
    形成一第一电极层在所述层间介电层上；以及
    对所述第一电极层及所述层间介电层进行一第二灰阶掩膜工艺，其中包含：
    图案化所述第一电极层以形成一第一电极图案层；及
    在所述层间介电层内形成一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区。
  5. 如权利要求4所述的显示面板的制造方法，还包含步骤：形成一电性材料图案层在所述第一电极图案层上及所述层间介电层的所述源极穿孔与所述漏极穿孔中，其中所述电性材料图案层包含一源极接触层及一漏极接触层，以及所述源极接触层通过所述源极穿孔电性连接所述源极区，所述漏极接触层通过所述漏极穿孔电性连接所述漏极区。
  6. 如权利要求5所述的显示面板的制造方法，其中所述电性材料图案层更包含一电极接触层，以及所述显示面板的制造方法还包含步骤：形成一钝化图案层在所述源极接触层及所述漏极接触层上，其中所述钝化图案层暴露所述电极接触层。
  7. 如权利要求6所述的显示面板的制造方法，还包含步骤：形成一第二电极图案层在所述钝化图案层及所述电极接触层上。
  8. 如权利要求4所述的显示面板的制造方法，其中所述第一灰阶掩膜工艺及所述第二灰阶掩膜工艺是选自于由一半色调光掩膜工艺及一灰色调光掩膜工艺所组成的一族群。
  9. 一种显示面板，其包含：
    一基板；
    一栅极，设在所述基板上；
    一栅极绝缘层，设在所述栅极及所述基板上；
    一多晶硅层，设在所述栅极绝缘层上，其中所述多晶硅层包含一源极区、一漏极区及设在所述源极区及所述漏极区之间的一有源区；
    一层间介电层，设在所述栅极绝缘层及所述多晶硅层上，所述层间介电层具有一源极穿孔与一漏极穿孔，其中所述源极穿孔暴露所述源极区及所述漏极穿孔暴露所述漏极区；以及
    一第一电极图案层，设在所述层间介电层上。
  10. 如权利要求9所述的显示面板，更包含一电性材料图案层，设在所述第一电极图案层上及所述层间介电层的所述源极穿孔与所述漏极穿孔中，其中所述电性材料图案层包含：
    一源极接触层，通过所述源极穿孔电性连接所述源极区；及
    一漏极接触层，通过所述漏极穿孔电性连接所述漏极区。
  11. 如权利要求10所述的显示面板，其中所述电性材料图案层更包含一电极接触层，以及所述显示面板包含一钝化图案层，所述钝化图案层设在所述源极接触层及所述漏极接触层上，其中所述钝化图案层暴露所述电极接触层。
  12. 如权利要求11所述的显示面板，还包含一第二电极图案层，设在所述钝化图案层及所述电极接触层上。
  13. 如权利要求9所述的显示面板，其中所述多晶硅层是通过一第一灰阶掩膜工艺设置，以及所述第一电极图案层与所述层间介电层是通过一第二灰阶掩膜工艺设置。
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