WO2020207400A1 - 薄膜晶体管及其制备方法、显示基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、显示基板和显示装置 Download PDF

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WO2020207400A1
WO2020207400A1 PCT/CN2020/083683 CN2020083683W WO2020207400A1 WO 2020207400 A1 WO2020207400 A1 WO 2020207400A1 CN 2020083683 W CN2020083683 W CN 2020083683W WO 2020207400 A1 WO2020207400 A1 WO 2020207400A1
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Prior art keywords
grooves
substrate
thin film
film transistor
sub
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PCT/CN2020/083683
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English (en)
French (fr)
Inventor
胡迎宾
赵策
丁远奎
宋威
倪柳松
孙学超
郝朝威
闫梁臣
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/254,851 priority Critical patent/US11616147B2/en
Publication of WO2020207400A1 publication Critical patent/WO2020207400A1/zh

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Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a thin film transistor and a preparation method thereof, a display substrate and a display device.
  • the semiconductor parts on both sides of the channel region of the active layer need to be conductive. Due to the diffusion effect, the channel region of the active layer also has the risk of being conductive, which will cause poor uniformity of the thin film transistor, resulting in undesirable phenomena such as bright spots on the display panel.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and to provide a thin film transistor that effectively prevents the channel region of the active layer from being conductive.
  • the technical solution adopted to solve the technical problems of the present disclosure is a thin film transistor, which includes a substrate, an active layer disposed on the substrate, and the active layer includes a channel region and two sides of the channel region.
  • a plurality of first sub grooves on one side and a plurality of second sub grooves on a side of the active layer away from the substrate, the plurality of first sub grooves and the plurality of second sub grooves Alternately arranged along a direction parallel to the extension of the channel region.
  • the plurality of first sub-grooves and the plurality of second sub-grooves have the same depth.
  • the thin film transistor further includes an insulating layer disposed between the active layer and the substrate; and the insulating layer has a plurality of A first groove, the position of the plurality of first grooves in the insulating layer corresponding to at least one of the source contact region and the drain contact region of the active layer is close to the channel The location of the zone, the plurality of first grooves correspond to the plurality of second sub-grooves one-to-one, and the orthographic projections on the substrate overlap.
  • the thin film transistor further includes a light shielding layer disposed between the substrate and the insulating layer.
  • a side of the light shielding layer close to the insulating layer has a plurality of second grooves, and the positions of the plurality of second grooves on the light shielding layer correspond to all the positions of the active layer. At least one of the source contact region and the drain contact region is close to the channel region, and the plurality of second grooves correspond to the plurality of second sub-grooves one-to-one and are in the substrate The orthographic projections overlap.
  • the thin film transistor further includes a gate insulating layer, a gate, and a source and drain that are sequentially disposed on the active layer.
  • the material of the light shielding layer includes metallic aluminum, molybdenum or copper.
  • the plurality of second grooves penetrate the light shielding layer.
  • the present disclosure also provides a method for manufacturing a thin film transistor, including forming a substrate, and forming an active layer on the substrate; the active layer includes a channel region and source contact regions located on both sides of the channel region And a drain contact region; wherein the active layer is formed in a portion close to the channel region of at least one of the source contact region and the drain contact region of the active layer facing the A plurality of first sub-grooves on one side of the substrate and a plurality of second sub-grooves on a side of the active layer away from the substrate, the plurality of first sub-grooves and the plurality of second sub-grooves
  • the grooves are alternately arranged along a direction parallel to the extension of the channel region.
  • the plurality of first sub-grooves and the plurality of second sub-grooves have the same depth.
  • the active layer on the substrate before forming the active layer on the substrate, it further includes: forming an insulating layer on the substrate, and on the side of the insulating layer close to the active layer and corresponding to the active layer.
  • a plurality of first grooves are formed in at least one of the source contact region and the drain contact region of the layer near the channel region; and an active layer is formed on the substrate on which the insulating layer is formed
  • the plurality of first grooves correspond to the plurality of second sub grooves one-to-one, and the orthographic projections on the substrate overlap.
  • the method before forming the insulating layer on the substrate, the method further includes forming a light shielding layer on the substrate.
  • forming a light-shielding layer on the substrate includes: forming a light-shielding layer on the substrate by a patterning process, and on a side of the light-shielding layer close to the insulating layer and corresponding to all of the active layer. At least one of the source contact region and the drain contact region is formed with a plurality of second grooves at a position close to the channel region, and the plurality of second grooves and the plurality of second sub- The grooves correspond one to one and the orthographic projections on the substrate overlap.
  • a gate insulating layer is formed on the active layer, and a gate and source and drain are formed on the gate insulating layer.
  • the thin film transistor is a top-gate thin film transistor.
  • the material of the light shielding layer includes metallic aluminum, molybdenum or copper.
  • the plurality of second grooves penetrate the light shielding layer.
  • the present disclosure also provides a display substrate, including a substrate, and a thin film transistor disposed on the substrate; the thin film transistor includes any one of the above-mentioned thin film transistors.
  • the present disclosure also provides a display device including any of the above-mentioned display substrates.
  • FIG. 1 is a schematic diagram of the structure of a thin film transistor according to some embodiments of the disclosure.
  • FIG. 2 is a schematic diagram of forming a light-shielding layer in a method of manufacturing a thin film transistor according to some embodiments of the disclosure
  • FIG. 3 is a schematic diagram of forming an insulating layer in a method of manufacturing a thin film transistor according to some embodiments of the present disclosure
  • FIG. 4 is a schematic diagram of forming an active layer in a method of manufacturing a thin film transistor according to some embodiments of the present disclosure
  • FIG. 5 is a schematic diagram of the structure of forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode in a method for manufacturing a thin film transistor of some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of forming a light-shielding layer in a method of manufacturing a thin film transistor according to other embodiments of the disclosure.
  • FIG. 7 is a schematic diagram of forming an active layer in a method of manufacturing a thin film transistor according to other embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of the structure of forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode in a method of manufacturing a thin film transistor according to other embodiments of the present disclosure
  • FIG. 9 is a flowchart of a method for manufacturing a thin film transistor according to some embodiments of the disclosure.
  • FIG. 10 is a flowchart of a method for manufacturing a thin film transistor according to other embodiments of the disclosure.
  • the present embodiment provides a thin film transistor, including a substrate 1, an active layer 2, a gate insulating layer 5, a gate electrode 6, and a source and drain disposed on the substrate 1 in sequence.
  • the source and drain include a source 7 and a drain 8.
  • the active layer 2 includes a channel region 21 and a source contact region 22 and a drain contact region 23 located on both sides of the channel region 21; at least of the source contact region 22 and the drain contact region 23 of the active layer 2
  • a part of one close to the channel region 21 includes a plurality of first sub-grooves 25 arranged on the side of the active layer 2 facing the substrate and a plurality of second sub-grooves 25 on the side of the active layer away from the substrate.
  • the sub-grooves 24, the plurality of first sub-grooves 25 and the plurality of second sub-grooves 24 are alternately arranged along a direction parallel to the extension of the channel region 21.
  • the plurality of first sub-grooves 24 and the plurality of second sub-grooves 25 have the same depth.
  • the source contact area 22 and the drain contact area 23 of the active layer 2 are semiconductor structures, and the source contact area 22 is electrically connected to the source 7, and the drain contact area 23 is electrically connected to the drain 8.
  • the extension of the source layer 2, especially the length of the source contact region 22 and the drain contact region 23 close to the channel region 21, reduces the thickness of the active layer 2, so that the source contact of the active layer 2
  • the region 22 and the drain contact region 23 are conductive, the transmission path of the conductive diffusion effect is effectively extended, and the influence on the channel region 21 is avoided as much as possible, thereby ensuring the good characteristics and uniformity of the thin film transistor.
  • the atomic arrangement of the material of the active layer 2 is distorted and chaotic, so that the diffusion of the conductive effect to the channel region 21 can be well blocked, and the good characteristics and characteristics of the thin film transistor can be guaranteed. Uniformity.
  • the thin film transistor is a top-gate thin film transistor.
  • a top-gate thin film transistor is taken as an example for description.
  • the top-gate thin film transistor further includes an insulating layer 3, which is disposed on the side of the active layer 2 close to the substrate 1; on the side of the insulating layer 3 close to the active layer 2, and corresponding to the source of the thin film transistor
  • At least one of the pole contact region 22 and the drain contact region 23 has a plurality of first grooves 31 at a position close to the channel region 21, and the plurality of first grooves 31 define the wave structure of the active layer 2.
  • the first grooves 31 are in one-to-one correspondence with the plurality of second sub-grooves 21 and the orthographic projections on the substrate overlap.
  • the insulating layer 3 is in contact with the active layer 2, and the first groove in the upper surface of the insulating layer 3 (the side facing away from the substrate 1) defines the wave structure of the active layer 2.
  • an insulating layer 3 can be prepared on the substrate 1, and the position of the source contact region 22 and the drain contact region 23 near the channel region 21 on the side of the insulating layer 3 facing away from the substrate 1
  • the first groove 31 is formed by etching. After that, the active layer 2 is formed on the substrate 1 on which the insulating layer 3 is formed.
  • the active layer 2 is positioned at the position corresponding to the first groove 31 (that is, the source contact area 22 and the drain).
  • the position of the contact region 23 close to the channel region 21 naturally forms a wave structure, and the plurality of first grooves 31 correspond to the plurality of second sub grooves 24 one-to-one, and the orthographic projections on the substrate overlap.
  • the plurality of second sub-grooves 24 and the plurality of first sub-grooves 25 are defined by the corrugated structure formed by etching the upper surface of the insulating layer 3.
  • the thickness of the insulating layer 3 includes to In some embodiments, the depth of etching the upper surface of the insulating layer 3 may be At this time, the depths of the plurality of second sub grooves 24 and the plurality of first sub grooves 25 are
  • the material of the insulating layer is silicon oxide, silicon nitride or a composite material of the two.
  • the top-gate thin film transistor may further include a light-shielding layer 4 disposed between the substrate 1 and the insulating layer 3.
  • the insulating layer 3 is disposed between the light-shielding layer 4 and the active layer 2. between.
  • the light shielding layer 4 is disposed on the side of the active layer 2 close to the substrate 1 to shield external light, so as to prevent the active layer 2 from being affected by the light and destructing the characteristics of the thin film transistor.
  • the material of the light shielding layer 4 may include metal, and a metal with good light reflection needs to be selected, which is usually Al, Mo, Cu.
  • the insulating layer 3 should be used to separate the light shielding layer 4 from the active layer 2.
  • the side of the light shielding layer 4 close to the insulating layer 3 has a plurality of second grooves 41 corresponding to at least one of the source contact region 22 and the drain contact region 23 and close to the channel region 21.
  • the second grooves 41 define a plurality of first grooves 31, and further define the wave structure.
  • the plurality of second grooves 41 correspond to the plurality of second sub-grooves 24 one by one and are orthographic projections on the substrate overlapping.
  • the corresponding source contact region 22 and the drain contact region 23 are close to each other on the upper surface of the light-shielding layer 4 (the side facing away from the substrate 1)
  • a plurality of second grooves 41 are formed at the position of the channel region 21, and then the insulating layer 3 is formed.
  • the insulating layer 3 will naturally form the first groove 31 at the position corresponding to the second groove 41, so that the subsequently formed active layer
  • the position of the source contact area 22 and the drain contact area 23 close to the channel area 21 of 2 has a wave structure, and the plurality of second grooves 41 correspond to the plurality of second sub grooves 24 one-to-one and are orthographic projections on the substrate overlapping.
  • the wrinkle structure causes the same wrinkles on the upper surface of the insulating layer 3 after the insulating layer 3 is provided on the light shielding layer 4
  • the structure further defines the plurality of second sub-grooves 24 and the plurality of first sub-grooves 25.
  • the thickness of the light shielding layer 4 includes to When the thickness of the light shielding layer 4 is When the upper surface of the light shielding layer 4 is etched, the depth may be less than or equal to
  • the second groove may penetrate the light shielding layer 4 (not shown in the drawings). At this time, the upper surface of the light shielding layer 4 is etched to a depth equal to the thickness of the light shielding layer 4. It can be understood that since the second groove is disposed at a position close to the channel region 21 corresponding to at least one of the source contact region 22 and the drain contact region 23 of the active layer 2, even if the second groove 41 penetrates through the light-shielding layer 4, and basically does not affect the light-shielding effect of the channel region 21 of the active layer 2, and does not greatly affect the characteristics of the thin film transistor.
  • the upper surface (the side facing away from the substrate 1) may not be etched to form a plurality of second grooves 41, that is, the upper surface of the light shielding layer 4 is flat. of.
  • the wave structure is defined by etching the upper surface of the insulating layer 3 provided on the light shielding layer 4 to form a plurality of first grooves 31.
  • the plurality of first grooves 31 and the plurality of second sub-grooves 24 are one One corresponds and the orthographic projections overlap on the base.
  • the present disclosure also provides a method for preparing a thin film transistor. As shown in FIGS. 2 to 5, the method for preparing a thin film transistor provided in this embodiment can be used to prepare the thin film transistor provided in Example 1.
  • the thin film transistor is a top gate thin film transistor, and the preparation method of this embodiment will be described in detail below by taking the preparation of a top gate thin film transistor as an example.
  • the first preparation method provided in this embodiment is shown in Figs. 2 to 4, and includes the following steps S11 to S13:
  • the material of the light shielding layer 4 may include opaque materials such as metal, such as Al, Mo, and Cu.
  • a photoresist is formed on the light-shielding layer 4, and then the light-shielding layer 4 with a plurality of second grooves 41 is formed on the substrate 1 through exposure, development, and etching processes. Graphics.
  • An insulating layer 3 is formed on the substrate 1 on which the light shielding layer 4 is formed, and the upper surface of the insulating layer 3 corresponds to the source contact area 22 and the drain contact area 23 of the active layer 4
  • a plurality of first grooves 31 are formed on at least one of the positions close to the channel region 21.
  • a whole layer of insulating layer 3 material can be directly formed on the substrate 1 on which the light shielding layer 4 is formed.
  • the second groove 41 in the light shielding layer 4 is used to make the insulating layer 3 in the corresponding second groove 41
  • the position is naturally sunken, that is, the first groove 31 is formed at a position close to the channel region 21 corresponding to at least one of the source contact region 22 and the drain contact region 23.
  • the wave structure refers to a plurality of first sub-grooves 25 arranged on the side of the active layer 2 facing the substrate and a plurality of second sub-grooves 25 on the side of the active layer away from the substrate.
  • the sub-grooves 24, the plurality of first sub-grooves 25 and the plurality of second sub-grooves 24 are alternately arranged along a direction parallel to the extension of the channel region 21. It should be noted that the plurality of first sub-grooves 24 and the plurality of second sub-grooves 25 have the same depth.
  • the material of the active layer 2 is directly formed on the substrate 1 on which the insulating layer 3 is formed.
  • the insulating layer 3 has a plurality of first grooves 31, when the material of the active layer 2 is formed, the material of the active layer 2 will naturally be located in the source contact region 22 and the drain contact region 23 near the channel region 21
  • the position of is sunken to form a wave structure
  • the plurality of first grooves 41 correspond to the plurality of second sub grooves 24 one-to-one, and the orthographic projections on the substrate overlap.
  • the thickness of the light shielding layer 4 includes to When the thickness of the light shielding layer 4 is When the upper surface of the light shielding layer 4 is etched, the depth may be less than or equal to
  • the conductive method can be an ion implantation method.
  • the ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method or a solid diffusion implantation method.
  • the conductive method can also adopt ion bombardment to hydrogenate or deoxidize the oxide semiconductor material in the conductive region.
  • this embodiment mode may further include the step of forming the gate insulating layer 5, the gate 6, the source 7 and the drain 8 of the thin film transistor on the substrate 1.
  • this embodiment mode may further include the step of forming the gate insulating layer 5, the gate 6, the source 7 and the drain 8 of the thin film transistor on the substrate 1.
  • the second preparation method provided in this embodiment is shown in Figs. 6 to 8, and includes the following steps S21 to S23:
  • the second preparation method is similar to the first preparation method. The difference is that in the second preparation method, there is no need to form multiple second grooves 41 on the light-shielding layer 4, and multiple first grooves 41 are directly formed on the insulating layer 3. ⁇ 31. Specifically, this implementation includes the following steps:
  • a light-shielding layer 4 is first formed on the substrate 1.
  • the light-shielding layer 4 is used to shield external light, so as to prevent the active layer 2 from being affected by the light and destroying the characteristics of the thin film transistor.
  • the material of the light shielding layer 4 may include metal, and a metal with good light reflection needs to be selected, which is usually Al, Mo, Cu.
  • the upper surface of the light-shielding layer 4 is a flat surface, and it is not necessary to form a plurality of second grooves 41 while forming the pattern of the light-shielding layer 4 through a patterning process.
  • An insulating layer 3 is formed on the substrate 1 on which the light shielding layer 4 is formed, and the upper surface of the insulating layer 3 corresponds to at least one of the source contact region 22 and the drain contact region 23 of the active layer 2 through a patterning process A plurality of first grooves 31 are formed close to the channel region 21.
  • a commonly used light-shielding agent can be injected to make the insulating layer 3 opaque, so as to play a light-shielding effect and avoid the influence of light on the active layer 2.
  • the insulating layer 3 can simultaneously realize the insulating function and the light-shielding function, it is not necessary to additionally provide the light-shielding layer 4 (not shown in the drawings).
  • the wave structure refers to a plurality of first sub-grooves 25 arranged on the side of the active layer 2 facing the substrate and a plurality of second sub-grooves 25 on the side of the active layer away from the substrate.
  • the sub-grooves 24, the plurality of first sub-grooves 25 and the plurality of second sub-grooves 24 are alternately arranged along a direction parallel to the extension of the channel region 21. It should be noted that the plurality of first sub-grooves 24 and the plurality of second sub-grooves 25 have the same depth.
  • the material of the active layer 2 can be directly formed on the substrate 1 on which the insulating layer 3 is formed.
  • the insulating layer 3 has a plurality of first grooves 31, when the material of the active layer 2 is formed, the material of the active layer 2 will naturally be located in the source contact region 22 and the drain contact region 23 near the channel region 21
  • the position of is sunken to form a wave structure, and the plurality of first grooves 31 correspond to the plurality of second sub grooves 24 one by one, and the orthographic projections on the substrate overlap.
  • the plurality of second sub-grooves 24 and the plurality of first sub-grooves 25 are formed by a corrugated structure formed by etching the upper surface of the insulating layer 3.
  • the thickness of the insulating layer 3 includes to In some embodiments, the depth of etching the upper surface of the insulating layer 3 may be At this time, the depths of the plurality of second sub grooves 24 and the plurality of first sub grooves 25 are
  • the conductive method can be an ion implantation method.
  • the ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method or a solid diffusion implantation method.
  • the conductive method can also adopt ion bombardment to hydrogenate or deoxidize the oxide semiconductor material in the conductive region.
  • this embodiment mode may further include a step of forming the gate insulating layer 5, the gate 6, the source 7 and the drain 8 of the thin film transistor on the substrate 1.
  • this embodiment mode may further include a step of forming the gate insulating layer 5, the gate 6, the source 7 and the drain 8 of the thin film transistor on the substrate 1.
  • the conductor of the thin film transistor in this embodiment since the positions of the source contact region 22 and the drain contact region 23 close to the channel region 21 have a wave structure, compared with the thin film transistor in the prior art, the conductor of the thin film transistor in this embodiment The transmission path of the diffusion effect is longer, and the conductive effect has less influence on the channel region 21, so the characteristics and uniformity of the prepared thin film transistor are good.
  • the wave structure part of the active layer 2 the atomic arrangement of the material of the active layer 2 is distorted and chaotic, so the diffusion of the conductive effect to the channel region 21 can be well blocked, so that the characteristics and uniformity of the thin film transistor good.
  • a plurality of second sub-grooves 24 may be formed close to at least one of the source contact region 22 and the drain contact region 23 (FIG. Not shown in).
  • the embodiment of the present disclosure also provides a display substrate, which includes a substrate 1 and a thin film transistor disposed on the substrate 1.
  • the thin film transistor in this embodiment may be any thin film transistor provided in the above embodiments.
  • the display substrate in this embodiment includes the thin film transistor in the above embodiment, the channel region 21 of the active layer 2 of the thin film transistor in this embodiment is less conductive, and the characteristics of the thin film transistor are good, and the display substrate The display effect is better.
  • An embodiment of the present disclosure also provides a display device, including the display substrate provided in the above embodiment.
  • the display device in this embodiment may be any product or component with a display function, such as liquid crystal panels, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.
  • a display function such as liquid crystal panels, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.
  • the display panel of this embodiment includes the display substrate provided in the above-mentioned embodiment, compared to the display panel in the prior art, the display panel of this embodiment has a good display effect.

Abstract

一种薄膜晶体管，基底（1），设置在所述基底（1）上的有源层（2），所述有源层（2）包括沟道区（21）和分别位于所述沟道区（21）两侧的源极接触区（22）和漏极接触区（23）；其中，所述源极接触区（22）和所述漏极接触区（23）中的至少一个的靠近所述沟道区（21）的部分包括设置在所述有源层（2）朝向所述基底一侧的多个第一子凹槽（25）和所述有源层远离所述基底一侧的多个第二子凹槽（24），所述多个第一子凹槽（25）和所述多个第二子凹槽（24）沿着平行于所述沟道区（21）的延伸的方向交替布置。

Description

薄膜晶体管及其制备方法、显示基板和显示装置
相关申请的交叉引用
本申请要求于2019年4月9日提交的中国专利申请No.201910281442.0的优先权，在此将其以引用方式整体并入本文。
技术领域
本公开属于显示技术领域，具体涉及一种薄膜晶体管及其制备方法、显示基板和显示装置。
背景技术
在制备薄膜晶体管时，需对有源层的沟道区的两侧的半导体部分进行导体化处理。由于扩散效应，有源层的沟道区也存在被导体化的风险，这样会造成薄膜晶体管的均一性较差，导致显示面板出现亮点等不良现象。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种有效避免有源层的沟道区被导体化的薄膜晶体管。
解决本公开技术问题所采用的技术方案是一种薄膜晶体管，包括基底，设置在所述基底上的有源层，所述有源层包括沟道区和分别位于所述沟道区两侧的源极接触区和漏极接触区；其中，所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的部分包括设置在所述有源层朝向所述基底一侧的多个第一子凹槽和所述有源层远离所述基底一侧的多个第二子凹槽，所述多个第一子凹槽和所述多个第二子凹槽沿着平行于所述沟道区的延伸的方向交替布置。
在一些实施例中，所述多个第一子凹槽和所述多个第二子凹槽深度相同。
在一些实施例中，所述薄膜晶体管还包括绝缘层，所述绝缘层设置于所述有源层与所述基底之间；以及所述绝缘层靠近所述有源层的一侧具有多个第一凹槽，所述多个第一凹槽在所述绝缘层的位置对应于所述有源层的所述源极接触区和所述漏极接触区的至少一个的靠近所述沟道区的位置，所述多个第一凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
在一些实施例中，所述薄膜晶体管还包括遮光层，所述遮光层设置于所述基底与所述绝缘层之间。
在一些实施例中，所述遮光层靠近所述绝缘层的一侧具有多个第二凹槽，所述多个第二凹槽在所述遮光层的位置对应于所述有源层的所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的位置，所述多个第二凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
在一些实施例中，薄膜晶体管还包括依次设置在所述有源层上的栅绝缘层、栅极以及源漏极。
在一些实施例中，所述遮光层的材料包括金属铝、钼或铜。
在一些实施例中，所述多个第二凹槽贯穿所述遮光层。
本公开还提供一种薄膜晶体管的制备方法，包括形成基底，在所述基底上形成有源层；所述有源层包括沟道区和分别位于所述沟道区两侧的源极接触区和漏极接触区；其中，在所述有源层的所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的部分形成所述有源层朝向所述基底一侧的多个第一子凹槽和所述有源层远离所述基底一侧的多个第二子凹槽，所述多个第一子凹槽和所述多个第二子凹槽沿着平行于所述沟道区的延伸的方向交替布置。
在一些实施例中，所述多个第一子凹槽和所述多个第二子凹槽深度相同。
在一些实施例中，在所述基底上形成有源层之前还包括：在所述基底上形成绝缘层，并在所述绝缘层靠近所述有源层的一侧且对应于所述有源层的所述源极接触区和漏极接触区中的至少一 个的靠近所述沟道区的位置上形成多个第一凹槽；以及在形成有所述绝缘层的基底上形成有源层，所述多个第一凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
在一些实施例中，在所述基底上形成绝缘层之前还包括在所述基底上形成遮光层。
在一些实施例中，在所述基底上形成遮光层包括：通过构图工艺在基底上形成遮光层，并在所述遮光层靠近所述绝缘层的一侧且对应于所述有源层的所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的位置上形成多个第二凹槽，所述多个第二凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
在一些实施例中，在所述有源层上形成栅绝缘层，以及，在所述栅绝缘层上形成栅极以及源漏极。
在一些实施例中，所述薄膜晶体管为顶栅型薄膜晶体管。
在一些实施例中，所述遮光层的材料包括金属铝、钼或铜。
在一些实施例中，所述多个第二凹槽贯穿所述遮光层。
本公开还提供一种显示基板，包括基底，以及设置在所述基底上的薄膜晶体管；所述薄膜晶体管包括上述任意一种薄膜晶体管。
本公开公开还提供一种显示装置，包括上述任意一种显示基板。
附图说明
图1为本公开的一些实施例的薄膜晶体管的结构示意图；
图2为本公开的一些实施例的薄膜晶体管的制备方法中形成遮光层的示意图；
图3为本公开的一些实施例的薄膜晶体管的制备方法中形成绝缘层的示意图；
图4为本公开的一些实施例的薄膜晶体管的制备方法中形成有源层的示意图；
图5为本公开的一些实施例的薄膜晶体管的制备方法中形成栅绝缘层、栅极、源极、漏极的结构示意图；
图6为本公开的另一些实施例的薄膜晶体管的制备方法中形成遮光层的示意图；
图7为本公开的另一些实施例的薄膜晶体管的制备方法中形成有源层的示意图；
图8为本公开的另一些实施例的薄膜晶体管的制备方法中形成栅绝缘层、栅极、源极、漏极的结构示意图；
图9为本公开的一些实施例的薄膜晶体管的制备方法的流程图；
图10为本公开的另一些实施例的薄膜晶体管的制备方法的流程图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
根据本公开的一些实施例，如图1所示，本实施例提供一种薄膜晶体管，包括基底1，依次设置在基底1上的有源层2、栅绝缘层5、栅极6以及源漏极，其中，源漏极包括源极7和漏级8。有源层2包括沟道区21和分别位于沟道区21两侧的源极接触区22、漏极接触区23；有源层2的源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的部分包括设置在所述有源层2朝向所述基底一侧的多个第一子凹槽25和所述有源层远离所述基底一侧的多个第二子凹槽24，所述多个第一子凹槽25和所述多个第二子凹槽24沿着平行于所述沟道区21的延伸的方向交替布置。
应当注意的是，所述多个第一子凹槽24和所述多个第二子凹槽25深度相同。
可以理解的是，有源层2的源极接触区22和漏极接触区23为半导体结构，且源极接触区22与源极7电连接，漏极接触区23与漏极8电连接。
如图1所示，在本实施例中，通过将有源层2的源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的部分设置为波浪结构，变相延长有源层2的长度，特别是源极接触区22和漏极接触区23的靠近沟道区21的部分的长度，降低了有源层2的厚度，从而在对有源层2的源极接触区22和漏极接触区23进行导体化时，有效延长导体化扩散效应的传输路径，尽量避免对沟道区21造成影响，进而保证薄膜晶体管的良好特性及均一性。同时，在形状为波浪结构的有源层2中，有源层2材料的原子排列扭曲混乱，从而能够很好地阻挡到导体化效应向沟道区21的扩散，保证薄膜晶体管的良好特性及均一性。
在一些实施例中，薄膜晶体管为顶栅型薄膜晶体管。为了对本实施例中的薄膜晶体管进行更为清楚、具体的说明，下面以顶栅型薄膜晶体管为例进行说明。
在一些实施例中，顶栅型薄膜晶体管还包括绝缘层3，其设置于有源层2靠近基底1的一侧；在绝缘层3靠近有源层2的一侧，且对应薄膜晶体管的源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的位置上具有多个第一凹槽31，多个第一凹槽31限定出有源层2的波浪结构，多个第一凹槽31与多个第二子凹槽21一一对应并且在基底上的正投影重叠。
也即，如图1所示，绝缘层3与有源层2接触，绝缘层3上表面(背离基底1的一面)中的第一凹槽限定出有源层2的波浪结构。具体的，在制备薄膜晶体管时，可在基底1上先制备绝缘层3，并在绝缘层3背离基底1的一面中对应源极接触区22和漏极接触区23靠近沟道区21的位置通过刻蚀形成第一凹槽31。之后在形成有绝缘层3的基底1上形成有源层2，利用第一凹槽的段差，使有源层2在对应第一凹槽31的位置(也即源极接触区22和漏极接触区23靠近沟道区21的位置)自然形成波浪结构，多个第一凹槽31与多个第二子凹槽24一一对应并且在基底上的正投影重叠。
需要说明的是，所述多个第二子凹槽24与多个第一子凹槽 25是由于通过对绝缘层3的上表面进行刻蚀后而形成的褶皱结构进行而限定出的。绝缘层3的厚度包括
Figure PCTCN2020083683-appb-000001
至
Figure PCTCN2020083683-appb-000002
在一些实施例中，对绝缘层3上表面进行刻蚀的深度可以为
Figure PCTCN2020083683-appb-000003
此时，多个第二子凹槽24与所述多个第一子凹槽25的深度为
Figure PCTCN2020083683-appb-000004
所述绝缘层的材料为氧化硅、氮化硅或者二者的复合材料。
在一些实施例中，顶栅型薄膜晶体管还可包括遮光层4，所述遮光层4设置于基底1与绝缘层3之间，此时绝缘层3设置于遮光层4与有源层2之间。如图1所示，遮光层4设置于有源层2靠近基底1的一侧，用于遮挡外界光线，以避免有源层2受到光线的影响而破坏薄膜晶体管的特性。其中，遮光层4的材料可包括金属，需要选择反光好的金属，常规为Al、Mo、Cu。为了避免遮光层4的导电性质将有源层2的源极接触区22和漏极接触区23导通，故应利用绝缘层3将遮光层4与有源层2隔开。
在一些实施例中，遮光层4靠近绝缘层3的一面，对应源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的位置具有多个第二凹槽41，多个第二凹槽41限定出多个第一凹槽31，进而限定出所述波浪结构，多个第二凹槽41与多个第二子凹槽24一一对应并且在基底上的正投影重叠。也即，在薄膜晶体管的制备过程中，可在基底1上形成遮光层4时，在遮光层4的上表面(背离基底1的一面)中对应源极接触区22和漏极接触区23靠近沟道区21的位置形成多个第二凹槽41，之后形成绝缘层3，绝缘层3在对应第二凹槽41的位置自然会形成第一凹槽31，从而使后续形成的有源层2的源极接触区22和漏极接触区23靠近沟道区21的位置为波浪结构，多个第二凹槽41与多个第二子凹槽24一一对应并且在基底上的正投影重叠。通过在形成遮光层4的同时在遮光层4中刻蚀形成第二凹槽41，无需增加额外的工艺步骤，从而可以简化薄膜晶体管的制备工艺，降低生产成本。
需要说明的是，由于通过对遮光层4的上表面进行刻蚀后而形成褶皱结构，该褶皱结构导致在遮光层4上设置绝缘层3后，绝缘层3的上表面也会存在同样的褶皱结构，进而限定出所述多 个第二子凹槽24与多个第一子凹槽25。遮光层4的厚度包括
Figure PCTCN2020083683-appb-000005
至
Figure PCTCN2020083683-appb-000006
当遮光层4的厚度为
Figure PCTCN2020083683-appb-000007
时，对遮光层4的上表面进行刻蚀的深度可以小于等于
Figure PCTCN2020083683-appb-000008
在一些实施例中，第二凹槽可贯穿遮光层4(附图未示出)，此时，对遮光层4的上表面进行刻蚀的深度等于遮光层4的厚度。其中，可以理解的是，由于第二凹槽设置在对应有源层2的源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的位置，故即使第二凹槽41贯穿遮光层4，也基本不会影响有源层2的沟道区21的遮光作用，不会对薄膜晶体管的特性造成太大影响。
另一点需要说明的是，当在形成遮光层4时，可以不对其上表面(背离基底1的一面)刻蚀形成多个第二凹槽41，也就是说，遮光层4的上表面是平整的。而通过在遮光层4上设置的绝缘层3的上表面刻蚀形成多个第一凹槽31的方式来限定出波浪结构，多个第一凹槽31与多个第二子凹槽24一一对应并且在基底上的正投影重叠。
本公开还提供一种薄膜晶体管的制备方法，如图2至5所示，本实施例提供的一种薄膜晶体管的制备方法，可用于制备实施例1中提供的薄膜晶体管。
其中，薄膜晶体管为顶栅型薄膜晶体管，以下以制备顶栅型薄膜晶体管为例对本实施例的制备方法进行具体说明。
本实施例提供的制备方法可包括以下两种实施方式：
本实施例提供的第一种制备方法参见附图2至图4，包括如下步骤S11至S13：
S11、形成基底1，通过构图工艺在基底1上形成遮光层4，并在遮光层4的上表面对应源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的位置形成多个第二凹槽41。
其中，遮光层4的材料可包括金属等不透光材料，例如Al、Mo、Cu。
具体的，在本步骤中，如图2所示，在遮光层4上形成光刻胶，之后通过曝光、显影、刻蚀工艺在基底1上形成具有多个第 二凹槽41的遮光层4的图形。
S12、在形成有遮光层4的基底1上形成绝缘层3，并在所述绝缘层3的上表面对应于所述有源层4的所述源极接触区22和漏极接触区23中的至少一个的靠近所述沟道区21的位置上形成多个第一凹槽31。
如图3所示，可直接在形成有遮光层4的基底1上形成一整层绝缘层3材料，利用遮光层4中的第二凹槽41，使绝缘层3在对应第二凹槽41位置处自然下陷，也即在对应源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的位置形成第一凹槽31。
S13、在形成有所述绝缘层3的基底1上形成有源层2。
需要说明的是，所述波浪结构指设置在所述有源层2朝向所述基底一侧的多个第一子凹槽25和所述有源层远离所述基底一侧的多个第二子凹槽24，所述多个第一子凹槽25和所述多个第二子凹槽24沿着平行于所述沟道区21的延伸的方向交替布置。应当注意的是，所述多个第一子凹槽24和所述多个第二子凹槽25深度相同。
具体的，如图4所示，本步骤中，直接在形成有所述绝缘层3的基底1上形成有源层2的材料。其中，由于绝缘层3具有多个第一凹槽31，故在形成有源层2材料时，有源层2材料自然会在源极接触区22和漏极接触区23的靠近沟道区21的位置下陷，形成波浪结构，多个第一凹槽41与多个第二子凹槽24一一对应并且在基底上的正投影重叠。
由于通过对遮光层4的上表面进行刻蚀后而形成褶皱结构，该褶皱结构导致在遮光层4上形成绝缘层3后，绝缘层3的上表面也会存在同样的褶皱结构，进而形成所述多个第二子凹槽24与多个第一子凹槽25。遮光层4的厚度包括
Figure PCTCN2020083683-appb-000009
至
Figure PCTCN2020083683-appb-000010
当遮光层4的厚度为
Figure PCTCN2020083683-appb-000011
时，对遮光层4的上表面进行刻蚀的深度可以小于等于
Figure PCTCN2020083683-appb-000012
可以理解的是，在本步骤中，在形成有所述绝缘层3的基底 1上形成有源层2的材料后，还包括对有源层2的源极接触区22和漏极接触区23进行导体化的步骤。导体化的方式可采用离子注入法，离子注入法包括具有质量分析仪的离子注入方式、不具有质量分析仪的离子云式注入方式、等离子注入方式或固态扩散式注入方式。导体化的方式也可采用离子轰击的方式，将导体化区域的氧化物半导体材料氢化或去氧化。
在一些实施例中，如图5所示，本实施例方式中还可包括在基底1上形成薄膜晶体管的栅绝缘层5、栅极6、源极7和漏极8结构的步骤，在此不再赘述。
本实施例提供的第二种制备方法参见附图6至图8，包括如下步骤S21至S23：
第二种制备方法与第一种制备方法相似，不同之处在于，第二种制备方法中无需在遮光层4上形成多个第二凹槽41，直接在绝缘层3上形成多个第一凹槽31。具体的，该实施方式包括以下步骤：
S21、形成基底1，并在基底1上形成遮光层4。
如图6所示，先在基底1上形成遮光层4，遮光层4用于遮挡外界光线，以避免有源层2受到光线的影响而破坏薄膜晶体管的特性。其中，遮光层4的材料可包括金属，需要选择反光好的金属，常规为Al、Mo、Cu。
应当注意的是，遮光层4上表面为平整的表面，无需在通过构图工艺形成遮光层4的图案的同时形成多个第二凹槽41。
S22、在形成有遮光层4的基底1上形成绝缘层3，并通过构图工艺在绝缘层3的上表面对应有源层2的源极接触区22和漏极接触区23中的至少一个的靠近沟道区21的位置形成多个第一凹槽31。
需要说明的是，可以在涂覆绝缘层3的材料时，注入常用的遮光剂以使得所述绝缘层3变得不透光，以起到遮光作用，避免光照对有源层2的影响。此时，由于绝缘层3可同时实现绝缘功能以及遮光功能，可以不用另外设置遮光层4(附图未示出)。
S23、在形成有绝缘层3的基底1上形成有源层2。
需要说明的是，所述波浪结构指设置在所述有源层2朝向所述基底一侧的多个第一子凹槽25和所述有源层远离所述基底一侧的多个第二子凹槽24，所述多个第一子凹槽25和所述多个第二子凹槽24沿着平行于所述沟道区21的延伸的方向交替布置。应当注意的是，所述多个第一子凹槽24和所述多个第二子凹槽25深度相同。
具体的，本步骤中，如图7所示，可直接在形成有绝缘层3的基底1上形成有源层2材料。其中，由于绝缘层3具有多个第一凹槽31，故在形成有源层2材料时，有源层2材料自然会在源极接触区22和漏极接触区23的靠近沟道区21的位置下陷，形成波浪结构，多个第一凹槽31与多个第二子凹槽24一一对应并且在基底上的正投影重叠。
由于所述多个第二子凹槽24与多个第一子凹槽25是通过对绝缘层3的上表面进行刻蚀后而形成的褶皱结构进而形成的。绝缘层3的厚度包括
Figure PCTCN2020083683-appb-000013
至
Figure PCTCN2020083683-appb-000014
在一些实施例中，对绝缘层3上表面进行刻蚀的深度可以为
Figure PCTCN2020083683-appb-000015
此时，多个第二子凹槽24与所述多个第一子凹槽25的深度为
Figure PCTCN2020083683-appb-000016
可以理解的是，在本步骤中，在形成有绝缘层3的基底1上形成有源层2材料后，还包括对源极接触区22和漏极接触区23进行导体化的步骤。导体化的方式可采用离子注入法，离子注入法包括具有质量分析仪的离子注入方式、不具有质量分析仪的离子云式注入方式、等离子注入方式或固态扩散式注入方式。导体化的方式也可采用离子轰击的方式，将导体化区域的氧化物半导体材料氢化或去氧化。
在一些实施例中，如图8所示，本实施例方式中还可包括在基底1上形成薄膜晶体管的栅绝缘层5、栅极6、源极7和漏极8结构的步骤，在此不再赘述。
本实施例中，由于源极接触区22和漏极接触区23的靠近沟道区21的位置为波浪结构，故相较于现有技术中的薄膜晶体管， 本实施例中的薄膜晶体管的导体化扩散效应的传输路径更长，导体化效应对沟道区21的影响较小，故而所制备的薄膜晶体管的特性及均一性良好。同时，在有源层2的波浪结构部分，有源层2材料的原子排列扭曲混乱，故也能够很好地阻挡到导体化效应向沟道区21的扩散，使得薄膜晶体管的特性及均一性良好。
在一些实施例中，也可直接在通过构图工艺形成有源层2时，在靠近源极接触区22和漏极接触区23中的至少一个的位置形成多个第二子凹槽24(图中未示出)。
本公开的实施例还提供一种显示基板，包括：基底1，以及设置在基底1上的薄膜晶体管。本实施例中的薄膜晶体管可以为上述实施例中提供的任意一种薄膜晶体管。
由于本实施例中的显示基板包括上述实施例中的薄膜晶体管，故本实施例中的薄膜晶体管的有源层2的沟道区21的导体化程度较低，薄膜晶体管的特性良好，显示基板的显示效果较好。
本公开的实施例还提供一种显示装置，包括上述实施例提供的显示基板。
具体的，本实施例中的显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于本实施例的显示面板包括上述实施例中提供的显示基板，故相对现有技术中的显示面板，本实施例的显示面板的显示效果良好。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种薄膜晶体管，包括：
    基底，
    设置在所述基底上的有源层，所述有源层包括沟道区和分别位于所述沟道区两侧的源极接触区和漏极接触区；其中，
    所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的部分包括设置在所述有源层朝向所述基底一侧的多个第一子凹槽和所述有源层远离所述基底一侧的多个第二子凹槽，所述多个第一子凹槽和所述多个第二子凹槽沿着平行于所述沟道区的延伸的方向交替布置。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述多个第一子凹槽和所述多个第二子凹槽深度相同。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，所述薄膜晶体管还包括绝缘层，所述绝缘层设置于所述有源层与所述基底之间；以及
    所述绝缘层靠近所述有源层的一侧具有多个第一凹槽，所述多个第一凹槽在所述绝缘层的位置对应于所述有源层的所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的位置，所述多个第一凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述薄膜晶体管还包括遮光层，所述遮光层设置于所述基底与所述绝缘层之间。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述遮光层靠近所述绝缘层的一侧具有多个第二凹槽，所述多个第二凹槽在所述遮光层的位置对应于所述有源层的所述源极接触区和所述漏极 接触区中的至少一个的靠近所述沟道区的位置，所述多个第二凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
  6. 根据权利要求1所述的薄膜晶体管，其中，还包括依次设置在所述有源层上的栅绝缘层、栅极以及源漏极。
  7. 根据权利要求4所述的薄膜晶体管，其中，所述遮光层的材料包括金属铝、钼或铜。
  8. 根据权利要求5所述的薄膜晶体管，其中，所述多个第二凹槽贯穿所述遮光层。
  9. 一种薄膜晶体管的制备方法，包括：
    形成基底，在所述基底上形成有源层；所述有源层包括沟道区和分别位于所述沟道区两侧的源极接触区和漏极接触区；其中，
    在所述有源层的所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的部分形成所述有源层朝向所述基底一侧的多个第一子凹槽和所述有源层远离所述基底一侧的多个第二子凹槽，所述多个第一子凹槽和所述多个第二子凹槽沿着平行于所述沟道区的延伸的方向交替布置。
  10. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述多个第一子凹槽和所述多个第二子凹槽深度相同。
  11. 根据权利要求9或10所述的薄膜晶体管的制备方法，其中，在所述基底上形成有源层之前还包括：
    在所述基底上形成绝缘层，并在所述绝缘层靠近所述有源层的一侧且对应于所述有源层的所述源极接触区和漏极接触区中的至少一个的靠近所述沟道区的位置上形成多个第一凹槽；以及
    在形成有所述绝缘层的基底上形成有源层，所述多个第一凹 槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
  12. 根据权利要求11所述的薄膜晶体管的制备方法，其中，在所述基底上形成绝缘层之前还包括在所述基底上形成遮光层。
  13. 根据权利要求12所述的薄膜晶体管的制备方法，其中，在所述基底上形成遮光层包括：
    通过构图工艺在基底上形成遮光层，并在所述遮光层靠近所述绝缘层的一侧且对应于所述有源层的所述源极接触区和所述漏极接触区中的至少一个的靠近所述沟道区的位置上形成多个第二凹槽，所述多个第二凹槽与所述多个第二子凹槽一一对应并且在基底上的正投影重叠。
  14. 根据权利要求9所述的薄膜晶体管的制备方法，其中，还包括：在所述有源层上形成栅绝缘层，以及，在所述栅绝缘层上形成栅极以及源漏极。
  15. 根据权利要求12所述的薄膜晶体管的制备方法，其中，所述遮光层的材料包括金属铝、钼或铜。
  16. 根据权利要求13所述的薄膜晶体管的制备方法，其中，所述多个第二凹槽贯穿所述遮光层。
  17. 一种显示基板，包括：
    基底，以及
    设置在所述基底上的薄膜晶体管；其中，
    所述薄膜晶体管包括权利要求1至8中任意一项所述的薄膜晶体管。
  18. 一种显示装置，其中，包括权利要求17所述的显示基板。
PCT/CN2020/083683 2019-04-09 2020-04-08 薄膜晶体管及其制备方法、显示基板和显示装置 WO2020207400A1 (zh)

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