CN106024909B - 薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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CN106024909B
CN106024909B CN201610599762.7A CN201610599762A CN106024909B CN 106024909 B CN106024909 B CN 106024909B CN 201610599762 A CN201610599762 A CN 201610599762A CN 106024909 B CN106024909 B CN 106024909B
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strip
shaped
thin film
film transistor
substrate
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CN106024909A (zh
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安晖
徐德智
段献学
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US15/567,060 priority patent/US10566461B2/en
Priority to PCT/CN2017/076276 priority patent/WO2018018893A1/zh
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Abstract

本发明提供了一种薄膜晶体管及其制备方法、阵列基板和显示装置，本发明的制备方法在形成薄膜晶体管的各层结构之前，利用构图工艺在衬底上形成条状凸出部，而后在条状凸出部上依次形成栅极、栅极绝缘层、有源层、源漏极，即可制备出沟道在宽度方向上与条状凸出部形状对应的薄膜晶体管。薄膜晶体管的沟道在宽度方向具有与条状凸出部对应的凹凸结构，可以在薄膜晶体管投影面积不变的情况下，增加宽长比，增加薄膜晶体管的导通电流，减小功耗；在保持相同宽长比的情况下，能够减小沟道长度，进而提高显示装置的开口率。

Description

薄膜晶体管及其制备方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板和显示装置。
背景技术
薄膜晶体管是液晶显示面板的重要元件，薄膜晶体管栅极对沟道的控制能力与薄膜晶体管的功耗密切相关，为了提高栅极对沟道的控制能力，降低功耗。晶体管开关的沟道宽长比越大，其驱动能力越强。一般通过增大沟道宽度的方式来提高沟道的宽长比，这种方式虽然提高了沟道的宽长比，提高了栅极对沟道的控制能力，却增加了薄膜晶体管的尺寸及投影面积，降低了开口率，进而影响了显示效果。
发明内容
(一)要解决的技术问题
为了解决现有技术存在的问题，本发明提供了一种薄膜晶体管及其制备方法、阵列基板和显示装置制备。
(二)技术方案
根据本发明的一个方面，提供了一种薄膜晶体管的制备方法，包括：在衬底上形成沿第一方向间隔排列的多个条状凸出部，所述条状凸出部沿第二方向延伸；依次形成覆盖所述多个条状凸出部的栅极、栅极绝缘层、有源层及源漏极，其中，源漏极之间的有源层对应所述条状凸出部的区域形成有条状凸起，多个所述条状凸起在所述源漏极之间沿所述第一方向间隔排列，且沿所述第二方向延伸；所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极垂直。
根据本发明的另一个方面，提供了一种薄膜晶体管，包括：沿第一方向间隔排列的多个条状凸出部，形成于衬底上，所述条状凸出部沿第二方向延伸；栅极、栅极绝缘层、有源层及源漏极，依次覆盖所述条状凸出部；源漏极之间的有源层对应所述条状凸出部的区域形成有条状凸起，多个所述条状凸起在所述源漏极之间沿所述第一方向间隔排列，且沿所述第二方向延伸；所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极垂直。
根据本发明的又一个方面，提供了一种阵列基板，包括上述薄膜晶体管。
根据本发明的再一个方面，提供了一种显示装置，包括上述阵列基板。
(三)有益效果
从上述技术方案可以看出，本发明的薄膜晶体管及其制备方法、阵列基板和显示装置制备至少具有以下有益效果之一：
(1)薄膜晶体管的沟道在宽度方向具有与条状凸出部对应的凹凸形状，可以在薄膜晶体管投影面积不变的情况下，增加宽长比，增加薄膜晶体管的导通电流，减小功耗；在保持相同宽长比的情况下，能够减小沟道长度，进而提高显示装置的开口率；
(2)在形成薄膜晶体管的各层结构之前，利用构图工艺在衬底上形成条状凸出部，在条状凸出部上依次形成栅极、栅极绝缘层、有源层、源漏极，即可制备出沟道在宽度方向上与条状凸出部对应形状的薄膜晶体管，该制备方法无需增加额外的工艺来专门处理栅极、栅极绝缘层、有源层，工艺流程简单，成本低；
(3)形成的栅极绝缘层和有源层具有均匀的厚度，有利于保持栅极对沟道的开关控制能力，提高导通电流和电流均匀性；
(4)利用本发明的制备方法制备ADS型显示装置的薄膜晶体管时，可在形成公共电极的同时同步形成条状凸出部，通过一次沉积和构图工艺即可形成条状凸出部与公共电极，无需针对条状凸出部增加额外工序，未增加构图工艺次数，进一步简化了工艺流程，降低了成本。
附图说明
图1为本发明的一个示例性实施例的薄膜晶体管的制备方法流程图；
图2为本发明的一个示例性实施例的薄膜晶体管的剖面结构图；
图3为本发明的一个示例性实施例的I型沟道薄膜晶体管的俯视图；
图4a为传统的薄膜晶体管的沟道结构示意图；图4b为本发明的一个示例性实施例的薄膜晶体管的沟道结构示意图；
图5为本发明的一个示例性实施例的U型沟道薄膜晶体管的俯视图；
图6为本发明的一个示例性实施例的阵列基板的制备方法流程图；
图7A至图7I为本发明的一个示例性实施例的阵列基板制备方法的工艺流程图；
图7A示出了衬底上沉积透明导电薄膜后的结构；图7B示出了形成图形化的电极和条状凸出部后的结构；图7C示出了形成栅极后的结构，图7D为形成栅极后的三维结构；图7E示出了形成栅极绝缘层后的结构；图7F示出了形成有源层后的结构，图7G为形成有源层后的三维结构；图7H示出了形成源漏极后的结构；图7I示出了形成绝缘层和像素电极后的结构。
【符号说明】
01-图形化的电极；02-条状凸出部；03-栅极；04-栅极绝缘层；05-有源层；06-源极；07-漏极；08-绝缘层；09-像素电极；
10、11-传统薄膜晶体管的栅极绝缘层和有源层。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
本发明的一个实施例提供了一种薄膜晶体管的制备方法，如图1所示，该薄膜晶体管的制备方法包括下述步骤：
步骤S102：在衬底上形成沿第一方向间隔排列的多个条状凸出部，所述条状凸出部沿第二方向延伸；
步骤S104：依次形成覆盖所述多个条状凸出部的栅极、栅极绝缘层、有源层及源漏极；
其中，源漏极之间的有源层对应所述条状凸出部的区域形成有条状凸起，多个所述条状凸起在所述源漏极之间沿所述第一方向间隔排列，且沿所述第二方向延伸；所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极垂直。
其中，在上述步骤S102中，可以利用构图工艺(例如，光刻和刻蚀)在衬底上形成沿第一方向间隔排列的多个条状凸出部，该步骤可以包括：在衬底上沉积一层绝缘材料，对绝缘材料进行构图工艺以形成沿第一方向间隔排列的多个条状凸出部，条状凸出部沿第二方向延伸。通过这种方式形成条状凸出部可适用于例如TN型显示装置的薄膜晶体管的制备。绝缘材料例如是但不限于SiNx、SiOx或SiON。
条状凸出部在第二方向上可以形成整体凸起状，或者条状凸出部在第二方向上可以由若干个分离的凸柱形成断续凸起状。
在上述步骤S104中，依次形成覆盖所述多个条状凸出部的栅极、栅极绝缘层、有源层及源漏极包括：
首先沉积一层金属材料，通过构图工艺形成图形化的覆盖条状凸出部的栅极，使得条状凸出部在衬底平面上的投影位于栅极在衬底平面上的投影的范围内。金属材料例如是但不限于Cu、MoAlMo或Mo。
接着沉积一层绝缘材料，通过构图工艺在栅极上形成图形化的栅极绝缘层，绝缘材料例如是但不限于SiNx、SiOx或SiON。
再沉积一层半导体材料，通过构图工艺在栅极绝缘层上形成图形化的有源层。半导体材料可以是但不限于a-Si、IGZO或p-Si。
最后在有源层背离栅极绝缘层的表面的沿第二方向的两端形成源漏极，有源层在源漏极之间的部分形成薄膜晶体管的沟道，沟道的长度方向为条状凸出部延伸的方向，即第二方向，沟道的宽度方向为垂直于沟道长度方向且平行于衬底平面的方向，即第一方向。
通过上述制备方法制备出的薄膜晶体管，薄膜晶体管的沟道在宽度方向上并非平面结构，而是具有与条状凸出部对应的凹凸形状，与常规的薄膜晶体管相比，可以在薄膜晶体管在衬底平面的投影面积不变的情况下，增加沟道宽度，由此，能够有效地增加薄膜晶体管的宽长比，增加薄膜晶体管的导通电流，减小功耗；而在保持与常规薄膜晶体管相同的宽长比的情况下，由于本实施例的薄膜晶体管的沟道的有效宽度增加，因此能够减小沟道长度，从而减小薄膜晶体管在衬底平面的投影面积，进而能够提高显示装置的开口率。
由此可见，本实施例的薄膜晶体管的制备方法，在形成薄膜晶体管的各层结构之前，利用构图工艺在衬底上形成条状凸出部，在条状凸出部上利用构图工艺依次形成栅极、栅极绝缘层、有源层以及源漏极，即可制备出沟道在宽度方向上与条状凸出部对应形状的薄膜晶体管，该制备方法无需增加额外的工艺来专门处理栅极、栅极绝缘层、有源层，工艺流程简单，成本低。
可以看出，形成覆盖条状凸出部的栅极，则栅极会形成与条状凸出部对应的凹凸结构，凹凸结构的凸部分别对应条状凸出部，凹凸结构的凹部分别对应条状凸出部之间的凹部部分；在栅极上形成栅极绝缘层，则栅极绝缘层也会形成与条状凸出部对应的凹凸结构，凹凸结构的凸部分别对应条状凸出部，凹凸结构的凹部分别对应条状凸出部之间的凹部部分，使得栅极绝缘层具有均匀的厚度，因此有利于保持栅极对沟道的开关控制能力；同样，形成于栅极绝缘层上的有源层也会形成与条状凸出部对应的凹凸结构，凹凸结构的凸部分别对应条状凸出部，凹凸结构的凹部分别对应条状凸出部之间的凹部部分，使得有源层具有均匀的厚度，因此有利于提高导通电流和电流均匀性。
根据本实施例的薄膜晶体管制备方法的另一方面，上述步骤S102还通过以下优选方式实现：在衬底上沉积一层透明导电薄膜，对透明导电薄膜进行构图工艺，以形成图形化的电极和沿第一方向间隔排列的多个条状凸出部。
其中，图形化的电极作为ADS型显示装置的公共电极，由此可见，通过本实施例的方法制备ADS型显示装置的薄膜晶体管时，在形成公共电极的同时同步形成条状凸出部，通过一次沉积和构图工艺即可形成条状凸出部与公共电极，因此，无需针对条状凸出部增加额外工序，未增加构图工艺次数，就能制备出沟道在宽度方向上具有与条状凸出部对应形状的薄膜晶体管，进一步简化了工艺流程，降低了成本。其中，上述构图工艺采用光刻和刻蚀等工艺，透明导电薄膜的材料可以是ITO等。
本发明的另一个实施例提供了一种薄膜晶体管，如图2所示，包括：沿第一方向间隔排列的多个条状凸出部02，形成于衬底上，条状凸出部沿第二方向延伸；栅极03、栅极绝缘层04、有源层05以及源漏极06、07，依次覆盖条状凸出部02。其中，源漏极之间的有源层对应所述条状凸出部的区域形成有条状凸起，多个所述条状凸起在所述源漏极之间沿所述第一方向间隔排列，且沿所述第二方向延伸；所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极垂直。
在本实施例中，薄膜晶体管的源极和漏极可以互换，即06代表漏极，07代表源极。
在本实施例中，如图3所示，条状凸出部02在衬底上相互平行，源极06和漏极07位于有源层背离栅极绝缘层的表面的沿条状凸出部02延伸方向的两端，沟道的长度方向即为条状凸出部02延伸的方向(即第二方向，如图3中的y轴方向)，沟道的宽度方向为垂直于沟道长度方向且平行于衬底平面的方向(即第一方向，如图3中的x轴方向)。条状凸出部在沟道长度方向上可以是整体凸起状；或者，条状凸出部在沟道长度方向上可以是由若干个分离的凸柱形成的断续凸起状。条状凸出部02在衬底平面上的投影位于栅极03在衬底平面上的投影的范围内；条状凸出部02的沿垂直于其延伸方向的剖面形状可以为梯形、矩形、三角形、半圆形或半椭圆形等。
图4a为传统的薄膜晶体管的沟道结构示意图，图4b为本实施例的薄膜晶体管的沟道结构示意图。传统薄膜晶体管的栅极绝缘层10和有源层11均为平面结构，其沟道在宽度方向(如图中4a的x轴方向)为平面形状，本实施例的薄膜晶体管的沟道在宽度方向(如图4b中的x轴方向)上并非平面结构，而是具有与条状凸出部对应的凹凸形状，因此，本发明可以在薄膜晶体管在衬底平面的投影面积不变的情况下，增加沟道宽度，由此，能够有效地增加薄膜晶体管的宽长比，增加薄膜晶体管的导通电流，减小功耗；而在保持与常规薄膜晶体管相同的宽长比的情况下，由于本实施例的薄膜晶体管的沟道的有效宽度增加，因此能够减小沟道长度，从而减小薄膜晶体管在衬底平面的投影面积，进而能够提高显示装置的开口率。
进一步地，本实施例的薄膜晶体管，栅极绝缘层的朝向衬底的表面和背离衬底的表面均具有与条状凸出部对应的凹凸形状，栅极绝缘层具有均匀的厚度，有利于保持栅极对沟道的开关控制能力；同样，有源层朝向衬底的表面和背离衬底的表面均具有与条状凸出部对应的凹凸结构，有源层具有均匀的厚度，有利于提高导通电流和电流均匀性。
可以理解，上述薄膜晶体管的制备方法和薄膜晶体管均是针对I型沟道薄膜晶体管，但本发明不限于此，其同样适用于其他形状沟道的薄膜晶体管，例如L型沟道薄膜晶体管和U型沟道薄膜晶体管。如图5所示，对于U型沟道薄膜晶体管，条状凸出部02并非在衬底上相互平行，而是相互之间间隔一定角度、整体呈扇形排列。有源层在源极06和漏极07之间的部分形成U型沟道，沟道的长度方向即为各个条状凸出部延伸的方向，沟道的宽度方向沿U型线延伸，该U型线垂直于沟道长度方向且位于平行于衬底的平面，本发明同样可以使U型沟道在宽度方向上形成与条状凸出部02对应的形状，从而增加沟道的有效宽度。
本发明的又一个实施例提供了一种阵列基板的制备方法，下面结合图6、图7A至图7I介绍其具体步骤：
步骤S602：首先在衬底上沉积一层透明导电薄膜，透明导电薄膜的材料可以是ITO等材料，如图7A所示；
步骤S604：对透明导电薄膜进行构图工艺以形成图形化的电极01和沿第一方向间隔排列的条状凸出部02，条状凸出部沿第二方向延伸；图形化的电极01作为ADS型显示装置的公共电极，上述构图工艺采用光刻和刻蚀等工艺，如图7B所示；
步骤S606：依次形成覆盖多个条状凸出部的栅极、栅极绝缘层、有源层及源漏极；其中，源漏极之间的有源层对应条状凸出部的区域形成有条状凸起，多个条状凸起在源漏极之间沿第一方向间隔排列，且沿第二方向延伸；第一方向与第二方向垂直，且第二方向与源漏极垂直。
在步骤S606中，如图7C所示，首先沉积一层金属材料，通过构图工艺形成图形化的覆盖条状凸出部02的栅极03，使得条状凸出部02在衬底平面上的投影位于栅极03在衬底平面上的投影的范围内。金属材料例如是但不限于Cu、MoAlMo或Mo。图7D为形成栅极03后的三维结构图。
如图7E所示，接着沉积一层绝缘材料，通过构图工艺在栅极03上形成图形化的栅极绝缘层04，绝缘材料例如是但不限于SiNx、SiOx或SiON。
如图7F所示，再沉积一层半导体材料，通过构图工艺在栅极绝缘层04上形成图形化的有源层05。半导体材料可以是但不限于a-Si、IGZO或p-Si。图7G为形成有源层05后的三维结构图。
如图7H所示，最后在有源层05上形成源极06和漏极07，有源层05在源极06和漏极07之间的部分形成薄膜晶体管的沟道。
在有源层背离栅极绝缘层的表面的沿第二方向的两端形成源漏极，有源层在源漏极之间的部分形成薄膜晶体管的沟道，沟道的长度方向为条状凸出部延伸的方向(即第二方向，如图中的y轴方向)，沟道的宽度方向为垂直于沟道长度方向且平行于衬底平面的方向(即第一方向，如图中的x轴方向)。
步骤S608：如图7I所示，在源极06、漏极07和有源层05对应的沟道区域上形成绝缘层08，并在绝缘层08的与漏极07对应的部分开设过孔，并在过孔内形成像素电极09。
由此可见，通过本实施例的方法制备ADS型显示装置的阵列基板时，与上述薄膜晶体管的制备方法类似，条状凸出部和公共电极同步形成，无需针对条状凸出部增加额外的工序，未增加构图工艺次数，制备出的阵列基板的薄膜晶体管沟道在宽度方向上具有与条状凸出部对应凹凸形状，工艺流程简单，成本低。
本发明的再一个实施例提供了一种上述制备方法制备的阵列基板，如图7I所示，该阵列基板包括：衬底；形成于衬底上的图形化的电极01和沿第一方向间隔排列的多个条状凸出部02，条状凸出部沿第二方向延伸，图形化的电极01作为ADS型显示装置的公共电极，其与条状凸出部02位于阵列基板的同一层且材料相同；薄膜晶体管，其栅极03、栅极绝缘层04、有源层05以及源漏极06、07依次覆盖条状凸出部02；其中，源漏极之间的有源层对应条状凸出部的区域形成有条状凸起，多个条状凸起在源漏极之间沿第一方向间隔排列，且沿第二方向延伸；所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极垂直；形成于源极、漏极和有源层上的绝缘层08，绝缘层的与漏极对应的部分具有过孔；形成于过孔内的像素电极09。
其中，条状凸出部在沟道长度方向上可以是整体凸起状；或者，条状凸出部在沟道长度方向上可以是由若干个分离的凸柱形成的断续凸起状。
在本实施例阵列基板的薄膜晶体管沟道在宽度方向上呈与条状凸出部对应的凹凸形状，可以在薄膜晶体管在衬底平面的投影面积不变的情况下，增加沟道宽度，能够有效地增加薄膜晶体管的宽长比，增加薄膜晶体管的导通电流，减小功耗；而在保持与常规薄膜晶体管相同的宽长比的情况下，由于薄膜晶体管的沟道的有效宽度增加，因此能够减小沟道长度，从而减小薄膜晶体管在衬底平面的投影面积，进而能够提高显示装置的开口率。
进一步地，本实施例阵列基板的薄膜晶体管，栅极绝缘层的朝向衬底的表面和背离衬底的表面均具有与条状凸出部对应的凹凸形状，栅极绝缘层具有均匀的厚度，有利于保持栅极对沟道的开关控制能力；同样，有源层朝向衬底的表面和背离衬底的表面均具有与条状凸出部对应的凹凸结构，有源层具有均匀的厚度，有利于提高导通电流和电流均匀性。
本发明的再一个实施例提供了一种显示装置，包括上述阵列基板。该显示装置可以包括TFT-LCD显示装置，如液晶电视、手机、电子书、平板电脑等。
至此，已经结合附图对本实施例进行了详细描述。依据以上描述，本领域技术人员应当对本发明的薄膜晶体管及其制备方法、阵列基板和显示装置有了清楚的认识。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本发明的保护范围；上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种薄膜晶体管的制备方法，其特征在于，包括：
在衬底上形成沿第一方向间隔排列的多个条状凸出部，所述条状凸出部沿第二方向延伸；
依次形成覆盖所述多个条状凸出部的栅极、栅极绝缘层、有源层及源漏极，其中，
源漏极之间的有源层具备与所述多个条状凸出部对齐的多个第一条状凸起，且所述源漏极的与所述多个第一条状凸起对齐的部分也具备多个第二条状凸起，多个所述第一条状凸起在所述源漏极之间沿所述第一方向间隔排列，且沿所述第二方向延伸；
所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极延伸的方向垂直；
其中，所述条状凸出部沿垂直于其延伸方向的剖面的形状为矩形、三角形、半圆形或半椭圆形；
其中，所述薄膜晶体管为U型沟道薄膜晶体管；
其中，所述条状凸出部并非在衬底上相互平行，而是相互之间间隔一定角度、整体呈扇形排列；和
其中，所述条状凸出部在沟道长度方向上由若干个分离的凸柱形成断续凸起状。
2.如权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述在衬底上形成沿第一方向间隔排列的多个条状凸出部包括：
在衬底上沉积绝缘材料层；
对所述绝缘材料层进行构图工艺，以形成所述沿第一方向间隔排列的多个条状凸出部。
3.如权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述在衬底上形成沿第一方向间隔排列的多个条状凸出部包括：
在衬底上沉积透明导电薄膜；
对所述透明导电薄膜进行构图工艺，以形成公共电极和所述沿第一方向间隔排列的多个条状凸出部。
4.如权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述栅极、所述栅极绝缘层和所述有源层中的任意一个都形成有凹凸结构，所述凹凸结构的凸部分别对应条状凸出部，所述凹凸结构的凹部分别对应条状凸出部之间的凹部部分。
5.一种薄膜晶体管，其特征在于，包括：
沿第一方向间隔排列的多个条状凸出部，形成于衬底上，所述条状凸出部沿第二方向延伸；
栅极、栅极绝缘层、有源层及源漏极，依次覆盖所述条状凸出部；
源漏极之间的有源层具备与所述多个条状凸出部对齐的多个第一条状凸起，且所述源漏极的与所述多个第一条状凸起对齐的部分也具备多个第二条状凸起，多个所述第一条状凸起在所述源漏极之间沿所述第一方向间隔排列，且沿所述第二方向延伸；
所述第一方向与所述第二方向垂直，且所述第二方向与所述源漏极延伸的方向垂直；
其中，所述条状凸出部沿垂直于其延伸方向的剖面的形状为矩形、三角形、半圆形或半椭圆形；
其中，所述薄膜晶体管为U型沟道薄膜晶体管；
其中，所述条状凸出部并非在衬底上相互平行，而是相互之间间隔一定角度、整体呈扇形排列；和
其中，所述条状凸出部在沟道长度方向上由若干个分离的凸柱形成断续凸起状。
6.如权利要求5所述的薄膜晶体管，其特征在于，所述有源层的朝向衬底的表面和背离衬底的表面均具有与条状凸出部对应的凹凸形状，所述有源层具有均匀的厚度。
7.如权利要求6所述的薄膜晶体管，其特征在于，所述栅极绝缘层在朝向衬底的表面和背离衬底的表面上均具有与条状凸出部对应的凹凸形状，所述栅极绝缘层具有均匀的厚度。
8.一种阵列基板，其特征在于，包括权利要求5-7任一项所述的薄膜晶体管。
9.一种显示装置，其特征在于，包括权利要求8所述的阵列基板。
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