CN107170829A - 一种薄膜晶体管及其制作方法、阵列基板和显示面板 - Google Patents

一种薄膜晶体管及其制作方法、阵列基板和显示面板 Download PDF

Info

Publication number
CN107170829A
CN107170829A CN201710338853.XA CN201710338853A CN107170829A CN 107170829 A CN107170829 A CN 107170829A CN 201710338853 A CN201710338853 A CN 201710338853A CN 107170829 A CN107170829 A CN 107170829A
Authority
CN
China
Prior art keywords
layer
film transistor
thin film
tft
light shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710338853.XA
Other languages
English (en)
Inventor
王铖铖
李贺飞
宫奎
董必良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201710338853.XA priority Critical patent/CN107170829A/zh
Publication of CN107170829A publication Critical patent/CN107170829A/zh
Priority to PCT/CN2018/086513 priority patent/WO2018210186A1/zh
Priority to US16/326,775 priority patent/US20190207037A1/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请提供一种薄膜晶体管及其制作方法、阵列基板和显示面板,以有效降低薄膜晶体管的漏电流,避免由于薄膜晶体管漏电流较大而导致显示器容易发生串扰和闪屏的问题。所述薄膜晶体管,包括:设置在衬底基板之上的遮光层;设置在所述遮光层之上的有源层;其中,所述遮光层在面向所述有源层的一面设置有凹槽,所述凹槽的底面在所述衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。

Description

一种薄膜晶体管及其制作方法、阵列基板和显示面板
技术领域
本申请涉及半导体技术领域,尤其涉及一种薄膜晶体管及其制作方法、阵列基板和显示面板。
背景技术
平面显示器(F1at Pane1Disp1ay,FPD)己成为市场上的主流产品,平面显示器的种类也越来越多,如液晶显示器(Liquid Crysta1Disp1ay,LCD)、有机发光二极管(OrganicLight Emitted Diode,OLED)显示器、等离子体显示面板(P1asma Disp1ay Pane1,PDP)及场发射显示器(Field Emission Display,FED)等。
而作为FPD产业核心技术的薄膜晶体管(Thin Film Transistor,TFT)背板技术,也在经历着深刻的变革。串扰和闪屏不良一直是伴随平面显示器的顽固不良,其中一个主要的原因是薄膜晶体管关态时漏电流太大。漏电流的机制主要是沟道的空穴电流和光照产生的漏电流。图1为现有技术的一种薄膜晶体管,包括:设置在衬底基板11之上的栅极12,设置在栅极12之上的栅极绝缘层13,设置在栅极绝缘层13之上的有源层14,设置在有源层14上的源极15和漏极16,即,为了防止薄膜晶体管在背光源照射下光漏过大,常设计成薄膜晶体管的有源层14被栅极12遮挡的底栅结构,来避免光漏电流。但是这种设计不能完全的遮挡全部光线,背光源的光线在经过反射和折射都会影响到有源层,增加光照时电子空穴对的产生概率,产生光照漏电流。即,现有技术的薄膜晶体管并不能有效地降低漏电流,仍然存在漏电流较大,进而导致形成的显示器容易产生串扰和闪屏的问题。
发明内容
本申请提供一种薄膜晶体管及其制作方法、阵列基板和显示面板,以有效降低薄膜晶体管的漏电流,避免由于薄膜晶体管漏电流较大而导致显示器容易发生串扰和闪屏的问题。
本申请实施例提供一种薄膜晶体管,包括:
设置在衬底基板之上的遮光层;
设置在所述遮光层之上的有源层;
其中,所述遮光层在面向所述有源层的一面设置有凹槽,所述凹槽的底面在所述衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。
优选的,所述遮光层为栅极,所述薄膜晶体管还包括:
设置在所述遮光层与所述有源层之间的栅极绝缘层;
设置在所述有源层之上的源极和漏极。
优选的,所述薄膜晶体管还包括:
设置在所述遮光层与所述有源层之间的钝化层;
设置在所述有源层之上的栅极绝缘层;
设置在所述栅极绝缘层之上的栅极;
设置在所述栅极之上的层间绝缘层;
设置在所述层间绝缘层之上的源极和漏极,其中,所述源极通过第一过孔与所述有源层连接,所述漏极通过第二过孔与所述有源层连接。
优选的,所述凹槽的开口深度为1000埃~10000埃。
优选的,所述凹槽的侧壁与所述凹槽的底部之间的夹角大于或等于90°。
本申请实施例还提供一种阵列基板,包括本申请实施例提供的所述的薄膜晶体管。
本申请实施例还提供一种显示面板,包括背光源,所述显示面板还包括本申请实施例提供的所述阵列基板,所述阵列基板设置在所述背光源的出光侧。
本申请实施例还提供一种薄膜晶体管的制作方法,所述制作方法包括:
在衬底基板之上形成包括有凹槽的遮光层;
在所述遮光层之上形成有源层,其中,所述凹槽的底面在衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。
优选的,所述在衬底基板之上形成包括有凹槽的遮光层,具体包括:
在衬底基板之上形成第一薄膜层;
通过半色调掩模板,在所述第一薄膜层之上形成具有不同厚度区域的光刻胶层的图案,其中,所述光刻胶层的图案包括第一区域和第二区域,所述光刻胶层在所述第二区域的厚度小于在所述第一区域的厚度,所述凹槽的所述底面在所述衬底基板的正投影与所述第二区域在所述衬底基板的正投影重叠;
去除未被图案化的所述光刻胶层遮挡的所述第一薄膜层;
去除所述第二区域的所述光刻胶;
对与所述第二区域对应的所述第一薄膜层刻蚀预设时长;
去除剩余的所述光刻胶层。
优选的,所述对与所述第二区域对应的所述第一薄膜层刻蚀预设时长,具体包括:对与所述第二区域对应的所述第一薄膜层刻蚀预设时长,以使与所述第二区域对应的所述第一薄膜层的厚度减半。
本申请实施例有益效果如下:本申请实施例通过在薄膜晶体管的遮光层面向有源层的一面设置凹槽,并使凹槽的底面在衬底基板上的正投影覆盖有源层在衬底基板上的正投影,进而可以使遮光层起到类似遮罩的效果,避免背光源产生的光线经反射或折射后照射到有源层,从而可以将光照产生的漏电流降到最低,极大的提高薄膜晶体管的特性,进而避免显示面板由于薄膜晶体管的漏电流过大而产生的串扰和闪屏的不良,提高显示品质。
附图说明
图1为现有技术的薄膜晶体管的结构示意图;
图2为本申请实施例提供的一种底栅型薄膜晶体管的结构示意图;
图3为本申请实施例提供的一种顶栅型薄膜晶体管的结构示意图;
图4为本申请实施例提供的一种凹槽的顶部面积大于底部面积的底栅型薄膜晶体管的结构示意图;
图5为本申请实施例提供的一种底栅型薄膜晶体管的制作流程意图;
图6为本申请实施例中,制作完成光刻胶层并进行光照时的示意图;
图7为本申请实施例中,形成图案化的光刻胶层后的底栅型薄膜晶体管的结构示意图;
图8为本申请实施例中,去除第二区域的光刻胶层后的底栅型薄膜晶体管的结构示意图;
图9为本申请实施例中,去除与第二区域对应的栅极金属薄膜层后的底栅型薄膜晶体管的结构示意图;
图10为本申请实施例中,将与第二区域对应的栅极金属薄膜的厚度减半后的底栅型薄膜晶体管的结构示意图;
图11为本申请实施例中,去除剩余光刻胶层后的底栅型薄膜晶体管的结构示意图;
图12为本申请实施例中,形成栅极后的底栅型薄膜晶体管的结构示意图;
图13为本申请实施例提供的一种阵列基板的结构示意图。
具体实施方式
下面结合说明书附图对本申请实施例的实现过程进行详细说明。需要注意的是,自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本申请,而不能理解为对本申请的限制。
参见图2,本申请实施例提供一种薄膜晶体管,包括:
设置在衬底基板21之上的遮光层22;
设置在遮光层22之上的有源层24;
其中,遮光层22在面向有源层24的一面设置有凹槽20,凹槽20的底面在衬底基板21的正投影覆盖有源层24在衬底基板21的正投影。
本申请实施例通过在遮光层面向有源层的一面设置凹槽20,并使凹槽20的底面在衬底基板21上的正投影覆盖有源层24在衬底基板21上的正投影,进而可以使遮光层22起到类似遮罩的效果,避免背光源产生的光线经反射或折射后照射到有源层24,从而可以将光照产生的漏电流降到最低,极大的提高薄膜晶体管的特性,进而避免显示面板由于薄膜晶体管的漏电流过大而产生的串扰和闪屏的不良,提高显示品质。
在具体实施时,对于本申请实施例提供的薄膜晶体管可以为底栅型薄膜晶体管,也可以为顶栅型薄膜晶体管。对于底栅型的薄膜晶体管,本申请实施例中的遮光层可以为如深色树脂的遮光或者吸光材料,或者可直接由栅极制作而成,即在栅极的面向有源层的一侧设置凹槽。而对于顶栅型的薄膜晶体管,其遮光层可能为异于栅极的独立膜层,进而,可以在遮光层的面向有源层的一侧设置凹槽来有效遮挡背光源光的照射。以下通过具体实施例对两种结构的薄膜晶体管进行举例说明。
例如,薄膜晶体管为底栅型薄膜晶体管,遮光层为栅极,参见图2所示,薄膜晶体管具体还包括:
设置在遮光层22与有源层24之间的栅极绝缘层23;
设置在有源层24之上的源极25和漏极26。
需要说明的是,将栅极作为遮光层时,需要栅极本身为遮光材料,例如,栅极的材质具体可以是Mo/Al、Mo/Nd或Al/Nd。
又例如,薄膜晶体管为顶栅型薄膜晶体管,参见图3所示,薄膜晶体管具体还包括:
设置在遮光层22与有源层24之间的钝化层210;
设置在有源层24之上的栅极绝缘层23;
设置在栅极绝缘层23之上的栅极29;
设置在栅极29之上的层间绝缘层213;
设置在层间绝缘层213之上的源极25和漏极26,其中,源极25通过第一过孔211与有源层24连接,漏极26通过第二过孔212与有源层24连接。
对于顶栅型薄膜晶体管,其具体的遮光层的材质可以与现有技术的顶栅型薄膜晶体管的遮光层的材质相同,例如,遮光层可以为与黑色树脂。
优选的,考虑到为了使凹槽能够有效地遮挡背光源的光,凹槽的开口深度为1000埃~10000埃。如果遮光层为金属,具体的,可以为1700埃。如果遮挡层为黑矩阵材质的,凹槽的开口深度可以为5000埃~7500埃。
优选的,凹槽的侧壁与凹槽的底部之间的夹角大于或等于90°。具体的,例如,具体凹槽20的开口在垂直于衬底基板的面方向上的截面图形可以为矩形或倒梯形,如图2和图4所示。
本申请实施例还提供一种阵列基板,包括本申请实施例提供的的薄膜晶体管。
本申请实施例还提供一种显示面板,包括背光源,液晶显示面板还包括本申请实施例提供的阵列基板,阵列基板设置在背光源的出光侧。
参见图5所示,本申请实施例还提供一种薄膜晶体管的制作方法,制作方法包括:
步骤101、在衬底基板之上形成包括有凹槽的遮光层;
步骤102、在遮光层之上形成有源层,其中,凹槽的底面在衬底基板的正投影覆盖有源层在衬底基板的正投影。
优选的,关于步骤101、在衬底基板之上形成包括有凹槽的遮光层,具体包括:
在衬底基板之上形成第一薄膜层;
通过半色调掩模板,在第一薄膜层之上形成具有不同厚度区域的光刻胶层的图案,其中,光刻胶层的图案包括第一区域和第二区域,光刻胶层在第二区域的厚度小于在第一区域的厚度,凹槽的底面在衬底基板的正投影与第二区域在衬底基板的正投影重叠;
去除未被图案化的光刻胶层遮挡的第一薄膜层;
去除第二区域的光刻胶;
对与第二区域对应的第一薄膜层刻蚀预设时长;
去除剩余的光刻胶层。
优选的,为了简化工艺制作,通过半掩模工艺形成凹槽,对与第二区域对应的第一薄膜层刻蚀预设时长,具体包括:对与第二区域对应的第一薄膜层刻蚀预设时长,以使与第二区域对应的第一薄膜层的厚度减半。
为了更详细的对本申请提供的薄膜晶体管的制作方法进行说明,以薄膜晶体管为底栅型薄膜晶体管,遮光层为栅极,结合附图6至附图12举例如下:
步骤一、在衬底基板21上采用磁控溅射方法沉积栅极金属薄膜220,并涂覆一层光刻胶层4,光刻胶可以为正性光刻胶。具体的衬底基板可以为玻璃基板,参见图6所示。
步骤二、采用特殊的半灰度掩模板进行曝光、显影。掩膜板5上AB区、EF区为全透光区,BC区、DE区为不透光区,CD区为半透光区,参见图6所示。通过显影之后,对应掩膜板曝光区域的光刻胶被去除,半曝光区域的光刻胶被部分保留下来,未曝光区域的光刻胶被保留下来,形成在第二区域42的厚度小于第一区域41的厚度的图案化的光刻胶层4,参见图7所示。
步骤三、采用湿法刻蚀工艺,将未被光刻胶覆盖的栅极金属薄膜220刻蚀去除,半曝光区域和未曝光区域的栅极金属薄膜220被保留下来,形成前期的遮光层22,参见图8所示。
步骤四、采用干法刻蚀工艺将第二区域42的光刻胶层4去除,参见图9所示。
步骤五、采用干法或湿法刻蚀工艺,控制刻蚀时间将第二区域对应的前期的遮光层22厚度减半,参见图10所示。
步骤六、采用剥离工艺将剩余的光刻胶层4除去,得到最后的遮光层22图案,参见图11所示。
步骤七、采用气体沉积法得到栅极绝缘层23层及有源层24,对有源层24进行曝光,控制有源层24等于或者小于凹槽的底面,参见图12所示。
步骤八、进行源极和漏极构图,参见图2。
步骤九、后面还可以进行绝缘保护层27和像素电极28的构图,得到最终的阵列基板,如图13所示。
本申请实施例有益效果如下:本申请实施例通过在遮光层面向有源层的一面设置凹槽,并使凹槽的内底面在衬底基板上的正投影覆盖有源层在衬底基板上的正投影,进而可以使遮光层起到类似遮罩的效果,避免背光源产生的光线反射或折射到有源层,从而将光照产生的漏电流降到最低,极大的提高TFT器件的特性,进而避免显示面板由于薄膜晶体管的漏电流过大而产生的串扰和闪屏的不良,提高显示品质。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。

Claims (10)

1.一种薄膜晶体管,其特征在于,包括:
设置在衬底基板之上的遮光层;
设置在所述遮光层之上的有源层;
其中,所述遮光层在面向所述有源层的一面设置有凹槽,所述凹槽的底面在所述衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。
2.如权利要求1所述的薄膜晶体管,其特征在于,所述遮光层为栅极,所述薄膜晶体管还包括:
设置在所述遮光层与所述有源层之间的栅极绝缘层;
设置在所述有源层之上的源极和漏极。
3.如权利要求1所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括:
设置在所述遮光层与所述有源层之间的钝化层;
设置在所述有源层之上的栅极绝缘层;
设置在所述栅极绝缘层之上的栅极;
设置在所述栅极之上的层间绝缘层;
设置在所述层间绝缘层之上的源极和漏极,其中,所述源极通过第一过孔与所述有源层连接,所述漏极通过第二过孔与所述有源层连接。
4.如权利要求2或3所述的薄膜晶体管,其特征在于,所述凹槽的开口深度为1000埃~10000埃。
5.如权利要求1所述的薄膜晶体管,其特征在于,所述凹槽的侧壁与所述凹槽的底部之间的夹角大于或等于90°。
6.一种阵列基板,其特征在于,包括如权利要求1-5任一项所述的薄膜晶体管。
7.一种显示面板,包括背光源,其特征在于,所述显示面板还包括如权利要求6所述的阵列基板,所述阵列基板设置在所述背光源的出光侧。
8.一种薄膜晶体管的制作方法,其特征在于,所述制作方法包括:
在衬底基板之上形成包括有凹槽的遮光层;
在所述遮光层之上形成有源层,其中,所述凹槽的底面在衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。
9.如权利要求8所述的制作方法,其特征在于,所述在衬底基板之上形成包括有凹槽的遮光层,具体包括:
在衬底基板之上形成第一薄膜层;
通过半色调掩模板,在所述第一薄膜层之上形成具有不同厚度区域的光刻胶层的图案,其中,所述光刻胶层的图案包括第一区域和第二区域,所述光刻胶层在所述第二区域的厚度小于在所述第一区域的厚度,所述凹槽的所述底面在所述衬底基板的正投影与所述第二区域在所述衬底基板的正投影重叠;
去除未被图案化的所述光刻胶层遮挡的所述第一薄膜层;
去除所述第二区域的所述光刻胶;
对与所述第二区域对应的所述第一薄膜层刻蚀预设时长;
去除剩余的所述光刻胶层。
10.如权利要求9所述的制作方法,其特征在于,所述对与所述第二区域对应的所述第一薄膜层刻蚀预设时长,具体包括:对与所述第二区域对应的所述第一薄膜层刻蚀预设时长,以使与所述第二区域对应的所述第一薄膜层的厚度减半。
CN201710338853.XA 2017-05-15 2017-05-15 一种薄膜晶体管及其制作方法、阵列基板和显示面板 Pending CN107170829A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710338853.XA CN107170829A (zh) 2017-05-15 2017-05-15 一种薄膜晶体管及其制作方法、阵列基板和显示面板
PCT/CN2018/086513 WO2018210186A1 (zh) 2017-05-15 2018-05-11 薄膜晶体管及其制作方法、阵列基板和显示面板
US16/326,775 US20190207037A1 (en) 2017-05-15 2018-05-11 Thin film transistor, manufacturing method thereof, array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710338853.XA CN107170829A (zh) 2017-05-15 2017-05-15 一种薄膜晶体管及其制作方法、阵列基板和显示面板

Publications (1)

Publication Number Publication Date
CN107170829A true CN107170829A (zh) 2017-09-15

Family

ID=59816079

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710338853.XA Pending CN107170829A (zh) 2017-05-15 2017-05-15 一种薄膜晶体管及其制作方法、阵列基板和显示面板

Country Status (3)

Country Link
US (1) US20190207037A1 (zh)
CN (1) CN107170829A (zh)
WO (1) WO2018210186A1 (zh)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018210186A1 (zh) * 2017-05-15 2018-11-22 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示面板
CN109037243A (zh) * 2018-08-01 2018-12-18 京东方科技集团股份有限公司 用于显示装置的基板及其制作方法、显示装置
CN109449181A (zh) * 2018-10-29 2019-03-08 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN110187547A (zh) * 2019-05-30 2019-08-30 厦门天马微电子有限公司 一种显示面板、显示装置及车载显示系统
CN110770911A (zh) * 2018-04-02 2020-02-07 京东方科技集团股份有限公司 阵列基板及其制造方法、显示设备、及减少电阻压降和显示设备中的数据损耗的方法
CN110911424A (zh) * 2019-12-11 2020-03-24 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN111208687A (zh) * 2020-01-13 2020-05-29 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
WO2020142881A1 (zh) * 2019-01-07 2020-07-16 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置
CN111627391A (zh) * 2020-04-17 2020-09-04 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路、显示面板及显示装置
CN111739841A (zh) * 2020-05-08 2020-10-02 福建华佳彩有限公司 一种顶栅结构的In-cell触控面板及制作方法
CN112928125A (zh) * 2021-01-22 2021-06-08 武汉华星光电技术有限公司 阵列基板及显示面板
CN113921577A (zh) * 2021-09-30 2022-01-11 惠科股份有限公司 阵列基板、阵列基板的制作方法和显示面板
WO2022266887A1 (zh) * 2021-06-23 2022-12-29 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
WO2023070789A1 (zh) * 2021-11-01 2023-05-04 武汉华星光电技术有限公司 阵列基板和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164875A (ja) * 1998-11-26 2000-06-16 Nec Corp 液晶表示装置用薄膜トランジスタ基板およびその製造方法
JP2012069842A (ja) * 2010-09-27 2012-04-05 Hitachi Displays Ltd 表示装置
CN103809320A (zh) * 2012-11-12 2014-05-21 乐金显示有限公司 液晶显示设备的阵列基板以及制造该阵列基板的方法
CN108695394A (zh) * 2017-04-06 2018-10-23 京东方科技集团股份有限公司 薄膜晶体管、其制备方法、阵列基板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7342622B2 (en) * 2001-10-22 2008-03-11 Samsung Electronics Co., Ltd. Liquid crystal display for enhancing reflection and method of manufacturing the same
US7211825B2 (en) * 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
CN103149760B (zh) * 2013-02-19 2015-03-11 合肥京东方光电科技有限公司 薄膜晶体管阵列基板、制造方法及显示装置
CN105867006B (zh) * 2016-03-10 2019-08-06 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置
CN106024909B (zh) * 2016-07-27 2021-01-26 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN106409920B (zh) * 2016-09-30 2018-03-06 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法、显示装置
CN107170829A (zh) * 2017-05-15 2017-09-15 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164875A (ja) * 1998-11-26 2000-06-16 Nec Corp 液晶表示装置用薄膜トランジスタ基板およびその製造方法
JP2012069842A (ja) * 2010-09-27 2012-04-05 Hitachi Displays Ltd 表示装置
CN103809320A (zh) * 2012-11-12 2014-05-21 乐金显示有限公司 液晶显示设备的阵列基板以及制造该阵列基板的方法
CN108695394A (zh) * 2017-04-06 2018-10-23 京东方科技集团股份有限公司 薄膜晶体管、其制备方法、阵列基板及显示装置

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018210186A1 (zh) * 2017-05-15 2018-11-22 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示面板
CN110770911A (zh) * 2018-04-02 2020-02-07 京东方科技集团股份有限公司 阵列基板及其制造方法、显示设备、及减少电阻压降和显示设备中的数据损耗的方法
CN109037243A (zh) * 2018-08-01 2018-12-18 京东方科技集团股份有限公司 用于显示装置的基板及其制作方法、显示装置
CN109037243B (zh) * 2018-08-01 2022-01-11 京东方科技集团股份有限公司 用于显示装置的基板及其制作方法、显示装置
CN109449181A (zh) * 2018-10-29 2019-03-08 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN111670503A (zh) * 2019-01-07 2020-09-15 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置
US11222904B2 (en) 2019-01-07 2022-01-11 Chongqing Boe Optoelectronics Technology Co., Ltd. Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device
WO2020142881A1 (zh) * 2019-01-07 2020-07-16 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置
CN110187547A (zh) * 2019-05-30 2019-08-30 厦门天马微电子有限公司 一种显示面板、显示装置及车载显示系统
CN110187547B (zh) * 2019-05-30 2024-01-30 厦门天马微电子有限公司 一种显示面板、显示装置及车载显示系统
CN110911424A (zh) * 2019-12-11 2020-03-24 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN110911424B (zh) * 2019-12-11 2022-08-09 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN111208687A (zh) * 2020-01-13 2020-05-29 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN111627391A (zh) * 2020-04-17 2020-09-04 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路、显示面板及显示装置
CN111627391B (zh) * 2020-04-17 2021-12-03 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路、显示面板及显示装置
CN111739841A (zh) * 2020-05-08 2020-10-02 福建华佳彩有限公司 一种顶栅结构的In-cell触控面板及制作方法
CN111739841B (zh) * 2020-05-08 2023-10-03 福建华佳彩有限公司 一种顶栅结构的In-cell触控面板及制作方法
CN112928125A (zh) * 2021-01-22 2021-06-08 武汉华星光电技术有限公司 阵列基板及显示面板
WO2022266887A1 (zh) * 2021-06-23 2022-12-29 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113921577A (zh) * 2021-09-30 2022-01-11 惠科股份有限公司 阵列基板、阵列基板的制作方法和显示面板
WO2023070789A1 (zh) * 2021-11-01 2023-05-04 武汉华星光电技术有限公司 阵列基板和显示面板

Also Published As

Publication number Publication date
US20190207037A1 (en) 2019-07-04
WO2018210186A1 (zh) 2018-11-22

Similar Documents

Publication Publication Date Title
CN107170829A (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示面板
KR101322885B1 (ko) 어레이 기판과 액정 디스플레이
CN107086181B (zh) 薄膜晶体管及其制作方法、阵列基板和显示器
CN104752489A (zh) 阵列基板、显示装置及用于制备阵列基板的方法
CN104867959A (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
JP6293905B2 (ja) Tft−lcdアレイ基板の製造方法、液晶パネル、液晶表示装置。
TWI515911B (zh) 薄膜電晶體基板及其製作方法以及顯示器
US20140091291A1 (en) Array substrate and manufacturing method thereof, oled display device
JP2011048400A (ja) 液晶ディスプレー下基板の製造方法
WO2021120378A1 (zh) 一种阵列基板及其制作方法
KR102278989B1 (ko) 포토마스크 구조 및 어레이 기판 제조 방법
CN110176462B (zh) 一种透明oled显示器制作方法及显示器
KR100875801B1 (ko) 액정 디스플레이 장치의 바닥 기판을 제조하는 방법
TWI396916B (zh) 薄膜電晶體陣列基板之製作方法
KR101127574B1 (ko) 액티브 매트릭스 기판의 제조방법 및 유기 발광 표시장치의 제조방법
CN103838047A (zh) 一种阵列基板及其制备方法、显示装置
CN103700626B (zh) 一种阵列基板的制作方法、阵列基板和显示装置
TWI540645B (zh) 畫素結構與其製造方法
CN113488517B (zh) 显示面板的制作方法及光罩
US20180210298A1 (en) Boa liquid crystal panel based on igzo-tft and method for manufacturing the same
KR20070072182A (ko) 액정표시소자 제조방법
US8007987B2 (en) Manufacturing methods of asymmetric bumps and pixel structure
KR101271527B1 (ko) 박막트랜지스터 액정표시장치 및 그 제조방법
CN105870055A (zh) 一种阵列基板的制造方法
TW201641994A (zh) 電連接結構、陣列基板及絕緣覆蓋層的製作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170915

RJ01 Rejection of invention patent application after publication