WO2017206697A1 - 一种阵列基板、显示面板及显示装置 - Google Patents

一种阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2017206697A1
WO2017206697A1 PCT/CN2017/084039 CN2017084039W WO2017206697A1 WO 2017206697 A1 WO2017206697 A1 WO 2017206697A1 CN 2017084039 W CN2017084039 W CN 2017084039W WO 2017206697 A1 WO2017206697 A1 WO 2017206697A1
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Prior art keywords
common electrode
line
array substrate
lines
pixel
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PCT/CN2017/084039
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English (en)
French (fr)
Inventor
先建波
程鸿飞
乔勇
马永达
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京东方科技集团股份有限公司
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Priority to US15/565,775 priority Critical patent/US10481444B2/en
Publication of WO2017206697A1 publication Critical patent/WO2017206697A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • Liquid crystal display technology is widely used in television, mobile phones and public information display, and is currently the most widely used display technology.
  • the liquid crystal molecules located at the edge of the display area are not easily deflected, which affects the display angle and display effect of the liquid crystal display.
  • the embodiments of the present disclosure provide an array substrate, a display panel, and a display device, which can at least solve the problem that liquid crystal molecules at the edge of the display region of the liquid crystal display are not easily deflected.
  • Embodiments of the present disclosure provide an array substrate including a display area and a non-display area located at a periphery of the display area.
  • the array substrate includes: a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines, wherein the data lines and the gate lines define a plurality of pixel units in the display area, and the pixel units include pixel electrodes.
  • At least one of the common electrode lines includes a body and a branch line, the branch line being located on at least one side of the body, and at least a portion of the branch line being located inside an edge of the display area.
  • a part of the branch line is located in a region where a pixel unit is located, and an orthographic projection of the branch line on a plane of the array substrate and a pixel electrode of a corresponding pixel unit are positive on a plane of the array substrate There is an overlap region in the projection.
  • a part of the branch line is located in an area where a plurality of pixel units are located.
  • the opposite sides of the body have the branch line.
  • the gate lines extend in a row direction, and two gate lines corresponding to two adjacent rows of pixel units form a gate line group, and the gate line group is located between corresponding adjacent two rows of pixel units,
  • the common electrode line is located between two adjacent rows of pixel units, and the gate line group and the common electrode line are spaced apart, and a row of pixel units is disposed between the adjacent gate line group and the common electrode line;
  • the branch line includes Said a first branch line on one side of the body and a second branch line on the opposite side of the body, the first branch line and the second branch line being parallel or on the same straight line.
  • the body is parallel to the gate line and has the same layer structure.
  • the branch line is parallel to the data line.
  • the length of the branch line is 3/5 to 8/9 of the length of the corresponding pixel unit.
  • a part of the branch line is located between the adjacent first pixel unit and the second pixel unit, and an orthographic projection of the branch line on a plane of the array substrate and a pixel electrode of the first pixel unit An overlap region exists between the orthographic projections of the pixel electrodes of the second pixel unit and the plane of the array substrate.
  • the plurality of common electrode lines include a first common electrode line and a second common electrode line on an opposite side of the first common electrode line, and the width of the first common electrode line and the second common electrode line
  • the width of the first common electrode line is larger than the width of the other common electrode lines; the first common electrode line is located on a side of the display area close to the region where the source driving chip is located.
  • the common electrode line includes a first common electrode line and a second common electrode line, wherein a width of the first common electrode line is greater than a width of the second common electrode line, the first common electrode line and the second The common electrode line spacing is set.
  • the common electrode lines are symmetrically distributed on a central axis of the array substrate.
  • the common electrode line is at least partially electrically connected within the display area.
  • two adjacent common electrode lines are electrically connected in the display area.
  • the present disclosure also provides a display panel including the array substrate provided by any one of the embodiments of the present disclosure.
  • the present disclosure also provides a display device including the display panel provided by any one of the embodiments of the present disclosure.
  • the present disclosure also provides an array substrate including a display area and a non-display area located at a periphery of the display area, the array substrate including a plurality of data lines extending in a column direction; a plurality of gate lines extending in a row direction, and Multiple common electrode lines.
  • the data line and the gate line define a plurality of pixel units in the display area, and the pixel unit includes a pixel electrode.
  • At least one of the common electrode lines includes a body extending in a row direction and a branch line extending in a column direction, the branch line being located At least one side of the body is located inside the edge of the display area; a portion of the branch line is located in an area where the at least one pixel unit is located, and an orthographic projection of the branch line on a plane of the array substrate and a pixel electrode of the corresponding pixel unit There is an overlap region in the orthographic projection on the plane of the array substrate.
  • Two gate lines corresponding to two adjacent rows of pixel units form a gate line group, the gate line group is located between corresponding adjacent two rows of pixel units, and the common electrode line is located between adjacent two rows of pixel units.
  • the gate line group and the common electrode line are spaced apart, and a row of pixel units is disposed between adjacent gate line groups and common electrode lines.
  • the body, the branch line and the gate line of the common electrode line are disposed in the same layer and the same material.
  • the beneficial effects of the above technical solutions of the present disclosure are as follows.
  • the branch line and the body can generate an electric field from different directions and the pixel electrode. Therefore, liquid crystal molecules which are difficult to deflect inside the edge of the display region can be deflected to enlarge the display angle.
  • FIG. 1 is a schematic diagram of a circuit arrangement of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the arrangement of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing the arrangement of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram showing the arrangement of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of the area division of the array substrate of the present disclosure.
  • FIG. 6 is a schematic diagram of a circuit arrangement of an array substrate according to an embodiment of the present disclosure.
  • the present disclosure first provides an array substrate including a display area and a non-display area located at the periphery of the display area.
  • the array substrate includes: a plurality of gate lines and a plurality of data lines and a plurality of common electrode lines.
  • the data lines and gate lines define a plurality of pixel cells within the display area.
  • the pixel unit includes a pixel electrode 101.
  • the common electrode line 102 includes a body 1021 and a branch line 1022, the branch line 1022 being located on one side of the body 1021, and at least a portion of the branch line 1022 being located inside the edge of the display area.
  • FIG. 1 In order to better illustrate the position of the common electrode line on the array substrate, only some of the components are shown in FIG. 1, and other related components and their positional relationship can be seen in FIG.
  • the branch line and the body can generate an electric field from different directions and the pixel electrode, so that the liquid crystal molecules that are difficult to deflect can be deflected to a certain extent, the display angle is improved, and the viewing angle range is expanded.
  • the common electrode line includes at least a branch line located inside the edge of the display area.
  • the array substrate area distribution is as shown in FIG. 5, and the area defined by the dotted line on the array substrate 501 represents the display area 502, and the area other than the display area 502 on the array substrate is the non-display area 503.
  • the inner side of the edge of the display area is the inner edge of the area within the dotted line in FIG. 5, that is, the edge of the edge line of the display area 502 away from the side of the array substrate 501.
  • a portion of the branch line is located in a region where a pixel unit is located, and an orthographic projection of the branch line on a plane of the array substrate and a pixel electrode of a corresponding pixel unit are located at the array substrate There is an overlapping area of the orthographic projection on the plane.
  • a portion of the branch lines are located in an area where the plurality of pixel units are located.
  • one side of the body has the branch line, or the opposite sides of the body have the branch line.
  • the gate lines 201 extend in a row direction, and two gate lines 201 corresponding to two adjacent rows of pixel units form a gate line group 202 , and the gate line group 202 is located between corresponding two rows of pixel units, and the common electrode line 203 is located between two adjacent rows of pixel units, that is, between adjacent two rows of pixel electrodes 206 shown in FIG. 2;
  • the gate line group 202 and the common electrode line 203 are spaced apart, and the adjacent gate line group 202 and the common electrode line 203 are spaced apart. There is a row of pixel units between them.
  • the branch line includes a first leg line 204 on one side of the body and a second leg line 205 on the opposite side of the body.
  • the first leg line 204 and the second leg line 205 are parallel or on the same straight line.
  • Figure 6 shows the case where the two are on the same straight line.
  • the first leg and the second leg are parallel to the data line.
  • the first branch line and the second branch line partially overlap with the pixel electrode, that is, the orthographic projection of the first branch line and the second branch line on the plane of the array substrate and the pixel electrode of the corresponding pixel unit on the plane of the array substrate
  • the orthographic projection has overlapping regions.
  • the branch line may have various shapes such as a long strip shape and a bent shape.
  • the body is parallel to the gate line and is of the same layer structure.
  • the legs are parallel to the data lines.
  • the body is strip-shaped, and the branch line is integrally formed with the body.
  • the length of the branch line is 3/5 to 8/9 of the length of the corresponding pixel unit in the extending direction of the data line, and thus, the shading effect can be performed as much as possible.
  • the length of the pixel unit refers to the length of the pixel unit in the extending direction of the data line.
  • a portion of the branch line is located between adjacent first pixel units and second pixel units, and an orthographic projection of the branch line on a plane of the array substrate and the first pixel There are overlapping regions in the orthographic projection of the pixel electrode of the unit and the pixel electrode of the second pixel unit on the plane of the array substrate.
  • the first common electrode line 402 and the second common electrode line 401 on the opposite side of the first common electrode line 402 are larger than the width of the other common electrode lines 403; the first common electrode line 402 is located on a side of the display area close to the source driving chip.
  • the source driver chip is located at a lower position in the figure of the first common electrode line 402 in FIG. This can increase the signal input of the common electrode line in the pixel region, reduce the delay of the common electrode line signal, and improve the deflection of the liquid crystal molecules at the edge of the pixel region.
  • the common electrode line includes a plurality of first common electrode lines 301 and a plurality of second common electrode lines 302, wherein a width of the first common electrode lines 301
  • the first common electrode line 301 and the second common electrode line 302 are spaced apart from each other by a width larger than the width of the second common electrode line 302. This design can reduce the signal difference between the common electrode lines.
  • the common electrode line is at least partially electrically connected within the display area.
  • two adjacent common electrode lines are electrically connected in the display area, which can reduce the signal difference between the common electrode lines.
  • the electrical connection here may be a connection method of a common electrode line well known in the art, and details are not described herein again.
  • the common electrode lines are symmetrically distributed along a central axis of the array substrate.
  • the gate insulating layer of the array substrate may be a single layer structure or a multilayer structure.
  • the gate insulating layer may include a silicon nitride layer or a silicon oxide layer.
  • the gate lines and the data lines of the array substrate may be prepared by using a metal material such as Cu, Al, Mo, Ti, Cr, W, or may be prepared by using an alloy of these materials, and the gate line may be a single
  • the layer structure can also adopt a multilayer structure.
  • the gate lines are a multi-layered structure, which in turn includes a Mo layer-aluminum layer-Mo layer, or a Ti layer-Cu layer-Ti layer in this order, or a Mo layer-Ti layer-Cu layer.
  • the array substrate further includes an active layer and a passivation layer; the material of the active layer may be amorphous silicon, or an oxide semiconductor.
  • the passivation layer may be made of an inorganic substance such as silicon nitride or an organic substance such as a resin.
  • the material of the pixel electrode is prepared by using ITO (indium tin oxide), IZO (indium zinc oxide) or other transparent metal oxide conductive material.
  • the fabrication process of the array substrate includes: depositing a metal layer by sputtering, the metal layer may be Al; by coating photoresist, exposure development, etching, Forming a pattern of gate lines, gate electrodes, and common electrode lines; depositing a gate insulating layer by PECVD (Plasma Enhanced Chemical Vapor Deposition), the gate insulating layer may be silicon nitride; depositing a semiconductor layer, Such as PECVD deposition of a-Si (amorphous silicon); or deposition of IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) by the Sputter process; coating photoresist, exposure development, etching, forming an active layer pattern; Sputter sputter deposits a metal layer, which may be Al; a photoresist, an exposure develop, an etch, and a pattern of data lines, source and drain.
  • PECVD Pullasma Enhanced Chemical Vapor Deposition
  • the gate insulating layer may be silicon
  • the fabrication process of the array substrate may further include the steps of forming a passivation layer and a pixel electrode.
  • the present disclosure provides a display panel, including any of the embodiments of the present disclosure.
  • Array substrate The display panel may further include a corresponding color film substrate and a driving circuit such as a source driving chip.
  • the present disclosure provides a display device including a display panel provided by any one of the embodiments of the present disclosure.
  • the display device may further include a power supply circuit, such as a structural component such as a button.
  • the present disclosure further provides an array substrate 600 including a display area 601 and a non-display area 602 located at a periphery of the display area, the array substrate including a plurality of data lines 603 extending in a column direction; A plurality of gate lines 604 extending in the row direction, and a plurality of common electrode lines 605.
  • the data line and the gate line define a plurality of pixel units 610 in the display area, and the pixel unit includes a pixel electrode 611.
  • At least one of the common electrode lines includes a body 6050 extending in a row direction and a branch line 6051, 60511, 60512 extending in a column direction, the branch line being located on at least one side of the body and located inside an edge of the display area; A portion of the branch line is located in an area where the at least one pixel unit is located, and an orthogonal projection of the branch line on a plane of the array substrate and an orthographic projection of a pixel electrode of the corresponding pixel unit on a plane of the array substrate exist.
  • Two gate lines corresponding to two adjacent rows of pixel units constitute a gate line group 6040, the gate line group is located between corresponding adjacent two rows of pixel units, and the common electrode line is located between adjacent two rows of pixel units
  • the gate line group and the common electrode line are spaced apart, and a row of pixel units is disposed between the adjacent gate line group and the common electrode line.
  • the body, the branch line and the gate line of the common electrode line are disposed in the same layer and the same material.
  • the array substrate, the display panel and the display device provided by the present disclosure are provided with a branch line on the common electrode line, and at least a part of the branch line is located at the edge of the display area, which can increase the storage capacitance of the array substrate.
  • the liquid crystal molecules which are difficult to deflect inside the edge of the display region can be deflected to enlarge the display angle.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板（501，600）、显示面板及显示装置。阵列基板（501，600），包括显示区域（502，601）和位于显示区域（502，601）外围的非显示区域（503，602）。阵列基板（501，600）包括：多条栅线（201，604）、多条数据线（603）以及多条公共电极线（102，203，605）。数据线（603）和栅线（201，604）以及公共电极线（102，203，605）在显示区域（502，601）内限定出多个像素单元（610），像素单元（610）包括像素电极（101，611）。至少一条公共电极线（102，203，605）包括本体（1021，6050）和支线（1022，6051，60511，60512），支线（1022，6051，60511，60512）位于本体（1021，6050）的至少一侧，且至少一部分支线（1022，6051，60511，60512）位于显示区域（502，601）的边缘内侧。

Description

一种阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请主张在2016年6月1日在中国提交的中国专利申请号No.201620525942.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板、显示面板及显示装置。
背景技术
液晶显示技术广泛应用于电视、手机以及公共信息显示，是目前使用最为广泛的显示技术。现有技术的液晶显示器，位于显示区域边缘的液晶分子不易偏转，影响了液晶显示器的显示角度和显示效果。
发明内容
本公开实施例提供一种阵列基板、显示面板及显示装置，至少可以一定程度解决液晶显示器显示区域边缘的液晶分子不易偏转的问题。
本公开实施例提供一种阵列基板，包括显示区域和位于显示区域外围的非显示区域。所述阵列基板包括：多条栅线、多条数据线以及多条公共电极线，所述数据线和栅线在显示区域内限定出多个像素单元，所述像素单元包括像素电极。至少一条所述公共电极线包括本体和支线，所述支线位于所述本体的至少一侧，且至少一部分所述支线位于显示区域的边缘内侧。
可选的，所述支线的一部分位于一像素单元所在的区域，且所述支线在所述阵列基板所在平面上的正投影与对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域。
可选的，一部分所述支线位于多个像素单元所在的区域。
可选的，所述本体的相对两侧均具有所述支线。
可选的，所述栅线沿行方向延伸，相邻两行像素单元对应的两条栅线组成一栅线组，所述栅线组位于对应的相邻两行像素单元之间，所述公共电极线位于相邻两行像素单元之间，且所述栅线组和所述公共电极线间隔设置，相邻的栅线组和公共电极线之间具有一行像素单元；所述支线包括位于所述 本体一侧的第一支线和位于所述本体相对另一侧的第二支线，所述第一支线和第二支线平行或位于同一条直线上。
可选的，所述本体与所述栅线平行，且为同层结构。
可选的，所述支线与所述数据线平行。
可选的，在所述数据线的延伸方向上，所述支线的长度为对应的像素单元的长度的3/5～8/9。
可选的，所述支线的一部分位于相邻的第一像素单元和第二像素单元之间，且所述支线在所述阵列基板所在平面上的正投影与所述第一像素单元的像素电极和第二像素单元的像素电极在所述阵列基板所在平面上的正投影均存在交叠区域。
可选的，所述多条公共电极线包括第一公共电极线以及位于第一公共电极线相对侧的第二公共电极线，所述第一公共电极线以及所述第二公共电极线的宽度大于其他公共电极线的宽度；所述第一公共电极线位于显示区域靠近源极驱动芯片所在区域的一侧。
可选的，所述公共电极线包括第一公共电极线和第二公共电极线，其中，第一公共电极线的宽度大于第二公共电极线的宽度，所述第一公共电极线和第二公共电极线间隔设置。
可选的，所述公共电极线以所述阵列基板的中心轴对称分布。
可选的，公共电极线在显示区域内至少部分电性连接。
可选的，相邻两条公共电极线在显示区域内电性连接。
同时，本公开还提供一种显示面板，包括本公开任意一项实施例所提供的阵列基板。
进一步，本公开还提供一种显示装置，包括本公开任意一项实施例所提供的显示面板。
同时，本公开还提供一种阵列基板，包括显示区域和位于显示区域外围的非显示区域，所述阵列基板包括沿列方向延伸的多条数据线；沿行方向延伸的多条栅线，以及多条公共电极线。其中，所述数据线和栅线在显示区域内限定出多个像素单元，所述像素单元包括像素电极。至少一条所述公共电极线均包括沿行方向延伸的本体和沿列方向延伸的支线，所述支线位于所述 本体的至少一侧且位于显示区域的边缘内侧；所述支线的一部分位于至少一个像素单元所在的区域，且所述支线在所述阵列基板所在平面上的正投影与对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域。相邻两行像素单元对应的两条栅线组成一栅线组，所述栅线组位于对应的相邻两行像素单元之间，所述公共电极线位于相邻两行像素单元之间，所述栅线组和所述公共电极线间隔设置，相邻的栅线组和公共电极线之间具有一行像素单元。所述公共电极线的本体、支线与所述栅线为同层同材料设置。
本公开的上述技术方案的有益效果如下：上述技术方案中，通过在公共电极线上设置有支线，至少有一部分所述支线位于显示区域的边缘，支线与本体可以从不同方位与像素电极产生电场，使得位于显示区域边缘内侧难以偏转的液晶分子能够偏转，扩大显示角度。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例的阵列基板线路布置示意图；
图2为本公开一种实施例的阵列基板线路布置示意图；
图3为本公开一种实施例的阵列基板线路布置示意图；
图4为本公开一种实施例的阵列基板线路布置示意图；
图5为本公开的阵列基板区域划分示意图；
图6为本公开一种实施例的阵列基板线路布置示意图。
具体实施方式
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
本公开首先提供一种阵列基板，包括显示区域和位于显示区域外围的非显示区域。所述阵列基板包括：多条栅线和多条数据线以及多条公共电极线。所述数据线和栅线在显示区域内限定出多个像素单元。参照图1和图6，所述像素单元包括：像素电极101。多条公共电极线102中，至少一条所述公 共电极线102包括本体1021和支线1022，所述支线1022位于所述本体1021的一侧，且至少一部分所述支线1022位于显示区域的边缘内侧。其中，为了更好地示出公共电极线在阵列基板上的位置，在图1中仅示出了部分组件，其它各相关组件及其之间的位置关系可以参见附图6。
通过设置所述支线，支线与本体可以从不同方位与像素电极产生电场，使得难以偏转的液晶分子可以一定程度的发生偏转，改善显示角度，扩大视角范围。
此外，还可以起到一定的遮光作用，减小彩膜基板上黑矩阵的面积。
在本公开具体实施例中，所述公共电极线至少包括位于显示区域边缘内侧的支线。
在本公开具体实施例中，所述阵列基板区域分布如图5所示，阵列基板501上虚线划分出的区域代表显示区域502，阵列基板上除了显示区域502以外的区域为非显示区域503，所述显示区域的边缘内侧，为图5中虚线以内的区域的内边缘，即所述显示区域502的边缘线的远离所述阵列基板501一侧的边缘。
在本公开一些实施例中，所述支线的一部分位于一像素单元所在的区域，且所述支线在所述阵列基板所在平面上的正投影与对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域。通过这种设置方式能够进一步增加阵列基板的存储电容，使得难以偏转的液晶分子偏转，改善显示效果。此外，还可以起到更好的遮光作用，减小彩膜基板上黑矩阵的面积。
在本公开一些实施例中，一部分所述支线位于所述多个像素单元所在的区域。
在本公开一些实施例中，所述本体的一侧具有所述支线，或者所述本体的相对两侧均具有所述支线。
在本公开一些实施例中，参照图2和图6，所述栅线201沿行方向延伸，相邻两行像素单元对应的两条栅线201组成一栅线组202，所述栅线组202位于对应的相邻两行像素单元之间，所述公共电极线203位于相邻两行像素单元之间，也就是位于图2所示的相邻两行像素电极206之间；且所述栅线组202和所述公共电极线203间隔设置，相邻的栅线组202和公共电极线203 之间具有一行像素单元。所述支线包括位于所述本体一侧的第一支线204和位于所述本体相对另一侧的第二支线205所述第一支线204和第二支线205平行或位于同一条直线上。例如，附图6示出了二者位于同一条直线上的情况。
在本公开具体实施例中，所述第一支线和第二支线平行于数据线。所述第一支线和第二支线与像素电极部分重叠，即第一支线和第二支线在阵列基板所在平面上的正投影与所述对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域。
在本公开具体实施例中，所述支线可以为长条状、弯折状等多种形状。
在本公开一些实施例中，所述本体与所述栅线平行，且为同层结构。
在本公开一些实施例中，所述支线与所述数据线平行。
在本公开一些实施例中，所述本体为条状，所述支线与所述本体一体成型。
在本公开一些实施例中，在所述数据线的延伸方向上，所述支线的长度为对应的像素单元的长度的3/5～8/9，如此，可以尽量起到遮光作用。具体的，所述像素单元的长度指像素单元在数据线延伸方向上的长度。
在本公开一些实施例中，所述支线的一部分位于相邻的第一像素单元和第二像素单元之间，且所述支线在所述阵列基板所在平面上的正投影与所述第一像素单元的像素电极和第二像素单元的像素电极在所述阵列基板所在平面上的正投影均存在交叠区域。
在本公开一些实施例中，参照图4，所述多条公共电极线中，第一公共电极线402以及位于第一公共电极线402相对侧的第二公共电极线401，第一公共电极线402以及第二公共电极线401的宽度大于其他公共电极线403的宽度；所述第一公共电极线402位于显示区域靠近源极驱动芯片的一侧。在一种具体实施例中，所述源极驱动芯片位于图4中第一公共电极线402在图中的下方位置。这样可以增大像素区公共电极线的信号输入，减小公共电极线信号延迟以及改善液晶分子在像素区边缘的偏转。
在本公开一些实施例中，参照图3，所述公共电极线包括多条第一公共电极线301和多条第二公共电极线302，其中，第一公共电极线301的宽度 大于第二公共电极线302的宽度，所述第一公共电极线301和第二公共电极线302间隔设置。这种设计可以减小公共电极线相互间的信号差异。
可选的，公共电极线在显示区域内至少部分电性连接。例如：相邻两条公共电极线在显示区域内电性连接，可以减小公共电极线相互间的信号差异。这里的电性连接可以采用本领域公知的公共电极线的连接方式，这里不再赘述。
在本公开一些实施例中，所述公共电极线以所述阵列基板的中心轴对称分布。
在本公开具体实施例中，阵列基板的栅绝缘层可以为单层结构或多层结构，例如，栅绝缘层可包括氮化硅层或氧化硅层。
在本公开具体实施例中，所述阵列基板的栅线、数据线可以采用Cu，Al，Mo，Ti，Cr，W等金属材料制备，也可以采用这些材料的合金制备，栅线可以是单层结构，也可以采用多层结构。例如，栅线为多层结构，依次包括Mo层-铝层-Mo层，或依次包括Ti层-Cu层-Ti层，或Mo层-Ti层-Cu层。
在本公开具体实施例中，所述阵列基板还包括有源层、钝化层；所述有源层的材料可以采用非晶硅，或氧化物半导体。所述钝化层可以采用无机物如氮化硅，也可以采用有机物如树脂。所述像素电极的材料采用ITO(氧化铟锡)，IZO(氧化铟锌)或其他透明金属氧化物导电材料制备。
在本公开具体实施例中，所述阵列基板的制作过程包括：采用Sputter(溅镀)溅射沉积金属层，所述金属层可以为Al；通过涂覆光刻胶、曝光显影、刻蚀，形成栅线、栅极和公共电极线的图形；利用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)沉积栅绝缘层，所述栅绝缘层可以为氮化硅；沉积半导体层，如PECVD沉积a-Si(无定形硅)；或利用Sputter工艺沉积IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)；涂覆光刻胶，曝光显影，刻蚀，形成有源层图形；利用Sputter溅射沉积金属层，所述金属层可以为Al；涂覆光刻胶，曝光显影，刻蚀，形成数据线、源极和漏极的图形。
所述阵列基板的制作过程还可以包括形成钝化层和像素电极的步骤。
进一步，本公开提供一种显示面板，包括本公开任意一项实施例所提供 的阵列基板。所述的显示面板还可以包括相应的彩膜基板以及驱动电路例如源极驱动芯片等组件。
进一步，本公开提供一种显示装置，包括本公开任意一项实施例提供的的显示面板。所述的显示装置还可以包括供电电路，输入装置例如按钮等结构组件。
同时，如图6所示，本公开还提供一种阵列基板600，包括显示区域601和位于显示区域外围的非显示区域602，所述阵列基板包括沿列方向延伸的多条数据线603；沿行方向延伸的多条栅线604，以及多条公共电极线605。其中，所述数据线和栅线在显示区域内限定出多个像素单元610，所述像素单元包括像素电极611。至少一条所述公共电极线均包括沿行方向延伸的本体6050和沿列方向延伸的支线6051、60511、60512，所述支线位于所述本体的至少一侧且位于显示区域的边缘内侧；所述支线的一部分位于至少一个像素单元所在的区域，且所述支线在所述阵列基板所在平面上的正投影与对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域。相邻两行像素单元对应的两条栅线组成一栅线组6040，所述栅线组位于对应的相邻两行像素单元之间，所述公共电极线位于相邻两行像素单元之间，所述栅线组和所述公共电极线间隔设置，相邻的栅线组和公共电极线之间具有一行像素单元。所述公共电极线的本体、支线与所述栅线为同层同材料设置。
从上面所述可以看出，本公开提供的阵列基板、显示面板和显示装置，在公共电极线上设置有支线，至少有一部分所述支线位于显示区域的边缘，能够增加阵列基板的存储电容，使得位于显示区域边缘内侧难以偏转的液晶分子能够偏转，扩大显示角度。
此外，可以起到一定的遮光作用，减小彩膜基板的黑矩阵面积。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。

Claims (17)

  1. 一种阵列基板，包括显示区域和位于显示区域外围的非显示区域，所述阵列基板包括：多条栅线、多条数据线以及多条公共电极线，其中，
    所述数据线和栅线在显示区域内限定出多个像素单元，所述像素单元包括像素电极；
    至少一条所述公共电极线包括本体和支线，所述支线位于所述本体的至少一侧，且至少一部分所述支线位于显示区域的边缘内侧。
  2. 根据权利要求1所述的阵列基板，其中，所述支线的一部分位于一像素单元所在的区域，且所述支线在所述阵列基板所在平面上的正投影与对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域。
  3. 根据权利要求2所述的阵列基板，其中，一部分所述支线位于所述多个像素单元所在的区域。
  4. 根据权利要求3所述的阵列基板，其中，所述本体的相对两侧均具有所述支线。
  5. 根据权利要求4所述的阵列基板，其中，所述栅线沿行方向延伸，相邻两行像素单元对应的两条栅线组成一栅线组，所述栅线组位于对应的相邻两行像素单元之间，所述公共电极线位于相邻两行像素单元之间，且所述栅线组和所述公共电极线间隔设置，相邻的栅线组和公共电极线之间具有一行像素单元；
    所述支线包括位于所述本体一侧的第一支线和位于所述本体相对另一侧的第二支线，所述第一支线和第二支线平行或位于同一条直线上。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，所述本体与所述栅线平行，且为同层结构。
  7. 根据权利要求1-5任意一项所述的阵列基板，其中，所述支线与所述数据线平行。
  8. 根据权利要求7所述的阵列基板，其中，在所述数据线的延伸方向上，所述支线的长度为对应的像素单元的长度的3/5～8/9。
  9. 根据权利要求1-5任一项所述的阵列基板，其中，所述支线的一部分位 于相邻的第一像素单元和第二像素单元之间，且所述支线在所述阵列基板所在平面上的正投影与所述第一像素单元的像素电极和第二像素单元的像素电极在所述阵列基板所在平面上的正投影均存在交叠区域。
  10. 根据权利要求1-5任一项所述的阵列基板，其中，所述多条公共电极线包括第一公共电极线以及在阵列基板上位于第一公共电极线相对侧的第二公共电极线，所述第一公共电极线以及第二公共电极的宽度大于其他公共电极线的宽度。
  11. 根据权利要求1-5任一项所述的阵列基板，其中，所述公共电极线包括多条第一公共电极线和多条第二公共电极线，其中，第一公共电极线的宽度大于第二公共电极线的宽度，所述第一公共电极线和第二公共电极线间隔设置。
  12. 根据权利要求9所述的阵列基板，其中，所述公共电极线以所述阵列基板的中心轴对称分布。
  13. 根据权利要求9所述的阵列基板，其中，所述公共电极线在显示区域内至少部分电性连接。
  14. 根据权利要求9所述的阵列基板，其中：相邻两条所述公共电极线在显示区域内电性连接。
  15. 一种显示面板，包括权利要求1-14中任一项所述的阵列基板。
  16. 一种显示装置，包括权利要求15所述的显示面板。
  17. 一种阵列基板，包括显示区域和位于显示区域外围的非显示区域，所述阵列基板包括：
    沿列方向延伸的多条数据线；
    沿行方向延伸的多条栅线，以及
    多条公共电极线；
    其中，所述数据线和栅线在显示区域内限定出多个像素单元，所述像素单元包括像素电极；
    至少一条所述公共电极线包括沿行方向延伸的本体和沿列方向延伸的支线，所述支线位于所述本体的至少一侧且位于显示区域的边缘内侧；所述支线的一部分位于至少一个像素单元所在的区域，且所述支线在所述阵列基板 所在平面上的正投影与对应的像素单元的像素电极在所述阵列基板所在平面上的正投影存在交叠区域；
    相邻两行像素单元对应的两条栅线组成一栅线组，所述栅线组位于对应的相邻两行像素单元之间，所述公共电极线位于相邻两行像素单元之间，所述栅线组和所述公共电极线间隔设置，相邻的栅线组和公共电极线之间具有一行像素单元；
    所述公共电极线的本体、支线与所述栅线为同层同材料设置。
PCT/CN2017/084039 2016-06-01 2017-05-12 一种阵列基板、显示面板及显示装置 WO2017206697A1 (zh)

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CN207369413U (zh) * 2017-09-27 2018-05-15 京东方科技集团股份有限公司 一种线路板、显示驱动装置及显示装置
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