WO2020253652A1 - 显示基板、其制作方法、显示面板及显示装置 - Google Patents

显示基板、其制作方法、显示面板及显示装置 Download PDF

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WO2020253652A1
WO2020253652A1 PCT/CN2020/096162 CN2020096162W WO2020253652A1 WO 2020253652 A1 WO2020253652 A1 WO 2020253652A1 CN 2020096162 W CN2020096162 W CN 2020096162W WO 2020253652 A1 WO2020253652 A1 WO 2020253652A1
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Prior art keywords
gate
layer
trace
base substrate
source
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PCT/CN2020/096162
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English (en)
French (fr)
Inventor
宋威
赵策
丁远奎
王明
刘宁
胡迎宾
彭俊林
倪柳松
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/264,827 priority Critical patent/US20210296368A1/en
Publication of WO2020253652A1 publication Critical patent/WO2020253652A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, a display panel and a display device.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the drive backplane made of TFT array is a key component for the display screen to achieve higher pixel density, aperture ratio and increase brightness.
  • the embodiment of the present disclosure provides a display substrate, including:
  • the active layer is located on the base substrate;
  • the gate metal layer is located on the active layer.
  • the gate metal layer includes a gate and a first trace.
  • the orthographic projection of the gate on the base substrate is in line with the active layer. There is an overlap area in the orthographic projection on the base substrate, and the orthographic projection of the first trace on the base substrate and the orthographic projection of the active layer on the base substrate do not overlap each other ;
  • the source and drain metal layer is located on the gate metal layer.
  • the source and drain metal layer includes a source and drain and a second wiring.
  • the source and drain are electrically connected to the active layer. There is an overlap area between the orthographic projection of the second trace on the base substrate and the orthographic projection of the first trace on the base substrate;
  • the gate insulating layer is located between the active layer and the gate metal layer.
  • the gate insulating layer includes a first part and a second part.
  • the first part is formed on the base substrate
  • the orthographic projection covers and exceeds the orthographic projection of the gate on the base substrate, and the orthographic projection of the second sub-section on the base substrate covers the first trace on the base substrate Orthographic projection
  • the portion of the first subsection that exceeds the gate has a first width value, and at the area where the second trace and the first trace overlap, the second subsection exceeds the first trace.
  • a portion of a trace has a second width value; the first width value is greater than the second width value.
  • the second width value is less than or equal to 20% of the first width value.
  • the second width value is 0.
  • the extension directions of the second trace and the first trace are different;
  • the orthographic projection of the first trace on the base substrate and the orthographic projection of the second branch on the base substrate coincide with each other.
  • the above-mentioned display substrate provided by an embodiment of the present disclosure further includes: an interlayer insulating layer located between the gate metal layer and the source and drain metal layers;
  • the source and drain electrodes are electrically connected to the active layer through a via hole penetrating the interlayer insulating layer.
  • embodiments of the present disclosure also provide a method for manufacturing the above-mentioned display substrate, including:
  • a pattern of a source and drain metal layer including a source and drain and a second wiring is formed on the pattern of the gate insulating layer.
  • a semi-exposure photolithography process is used to form a patterned photoresist layer on the gate metal film, including:
  • the positive photoresist film is exposed and developed, and the pattern of the obtained photoresist layer has the first thickness on the part above the gate to be formed,
  • the portion of the overlapping area between the first trace and the second trace to be formed has a second thickness, and the first thickness is greater than the second thickness.
  • the halftone mask or the gray tone mask includes a completely transparent area and a partial transparent area; the fully transparent area corresponds to the photoresist The first thickness in the layer, and the partially transparent region corresponds to the second thickness in the photoresist layer.
  • the second thickness is less than or equal to half of the first thickness.
  • the method before forming a pattern of a source and drain metal layer including a source and drain and a second wiring on the pattern of the gate insulating layer, the method further includes:
  • An interlayer insulating layer with via holes is formed on the pattern of the gate insulating layer, so that the source and drain electrodes to be formed are electrically connected to the active layer through the via holes.
  • an embodiment of the present disclosure also provides a display panel, including the above-mentioned display substrate provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view of a display substrate provided by related art
  • FIG. 2 is a schematic cross-sectional view of a display substrate provided by related art
  • FIG. 3 is a schematic cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a structure in the process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a structure in the process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a structure in a process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a structure in the process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a structure in the process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a structure in the process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of a structure in the process of manufacturing a display substrate provided by an embodiment of the disclosure.
  • the TFT of the top emission structure can effectively reduce the parasitic capacitance, and the refresh frequency is better; the channel is shorter and the size is smaller, which can better meet the needs of the development of display panels.
  • the characteristics of top-emission TFTs are susceptible to the short-channel effect.
  • the gate insulating layer In order to reduce the short-channel effect of top-emission TFTs, the gate insulating layer must be ensured during the preparation of top-emission TFTs.
  • the length of the (Gate Insulator, GI) 10 is longer than the length of the gate metal layer (Gate) 20, as shown in FIG. 1.
  • the portion of GI 10 that is more than Gate 20 is called GI Tail 101.
  • GI Tail will cause wrinkles at the overlap of the Inter Layer Dielectrics (ILD) 30 and Gate 20, and this wrinkle is in the source and drain metal layer (SD)
  • ILD Inter Layer Dielectrics
  • SD source and drain metal layer
  • the coverage of ILD 30 between Gate 20 and SD 40 deteriorates and the thickness becomes thinner, so that a similar tip phenomenon will be formed after SD 40 is deposited.
  • the gate metal layer and source are prone to occur.
  • the short circuit (Data Gate Short, DGS) between the drain metal layers is defective.
  • the ratio of the gate insulating layer at the overlapped area of the metal traces is reduced to make it smaller than the value of GI Tail. That is, remove the GI Tail as much as possible in the area where the metal traces overlap, so as to reduce DGS defects and improve the yield of the display substrate.
  • a display substrate provided by an embodiment of the present disclosure, the display substrate including:
  • the active layer 201 is located on the base substrate 200;
  • the gate metal layer is located on the active layer 201.
  • the gate metal layer includes the gate 203 and the first trace 103.
  • the orthographic projection of the gate 203 on the base substrate 200 and the active layer 201 on the base substrate 200 There is an overlapping area in the orthographic projection on the upper side, and the orthographic projection of the first trace 103 on the base substrate 200 and the orthographic projection of the active layer 201 on the base substrate 200 do not overlap each other;
  • the source and drain metal layer is located on the gate metal layer.
  • the source and drain metal layer includes a source and drain 206 and a second wiring 106.
  • the source and drain 206 are electrically connected to the active layer 201.
  • the gate insulating layer is located between the active layer 201 and the gate metal layer.
  • the gate insulating layer includes a first part 202 and a second part 102.
  • the orthographic projection of the first part 202 on the base substrate 200 covers and exceeds
  • the orthographic projection of the gate electrode 203 on the base substrate 200, and the orthographic projection of the second sub-section 102 on the base substrate 200 covers the orthographic projection of the first trace 103 on the base substrate 200;
  • the portion of the first subsection 202 that exceeds the gate 203 has a first width value d1.
  • the portion of the second subsection 102 that exceeds the first trace 103 It has a second width value d2; the first width value d1 is greater than the second width value d2.
  • the area where the active layer 201, the gate 203, and the source and drain 206 are located can be called a control area (or transistor area), and the first wiring 103 and the second
  • the area where the two wires 106 overlap is called a metal wire area, and the control area and the metal wire area are independent of each other.
  • the area of the first subsection 202 of the gate insulating layer in the control region is larger than the area of the gate 203 thereon. It can also be considered that in the direction along the channel extension of the active layer 201, the first subsection of the gate insulating layer
  • the length of 202 is greater than the length of the gate 203, that is, it can be understood that there is a GI Tail in the control area. Since the active layer 201 is conductively processed, the area covered by GI Tail will not be conductive. Therefore, when the display substrate is manufactured, the first part 202 can be controlled to exceed the first width of the gate 203.
  • the value d1 is used to adjust the channel length of the active layer 201, so as to minimize the influence of the short channel effect.
  • the first wiring 103 may be a signal line such as a gate line
  • the second wiring 106 may be a signal line such as a data line and a touch line.
  • the extension direction of the line 103 and the second trace 106 are generally different.
  • the gate line as the first trace 103 generally extends along the row direction of the display substrate
  • the data line as the second trace 106 generally extends along the column of the display substrate.
  • the data line and the gate line are insulated from each other at the overlapping position.
  • first wire and the second wire existing as a patch cord or jumper have the same extending direction at a specific position, and the two are electrically connected to each other in the overlapping area. Since the first wiring 103 and the second wiring 106 are only used to transmit signals, and an active layer with a channel region is generally not provided under them, so there is no need for the existence of GI Tail under the first wiring 103.
  • the size of the second subsection 102 located below the overlapping area of the first wiring 103 and the second wiring 106 is minimized in order to minimize the overlap
  • the edge difference between the second sub-portion 102 of the area and the first trace 103 is the second width value d2, so as to reduce the GI Tail in the overlap area, reduce wrinkles in the overlap area, thereby reduce DGS defects, and improve the display substrate The yield rate.
  • the second width value d2 can be 0, that is, at the overlapping area, the second subsection 102 will not exceed the area where the first trace 103 is located, and the sizes of the two are the same to completely remove the GI Tail band The DGS that came is bad.
  • all the second subsections 102 under the first trace 103 can be set to completely remove the GI Tail, that is, the first trace 103 is on the base substrate 200.
  • the orthographic projection and the orthographic projection of the second sub-part 102 on the base substrate 200 coincide with each other.
  • the second width value d2 is less than or equal to 20% of the first width value d1, that is, the size of the second subsection 102 in the overlapping area is larger than the size of the first trace 103, and The difference in size is smaller than the size of the GI Tail. Try to minimize the size of the GI Tail in the overlapping area, which reduces the requirements for the process and is easier to implement.
  • an interlayer insulating layer 204 located between the gate metal layer and the source and drain metal layers, the gate 203 and the source and drain metal are generally included.
  • An interlayer insulating layer 204 is also disposed between the layers 205, the interlayer insulating layer 204 is disposed on the entire surface, and the source and drain electrodes 206 are electrically connected to the active layer 201 through via holes penetrating the interlayer insulating layer 204.
  • the portion of the interlayer insulating layer 204 between the first wiring 103 and the second wiring 106 can function to insulate the two.
  • Reducing or removing the size of the GI Tail at the overlapping area can alleviate or remove the wrinkles of the interlayer insulating layer 204 at the overlapping area, which can avoid the occurrence of similar tip discharge phenomena after the formation of the second trace 106.
  • DGS is bad.
  • a buffer layer (Buffer) 207 located between the base substrate 200 and the active layer 201, and a buffer layer between the source and drain metal layers may generally be included.
  • Buffer buffer layer
  • a display panel which includes any display substrate as described above.
  • the display panel can be any display panel including a display substrate, such as a liquid crystal display panel, an organic electroluminescence display panel, a plasma display panel, and the like.
  • the display panel may be a rigid display panel or a flexible display panel.
  • the display panel please refer to the above-mentioned embodiment of the display substrate, and the repetition will not be repeated.
  • the display panel is a liquid crystal display panel, it may also include a pixel electrode layer, an insulating layer, a common electrode layer, etc.
  • the source and drain metal layer may also include a flat layer, an anode layer, a pixel defining layer, an organic light-emitting function film layer, a cathode layer and other film layers, as well as an encapsulation structure.
  • an embodiment of the invention also provides a display device, including the above-mentioned display panel provided by the embodiment of the invention.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present invention.
  • an embodiment of the present disclosure also provides a manufacturing method of the above-mentioned display substrate.
  • the manufacturing method includes the following steps:
  • the above step S401 forms the pattern of the active layer 201 on the base substrate 200, and the plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD) may be used first in the substrate.
  • An insulating film is deposited on the base substrate 200, for example, a layer of silicon oxide, silicon nitride, etc. is deposited as a buffer layer (Buffer) 207; and then an oxide semiconductor film is deposited on the buffer layer 207, such as indium gallium zinc oxide (indium gallium zinc oxide). gallium zinc oxide (IGZO), indium zinc oxide (IZO), etc.
  • the active layer 201 (Active); then the active layer 201 is patterned by mask and etching processes to form the active layer 201 Graphics. Alternatively, materials such as polysilicon can also be used to make the pattern of the active layer 201, which is not limited here.
  • an insulating film 302 and a gate metal film 303 are sequentially formed on the pattern of the active layer 201.
  • an insulating film 302 can be deposited on the active layer 201 by PECVD.
  • a layer of silicon oxide, silicon nitride, etc. is deposited, and then a layer of gate metal film 303 is deposited on the insulating film 302 using a magnetron sputtering device, such as copper (Cu), aluminum (Al), etc.).
  • step S403 adopts a halftone mask to form a patterned photoresist layer 205 on the gate metal film 303, which may specifically include the following steps:
  • a positive photoresist film 305 is formed on the gate metal film 303;
  • the positive photoresist film 305 is exposed and developed to obtain a photoresist layer 205
  • the portion above the gate 203 to be formed has a first thickness H1
  • the portion of the overlapping area between the first wiring 103 and the second wiring 106 to be formed has a second thickness H2
  • the thickness H1 is greater than the second thickness H2.
  • the halftone mask or the gray tone mask includes a completely transparent area and a partially transparent area; the completely transparent area corresponds to the first thickness H1 in the photoresist layer 205, and the partially transparent area corresponds to the photolithography
  • the ultraviolet light transmission ability of the completely transparent region and the partially transparent region are different.
  • the second thickness H2 obtained after the final exposure and development can be controlled to be less than or equal to half of the first thickness H1, so that there is a GI Tail under the gate 103, and the GI Tail is removed in the overlap area. .
  • step S404 may specifically use the patterned photoresist layer 205 to shield the gate metal film 303 to form a gate including the gate 203 and the first wiring 103.
  • the graphics of the extremely metal layer may specifically use the patterned photoresist layer 205 to shield the gate metal film 303 to form a gate including the gate 203 and the first wiring 103.
  • the above step S405 uses the patterned photoresist layer 205 to shield the insulating film 302 by dry etching, since the second thickness H2 is thinner than the first thickness H1, During dry etching, the thinner second thickness H2 ashes faster at the edge position, which makes the size of the photoresist layer 205 of the second thickness H2 gradually decrease faster than the photolithography of the first thickness H1 The size of the glue layer 205 gradually decreases in speed.
  • the photoresist layer 205 with the second thickness H2 can be controlled to be almost the same size as the first trace 103 below.
  • the size of the photoresist layer 205 with the second thickness H2 becomes smaller, the area covered by the insulating film 302 will also become smaller.
  • the size of the first part 102 in the pattern of the gate insulating layer is basically the same as that of the first part.
  • the size of a trace 103 is the same, so that the influence of GI Tail can be eliminated.
  • the photoresist layer 205 with the first thickness H1 is relatively thick, the edge position ashing is relatively slow during dry etching, which makes the size of the photoresist layer 205 with the first thickness H1 basically unchanged. It can ensure that the GI Tail on the active layer 201 exists.
  • the remaining photoresist layer 205 can be removed by using Strip liquid, and the structure shown in FIG. 11 is obtained.
  • the method further includes: When the active layer is made of polysilicon material, the gate metal layer and the gate insulating layer are used to shield the active layer 201; and an interlayer insulating layer with via holes is formed on the pattern of the gate insulating layer 204, so that the source and drain 206 to be formed are electrically connected to the active layer 201 through the via hole.
  • the display substrate in the embodiment of the present disclosure retains the GI Tail under the active layer, and reduces the size of the GI Tail at the area where the first trace and the second trace overlap. It can be understood that the GI Tail should be removed as much as possible at the overlapping area of the first trace and the second trace, so that the size of the second part of the gate insulating layer is the same as or similar to the size of the first trace, thereby reducing the size of the overlap area. DGS defects caused by wrinkles improve the yield of the display substrate.

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Abstract

本公开提供了一种显示基板、其制作方法、显示面板及显示装置，用于降低显示器件发生DGS的概率，提高显示基板的良率。其中的显示基板包括：衬底基板、位于衬底基板上的有源层、位于有源层上的栅绝缘层、位于栅绝缘层上的栅极金属层，以及位于栅极金属层上的源漏极金属层；其中，栅极金属层包括栅极和第一走线，源漏极金属层包括源漏极和第二走线，栅绝缘层包括位于栅极和有源层之间的第一分部，以及位于第一走线和第二走线交叠区域下方的第二分部，第一分部超出栅极的部分具有第一宽度值，在第二走线与所述第一走线交叠区域处，第二分部超出第一走线的部分具有第二宽度值；第一宽度值大于第二宽度值。

Description

显示基板、其制作方法、显示面板及显示装置
相关申请的交叉引用
本公开要求在2019年06月19日提交中国专利局、申请号为201910531872.3、申请名称为“一种阵列基板及其制作方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板、其制作方法、显示面板及显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)主要用于驱动液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)等显示器的子像素。采用TFT阵列制成的驱动背板是显示屏能够实现更高的像素密度、开口率和提升亮度的关键部件。
发明内容
本公开实施例提供了一种显示基板，包括：
衬底基板；
有源层，位于所述衬底基板之上；
栅极金属层，位于所述有源层之上，所述栅极金属层包括栅极和第一走线，所述栅极在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影存在交叠区域，所述第一走线在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影互不交叠；
源漏极金属层，位于所述栅极金属层之上，所述源漏极金属层包括源漏极和第二走线，所述源漏极与所述有源层电连接，所述第二走线在所述衬底 基板上的正投影与所述第一走线在所述衬底基板上的正投影存在交叠区域；
栅绝缘层，位于所述有源层与所述栅极金属层之间，所述栅绝缘层包括第一分部和第二分部，所述第一分部在所述衬底基板上的正投影覆盖且超出所述栅极在所述衬底基板上的正投影，所述第二分部在所述衬底基板上的正投影覆盖所述第一走线在所述衬底基板上的正投影；
其中，所述第一分部超出所述栅极的部分具有第一宽度值，在所述第二走线与所述第一走线交叠区域处，所述第二分部超出所述第一走线的部分具有第二宽度值；所述第一宽度值大于所述第二宽度值。
可选地，本公开实施例提供的上述显示基板中，所述第二宽度值小于或等于所述第一宽度值的20％。
可选地，本公开实施例提供的上述显示基板中，所述第二宽度值为0。
可选地，本公开实施例提供的上述显示基板中，所述第二走线与所述第一走线的延伸方向不同；
所述第一走线在所述衬底基板上的正投影与所述第二分部在所述衬底基板上的正投影相互重合。
可选地，本公开实施例提供的上述显示基板中，还包括：层间绝缘层，位于所述栅极金属层与所述源漏极金属层之间；
所述源漏极通过贯穿所述层间绝缘层的过孔与所述有源层电连接。
另一方面，本公开实施例还提供了一种上述显示基板的制作方法，包括：
在衬底基板上形成有源层的图形；
在所述有源层的图形上依次形成绝缘薄膜和栅极金属薄膜；
采用半曝光光刻工艺，在所述栅极金属薄膜上形成图案化的光刻胶层；
利用图案化的光刻胶层的遮挡，对所述栅极金属薄膜进行刻蚀，形成包括栅极和第一走线的栅极金属层的图形；
利用图案化的光刻胶层的遮挡，对所述绝缘薄膜进行干法刻蚀，形成包括第一分部和第二分部的栅绝缘层的图形，并去除所述光刻胶层；
在所述栅绝缘层的图形上形成包括源漏极和第二走线的源漏极金属层的 图形。
可选地，本公开实施例提供的上述方法中，采用半曝光光刻工艺，在所述栅极金属薄膜上形成图案化的光刻胶层，包括：
在所述栅极金属薄膜上形成正性光刻胶薄膜；
采用半色调掩模板或灰色调掩模板，对所述正性光刻胶薄膜进行曝光显影处理，得到的光刻胶层的图形中，在将要形成的栅极之上的部分具有第一厚度，在将要形成的第一走线和第二走线之间交叠区域的部分具有第二厚度，所述第一厚度大于所述第二厚度。
可选地，本公开实施例提供的上述方法中，所述半色调掩膜板或灰色调掩模板包括完全透光区域和部分透光区域；所述完全透光区域对应于所述光刻胶层中的第一厚度，所述部分透光区域对应于所述光刻胶层中的第二厚度。
可选地，本公开实施例提供的上述方法中，所述第二厚度小于或等于所述第一厚度的一半。
可选地，本公开实施例提供的上述方法中，在所述栅绝缘层的图形上形成包括源漏极和第二走线的源漏极金属层的图形之前，还包括：
在所述栅绝缘层的图形上形成具有过孔的层间绝缘层，以使将要形成的源漏极通过所述过孔与所述有源层电连接。
另一方面，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。
另一方面，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。
附图说明
图1为相关技术提供的显示基板的截面示意图；
图2为相关技术提供的显示基板的截面示意图；
图3为本公开实施例提供的显示基板的截面示意图；
图4为本公开实施例提供的显示基板的制作方法的流程图；
图5为本公开实施例提供的制作显示基板过程中的结构示意图；
图6为本公开实施例提供的制作显示基板过程中的结构示意图；
图7为本公开实施例提供的制作显示基板过程中的结构示意图；
图8为本公开实施例提供的制作显示基板过程中的结构示意图；
图9为本公开实施例提供的制作显示基板过程中的结构示意图；
图10为本公开实施例提供的制作显示基板过程中的结构示意图；
图11为本公开实施例提供的制作显示基板过程中的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。应当理解，下面所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
通常顶发射型结构的TFT能够有效的降低寄生电容，刷新频率更好；沟道更短，尺寸更小，更能满足显示面板发展的需要。但顶发射型结构的TFT的特性易受短沟道效应的影响，为了降低顶发射型结构的TFT短沟道效应的影响，在顶发射型结构的TFT的制备过程中要保证栅极绝缘层(Gate Insulator，GI)10的长度比栅极金属层(Gate)20的长度要长，如图1所示。GI 10相比于Gate 20多出来的部分称为栅极绝缘层尾部(GI Tail)101。
在非TFT所在区域例如在金属走线区，GI Tail会导致层间绝缘层(Inter Layer Dielectrics，ILD)30与Gate 20的交叠处出现褶皱，这种褶皱在源漏极金属层(SD)40搭接之后，导致Gate 20与SD 40之间的ILD 30覆盖能力变差导致厚度变薄，使得SD 40沉积后会形成类似尖端现象，如图2所示，容易发生栅极金属层和源漏极金属层之间的短路(Data Gate Short，DGS)不良。
鉴于此，本公开实施例提供的显示基板中，缩减金属走线交叠区域处的栅极绝缘层的比例，使其小于GI Tail的数值。即在金属走线交叠区域尽量去 掉GI Tail，从而降低DGS不良，提升显示基板的良率。
下面结合附图，对本公开实施例提供的显示基板、其制作方法、显示面板和显示装置的具体实施方式进行详细地说明。附图中各膜层的厚度和形状不反映真实比例，目的只是示意说明本公开内容。
请参见图3，本公开实施例提供的一种显示基板，该显示基板包括：
衬底基板200；
有源层201，位于衬底基板200之上；
栅极金属层，位于有源层201之上，栅极金属层包括栅极203和第一走线103，栅极203在衬底基板200上的正投影与有源层201在衬底基板200上的正投影存在交叠区域，第一走线103在衬底基板200上的正投影与有源层201在衬底基板200上的正投影互不交叠；
源漏极金属层，位于栅极金属层之上，源漏极金属层包括源漏极206和第二走线106，源漏极206与有源层201电连接，第二走线106在衬底基板200上的正投影与第一走线103在衬底基板200上的正投影存在交叠区域；
栅绝缘层，位于有源层201与栅极金属层之间，栅绝缘层包括第一分部202和第二分部102，第一分部202在衬底基板200上的正投影覆盖且超出栅极203在衬底基板200上的正投影，第二分部102在衬底基板200上的正投影覆盖第一走线103在衬底基板200上的正投影；
其中，第一分部202超出栅极203的部分具有第一宽度值d1，在第二走线106与第一走线103交叠区域处，第二分部102超出第一走线103的部分具有第二宽度值d2；第一宽度值d1大于第二宽度值d2。
具体地，在本公开实施例提供的上述显示基板中，可以将有源层201、栅极203和源漏极206所在区域称为控制区(或晶体管区)，将第一走线103和第二走线106交叠的区域称为金属走线区，控制区和金属走线区相互独立。
具体地，在控制区的栅绝缘层的第一分部202面积大于其上的栅极203面积，也可以认为在沿着有源层201的沟道延伸方向，栅绝缘层的第一分部202长度大于栅极203的长度，即可以理解为在控制区存在GI Tail。由于在对 有源层201进行导体化处理时，被GI Tail覆盖的区域不会被导体化，因此，在制作显示基板时，可以通过控制第一分部202超出栅极203部分的第一宽度值d1，来调控有源层201的沟道长度，从而尽量降低短沟道效应的影响。
具体地，在本公开实施例提供的上述显示基板中，第一走线103例如可以为栅线等信号线，第二走线106例如可以为数据线、触控线等信号线，第一走线103和第二走线106的延伸方向一般不同，例如作为第一走线103的栅线一般沿着显示基板的行方向延伸，作为第二走线106的数据线一般沿着显示基板的列方向延伸，且数据线和栅线之间在交叠位置处相互绝缘。当然不排除作为转接线或跳线存在的第一走线和第二走线在特定位置延伸方向一致，且两者之间在交叠区域相互电连接的情况。由于第一走线103和第二走线106只用于传输信号，其下方一般不会设置具有沟道区域的有源层，因此在第一走线103下方不需要GI Tail的存在。基于此，在本公开实施例提供的上述显示基板中尽量缩小位于第一走线103和第二走线106在交叠区域处下方的第二分部102的尺寸，以便尽量减小在交叠区域第二分部102与第一走线103的边缘差值即第二宽度值d2，以达到在交叠区域减小GI Tail，减轻在交叠区域发生褶皱，进而降低DGS不良，提升显示基板的良率。
在具体实施过程中，第二宽度值d2可以是0，即在交叠区域处，第二分部102不会超出第一走线103所在区域，两者的尺寸相同，以完全去除GI Tail带来的DGS不良。
并且，为了简化制作工艺难度，除了交叠区域，可以将在第一走线103下方的全部第二分部102均设置为完全去除GI Tail，即第一走线103在衬底基板200上的正投影与第二分部102在衬底基板200上的正投影相互重合。
在另一种可能的实施方式中，第二宽度值d2小于或等于第一宽度值d1的20％，即在交叠区域的第二分部102的尺寸大于第一走线103的尺寸，两者尺寸之差小于GI Tail的尺寸，尽量减小交叠区域的GI Tail的尺寸，对工艺的要求降低，更易实现。
请继续参见图3，在本公开实施例提供的上述显示基板中，一般还会包括 位于栅极金属层与源漏极金属层之间的层间绝缘层204，栅极203和源漏极金属层205之间还设置层间绝缘层204，层间绝缘层204整面设置，且源漏极206通过贯穿层间绝缘层204的过孔与有源层201电连接。层间绝缘层204在第一走线103和第二走线106之间的部分可以起到使两者绝缘的作用。缩小或去除交叠区域处的GI Tail尺寸，可以缓解或去除层间绝缘层204在交叠区域处出现褶皱，可以避免这种褶皱在第二走线106形成后出现类似尖端放电现象而发生的DGS不良。
请继续参见图3，在本公开实施例提供的上述显示基板中，一般还可以包括位于衬底基板200和有源层201之间的缓存层(Buffer)207，以及在源漏极金属层之上的其他膜层，在此不作详述。
基于同一发明构思，本公开实施例还提供了一种显示面板，该显示面板包括如上述的任一显示基板。该显示面板可以为：液晶显示面板、有机电致发光显示面板、等离子体显示面板等任何包含显示基板的显示面板。该显示面板可以是刚性的显示面板也可以是柔性的显示面板，该显示面板的实施可以参见上述显示基板的实施例，重复之处不再赘述。当显示面板为液晶显示面板时，在源漏极金属层之上还可以包括像素电极层、绝缘层和公共电极层等，并且还可以设置与显示基板相对而置的彩膜基板，以及位于彩膜基板与显示基板之间的液晶层等。当显示面板为有机电致发光显示面板时，在源漏极金属层之上还可以包括平坦层、阳极层、像素限定层、有机发光功能膜层、阴极层等膜层，以及封装结构等。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置的实施可以参见上述显示基板的实施例，重复之处不再赘述。
请参见图4，基于同一发明构思，本公开实施例还提供了一种上述显示基 板的制作方法，该制作方法包括以下步骤：
S401、在衬底基板200上形成有源层201的图形；
S402、在有源层201的图形上依次形成绝缘薄膜302和栅极金属薄膜303；
S403、采用半曝光光刻工艺，在栅极金属薄膜303上形成图案化的光刻胶层205；
S404、利用图案化的光刻胶层205的遮挡，对栅极金属薄膜303进行刻蚀，形成包括栅极203和第一走线103的栅极金属层的图形；
S405、利用图案化的光刻胶层205的遮挡，对绝缘薄膜302进行干法刻蚀，形成包括第一分部202和第二分部102的栅绝缘层的图形，并去除光刻胶层205；
S406、在栅绝缘层的图形上形成包括源漏极206和第二走线106的源漏极金属层的图形。
在具体实施时，请参见图5，上述步骤S401在衬底基板200上形成有源层201的图形，可以具体采用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)先在衬底基板200上沉积一层绝缘薄膜，例如沉积一层氧化硅、氮化硅等作为缓存层(Buffer)207；再在缓存层207上沉积氧化物半导体薄膜，例如沉积铟镓锌氧化物(indium gallium zinc oxide，IGZO)、铟锌氧化物(indium zinc oxide，IZO)等作为有源层201(Active)；之后通过Mask和刻蚀工艺对有源层201进行图形化，形成有源层201的图形。或者，也可以采用多晶硅等材料制作有源层201的图形，在此不做限定。
在具体实施时，请参见图6，上述步骤S402在有源层201的图形上依次形成绝缘薄膜302和栅极金属薄膜303，具体可以在有源层201上采用PECVD沉积一层绝缘薄膜302，例如沉积一层氧化硅、氮化硅等，再采用磁控溅射设备在绝缘薄膜302上沉积一层栅极金属薄膜303，例如沉积铜(Cu)、铝(Al)等)。
在具体实施时，请参见图7和图8，上述步骤S403采用半色调掩模板， 在栅极金属薄膜303上形成图案化的光刻胶层205，具体可以包括如下步骤：
参见图7，首先，在栅极金属薄膜303上形成正性光刻胶薄膜305；
参见图8，之后，采用半色调掩模板(Half-tone Mask)或灰色调掩模板(Gray-tone Mask)，对正性光刻胶薄膜305进行曝光显影处理，得到的光刻胶层205的图形中，在将要形成的栅极203之上的部分具有第一厚度H1，在将要形成的第一走线103和第二走线106之间交叠区域的部分具有第二厚度H2，第一厚度H1大于第二厚度H2。
具体地，半色调掩膜板或灰色调掩模板包括完全透光区域和部分透光区域；完全透光区域对应于光刻胶层205中的第一厚度H1，部分透光区域对应于光刻胶层205中的第二厚度H2，完全透光区域和部分透光区域的透过紫外光能力不同。采用半色调掩膜板对正性光刻胶薄膜进行曝光显影处理后，可以去除未被曝光的光刻胶薄膜，且使得在部分透光区域对应位置处的厚度小于完全透光区域对应位置处的厚度。
并且，可以通过调整曝光时间和曝光量，控制最后曝光显影后得到的第二厚度H2小于或等于第一厚度H1的一半，从而使得栅极103下方存在GI Tail，同时交叠区域内祛除GI Tail。
在具体实施时，请参见图9，上述步骤S404具体可以利用图案化的光刻胶层205的遮挡，对栅极金属薄膜303进行蚀刻工艺，形成包括栅极203和第一走线103的栅极金属层的图形。
在具体实施时，请参见图10，上述步骤S405利用图案化的光刻胶层205的遮挡，对绝缘薄膜302进行干法刻蚀时，由于第二厚度H2薄于第一厚度H1，则在进行干法蚀刻时厚度较薄的第二厚度H2在边缘位置灰化的比较快，这就使第二厚度H2的光刻胶层205的尺寸逐渐减小速度高于第一厚度H1的光刻胶层205的尺寸逐渐减小速度。可以控制到第二厚度H2的光刻胶层205几乎与下方的第一走线103尺寸相同。由于第二厚度H2的光刻胶层205尺寸变小，绝缘薄膜302中被覆盖的区域也会变小，经过干法蚀刻后使得栅绝缘层的图形中第一分部102的尺寸基本与第一走线103的尺寸一致，从而可以 祛除GI Tail的影响。并且，由于第一厚度H1的光刻胶层205相对较厚，在进行干法蚀刻时边缘位置灰化的比较慢，这就使第一厚度H1的光刻胶层205的尺寸基本不发生变化，可以确保有源层201之上的GI Tail存在。
之后，可以采用Strip液祛除残留的光刻胶层205，得到如图11所示的结构。
在一些实施例中，在形成栅绝缘层的图形之后，即在上述步骤S406栅绝缘层的图形上形成包括源漏极和第二走线的源漏极金属层的图形之前，还包括：若采用多晶硅材料制作有源层时，则利用栅极金属层和栅绝缘层的遮挡，对有源层201进行导体化处理；以及，在栅绝缘层的图形上形成具有过孔的层间绝缘层204，以使将要形成的源漏极206通过过孔与有源层201电连接。
综上，本公开实施例中的显示基板在有源层下方保留GI Tail，在第一走线和第二走线交叠区域处缩减GI Tail尺寸。可以理解为，在第一走线和第二走线交叠区域处尽量去掉GI Tail，使得栅绝缘层的第二分部尺寸与第一走线尺寸相同或相近，从而降低在交叠区域处发生褶皱而产生的DGS不良，提升显示基板的良率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种显示基板，其中，包括：
    衬底基板；
    有源层，位于所述衬底基板之上；
    栅极金属层，位于所述有源层之上，所述栅极金属层包括栅极和第一走线，所述栅极在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影存在交叠区域，所述第一走线在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影互不交叠；
    源漏极金属层，位于所述栅极金属层之上，所述源漏极金属层包括源漏极和第二走线，所述源漏极与所述有源层电连接，所述第二走线在所述衬底基板上的正投影与所述第一走线在所述衬底基板上的正投影存在交叠区域；
    栅绝缘层，位于所述有源层与所述栅极金属层之间，所述栅绝缘层包括第一分部和第二分部，所述第一分部在所述衬底基板上的正投影覆盖且超出所述栅极在所述衬底基板上的正投影，所述第二分部在所述衬底基板上的正投影覆盖所述第一走线在所述衬底基板上的正投影；
    其中，所述第一分部超出所述栅极的部分具有第一宽度值，在所述第二走线与所述第一走线交叠区域处，所述第二分部超出所述第一走线的部分具有第二宽度值；所述第一宽度值大于所述第二宽度值。
  2. 如权利要求1所述的显示基板，其中，所述第二宽度值小于或等于所述第一宽度值的20％。
  3. 如权利要求1所述的显示基板，其中，所述第二宽度值为0。
  4. 如权利要求3所述的显示基板，其中，所述第二走线与所述第一走线的延伸方向不同；
    所述第一走线在所述衬底基板上的正投影与所述第二分部在所述衬底基板上的正投影相互重合。
  5. 如权利要求1所述的显示基板，其中，还包括：层间绝缘层，位于所 述栅极金属层与所述源漏极金属层之间；
    所述源漏极通过贯穿所述层间绝缘层的过孔与所述有源层电连接。
  6. 一种如权利要求1-5任一项所述的显示基板的制作方法，其中，包括：
    在衬底基板上形成有源层的图形；
    在所述有源层的图形上依次形成绝缘薄膜和栅极金属薄膜；
    采用半曝光光刻工艺，在所述栅极金属薄膜上形成图案化的光刻胶层；
    利用图案化的光刻胶层的遮挡，对所述栅极金属薄膜进行刻蚀，形成包括栅极和第一走线的栅极金属层的图形；
    利用图案化的光刻胶层的遮挡，对所述绝缘薄膜进行干法刻蚀，形成包括第一分部和第二分部的栅绝缘层的图形，并去除所述光刻胶层；
    在所述栅绝缘层的图形上形成包括源漏极和第二走线的源漏极金属层的图形。
  7. 如权利要求6所述的方法，其中，采用半曝光光刻工艺，在所述栅极金属薄膜上形成图案化的光刻胶层，包括：
    在所述栅极金属薄膜上形成正性光刻胶薄膜；
    采用半色调掩模板或灰色调掩模板，对所述正性光刻胶薄膜进行曝光显影处理，得到的光刻胶层的图形中，在将要形成的栅极之上的部分具有第一厚度，在将要形成的第一走线和第二走线之间交叠区域的部分具有第二厚度，所述第一厚度大于所述第二厚度。
  8. 如权利要求7所述的方法，其中，所述半色调掩膜板或灰色调掩模板包括完全透光区域和部分透光区域；所述完全透光区域对应于所述光刻胶层中的第一厚度，所述部分透光区域对应于所述光刻胶层中的第二厚度。
  9. 如权利要求7所述的方法，其中，所述第二厚度小于或等于所述第一厚度的一半。
  10. 如权利要求6-9任一所述的方法，其中，在所述栅绝缘层的图形上形成包括源漏极和第二走线的源漏极金属层的图形之前，还包括：
    在所述栅绝缘层的图形上形成具有过孔的层间绝缘层，以使将要形成的 源漏极通过所述过孔与所述有源层电连接。
  11. 一种显示面板，其中，包括如权利要求1-5任一所述的显示基板。
  12. 一种显示装置，其中，包括如权利要求11所述的显示面板。
PCT/CN2020/096162 2019-06-19 2020-06-15 显示基板、其制作方法、显示面板及显示装置 WO2020253652A1 (zh)

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