WO2023164961A1 - 指纹采集器件、显示面板 - Google Patents

指纹采集器件、显示面板 Download PDF

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Publication number
WO2023164961A1
WO2023164961A1 PCT/CN2022/080189 CN2022080189W WO2023164961A1 WO 2023164961 A1 WO2023164961 A1 WO 2023164961A1 CN 2022080189 W CN2022080189 W CN 2022080189W WO 2023164961 A1 WO2023164961 A1 WO 2023164961A1
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WO
WIPO (PCT)
Prior art keywords
layer
light
base substrate
away
via hole
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Application number
PCT/CN2022/080189
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English (en)
French (fr)
Inventor
龚帆
艾飞
宋继越
宋德伟
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武汉华星光电技术有限公司
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Priority to US17/769,396 priority Critical patent/US20240233433A9/en
Publication of WO2023164961A1 publication Critical patent/WO2023164961A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02162—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
    • H01L31/02164—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors for shielding light, e.g. light blocking layers, cold shields for infrared detectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present application relates to the field of display technology, in particular to a fingerprint collection device and a display panel.
  • optical fingerprints use the difference in light reflection between finger valleys and ridges to convert optical signals into electrical signals to achieve the purpose of fingerprint identification.
  • the current fingerprint acquisition devices have many manufacturing processes, resulting in high costs.
  • Embodiments of the present application provide a fingerprint collection device and a display panel to solve the technical problem that the existing fingerprint collection device has many manufacturing processes, resulting in high cost.
  • the fingerprint acquisition device provided according to the application includes:
  • the driving circuit layer is arranged on one side of the base substrate, the driving circuit layer includes a control transistor and a plurality of signal wires, and the control transistor includes gates stacked in sequence along a direction away from the base substrate, A gate insulating layer, an active layer, and a source-drain metal layer, and the plurality of signal wires include a first signal wire arranged on the same layer as the gate and a first signal wire arranged on the same layer as the source-drain metal layer.
  • the source-drain metal layer includes a source and a drain, the drain is electrically connected to the photodiode, and the source is electrically connected to the second signal wire;
  • An electrode layer is arranged on the side of the second passivation layer away from the base substrate, the electrode layer includes a first electrode part and a second electrode part, and the first electrode part passes through the second passivation layer.
  • the second via hole in the layer is electrically connected to the photodiode, and the second electrode part is electrically connected to the first signal trace and the second signal trace through the third via hole and the fourth via hole respectively.
  • the third via hole penetrates the second passivation layer, the first passivation layer and the gate insulating layer, and the fourth via hole penetrates the second passivation layer and the gate insulating layer. the first passivation layer.
  • the material of the active layer is amorphous silicon; the control transistor further includes an ohmic contact layer, and the ohmic contact layer is arranged on the active layer away from the base substrate. side.
  • the fingerprint collection device further includes a light-shielding layer, the light-shielding layer is disposed on the side of the first passivation layer away from the base substrate and is disposed corresponding to the control transistor;
  • the light-shielding layer is set on the same layer as the photodiode.
  • the light-shielding layer at least includes a first light-shielding layer and a second light-shielding layer that are stacked in sequence
  • the photodiode includes at least a first semiconductor layer and an intrinsic semiconductor layer that are stacked in sequence
  • the first light-shielding layer is set on the same layer as the first semiconductor layer
  • the second light-shielding layer is set on the same layer as the intrinsic semiconductor layer.
  • the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate.
  • the light-shielding layer further includes a third light-shielding layer, and the third light-shielding layer is arranged on the side of the second light-shielding layer away from the base substrate;
  • the photodiode also includes A second semiconductor layer, the second semiconductor layer is disposed on a side of the intrinsic semiconductor layer away from the base substrate, and the third light-shielding layer is disposed on the same layer as the second semiconductor layer.
  • the material of the active layer is metal oxide.
  • the electrode layer further includes a third electrode part
  • the driving circuit layer further includes a binding terminal provided on the same layer as the source-drain metal layer
  • the third electrode part passes through The fifth via hole penetrating through the second passivation layer is electrically connected to the bonding terminal.
  • the application provides a fingerprint collection device, including:
  • the driving circuit layer is arranged on one side of the base substrate, the driving circuit layer includes a control transistor and a plurality of signal wires, and the control transistor includes gates stacked in sequence along a direction away from the base substrate, A gate insulating layer, an active layer, and a source-drain metal layer, and the plurality of signal wires include a first signal wire arranged on the same layer as the gate and a first signal wire arranged on the same layer as the source-drain metal layer.
  • a photodiode disposed on a side of the first passivation layer away from the base substrate, the photodiode is electrically connected to the control transistor through a first via hole penetrating through the first passivation layer;
  • An electrode layer is arranged on the side of the second passivation layer away from the base substrate, the electrode layer includes a first electrode part and a second electrode part, and the first electrode part passes through the second passivation layer.
  • the second via hole in the layer is electrically connected to the photodiode, and the second electrode part is electrically connected to the first signal trace and the second signal trace through the third via hole and the fourth via hole respectively.
  • the third via hole penetrates the second passivation layer, the first passivation layer and the gate insulating layer, and the fourth via hole penetrates the second passivation layer and the gate insulating layer. the first passivation layer.
  • the material of the active layer is amorphous silicon; the control transistor further includes an ohmic contact layer, and the ohmic contact layer is arranged on the active layer away from the base substrate. side.
  • the fingerprint collection device further includes a light-shielding layer, the light-shielding layer is disposed on the side of the first passivation layer away from the base substrate and is disposed corresponding to the control transistor;
  • the light-shielding layer is set on the same layer as the photodiode.
  • the light-shielding layer at least includes a first light-shielding layer and a second light-shielding layer that are stacked in sequence
  • the photodiode includes at least a first semiconductor layer and an intrinsic semiconductor layer that are stacked in sequence
  • the first light-shielding layer is set on the same layer as the first semiconductor layer
  • the second light-shielding layer is set on the same layer as the intrinsic semiconductor layer.
  • the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the active layer on the substrate.
  • the light-shielding layer further includes a third light-shielding layer, and the third light-shielding layer is arranged on the side of the second light-shielding layer away from the base substrate;
  • the photodiode also includes A second semiconductor layer, the second semiconductor layer is disposed on a side of the intrinsic semiconductor layer away from the base substrate, and the third light-shielding layer is disposed on the same layer as the second semiconductor layer.
  • the first semiconductor layer is an N-type semiconductor layer
  • the second semiconductor layer is a P-type semiconductor layer.
  • the material of the active layer is metal oxide.
  • the electrode layer further includes a third electrode part
  • the driving circuit layer further includes a binding terminal provided on the same layer as the source-drain metal layer
  • the third electrode part passes through The fifth via hole penetrating through the second passivation layer is electrically connected to the bonding terminal.
  • the present application provides a display panel, including the above-mentioned fingerprint acquisition device
  • the panel body, the optical path structure is arranged on the non-display surface side of the panel body, and the fingerprint collection device is arranged on the side of the optical path structure away from the panel body;
  • the fingerprint collection device includes:
  • the driving circuit layer is arranged on one side of the base substrate, the driving circuit layer includes a control transistor and a plurality of signal wires, and the control transistor includes gates stacked in sequence along a direction away from the base substrate, A gate insulating layer, an active layer, and a source-drain metal layer, and the plurality of signal wires include a first signal wire arranged on the same layer as the gate and a first signal wire arranged on the same layer as the source-drain metal layer.
  • a photodiode disposed on a side of the first passivation layer away from the base substrate, the photodiode is electrically connected to the control transistor through a first via hole penetrating through the first passivation layer;
  • An electrode layer is arranged on the side of the second passivation layer away from the base substrate, the electrode layer includes a first electrode part and a second electrode part, and the first electrode part passes through the second passivation layer.
  • the second via hole in the layer is electrically connected to the photodiode, and the second electrode part is electrically connected to the first signal trace and the second signal trace through the third via hole and the fourth via hole respectively.
  • the third via hole penetrates the second passivation layer, the first passivation layer and the gate insulating layer
  • the fourth via hole penetrates the second passivation layer and the gate insulating layer. the first passivation layer.
  • the base substrate is located on a side of the optical path structure away from the panel body;
  • the driving circuit layer is located on a side of the base substrate away from the panel body;
  • the first passivation layer covers the side of the driving circuit layer away from the panel main body;
  • the photodiode is located on a side of the first passivation layer away from the panel body;
  • the second passivation layer covers the side of the photodiode away from the panel main body;
  • the electrode layer is located on a side of the second passivation layer away from the panel main body.
  • the fingerprint collection device further includes a light-shielding layer, the light-shielding layer is located on the side of the first passivation layer away from the panel main body and is arranged corresponding to the control transistor of the driving circuit layer ;
  • the light-shielding layer is set on the same layer as the photodiode.
  • the fingerprint acquisition device includes a base substrate, a driving circuit layer, a first passivation layer, a photodiode, a second passivation layer and an electrode layer, and the electrode layer
  • the first electrode portion of the first electrode is electrically connected to the photodiode through the second via hole penetrating through the second passivation layer.
  • the driving circuit layer includes a control transistor and a plurality of signal traces, and the first signal trace and the gate of the control transistor are arranged on the same layer.
  • the second signal trace is set on the same layer as the source-drain metal layer of the control transistor; compared with the prior art, the first signal trace and the second signal trace are electrically connected through a via hole penetrating the gate insulating layer,
  • the second electrode portion of the electrode layer in this application is electrically connected to the first signal trace and the second signal trace respectively through the third via hole and the fourth via hole to form a bridge structure, and the third via hole penetrates the second passivation layer , the first passivation layer and the gate insulating layer, and the fourth via hole penetrates the second passivation layer and the first passivation layer, because the third via hole and the fourth via hole are prepared by the same process as the second via hole , so that one process can be saved, which is beneficial to cost saving.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first fingerprint acquisition device provided in an embodiment of the present application
  • Fig. 2 is a schematic cross-sectional structure diagram of a second fingerprint collection device provided in an embodiment of the present application
  • Fig. 3 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a flow chart of a method for manufacturing a fingerprint collection device provided in an embodiment of the present application
  • FIG. 4A to FIG. 4K are schematic flow charts of a manufacturing method of a fingerprint acquisition device provided in an embodiment of the present application.
  • Fingerprint collection device 100.
  • Optical path structure 300.
  • Panel main body 300.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first fingerprint collection device provided in an embodiment of the present application.
  • the fingerprint acquisition device 100 provided in the embodiment of the present application includes a base substrate 10, a driving circuit layer 20, a first passivation layer 30, a photodiode 40, a second passivation layer 60, and an electrode layer 70.
  • the driving circuit layer 20 It is arranged on one side of the base substrate 10, the first passivation layer 30 covers the side of the driving circuit layer 20 away from the base substrate 10, and the photodiode 40 is arranged on the first passivation layer 30.
  • the passivation layer 30 is away from the side of the base substrate 10
  • the second passivation layer 60 covers the side of the photodiode 40 away from the base substrate 10
  • the electrode layer 70 is arranged on the first passivation layer 60.
  • the second passivation layer 60 is away from the side of the base substrate 10 .
  • the driving circuit layer 20 includes a control transistor 20a and a plurality of signal wires 20b, the photodiode 40 is electrically connected to the control transistor 20a through a first via hole 601 penetrating through the first passivation layer 30, the
  • the electrode layer 70 includes a first electrode portion 701, a second electrode portion 702 and a third electrode portion 703, the first electrode portion 701 is connected to the photodiode through the second via hole 602 penetrating through the second passivation layer 60 40 electrical connections.
  • the control transistor 20a includes a gate 201, a gate insulating layer 203, an active layer 204, and a source-drain metal layer 206 that are sequentially stacked.
  • the first signal wiring 202 and the second signal wiring 207 provided on the same layer as the source-drain metal layer 206, the second electrode part 702 is respectively connected to the said second via hole 603 and the fourth via hole 604.
  • the first signal trace 202 and the second signal trace 207 are electrically connected to form a bridge structure 20c, and the third via hole 603 penetrates through the second passivation layer 60, the first passivation layer 30 and the The gate insulating layer 203 , the fourth via hole 604 penetrates through the second passivation layer 60 and the first passivation layer 30 .
  • the present application passes the second electrode part 702 of the electrode layer 70 through the third
  • the via hole 603 and the fourth via hole 604 are respectively electrically connected to the first signal trace 202 and the second signal trace 207 to form a bridge structure 20c, since the third via hole 603 and the fourth via hole 604 pass through the second via hole 602
  • the same process is prepared and formed, thereby saving one process and helping to save costs.
  • the source-drain metal layer 206 includes a source and a drain, the cathode of the photodiode 40 is electrically connected to the drain, and the anode of the photodiode 40 is grounded.
  • the source can be electrically connected to the second signal wire 207
  • the gate 201 of the control transistor 20 a is electrically connected to the first signal wire 202 .
  • the first signal wiring 202 can be a scanning signal wiring
  • the second signal wiring 207 can be a data signal wiring
  • the first signal wiring 202 needs to be connected to the second signal wiring by a jumper.
  • After 207 it is electrically connected with a driving chip (not shown in the figure), and the driving chip transmits signals to the first signal wiring 202 and the second signal wiring 207 .
  • the fingerprint collection device 100 When a finger presses the fingerprint collection device 100, the reflected light intensities of the valleys and ridges of the fingerprint are inconsistent, so that the voltage drop generated at both ends of the photodiode 40 is different, and then the photodiode 40 will generate different current values, so The fingerprint collection device 100 can identify the corresponding positions of valleys and ridges according to different current values, that is, obtain the fingerprint information of the subject.
  • the gate 201 of the control transistor 20a when the gate 201 of the control transistor 20a is turned on, a potential V1 is charged to the negative terminal of the photodiode 40 first, and then the gate 201 of the control transistor 20a is turned off, this , the drain potential of the control transistor 20a is V1, and the photodiode 40 is in the reverse bias state at this moment; Photodiode 40, photons will cause the current value of the photodiode 40 reversely biased to change, because the light intensity of the valleys and ridges is different, the change of the current value is different; when the gate 201 of the photodiode 40 is turned on again , the drain of the control transistor 20a will output different current values, and finally, different current values can be obtained by reading the second signal trace 207, so as to facilitate subsequent identification of the corresponding positions of valleys and ridges, that is, The subject's fingerprint information.
  • the base substrate 10 is a glass substrate. Compared with the fingerprint collection device 100 in the prior art that uses a single crystal silicon substrate 10, the cost of the glass substrate is reduced, which is beneficial to saving costs.
  • the photodiode 40 at least includes a first semiconductor layer 401 and an intrinsic semiconductor layer 402 stacked in sequence.
  • the intrinsic semiconductor layer 402 is an undoped layer. Under the action of a reverse bias voltage, the intrinsic semiconductor layer 402 It is depleted to become a light absorption region, so that the photodiode 40 has a higher quantum efficiency and a shorter response time.
  • the photodiode 40 includes the first semiconductor layer 401 and the intrinsic semiconductor layer 402, and the first semiconductor layer 401 may be an N-type semiconductor layer.
  • the material of the first semiconductor layer 401 is N+a-Si (amorphous silicon), and the material of the intrinsic semiconductor layer 402 is amorphous silicon a-Si.
  • the photodiode 40 includes the first semiconductor layer 401, the intrinsic semiconductor layer 402, and a second semiconductor layer (not shown in the figure) stacked in sequence, and the second semiconductor layer Located on the side of the intrinsic semiconductor layer 402 away from the base substrate 10 , the first semiconductor layer 401 is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.
  • the material of the first semiconductor layer 401 is N+a-Si (amorphous silicon)
  • the material of the intrinsic semiconductor layer 402 is amorphous silicon a-Si
  • the material of the second semiconductor layer is P+a -Si.
  • the fingerprint collection device 100 in the prior art uses a silicon-based substrate.
  • the silicon-based substrate is usually a plug-in type.
  • the fingerprint recognition area on the screen is only about the size of a thumb.
  • the fingerprint recognition area is relatively small and increases.
  • the size of the fingerprint identification area will increase the cost of fingerprint identification.
  • the material of the active layer 204 is amorphous silicon a-Si, which can realize large-area fabrication on the display panel, and selectively open holes in any area of the screen as a fingerprint identification area , can realize the identification of single-region and multi-region optical fingerprints, and the cost is greatly reduced.
  • the control transistor 20a further includes an ohmic contact layer 205, the ohmic contact layer 205 is disposed on the side of the active layer 204 away from the base substrate 10, the ohmic contact layer 205 is located on the active layer 204 and between the source and drain metal layer 206 .
  • the material of the ohmic contact layer 205 may be N+a-Si, and N+a-Si refers to the use of N-type doped a-Si material.
  • the electrode layer 70 is multiplexed as a common electrode, the electrode layer 70 is a transparent electrode layer 70 , and the material of the electrode layer 70 includes ITO (Indium tin oxide, indium tin oxide).
  • amorphous silicon a-Si has strong absorption of visible light, when visible light irradiates on the active layer 204, it will cause interference to the active layer 204, causing the control transistor 20a performance drops, thus affecting the sensitivity of the fingerprint collection device 100 .
  • the fingerprint collection device 100 further includes a light-shielding layer 50, and the light-shielding layer 50 is disposed on the side of the first passivation layer 30 away from the base substrate 10 and in contact with
  • the control transistor 20a is arranged correspondingly; the light-shielding layer 50 is set on the same layer as the photodiode 40, so that the light-shielding layer 50 and the photodiode 40 can be formed through the same patterning process, which can simplify
  • the manufacturing process of the fingerprint collection device 100 is beneficial to further reduce the cost.
  • the light-shielding layer 50 includes at least a first light-shielding layer 501 and a second light-shielding layer 502 stacked in sequence
  • the photodiode 40 includes at least a first semiconductor layer 401 and an intrinsic semiconductor layer stacked in sequence. layer 402 ; the first light-shielding layer 501 is set on the same layer as the first semiconductor layer 401 , and the second light-shielding layer 502 is set on the same layer as the intrinsic semiconductor layer 402 .
  • the first light-shielding layer 501 and the first semiconductor layer 401 are formed through the same patterning process, and the second light-shielding layer 502 and the intrinsic semiconductor layer 402 are formed through the same patterning process. While controlling the transistor 20a to realize the light-shielding effect, the manufacturing process of the fingerprint collection device 100 can be simplified, which is beneficial to further reduce the cost.
  • the first light-shielding layer 501 is made of the same material as the first semiconductor layer 401, and N+a-Si (amorphous silicon) can be used, and the second light-shielding layer 502 and the intrinsic semiconductor layer 402 The material is the same, and amorphous silicon a-Si can be used. Since amorphous silicon has a strong absorption capacity for visible light, it can absorb incident light and reflected light reflected by fingers to the light-shielding layer 50, thereby preventing light from irradiating the light-shielding layer 50.
  • the control transistor 20a avoids adverse effects on the performance of the control transistor 20a.
  • the thickness of the first light-shielding layer 501 is the same as that of the first semiconductor layer 401
  • the thickness of the second light-shielding layer 502 is the same as that of the second semiconductor layer.
  • the light-shielding layer 50 may further include a third light-shielding layer, and the third light-shielding layer is disposed on The second light-shielding layer 502 is away from the side of the base substrate 10 , and the first light-shielding layer 501 , the second light-shielding layer 502 and the third light-shielding layer are along a direction away from the base substrate 10 Cascade settings one by one.
  • the third light-shielding layer and the second semiconductor layer are arranged in the same layer, that is, the third light-shielding layer and the second semiconductor layer are formed through the same patterning process, and the third light-shielding layer and the second semiconductor layer
  • the materials of the semiconductor layers are the same, and P+a-Si can be used.
  • the orthographic projection of the shading layer 50 on the base substrate 10 covers the orthographic projection of the control transistor 20a on the base substrate 10, further, the The orthographic projection of the light-shielding layer 50 on the base substrate 10 covers the orthographic projection of the active layer 204 on the base substrate 10 , further, the light-shielding layer 50 on the base substrate 10 The orthographic projection coincides with the orthographic projection of the active layer 204 on the base substrate 10 .
  • FIG. 2 is a schematic cross-sectional structure diagram of a second fingerprint collection device provided in an embodiment of the present application.
  • the difference between FIG. 2 and FIG. 1 is that the active layer 204
  • the material is metal oxide.
  • the material of the active layer 204 may include IGZO (Indium gallium zinc oxide, indium gallium zinc oxide), IZO (Indium tin oxide, indium zinc oxide), ITZO (Indium gallium tin oxide, indium tin zinc oxide) and ZnO (Zinc oxide, zinc oxide).
  • the fingerprint collection device 100 can be fabricated in a large area on the display panel, and holes can be selectively opened in any area of the screen as a fingerprint identification area, which can realize The cost of single-region and multi-region optical fingerprint recognition is greatly reduced.
  • metal oxides do not absorb visible light, when the incident light and the reflected light reflected by the finger to the light-shielding layer 50 irradiate the control transistor 20a, there will be no damage to the control transistor 20a.
  • the active layer 204 interferes without adversely affecting the performance of the control transistor 20a. Therefore, in the embodiment of the present application, the fingerprint collection device 100 does not need to arrange the light shielding layer 50 above the control transistor 20a.
  • the driving circuit layer 20 also includes a binding terminal 208 provided on the same layer as the source-drain metal layer 206 for binding connection with the driving chip, and the third electrode part 703 passes through the second
  • the fifth via hole 605 of the passivation layer 60 is electrically connected to the binding terminal 208, and the driving chip is configured to apply a driving voltage to the third electrode portion 703 to drive the fingerprint collection device 100 for fingerprint recognition .
  • the second via hole 602 , the third via hole 603 , the fourth via hole 604 and the fifth via hole 605 are manufactured through the same yellow light process, which is beneficial to reduce the process and cost.
  • Fig. 3 is a schematic cross-sectional structure diagram of a display panel provided by the embodiment of the present application; the embodiment of the present application also provides a display panel, the display panel includes the fingerprint collection device 100 in the above embodiment , the display panel can realize the identification of single-region and multi-region optical fingerprints; the display panel also includes an optical path structure 200 and a panel main body 300, and the optical path structure 200 is arranged on the non-display surface side of the panel main body 300, so
  • the fingerprint collection device 100 is arranged on the side of the optical path structure 200 away from the panel main body 300, that is, the optical path structure 200 is arranged on the light-incident side of the fingerprint collection device 100, and the optical path structure 200 includes an optical fiber guide Straight layer, to play a collimation role, when performing fingerprint identification, the finger is pressed on the display surface side of the panel body 300, and the light reflected by the finger passes through the optical path structure 200 and then gathers to the fingerprint acquisition device 100, the fingerprint collection device 100 can simultaneously receive the
  • the fingerprint collection device 100 has a flip-chip structure relative to the panel body 300 and the optical path structure 200.
  • the fingerprint collection device 100 includes a base substrate 10, a driving circuit layer 20, The first passivation layer 30, the photodiode 40, the second passivation layer 60 and the electrode layer 70; wherein, the base substrate 10 is located on the side of the optical path structure 200 away from the panel main body 300; the driving circuit The layer 20 is located on the side of the base substrate 10 away from the panel body 300; the first passivation layer 30 is covered on the side of the driving circuit layer 20 away from the panel body 300; the photodiode 40 Located on the side of the first passivation layer 30 away from the panel body 300; the second passivation layer 60 covers the side of the photodiode 40 away from the panel body 300; the electrode layer 70 is located The side of the second passivation layer 60 away from the panel main body 300 .
  • the fingerprint collection device 100 also includes a light-shielding layer 50, and the light-shielding layer 50 is used to block the external light away from the side of the optical path structure 200, so as to prevent it from mixing with the light reflected from the finger and causing damage to the fingerprint collection device 100.
  • the normal recognition of the device causes interference.
  • the light-shielding layer 50 is located on the side of the first passivation layer 30 away from the panel body 300 and is arranged corresponding to the control transistor 20a of the driving circuit layer 20; The diode 40 is arranged on the same layer.
  • Fig. 3 is the flow chart of the preparation method of a kind of fingerprint collection device provided by the embodiment of the application;
  • Fig. 4A ⁇ Fig. 4K is a kind of fingerprint collection device provided by the embodiment of the application Schematic diagram of the process structure of the preparation method.
  • the embodiment of the present application also provides a method for preparing a fingerprint collection device, including the following steps:
  • Step S10 providing a base substrate 10 .
  • the base substrate 10 is a glass substrate.
  • Step S20 Form a driving circuit layer 20 on one side of the base substrate 10, the driving circuit layer 20 includes a control transistor 20a and a plurality of signal traces, and the control transistor 20a includes a
  • the gate 201, the gate insulating layer 203, the active layer 204 and the source-drain metal layer 206 are stacked in sequence, and the plurality of signal traces include the first signal trace disposed on the same layer as the gate 201 202 and the second signal wiring 207 provided on the same layer as the source-drain metal layer 206 .
  • step S20 includes the following steps:
  • Step S201 forming the gate 201 and the first signal wiring 202 on the base substrate 10 .
  • a layer of gate material is deposited on the substrate 10, and a yellow light process is used to expose, develop and etch the gate material to form the gate 201 and the gate 201.
  • the first signal wire 202 is a layer of gate material deposited on the substrate 10, and a yellow light process is used to expose, develop and etch the gate material to form the gate 201 and the gate 201.
  • the first signal wire 202 is a yellow light process used to expose, develop and etch the gate material to form the gate 201 and the gate 201.
  • Step S202 forming a gate insulating layer 203 covering the gate 201 and the first signal trace 202 .
  • a layer of inorganic material is deposited on the base substrate 10 , the gate 201 and the first signal wiring 202 to form the gate insulating layer 203 , and the inorganic material can be nitrogen.
  • the inorganic material can be nitrogen.
  • Step S203 forming the active layer 204 on the side of the gate insulating layer 203 away from the base substrate 10 .
  • a layer of active layer material is deposited on the gate insulating layer 203; then, a yellow light process is used to expose, develop and etch the active layer material to form the active layer.
  • source layer 204 a layer of active layer material is deposited on the gate insulating layer 203; then, a yellow light process is used to expose, develop and etch the active layer material to form the active layer.
  • source layer 204 the material of the active layer 204 is amorphous silicon a-Si as an example for illustration;
  • the step S103 further includes: forming an ohmic contact layer 205 on the side of the active layer 204 away from the base substrate 10, the material of the ohmic contact layer 205 is N+a-Si, the The ohmic contact layer 205 and the active layer 204 are prepared by the same yellow light process.
  • Step S204 forming the source-drain metal layer 206 , the second signal trace 207 and the bonding terminal 208 on the side of the active layer 204 away from the substrate 10 .
  • Source-drain metal layer material on the active layer 204, specifically, form a layer covering the gate insulating layer 203, the active layer 204 and the ohmic contact layer.
  • source and drain metal layer materials then, use a yellow light process to expose, develop and etch the source and drain metal layer materials to form the source and drain metal layer 206 and the second signal wiring 207 and the binding terminal 208.
  • the source-drain metal layer 206 includes a source and a drain, and a channel is formed between the source and the drain.
  • the material of the source-drain metal layer 206 , the second signal wire 207 and the binding terminal 208 is N+a-Si.
  • Step S30 forming a first passivation layer 30 covering a side of the driving circuit layer 20 away from the base substrate 10 .
  • the first passivation layer 30 is deposited and formed on the gate insulating layer 203 , the source-drain metal layer 206 , the second signal wire 207 and the channel.
  • a material of the passivation layer 30 can be one of silicon nitride, silicon oxide or silicon oxynitride.
  • Step S40 forming a first via hole 601 penetrating through the first passivation layer 30 .
  • the first passivation layer 30 is exposed, developed and etched using a yellow light process to form a first via hole 601 penetrating through the first passivation layer 30 .
  • Step S50 forming a photodiode 40 on a side of the first passivation layer 30 away from the base substrate 10 , the photodiode 40 is electrically connected to the control transistor 20 a through the first via hole 601 .
  • step S50 includes the following steps:
  • Step S501 forming a first semiconductor layer 401 and an intrinsic semiconductor layer 402 in the first passivation layer 30 and the first via hole 601 .
  • the material of the first semiconductor layer 401 may be N+a-Si, and the material of the intrinsic semiconductor layer 402 may be amorphous silicon a-Si.
  • the step S501 further includes: forming a light-shielding layer 50 on a side of the first passivation layer 30 away from the base substrate 10, the light-shielding layer 50 is arranged corresponding to the control transistor 20a, the The light shielding layer 50 is formed by the same process as the photodiode 40 .
  • a stacked first light-shielding layer 501 and a second light-shielding layer 502 are formed on the side of the first passivation layer 30 away from the base substrate 10 .
  • the first light-shielding layer 501 is set on the same layer as the first semiconductor layer 401
  • the second light-shielding layer 502 is set on the same layer as the intrinsic semiconductor layer 402
  • the material of the first light-shielding layer 501 can be N +a-Si
  • the material of the intrinsic semiconductor layer 402 may be amorphous silicon a-Si.
  • the first light-shielding layer 501 and the second light-shielding layer 502 are prepared by the same yellow light process as the first semiconductor layer 401 and the intrinsic semiconductor layer 402 .
  • Step S60 forming a second passivation layer 60 covering the side of the photodiode 40 away from the base substrate 10 .
  • the second passivation layer 60 is deposited and formed on the first passivation layer 30 , the second light-shielding layer 502 and the intrinsic semiconductor layer 402 , and the second passivation layer 60
  • the material can be one of silicon nitride, silicon oxide or silicon oxynitride.
  • Step S70 forming a second via hole 602, a third via hole 603 and a fourth via hole 604, the second via hole 602 penetrates the second passivation layer 60, the third via hole 603 penetrates the first via hole The second passivation layer 60 , the first passivation layer 30 and the gate insulating layer 203 , the fourth via hole 604 penetrates through the second passivation layer 60 and the first passivation layer 30 .
  • the second passivation layer 60 is exposed, developed and etched using a yellow light process to form the second via hole 602 , the third via hole 603 and the fourth via hole 602 .
  • the via hole 604 since the third via hole 603, the fourth via hole 604 and the second via hole 602 are formed through the same process, a process can be saved, which is beneficial to saving costs.
  • the step S70 further includes: forming a fifth via hole 605 penetrating through the second passivation layer 60 .
  • the second via hole 602 , the third via hole 603 , the fourth via hole 604 and the fifth via hole 605 are manufactured through the same yellow light process, which is beneficial to reduce the process and cost.
  • Step S80 forming an electrode layer 70 on the side of the second passivation layer 60 away from the base substrate 10, the electrode layer 70 includes a first electrode part 701 and a second electrode part 702, the first electrode Part 701 is electrically connected to the photodiode 40 by passing through the second via hole 602, and the second electrode part 702 is connected to the first signal via the third via hole 603 and the fourth via hole 604 respectively.
  • the wiring 202 is electrically connected to the second signal wiring 207 to form a bridge structure 20c.
  • a layer of electrode material is deposited on the second passivation layer 60, and the electrode material covers the second passivation layer 60, the second via hole 602, the The third via hole 603 , the fourth via hole 604 and the fifth via hole 605 ; then, the electrode material is exposed, developed and etched using a yellow light process to form the electrode layer 70 .
  • the material of the electrode layer 70 includes ITO.
  • the method for manufacturing the fingerprint collection device 100 requires a total of 7 yellow light processes to complete the preparation of the fingerprint collection device 100, specifically: the gate 201/the first signal wiring 202/the binding terminal 208, the active layer 204/the ohmic contact layer 205, the source-drain metal layer 206/the second signal wiring 207/the binding terminal 208, the The first via hole 601, the photodiode 40/the light shielding layer 50, the second via hole 602/the third via hole 603/the fourth via hole 604/the fifth via hole 605,
  • the electrode layer 70 requires fewer manufacturing processes, which is beneficial to reduce costs.
  • the active layer 204 in the fingerprint acquisition device 100 in this application is made of amorphous silicon, which can be fabricated on a large area of the display panel, and can selectively open holes in any area of the screen as a fingerprint identification area. The identification of single-region and multi-region optical fingerprints can be realized, and the cost is greatly reduced.
  • the fingerprint collection device includes a substrate, a driving circuit layer, a first passivation layer, a photodiode, a second passivation layer and an electrode layer, and the electrode layer
  • the first electrode portion is electrically connected to the photodiode through the second via hole penetrating through the second passivation layer.
  • the driving circuit layer includes a control transistor and a plurality of signal traces. The first signal trace is arranged on the same layer as the gate of the control transistor.
  • the second signal trace is set on the same layer as the source-drain metal layer of the control transistor; compared with the prior art where the first signal trace and the second signal trace are electrically connected through a via hole penetrating the gate insulating layer, this invention
  • the second electrode portion of the electrode layer in the application is electrically connected to the first signal trace and the second signal trace respectively through the third via hole and the fourth via hole to form a bridge structure, and the third via hole penetrates the second passivation layer,
  • the first passivation layer and the gate insulating layer, the fourth via hole penetrates through the second passivation layer and the first passivation layer, since the third via hole and the fourth via hole are formed through the same process as the second via hole,
  • one process can be saved, which is beneficial to cost saving.

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Abstract

一种指纹采集器件（100）、显示面板，指纹采集器件（100）包括驱动电路层（20）、第一钝化层（30）、光电二极管（40）、第二钝化层（60）和电极层（70），第一电极部（701）通过第二过孔（602）与光电二极管（40）电连接，第二电极部（702）通过第三过孔（603）与第四过孔（604）分别与第一信号走线（202）和第二信号走线（207）电连接形成桥接结构（20c），第三过孔（603）与第四过孔（604）与第二过孔（602）通过同一道制程制备，节省了制程。

Description

指纹采集器件、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种指纹采集器件、显示面板。
 背景技术
随着面板产业的迅猛发展，除了对显示器高分辨、宽视角、低功耗等要求外，丰富面板功能和增加人机互动是目前显示面板的主要发展方向之一。其中光学指纹是利用手指谷和脊对光反射的差异，把光信号转成电信号达到指纹识别的目的，然而，目前的指纹采集器件的制程较多，导致成本较高。
 技术问题
本申请实施例提供一种指纹采集器件、显示面板，以解决现有的指纹采集器件的制程较多，导致成本较高的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
根据本申请提供的指纹采集器件，包括：
衬底基板；
驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括控制晶体管和多条信号走线，所述控制晶体管包括沿远离所述衬底基板的方向依次层叠设置的栅极、栅极绝缘层、有源层和源漏极金属层，多条所述信号走线包括与所述栅极同层设置的第一信号走线及与所述源漏极金属层同层设置的第二信号走线；
第一钝化层，覆于所述驱动电路层远离所述衬底基板的一侧；
光电二极管，设置于所述第一钝化层远离所述衬底基板的一侧，所述光电二极管通过贯穿所述第一钝化层的第一过孔与所述控制晶体管电连接，所述源漏极金属层包括源极和漏极，所述漏极与所述光电二极管电连接，所述源极与所述第二信号走线电连接；
第二钝化层，覆于所述光电二极管远离所述衬底基板的一侧；以及
电极层，设置于所述第二钝化层远离所述衬底基板的一侧，所述电极层包括第一电极部和第二电极部，所述第一电极部通过贯穿所述第二钝化层的第二过孔与所述光电二极管电连接，所述第二电极部通过第三过孔及第四过孔分别与所述第一信号走线和所述第二信号走线电连接形成桥接结构，所述第三过孔贯穿所述第二钝化层、所述第一钝化层和所述栅极绝缘层，所述第四过孔贯穿所述第二钝化层和所述第一钝化层。
根据本申请提供的指纹采集器件，所述有源层的材料为非晶硅；所述控制晶体管还包括欧姆接触层，所述欧姆接触层设置于所述有源层远离所述衬底基板的一侧。
根据本申请提供的指纹采集器件，所述指纹采集器件还包括遮光层，所述遮光层设置于所述第一钝化层远离所述衬底基板的一侧且与所述控制晶体管对应设置；所述遮光层与所述光电二极管同层设置。
根据本申请提供的指纹采集器件，所述遮光层至少包括依次层叠设置的第一遮光层和第二遮光层，所述光电二极管至少包括依次层叠设置的第一半导体层和本征半导体层；所述第一遮光层与所述第一半导体层同层设置，所述第二遮光层与所述本征半导体层同层设置。
根据本申请提供的指纹采集器件，所述遮光层在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
根据本申请提供的指纹采集器件，所述遮光层还包括第三遮光层，所述第三遮光层设置于所述第二遮光层远离所述衬底基板的一侧；所述光电二极管还包括第二半导体层，所述第二半导体层设置于所述本征半导体层远离所述衬底基板的一侧，所述第三遮光层与所述第二半导体层同层设置。
根据本申请提供的指纹采集器件，所述有源层的材料为金属氧化物。
根据本申请提供的指纹采集器件，所述电极层还包括第三电极部，所述驱动电路层还包括与所述源漏极金属层同层设置的绑定端子，所述第三电极部通过贯穿所述第二钝化层的第五过孔与所述绑定端子电连接。
本申请提供一种指纹采集器件，包括：
衬底基板；
驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括控制晶体管和多条信号走线，所述控制晶体管包括沿远离所述衬底基板的方向依次层叠设置的栅极、栅极绝缘层、有源层和源漏极金属层，多条所述信号走线包括与所述栅极同层设置的第一信号走线及与所述源漏极金属层同层设置的第二信号走线；
第一钝化层，覆于所述驱动电路层远离所述衬底基板的一侧；
光电二极管，设置于所述第一钝化层远离所述衬底基板的一侧，所述光电二极管通过贯穿所述第一钝化层的第一过孔与所述控制晶体管电连接；
第二钝化层，覆于所述光电二极管远离所述衬底基板的一侧；以及
电极层，设置于所述第二钝化层远离所述衬底基板的一侧，所述电极层包括第一电极部和第二电极部，所述第一电极部通过贯穿所述第二钝化层的第二过孔与所述光电二极管电连接，所述第二电极部通过第三过孔及第四过孔分别与所述第一信号走线和所述第二信号走线电连接形成桥接结构，所述第三过孔贯穿所述第二钝化层、所述第一钝化层和所述栅极绝缘层，所述第四过孔贯穿所述第二钝化层和所述第一钝化层。
根据本申请提供的指纹采集器件，所述有源层的材料为非晶硅；所述控制晶体管还包括欧姆接触层，所述欧姆接触层设置于所述有源层远离所述衬底基板的一侧。
根据本申请提供的指纹采集器件，所述指纹采集器件还包括遮光层，所述遮光层设置于所述第一钝化层远离所述衬底基板的一侧且与所述控制晶体管对应设置；所述遮光层与所述光电二极管同层设置。
根据本申请提供的指纹采集器件，所述遮光层至少包括依次层叠设置的第一遮光层和第二遮光层，所述光电二极管至少包括依次层叠设置的第一半导体层和本征半导体层；所述第一遮光层与所述第一半导体层同层设置，所述第二遮光层与所述本征半导体层同层设置。
根据本申请提供的指纹采集器件，所述遮光层在所述衬底基板上的正投影覆盖所述有源层在所述基板上的正投影。
根据本申请提供的指纹采集器件，所述遮光层还包括第三遮光层，所述第三遮光层设置于所述第二遮光层远离所述衬底基板的一侧；所述光电二极管还包括第二半导体层，所述第二半导体层设置于所述本征半导体层远离所述衬底基板的一侧，所述第三遮光层与所述第二半导体层同层设置。
根据本申请提供的指纹采集器件，所述第一半导体层为N型半导体层，所述第二半导体层为P型半导体层。
根据本申请提供的指纹采集器件，所述有源层的材料为金属氧化物。
根据本申请提供的指纹采集器件，所述电极层还包括第三电极部，所述驱动电路层还包括与所述源漏极金属层同层设置的绑定端子，所述第三电极部通过贯穿所述第二钝化层的第五过孔与所述绑定端子电连接。
本申请提供一种显示面板，包括上述指纹采集器件；
光路结构；以及
面板主体，所述光路结构设置于所述面板主体非显示面一侧，所述指纹采集器件设置于所述光路结构远离所述面板主体的一侧；
其中，所述指纹采集器件包括：
衬底基板；
驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括控制晶体管和多条信号走线，所述控制晶体管包括沿远离所述衬底基板的方向依次层叠设置的栅极、栅极绝缘层、有源层和源漏极金属层，多条所述信号走线包括与所述栅极同层设置的第一信号走线及与所述源漏极金属层同层设置的第二信号走线；
第一钝化层，覆于所述驱动电路层远离所述衬底基板的一侧；
光电二极管，设置于所述第一钝化层远离所述衬底基板的一侧，所述光电二极管通过贯穿所述第一钝化层的第一过孔与所述控制晶体管电连接；
第二钝化层，覆于所述光电二极管远离所述衬底基板的一侧；以及
电极层，设置于所述第二钝化层远离所述衬底基板的一侧，所述电极层包括第一电极部和第二电极部，所述第一电极部通过贯穿所述第二钝化层的第二过孔与所述光电二极管电连接，所述第二电极部通过第三过孔及第四过孔分别与所述第一信号走线和所述第二信号走线电连接形成桥接结构，所述第三过孔贯穿所述第二钝化层、所述第一钝化层和所述栅极绝缘层，所述第四过孔贯穿所述第二钝化层和所述第一钝化层。根据本申请提供的显示面板，
所述衬底基板位于所述光路结构远离所述面板主体的一侧；
所述驱动电路层位于所述衬底基板远离所述面板主体的一侧；
所述第一钝化层覆于所述驱动电路层远离所述面板主体的一侧；
所述光电二极管位于所述第一钝化层远离所述面板主体的一侧；
所述第二钝化层覆于所述光电二极管远离所述面板主体的一侧；以及
所述电极层位于所述第二钝化层远离所述面板主体的一侧。
根据本申请提供的显示面板，所述指纹采集器件还包括遮光层，所述遮光层位于所述第一钝化层远离所述面板主体的一侧且与所述驱动电路层的控制晶体管对应设置；所述遮光层与所述光电二极管同层设置。
 有益效果
本申请的有益效果为：本申请提供的指纹采集器件、显示面板，指纹采集器件包括衬底基板、驱动电路层、第一钝化层、光电二极管、第二钝化层和电极层，电极层的第一电极部通过贯穿第二钝化层的第二过孔与光电二极管电连接，驱动电路层包括控制晶体管和多条信号走线，第一信号走线与控制晶体管的栅极同层设置，第二信号走线与控制晶体管的源漏极金属层同层设置；相较于现有技术中的第一信号走线和第二信号走线通过贯穿栅极绝缘层的过孔电连接，本申请中的电极层的第二电极部通过第三过孔与第四过孔分别与第一信号走线和第二信号走线电连接形成桥接结构，第三过孔贯穿第二钝化层、第一钝化层和栅极绝缘层，第四过孔贯穿第二钝化层和第一钝化层，由于第三过孔和第四过孔与第二过孔通过同一道制程制备形成，从而能够节省一道制程，有利于节省成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的第一种指纹采集器件的截面结构示意图；
图2是本申请实施例提供的第二种指纹采集器件的截面结构示意图；
图3是本申请实施例提供的一种显示面板的截面结构示意图；
图4是本申请实施例提供的一种指纹采集器件的制备方法的流程图；
图4A~图4K是本申请实施例提供的一种指纹采集器件的制备方法的流程结构示意图。
附图标记说明：
100、指纹采集器件；200、光路结构；300、面板主体；
10、衬底基板；20、驱动电路层；20a、控制晶体管；20b、信号走线；20c、桥接结构；30、第一钝化层；40、光电二极管；50、遮光层；60、第二钝化层；70、电极层；701、第一电极部；702、第二电极部；703、第三电极部；201、栅极；202、第一信号走线；203、栅极绝缘层；204、有源层；205、欧姆接触层；206、源漏极金属层；207、第二信号走线；208、绑定端子；401、第一半导体层；402、本征半导体层；501、第一遮光层；502、第二遮光层；601、第一过孔；602、第二过孔；603、第三过孔；604、第四过孔；605、第五过孔。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
请参阅图1，图1是本申请实施例提供的第一种指纹采集器件的截面结构示意图。本申请实施例提供的指纹采集器件100，包括衬底基板10、驱动电路层20、第一钝化层30、光电二极管40、第二钝化层60和电极层70，所述驱动电路层20设置于所述衬底基板10一侧，所述第一钝化层30覆于所述驱动电路层20远离所述衬底基板10的一侧，所述光电二极管40设置于所述第一钝化层30远离所述衬底基板10的一侧，所述第二钝化层60覆于所述光电二极管40远离所述衬底基板10的一侧，所述电极层70设置于所述第二钝化层60远离所述衬底基板10的一侧。
所述驱动电路层20包括控制晶体管20a和多条信号走线20b，所述光电二极管40通过贯穿所述第一钝化层30的第一过孔601与所述控制晶体管20a电连接，所述电极层70包括第一电极部701、第二电极部702和第三电极部703，所述第一电极部701通过贯穿所述第二钝化层60的第二过孔602与所述光电二极管40电连接。
所述控制晶体管20a包括依次层叠设置的栅极201、栅极绝缘层203、有源层204和源漏极金属层206，多条所述信号走线包括与所述栅极201同层设置的第一信号走线202及与所述源漏极金属层206同层设置的第二信号走线207，所述第二电极部702通过第三过孔603及第四过孔604分别与所述第一信号走线202和所述第二信号走线207电连接形成桥接结构20c，所述第三过孔603贯穿所述第二钝化层60、所述第一钝化层30和所述栅极绝缘层203，所述第四过孔604贯穿所述第二钝化层60和所述第一钝化层30。
相较于现有技术中的第一信号走线202和第二信号走线207通过贯穿栅极绝缘层203的过孔电连接，本申请通过将电极层70的第二电极部702通过第三过孔603与第四过孔604分别与第一信号走线202和第二信号走线207电连接形成桥接结构20c，由于第三过孔603和第四过孔604与第二过孔602通过同一道制程制备形成，从而能够节省一道制程，有利于节省成本。
具体的，所述源漏极金属层206包括源极和漏极，所述光电二极管40的负极与所述漏极电连接，所述光电二极管40的正极接地。所述源极可与所述第二信号走线207电连接，所述控制晶体管20a的所述栅极201与所述第一信号走线202电连接。所述第一信号走线202可为扫描信号走线，所述第二信号走线207可为数据信号走线，所述第一信号走线202需要通过跳线到所述第二信号走线207后与驱动芯片（图中未示出）电连接，所述驱动芯片将信号传递至所述第一信号走线202和所述第二信号走线207。
当手指按压所述指纹采集器件100时，指纹中谷和脊的反射光强不一致，使得所述光电二极管40两端产生的压降不同，进而，所述光电二极管40会产生不同的电流值，所述指纹采集器件100根据不同的电流值，便可以识别出谷和脊的相应位置，即得到受测者的指纹信息。
示例性的，当所述控制晶体管20a的所述栅极201打开时，先给所述光电二极管40的负极端充入一个电位V1，然后关闭所述控制晶体管20a的所述栅极201，此时，所述控制晶体管20a的所述漏极电位即为V1，此刻所述光电二极管40处于反偏状态；当手指按压所述指纹采集器件100表面时，谷或脊的反射光线照射至所述光电二极管40，光子会引起反偏的所述光电二极管40的电流值改变，由于谷脊光强不同，则电流值的改变大小不同；当所述光电二极管40的所述栅极201再次打开时，所述控制晶体管20a的所述漏极会输出不同电流值，最终，可以通过读取所述第二信号走线207得到不同的电流值，以便于后续识别谷和脊的相应位置，即得到受测者的指纹信息。
可选的，所述衬底基板10为玻璃基板，相较于现有技术中的指纹采集器件100采用单晶硅衬底基板10，玻璃基板的成本降低，有利于节省成本。
所述光电二极管40至少包括依次层叠设置的第一半导体层401和本征半导体层402，所述本征半导体层402为非掺杂层，在反偏电压作用下，所述本征半导体层402被耗尽成为光吸收区，使得光电二极管40具有较高的量子效率和较短的响应时间。在本申请实施例中，所述光电二极管40包括所述第一半导体层401和所述本征半导体层402，所述第一半导体层401可以为N型半导体层。所述第一半导体层401的材料为N+a-Si（非晶硅），所述本征半导体层402的材料为非晶硅a-Si。
在其它实施例中，所述光电二极管40包括依次层叠设置的所述第一半导体层401、所述本征半导体层402和第二半导体层（图中未示出），所述第二半导体层设置于所述本征半导体层402远离所述衬底基板10的一侧，所述第一半导体层401为N型半导体层，所述第二半导体层为P型半导体层。所述第一半导体层401的材料为N+a-Si（非晶硅），所述本征半导体层402的材料为非晶硅a-Si，所述第二半导体层的材料为P+a-Si。
现有技术中的指纹采集器件100采用硅基衬底，硅基衬底通常为外挂式，屏幕上的指纹识别区域面积大概仅有一个拇指面积左右大小，指纹识别区域相对较小，而增大指纹识别区域面积则会提高指纹识别的成本。相对地，在本申请实施例中，所述有源层204的材料为非晶硅a-Si，可实现在显示面板上大面积制备，可在屏幕任何区域选择性开孔以作为指纹识别区域，能够实现单区域和多区域光学指纹的识别，成本得到大幅度降低。
所述控制晶体管20a还包括欧姆接触层205，所述欧姆接触层205设置于所述有源层204远离所述衬底基板10的一侧，所述欧姆接触层205位于所述有源层204和所述源漏极金属层206之间。所述欧姆接触层205的材料可为N+a-Si，N+a-Si是指采用N型掺杂a-Si材料。
所述电极层70复用为公共电极，所述电极层70为透明电极层70，所述电极层70的材料包括ITO（Indium tin oxide，氧化铟锡）。
可以理解的是，由于非晶硅a-Si对可见光具有较强的吸收性，可见光照射至所述有源层204上时，会对所述有源层204造成干扰，导致所述控制晶体管20a的性能下降，从而影响所述指纹采集器件100的灵敏性。
有鉴于此，在本申请实施例中，所述指纹采集器件100还包括遮光层50，所述遮光层50设置于所述第一钝化层30远离所述衬底基板10的一侧且与所述控制晶体管20a对应设置；所述遮光层50与所述光电二极管40同层设置，如此设置，可以将所述遮光层50与所述光电二极管40通过同一图案化工艺形成，由此可以简化所述指纹采集器件100的制作工序，有利于进一步降低成本。
在本申请实施例中，所述遮光层50至少包括依次层叠设置的第一遮光层501和第二遮光层502，所述光电二极管40至少包括依次层叠设置的第一半导体层401和本征半导体层402；所述第一遮光层501与所述第一半导体层401同层设置，所述第二遮光层502与所述本征半导体层402同层设置。即，所述第一遮光层501与所述第一半导体层401通过同一图案化工艺形成，所述第二遮光层502与所述本征半导体层402通过同一图案化工艺形成，在对所述控制晶体管20a实现遮光效果的同时，可以简化所述指纹采集器件100的制作工序，有利于进一步降低成本。
具体的，所述第一遮光层501与所述第一半导体层401的材料相同，可采用N+a-Si（非晶硅），所述第二遮光层502与所述本征半导体层402的材料相同，可采用非晶硅a-Si，由于非晶硅对可见光的吸收能力较强，能够吸收入射光和经手指反射至所述遮光层50的反射光，从而防止光照射至所述控制晶体管20a，避免对所述控制晶体管20a的性能产生不良影响。在本实施例中，所述第一遮光层501与所述第一半导体层401的厚度相同，所述第二遮光层502与所述第二半导体层的厚度相同。
在其它实施例中，当所述光电二极管40还包括所述第二半导体层（图中未示出）时，所述遮光层50还可包括第三遮光层，所述第三遮光层设置于所述第二遮光层502远离所述衬底基板10的一侧，所述第一遮光层501、所述第二遮光层502和所述第三遮光层沿远离所述衬底基板10的方向依次层叠设置。所述第三遮光层和所述第二半导体层同层设置，即，所述第三遮光层和所述第二半导体层通过同一图案化工艺形成，所述第三遮光层与所述第二半导体层的材料相同，可采用P+a-Si。
进一步的，为了更好地实现遮光效果，所述遮光层50在所述衬底基板10上的正投影覆盖所述控制晶体管20a在所述衬底基板10上的正投影，进一步的，所述遮光层50在所述衬底基板10上的正投影覆盖所述有源层204在所述衬底基板10上的正投影，进一步地，所述遮光层50在所述衬底基板10上的正投影与所述有源层204在所述衬底基板10上的正投影重合。
在一种实施例中，请参阅图2，图2是本申请实施例提供的第二种指纹采集器件的截面结构示意图，图2与图1的不同之处在于，所述有源层204的材料为金属氧化物，可选地，所述有源层204的材料可包括IGZO(Indium gallium zinc oxide，铟镓锌氧化物)、IZO（Indium tin oxide，氧化铟锌）、ITZO（Indium gallium tin oxide，氧化铟锡锌）和ZnO（Zinc oxide，氧化锌）中的其中一种。
同样的，以金属氧化物作为所述有源层204的材料，所述指纹采集器件100可实现在显示面板上大面积制备，可在屏幕任何区域选择性开孔以作为指纹识别区域，能够实现单区域和多区域光学指纹的识别，成本得到大幅度降低。此外，和非晶硅不同的是，由于金属氧化物对可见光不吸收，因此，入射光和经手指反射至所述遮光层50的反射光照射至所述控制晶体管20a时，不会对所述有源层204造成干扰，不会对所述控制晶体管20a的性能产生不良影响。因此，在本申请实施例中，所述指纹采集器件100无需在所述控制晶体管20a上方设置所述遮光层50。
所述驱动电路层20还包括与所述源漏极金属层206同层设置的绑定端子208，用于与所述驱动芯片绑定连接，所述第三电极部703通过贯穿所述第二钝化层60的第五过孔605与所述绑定端子208电连接，所述驱动芯片被配置为向所述第三电极部703施加驱动电压，以驱动所述指纹采集器件100进行指纹识别。
所述第二过孔602、所述第三过孔603、所述第四过孔604和所述第五过孔605通过同一黄光制程制备而成，有利于减少制程，降低成本。
请参阅图3，图3是本申请实施例提供的一种显示面板的截面结构示意图；本申请实施例还提供一种显示面板，所述显示面板包括上述实施例中的所述指纹采集器件100，所述显示面板能够实现单区域和多区域光学指纹的识别；所述显示面板还包括光路结构200和面板主体300，所述光路结构200设置于所述面板主体300非显示面一侧，所述指纹采集器件100设置于所述光路结构200远离所述面板主体300的一侧，即，所述光路结构200设置于所述指纹采集器件100的入光侧，所述光路结构200包括光纤准直层，以起到准直作用，当进行指纹识别时，手指按在所述面板主体300的显示面一侧，经手指反射回的光线通过所述光路结构200之后聚集至所述指纹采集器件100，所述指纹采集器件100可以同时接收经过手指反射回的光线，所述指纹采集器件100中的驱动芯片可以将光信号转换成强度不同的电信号，从而对含有两个及以上手指的指纹信息的电信号进行处理、辨识，如此可以实现双指或者多指的指纹识别的功能。
在本实施例中，所述指纹采集器件100相对于所述面板主体300及所述光路结构200呈倒装结构，具体的，所述指纹采集器件100包括衬底基板10、驱动电路层20、第一钝化层30、光电二极管40、第二钝化层60和电极层70；其中，所述衬底基板10位于所述光路结构200远离所述面板主体300的一侧；所述驱动电路层20位于所述衬底基板10远离所述面板主体300的一侧；所述第一钝化层30覆于所述驱动电路层20远离所述面板主体300的一侧；所述光电二极管40位于所述第一钝化层30远离所述面板主体300的一侧；所述第二钝化层60覆于所述光电二极管40远离所述面板主体300的一侧；所述电极层70位于所述第二钝化层60远离所述面板主体300的一侧。
进一步的所述指纹采集器件100还包括遮光层50，所述遮光层50用于遮挡远离所述光路结构200侧的外界光线，避免其与手指反射回的光线混合而对所述指纹采集器件100的正常识别造成干扰。具体的，所述遮光层50位于所述第一钝化层30远离所述面板主体300的一侧且与所述驱动电路层20的控制晶体管20a对应设置；所述遮光层50与所述光电二极管40同层设置。
请参阅图4和图4A~图4K，图3是本申请实施例提供的一种指纹采集器件的制备方法的流程图；图4A~图4K是本申请实施例提供的一种指纹采集器件的制备方法的流程结构示意图。本申请实施例还提供一种指纹采集器件的制备方法，包括以下步骤：
步骤S10：提供一衬底基板10。
具体的，请参阅图4A，所述衬底基板10为玻璃基板。
步骤S20：在所述衬底基板10一侧形成驱动电路层20，所述驱动电路层20包括控制晶体管20a和多条信号走线，所述控制晶体管20a包括沿远离所述衬底基板10的方向依次层叠设置的栅极201、栅极绝缘层203、有源层204和源漏极金属层206，多条所述信号走线包括与所述栅极201同层设置的第一信号走线202及与所述源漏极金属层206同层设置的第二信号走线207。
具体的，所述步骤S20包括以下步骤：
步骤S201：在所述衬底基板10上形成所述栅极201和所述第一信号走线202。
请参阅图4B，首先，在所述衬底基板10上沉积一层栅极材料，采用一道黄光制程对栅极材料进行曝光、显影和刻蚀处理，以形成所述栅极201和所述第一信号走线202。
步骤S202：形成覆于所述栅极201和所述第一信号走线202上的栅极绝缘层203。
请参阅图4C，在所述衬底基板10、所述栅极201和所述第一信号走线202上沉积一层无机材料以形成所述栅极绝缘层203，所述无机材料可为氮化硅、氧化硅和氮氧化硅中的其中一种。
步骤S203：在所述栅极绝缘层203远离所述衬底基板10的一侧形成所述有源层204。
请参阅图4D，首先，在所述栅极绝缘层203上沉积一层有源层材料；接着，采用一道黄光制程对有源层材料进行曝光、显影和刻蚀处理，以形成所述有源层204。本申请实施例以所述有源层204的材料为非晶硅a-Si为例进行阐述说明；
进一步的，所述步骤S103还包括：在所述有源层204远离所述衬底基板10的一侧形成欧姆接触层205，所述欧姆接触层205的材料为N+a-Si，所述欧姆接触层205和所述有源层204采用同一道黄光制程制备而成。
步骤S204：在所述有源层204远离所述衬底基板10的一侧形成所述源漏极金属层206、所述第二信号走线207和绑定端子208。
请参阅图4E，首先，在所述有源层204上沉积一层源漏极金属层材料，具体地，形成覆盖所述栅极绝缘层203、所述有源层204和所述欧姆接触层205的源漏极金属层材料；接着，采用一道黄光制程对源漏极金属层材料进行曝光、显影和刻蚀处理，以形成所述源漏极金属层206、所述第二信号走线207和所述绑定端子208。所述源漏极金属层206包括源极和漏极，所述源极和所述漏极之间形成沟道。所述源漏极金属层206、所述第二信号走线207和所述绑定端子208的材料为N+a-Si。
步骤S30：形成覆于所述驱动电路层20远离所述衬底基板10的一侧的第一钝化层30。
请参阅图4F，在所述栅极绝缘层203、所述源漏极金属层206、所述第二信号走线207和所述沟道上沉积形成所述第一钝化层30，所述第一钝化层30的材料可以为氮化硅、氧化硅或氮氧化硅中的其中一种。
步骤S40：形成贯穿所述第一钝化层30的第一过孔601。
请参阅图4G，采用一道黄光制程对所述第一钝化层30进行曝光、显影和刻蚀处理，以形成贯穿所述第一钝化层30的第一过孔601。
步骤S50：在所述第一钝化层30远离所述衬底基板10的一侧形成光电二极管40，所述光电二极管40通过贯穿所述第一过孔601与所述控制晶体管20a电连接。
具体的，所述步骤S50包括以下步骤：
步骤S501：在所述第一钝化层30和所述第一过孔601内形成第一半导体层401和本征半导体层402。
请参阅图4H，首先，在所述第一钝化层30和所述第一过孔601内的所述源漏极金属层206上沉积形成层叠设置的第一半导体层材料和本征半导体层材料；接着，采用一道黄光制程对第一半导体层材料对本征半导体层材料进行曝光、显影和刻蚀处理，以形成所述第一半导体层401。所述第一半导体层401的材料可以为N+a-Si，所述本征半导体层402的材料可以为非晶硅a-Si。
进一步的，所述步骤S501还包括：在所述第一钝化层30远离所述衬底基板10的一侧形成遮光层50，所述遮光层50与所述控制晶体管20a对应设置，所述遮光层50与所述光电二极管40采用同一制程形成。
具体的，在所述第一钝化层30远离所述衬底基板10的一侧形成层叠设置的第一遮光层501和第二遮光层502。所述第一遮光层501与所述第一半导体层401同层设置，所述第二遮光层502与所述本征半导体层402同层设置，所述第一遮光层501的材料可以为N+a-Si，所述本征半导体层402的材料可以为非晶硅a-Si。所述第一遮光层501及所述第二遮光层502，与所述第一半导体层401及所述本征半导体层402采用同一道黄光制程制备而成。
步骤S60：形成覆于所述光电二极管40远离所述衬底基板10的一侧的第二钝化层60。
请参阅图4I，在所述第一钝化层30、所述第二遮光层502和所述本征半导体层402上沉积形成所述第二钝化层60，所述第二钝化层60的材料可以为氮化硅、氧化硅或氮氧化硅中的其中一种。
步骤S70：形成第二过孔602、第三过孔603和第四过孔604，所述第二过孔602贯穿所述第二钝化层60，所述第三过孔603贯穿所述第二钝化层60、所述第一钝化层30和所述栅极绝缘层203，所述第四过孔604贯穿所述第二钝化层60和所述第一钝化层30。
请参阅图4J，采用一道黄光制程对所述第二钝化层60进行曝光、显影和刻蚀处理，以形成所述第二过孔602、所述第三过孔603和所述第四过孔604，由于所述第三过孔603及所述第四过孔604与所述第二过孔602通过同一道制程制备形成，从而能够节省一道制程，有利于节省成本。
进一步的，所述步骤S70还包括：形成贯穿所述第二钝化层60的第五过孔605。所述第二过孔602、所述第三过孔603、所述第四过孔604和所述第五过孔605通过同一黄光制程制备而成，有利于减少制程，降低成本。
步骤S80：在所述第二钝化层60远离所述衬底基板10的一侧形成电极层70，所述电极层70包括第一电极部701和第二电极部702，所述第一电极部701通过贯穿所述第二过孔602与所述光电二极管40电连接，所述第二电极部702通过所述第三过孔603及所述第四过孔604分别与所述第一信号走线202和所述第二信号走线207电连接形成桥接结构20c。
具体的，请参阅图4K，首先，在所述第二钝化层60上沉积一层电极材料，所述电极材料覆盖所述第二钝化层60、所述第二过孔602、所述第三过孔603、所述第四过孔604和所述第五过孔605；接着，采用一道黄光制程对电极材料进行曝光、显影和刻蚀处理，以形成所述电极层70。所述电极层70的材料包括ITO。
由上可知，本申请实施例提供的指纹采集器件100的制备方法，制备完成所述指纹采集器件100共需要7道黄光制程，具体为：所述栅极201/所述第一信号走线202/所述绑定端子208、所述有源层204/所述欧姆接触层205、所述源漏极金属层206/所述第二信号走线207/所述绑定端子208、所述第一过孔601、所述光电二极管40/所述遮光层50、所述第二过孔602/所述第三过孔603/所述第四过孔604/所述第五过孔605、所述电极层70，相较于现有技术中的采用硅基衬底的指纹采集器件100，所需制程减少，有利于降低成本。
此外，本申请中的所述指纹采集器件100中的所述有源层204采用非晶硅，可实现在显示面板上大面积制备，可在屏幕任何区域选择性开孔以作为指纹识别区域，能够实现单区域和多区域光学指纹的识别，成本得到大幅度降低。
有益效果为：本申请实施例提供的指纹采集器件、显示面板，指纹采集器件包括衬底基板、驱动电路层、第一钝化层、光电二极管、第二钝化层和电极层，电极层的第一电极部通过贯穿第二钝化层的第二过孔与光电二极管电连接，驱动电路层包括控制晶体管和多条信号走线，第一信号走线与控制晶体管的栅极同层设置，第二信号走线与控制晶体管的源漏极金属层同层设置；相较于现有技术中的第一信号走线和第二信号走线通过贯穿栅极绝缘层的过孔电连接，本申请中的电极层的第二电极部通过第三过孔与第四过孔分别与第一信号走线和第二信号走线电连接形成桥接结构，第三过孔贯穿第二钝化层、第一钝化层和栅极绝缘层，第四过孔贯穿第二钝化层和第一钝化层，由于第三过孔和第四过孔与第二过孔通过同一道制程制备形成，从而能够节省一道制程，有利于节省成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种指纹采集器件，包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括控制晶体管和多条信号走线，所述控制晶体管包括沿远离所述衬底基板的方向依次层叠设置的栅极、栅极绝缘层、有源层和源漏极金属层，多条所述信号走线包括与所述栅极同层设置的第一信号走线及与所述源漏极金属层同层设置的第二信号走线；
    第一钝化层，覆于所述驱动电路层远离所述衬底基板的一侧；
    光电二极管，设置于所述第一钝化层远离所述衬底基板的一侧，所述光电二极管通过贯穿所述第一钝化层的第一过孔与所述控制晶体管电连接，所述源漏极金属层包括源极和漏极，所述漏极与所述光电二极管电连接，所述源极与所述第二信号走线电连接；
    第二钝化层，覆于所述光电二极管远离所述衬底基板的一侧；以及
    电极层，设置于所述第二钝化层远离所述衬底基板的一侧，所述电极层包括第一电极部和第二电极部，所述第一电极部通过贯穿所述第二钝化层的第二过孔与所述光电二极管电连接，所述第二电极部通过第三过孔及第四过孔分别与所述第一信号走线和所述第二信号走线电连接形成桥接结构，所述第三过孔贯穿所述第二钝化层、所述第一钝化层和所述栅极绝缘层，所述第四过孔贯穿所述第二钝化层和所述第一钝化层。
  2. 根据权利要求1所述的指纹采集器件，其中，所述有源层的材料为非晶硅；所述控制晶体管还包括欧姆接触层，所述欧姆接触层设置于所述有源层远离所述衬底基板的一侧。
  3. 根据权利要求2所述的指纹采集器件，其中，所述指纹采集器件还包括遮光层，所述遮光层设置于所述第一钝化层远离所述衬底基板的一侧且与所述控制晶体管对应设置；所述遮光层与所述光电二极管同层设置。
  4. 根据权利要求3所述的指纹采集器件，其中，所述遮光层至少包括依次层叠设置的第一遮光层和第二遮光层，所述光电二极管至少包括依次层叠设置的第一半导体层和本征半导体层；所述第一遮光层与所述第一半导体层同层设置，所述第二遮光层与所述本征半导体层同层设置。
  5. 根据权利要求3所述的指纹采集器件，其中，所述遮光层在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
  6. 根据权利要求3所述的指纹采集器件，其中，所述遮光层还包括第三遮光层，所述第三遮光层设置于所述第二遮光层远离所述衬底基板的一侧；所述光电二极管还包括第二半导体层，所述第二半导体层设置于所述本征半导体层远离所述衬底基板的一侧，所述第三遮光层与所述第二半导体层同层设置。
  7. 根据权利要求1所述的指纹采集器件，其中，所述有源层的材料为金属氧化物。
  8. 根据权利要求1所述的指纹采集器件，其中，所述电极层还包括第三电极部，所述驱动电路层还包括与所述源漏极金属层同层设置的绑定端子，所述第三电极部通过贯穿所述第二钝化层的第五过孔与所述绑定端子电连接。
  9. 一种指纹采集器件，包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括控制晶体管和多条信号走线，所述控制晶体管包括沿远离所述衬底基板的方向依次层叠设置的栅极、栅极绝缘层、有源层和源漏极金属层，多条所述信号走线包括与所述栅极同层设置的第一信号走线及与所述源漏极金属层同层设置的第二信号走线；
    第一钝化层，覆于所述驱动电路层远离所述衬底基板的一侧；
    光电二极管，设置于所述第一钝化层远离所述衬底基板的一侧，所述光电二极管通过贯穿所述第一钝化层的第一过孔与所述控制晶体管电连接；
    第二钝化层，覆于所述光电二极管远离所述衬底基板的一侧；以及
    电极层，设置于所述第二钝化层远离所述衬底基板的一侧，所述电极层包括第一电极部和第二电极部，所述第一电极部通过贯穿所述第二钝化层的第二过孔与所述光电二极管电连接，所述第二电极部通过第三过孔及第四过孔分别与所述第一信号走线和所述第二信号走线电连接形成桥接结构，所述第三过孔贯穿所述第二钝化层、所述第一钝化层和所述栅极绝缘层，所述第四过孔贯穿所述第二钝化层和所述第一钝化层。
  10. 根据权利要求9所述的指纹采集器件，其中，所述有源层的材料为非晶硅；所述控制晶体管还包括欧姆接触层，所述欧姆接触层设置于所述有源层远离所述衬底基板的一侧。
  11. 根据权利要求10所述的指纹采集器件，其中，所述指纹采集器件还包括遮光层，所述遮光层设置于所述第一钝化层远离所述衬底基板的一侧且与所述控制晶体管对应设置；所述遮光层与所述光电二极管同层设置。
  12. 根据权利要求11所述的指纹采集器件，其中，所述遮光层至少包括依次层叠设置的第一遮光层和第二遮光层，所述光电二极管至少包括依次层叠设置的第一半导体层和本征半导体层；所述第一遮光层与所述第一半导体层同层设置，所述第二遮光层与所述本征半导体层同层设置。
  13. 根据权利要求11所述的指纹采集器件，其中，所述遮光层在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
  14. 根据权利要求11所述的指纹采集器件，其中，所述遮光层还包括第三遮光层，所述第三遮光层设置于所述第二遮光层远离所述衬底基板的一侧；所述光电二极管还包括第二半导体层，所述第二半导体层设置于所述本征半导体层远离所述衬底基板的一侧，所述第三遮光层与所述第二半导体层同层设置。
  15. 根据权利要求14所述的指纹采集器件，其中，所述第一半导体层为N型半导体层，所述第二半导体层为P型半导体层。
  16. 根据权利要求9所述的指纹采集器件，其中，所述有源层的材料为金属氧化物。
  17. 根据权利要求9所述的指纹采集器件，其中，所述电极层还包括第三电极部，所述驱动电路层还包括与所述源漏极金属层同层设置的绑定端子，所述第三电极部通过贯穿所述第二钝化层的第五过孔与所述绑定端子电连接。
  18. 一种显示面板，包括指纹采集器件；
    光路结构；以及
    面板主体，所述光路结构设置于所述面板主体非显示面一侧，所述指纹采集器件设置于所述光路结构远离所述面板主体的一侧；
    其中，所述指纹采集器件包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括控制晶体管和多条信号走线，所述控制晶体管包括沿远离所述衬底基板的方向依次层叠设置的栅极、栅极绝缘层、有源层和源漏极金属层，多条所述信号走线包括与所述栅极同层设置的第一信号走线及与所述源漏极金属层同层设置的第二信号走线；
    第一钝化层，覆于所述驱动电路层远离所述衬底基板的一侧；
    光电二极管，设置于所述第一钝化层远离所述衬底基板的一侧，所述光电二极管通过贯穿所述第一钝化层的第一过孔与所述控制晶体管电连接；
    第二钝化层，覆于所述光电二极管远离所述衬底基板的一侧；以及
    电极层，设置于所述第二钝化层远离所述衬底基板的一侧，所述电极层包括第一电极部和第二电极部，所述第一电极部通过贯穿所述第二钝化层的第二过孔与所述光电二极管电连接，所述第二电极部通过第三过孔及第四过孔分别与所述第一信号走线和所述第二信号走线电连接形成桥接结构，所述第三过孔贯穿所述第二钝化层、所述第一钝化层和所述栅极绝缘层，所述第四过孔贯穿所述第二钝化层和所述第一钝化层。
  19. 根据权利要求18所述的显示面板，其中，
    所述衬底基板位于所述光路结构远离所述面板主体的一侧；
    所述驱动电路层位于所述衬底基板远离所述面板主体的一侧；
    所述第一钝化层覆于所述驱动电路层远离所述面板主体的一侧；
    所述光电二极管位于所述第一钝化层远离所述面板主体的一侧；
    所述第二钝化层覆于所述光电二极管远离所述面板主体的一侧；以及
    所述电极层位于所述第二钝化层远离所述面板主体的一侧。
  20. 根据权利要求19所述的显示面板，其中，所述指纹采集器件还包括遮光层，所述遮光层位于所述第一钝化层远离所述面板主体的一侧且与所述驱动电路层的控制晶体管对应设置；所述遮光层与所述光电二极管同层设置。
PCT/CN2022/080189 2022-03-02 2022-03-10 指纹采集器件、显示面板 WO2023164961A1 (zh)

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