WO2020063128A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2020063128A1
WO2020063128A1 PCT/CN2019/099787 CN2019099787W WO2020063128A1 WO 2020063128 A1 WO2020063128 A1 WO 2020063128A1 CN 2019099787 W CN2019099787 W CN 2019099787W WO 2020063128 A1 WO2020063128 A1 WO 2020063128A1
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Prior art keywords
groove
layer
insulating layer
fan
signal line
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PCT/CN2019/099787
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English (en)
French (fr)
Inventor
程鸿飞
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to EP19838922.3A priority Critical patent/EP3859783A4/en
Priority to JP2020564599A priority patent/JP7500908B2/ja
Priority to US16/634,258 priority patent/US11271018B2/en
Publication of WO2020063128A1 publication Critical patent/WO2020063128A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to the field of display technology, and particularly to an array substrate, a display panel, and a display device.
  • OLED display devices also known as organic electric laser display devices, are widely used in display devices because of their self-luminous, thin, and power-saving features.
  • OLED display screen can be made into a flexible and flexible screen, which makes the display products more diversified and has a broad market application prospect.
  • the driving chip IC is also directly fabricated on the flexible substrate made into the display area, and the portion of the flexible substrate provided with the driving circuit is bent compared to the portion provided with the display area, which is usually bent to set Based on this setting structure, the signal line connecting the driving circuit and the display area is provided on the bent area of the flexible substrate based on the rear surface of the display area.
  • the signal line connection between the driving circuit and the display area has a higher risk of breakage, thereby affecting the use performance of the flexible OLED display.
  • An object of the technical solution of the present disclosure is to provide an array substrate, a display panel, and a display device.
  • the present disclosure provides an array substrate including:
  • a substrate body including a display area and a non-display area on the substrate body, the non-display area including a fan-out area provided with a fan-out signal line, and the fan-out signal line is connected to the signal line in the display area;
  • the fan-out region includes an inorganic insulating layer provided between the substrate body and a flat layer, a first groove is formed on the inorganic insulating layer, and at least a part of the fan-out signal line is in the The orthographic projection on the substrate body is located within the orthographic projection of the first groove on the substrate body.
  • the flat layer is deposited on the fan-out signal line and is connected to the fan-out signal line.
  • the bottom of the first groove is opposite to the opening of the first groove, and a part of the surface of the substrate body constitutes the bottom of the first groove, and A portion of the fan-out signal line provided on the bottom of the first groove is in direct contact with the substrate body.
  • the bottom of the first groove is opposite to the opening of the first groove, and a part of the surface of the substrate body constitutes the bottom of the first groove, and the first groove is filled with An organic polymer material layer, the organic polymer material layer is in direct contact with the bottom of the first groove, and the fan-out signal line is disposed on a side of the organic polymer material layer away from the substrate body, It is in direct contact with the organic polymer material layer, and the flat layer is disposed on a side of the fan-out signal line remote from the substrate body.
  • the bottom of the first groove is opposite to the opening of the first groove, a part of the surface of the substrate body constitutes the bottom of the first groove, and the organic polymer material layer and the Part of the surface of the substrate body is in direct contact.
  • the inorganic insulating layer includes a buffer layer, a gate insulating layer, and an interlayer insulating layer sequentially disposed on the substrate body, and the depth of the first groove is not greater than A sum of the thicknesses of the buffer layer, the gate insulation layer, and the interlayer insulation layer, and the fan-out signal line is disposed on the interlayer insulation layer, and a part of the fanout signal line is disposed on the first groove Inside.
  • the first groove penetrates the buffer layer, the gate insulation layer, and the interlayer insulation layer to expose a part of the surface of the substrate body, and the fan
  • the outgoing signal line is in direct contact with the partial surface of the substrate body.
  • the inorganic insulating layer includes at least a two-layer structure, and an opening dimension of the first groove parallel to the substrate body is perpendicular to the substrate body and away from the substrate. The direction of the substrate body gradually increases.
  • a surface of a sidewall of the first groove is a stepped surface or a plane.
  • the inorganic insulating layer includes a first sub inorganic insulating layer and a second sub inorganic insulating layer which are in direct contact with each other.
  • the inorganic insulating layer includes a buffer layer, a gate insulating layer, and an interlayer insulating layer sequentially disposed on the substrate body, and the first groove is in the gate
  • the opening size of the pole insulating layer is larger than the opening size of the first groove in the buffer layer, and the opening size of the first groove in the interlayer insulation layer is larger than that of the first groove in the gate.
  • the opening size of the electrode insulation layer is larger than the opening size of the electrode insulation layer.
  • a side wall of a portion of the first groove penetrating the gate insulating layer and the interlayer insulating layer is a first plane
  • the first groove penetrates the A side wall of a portion of the buffer layer is a second plane
  • the first plane and the second plane are located on different planes.
  • a side wall of a portion where the first groove penetrates the interlayer insulating layer is a third plane, and the first groove penetrates the gate insulating layer and the substrate.
  • a side wall of a portion of the buffer layer is a fourth plane, and the third plane and the fourth plane are located on different planes.
  • the organic polymer material layer further includes a portion located outside the first groove and connected to the inorganic insulating layer.
  • the fan-out signal line includes a first line portion provided in the same layer and the same material as the data line of the pixel unit and the same layer and the same material as the gate line of the pixel unit.
  • the first circuit portion is disposed in the first groove.
  • the substrate body is a flexible substrate body.
  • the organic polymer material layer is a flexible organic polymer material layer.
  • a plurality of pixel units are provided in the display area, and a driving circuit is further provided in the non-display area or the display area, and the driving circuit passes the fan-out A signal line and a signal line in the display area are connected to the plurality of pixel units.
  • An embodiment of the present disclosure further provides a display panel including the array substrate according to any one of the above.
  • An embodiment of the present disclosure further provides a display device including the display panel as described above.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of forming an array substrate in a bent state according to an embodiment of the present disclosure
  • FIG. 3 is a schematic circuit structure diagram of a driving circuit of a pixel unit on an array substrate in an OLED display;
  • FIG. 4 is a schematic plan view of a pixel unit on the array substrate
  • FIG. 5 is a schematic cross-sectional view of a portion at BB 'in FIG. 4;
  • FIG. 6 is a schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiments of the present disclosure
  • FIG. 7 is another schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiment of the present disclosure
  • FIG. 8 is another schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiment of the present disclosure
  • FIG. 9 is another schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiment of the present disclosure.
  • FIG. 10 is another schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiment of the present disclosure
  • FIG. 11 is another schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiment of the present disclosure.
  • FIG. 12 is another schematic cross-sectional view of the fan-out area at A-A 'in some implementation structures of the array substrate according to the embodiment of the present disclosure.
  • the array substrate according to the embodiment of the present disclosure is provided with a groove on the inorganic insulation layer in the fan-out area to reduce the inorganic insulation on the fan-out area.
  • the thickness of the layer increases the thickness of the flat layer with better flexibility, thereby solving the problem that the signal line is easily broken by bending in the fan-out area.
  • the array substrate includes:
  • a flexible substrate body comprising: a pixel area provided with a plurality of pixel units and a fan-out area provided with a fan-out signal line, the fan-out signal line being connected to the signal line of the pixel area;
  • the fan-out area includes an inorganic insulating layer provided between the substrate body and the flat layer, a groove is formed in the inorganic insulating layer, and at least a part of the fan-out signal line is provided in the groove.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • the flexible substrate body 100 of the array substrate includes a pixel region 110 corresponding to a display area, and a driving circuit 120 is also fabricated on the substrate body 100.
  • the driving circuit 120 is connected to the signal lines of the pixel region 110 through fan-out signal lines.
  • the arrangement area of the fan-out signal lines on the substrate body 100 that is, the area between the pixel area 110 and the driving circuit 120 is formed as a fan-out area 140.
  • a plurality of pixel units 11 are provided in a display area, and a driving circuit 120 is connected to the plurality of pixel units 11 through a fan-out signal line 300 and gate lines 13 and data lines 12 in the display area.
  • the flexible substrate body 100 can be made of a polymer material such as polyimide plastic, polyetheretherketone, or transparent conductive polyester, for example, and has the characteristics of light weight, thin thickness, softness and flexibility.
  • FIG. 2 A schematic structural diagram of forming one of the folded states of the array substrate according to the embodiment of the present disclosure shown in FIG. 2.
  • the fan-out region 140 can be bent to the back of the pixel region 110. Based on the bent state of the fan-out region 140, a part of the fan-out region 140 is formed into a bent region. 141, and the bending area 141 divides the rest of the fan-out area 140 into a first fan-out area 142 and a second fan-out area 143, as shown in FIG.
  • the fan-out area 140 includes a bent area 141, a first fan-out area 142, and a second fan-out area 143.
  • the fan-out region 140 includes an inorganic insulating layer disposed between the substrate body and the flat layer, wherein a groove is formed in the inorganic insulating layer, and at least a part of the fan-out signal line is disposed in the recess. Inside the slot.
  • the portion where the groove is provided on the fan-out area 140 is formed as the bending area 141.
  • the thickness of the inorganic insulating layer in the bending area 141 is reduced and the thickness is increased.
  • the thickness of the flat layer with better flexibility, thereby solving the problem that the bending of the bending region 141 easily breaks the signal line.
  • FIG. 3 is a schematic circuit structure diagram of a driving circuit of a pixel unit on an array substrate in an OLED display
  • FIG. 4 is a schematic plan structure diagram of a pixel unit on the array substrate.
  • the pixel unit of the array substrate includes a thin film transistor (TFT) T1 for implementing OLED switching control, a thin film transistor T2 for implementing OLED driving, and a storage capacitor Cs, among which the switching TFT
  • TFT thin film transistor
  • the gate of T1 is connected to the gate line, the source is connected to the data line, the drain is connected to the gate of the driving TFT T2; the source of the driving TFT T2 is connected to the power line (V dd ), and the drain is connected to the pixel electrode ( The anode layer of the OLED 1061); one electrode of the storage capacitor Cs is connected to the drain of the switching TFT T1 and the gate of the driving TFT T2, and the other electrode is connected to the source of the TFT T2.
  • each pixel unit of the pixel region of the array substrate includes: from bottom to top, the substrate body 100 and the buffer The layer 101, the gate insulating layer 102, the interlayer insulating layer 103, the passivation layer 104, the flat layer 105, and the pixel defining layer 106, wherein the corresponding pixel defining layer 106 is provided with an anode layer 1061, an organic light emitting layer 1062, and a cathode of the OLED.
  • Layer 1063 is provided with an anode layer 1061, an organic light emitting layer 1062, and a cathode of the OLED.
  • an active layer 1011 is further provided on the buffer layer 101, and a gate 1021 for driving the TFT T2 is provided on the gate insulating layer 102 to penetrate the via holes of the gate insulating layer 102 and the interlayer insulating layer 103.
  • a source 1022 and a drain 1023 of the driving TFT T2 are provided therein, and a Vdd line 1 and a data line 2 are provided on the interlayer insulating layer 103.
  • the drain 1023 of the driving TFT T2 is connected to the anode of the OLED through a via The layer 1061 is connected, and the source 1022 of the driving TFT T2 is connected to the Vdd line.
  • FIG. 4 and FIG. 5 show one implementation structure diagram of the pixel region 110 on the substrate body 100. It can be understood that the fan-out region 140 corresponding to FIG. 1 is provided with a pixel layer 110 corresponding to the pixel region 110 and manufactured on the same layer.
  • the buffer layer 101, the gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 on the substrate body 100 are made of an inorganic material, and there is a high risk of fracture when repeatedly bent, as described in the embodiment of the present disclosure.
  • the fan-out signal line is set in the groove by opening a groove in the inorganic insulating layer on the substrate body 100 of the fan-out region 140, thereby reducing the inorganic insulation in the bent region 141 of the fan-out region 140.
  • the thickness of the layer increases the thickness of the flat layer with better flexibility, so as to solve the problem that the signal line is easily broken when the inorganic insulating layer is bent in the bending region.
  • the inorganic insulating layer provided with the groove may be any one of the buffer layer 101, the gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104, or a buffer layer. At least two of the layer 101, the gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 are adjacent.
  • the inorganic insulating layer provided with the groove 200 may include three sub-inorganic insulating layers that are in direct contact with each other. As shown in FIGS. 6 to 11, the inorganic insulating layer includes a buffer layer 101, a gate insulating layer 102, and an interlayer.
  • the insulating layer 103; or the inorganic insulating layer provided with the groove 200 may include, as shown in FIG. 12, the gate insulating layer 102 and the interlayer insulating layer 103 included in the inorganic insulating layer.
  • the fan-out signal line of the fan-out area 140 is in direct contact with a flexible organic polymer material layer in the opened groove to increase the flexibility of the signal line.
  • the groove is filled with a flexible organic polymer material layer, and the fan-out signal line is in direct contact with the flexible organic polymer material layer; or, the fan-out signal line is in contact with a flexible organic polymer material
  • the substrate body is in direct contact.
  • the flexible organic polymer material layer may be made of a resin (such as epoxy resin) material, and is not specifically limited to being able to adopt only this kind of material.
  • a resin such as epoxy resin
  • FIG. 1 a schematic cross-sectional view of the fan-out region at AA ′ is shown in FIG. 6, and in a bent region 141 of the fan-out region 140, Grooves are formed in the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103, and the grooves in the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 communicate with each other and are formed as interlayers
  • the insulating layer 103 penetrates to the groove 200 of the buffer layer 101, that is, a groove formed by combining the grooves on the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 with each other.
  • the fan-out signal line 300 is provided. On the interlayer insulating layer 103, in the groove 200, a part of the fan-out signal line 300 passes through the grooves on the interlayer insulating layer 103, the gate insulating layer 102, and the buffer layer 101 in order, and then is deposited on the substrate body 100. . That is, in the fan-out region 140, the number of the inorganic insulating layers provided with the grooves is at least two, and the grooves of the at least two inorganic insulating layers communicate with each other up and down, and the fan-out signal lines 300 are provided in all of the opened recesses A part of the inorganic insulating layer of the groove passes through the groove of each inorganic insulating layer in turn.
  • the fan-out signal line 300 is in direct contact with the flexible organic polymer material substrate body in the groove 200 to ensure that the signal line 300 is fanned out at the bent area 141 of the fan-out area 140 Flexibility, reducing the risk of fracture.
  • the fan-out signal line 300 and the data line of the pixel area 110 are disposed on the same layer and the same material over the entire fan-out area 140.
  • the fan-out signal line 300 is connected to the lead-out line of the data line, and the fan-out signal line 300 is connected to the signal line of the pixel area 110 through the lead-out line of the data line.
  • the grooves provided on the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are provided on the same center line, and the interlayer insulating layer 103 is provided.
  • the size of the groove is larger than the size of the groove provided on the gate insulating layer 102, and the size of the groove provided on the gate insulating layer 102 is larger than the size of the groove provided on the buffer layer 101. That is, in the fan-out area 140, when at least two inorganic insulating layers are provided with grooves from top to bottom, the distance between the first inorganic insulating layer and the substrate body 100 is greater than the distance between the second inorganic insulating layer and the substrate body 100.
  • the orthographic projection of the groove on the first non-insulating layer on the plane where the second inorganic insulating layer is located covers the entire first insulating layer.
  • Two grooves on the inorganic insulating layer By adopting the above-mentioned setting method, at the bent area 141 of the fan-out area 140, the entire groove 200 formed by combining the grooves on the inorganic insulating layer for making the fan-out signal line 300 pass through is formed so that the upper opening is larger than Structure with open bottom.
  • the surfaces of the sidewalls of the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 forming the groove are all formed as inclined surfaces, and the buffer layer 101 and the gate are insulated.
  • the surfaces of the inner side walls of the groove formed by the layer 102 and the interlayer insulating layer 103 are combined to form two opposite planes.
  • the surfaces of the sidewalls of each of the inorganic insulating layers forming the grooves are formed as inclined surfaces, and all The surface of the inner side wall of the inorganic insulating layer forming the groove is combined to form two opposite planes.
  • the fan-out signal line 300 is deposited on the flexible substrate body 100 in the groove at the bending area, Direct contact with the substrate of the flexible organic polymer material.
  • the fan-out signal line 300 is sequentially provided with a passivation layer 104 and a flat layer 105. Due to the arrangement of the grooves, the thickness of the flexible flat layer 105 is increased, and the thickness of the brittle inorganic layer is reduced. It is small, and because the fan-out signal line 300 is deposited on the flexible organic polymer material substrate body, the flexibility of the fan-out signal line 300 at the bending area 141 of the fan-out area 140 can be guaranteed, and the risk of fracture is reduced.
  • FIG. 7 a schematic cross-sectional view of the fan-out region at AA ′ is shown in FIG. 7, and in the bent region 141 of the fan-out region 140.
  • Grooves are formed in the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103, and the grooves on the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 communicate with each other, and are formed as slave layers
  • the inter-insulating layer 103 penetrates to the groove 200 of the buffer layer 101.
  • a resin layer 210 is deposited in the groove 200, and the resin layer 210 in the groove 200 is provided according to the shape of the groove 200, At the bottom of 200, the resin layer 210 is in direct contact with the substrate body 100.
  • a top opening of the groove 200 is located in a plane of the interlayer insulating layer 103 on a side away from the substrate body 100, and the substrate body 100 is close to the flat layer 105.
  • Part of the surface on one side constitutes the bottom of the groove 200, so that in the embodiment shown in FIG. 6, the depth of the groove 200 (that is, the distance from the top opening to the bottom) is the buffer layer 101 and the gate insulation layer The sum of the thicknesses of 102 and the interlayer insulating layer 103.
  • the depth of the groove 200 may also be smaller than the sum of the thicknesses of the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 (in this case, the top opening position of the groove 200 Unchanged, and the bottom position moves up), but cannot be greater than the sum of the thicknesses of the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103.
  • the opening size of the groove 200 parallel to the substrate body 100 gradually increases in a direction perpendicular to the substrate body 100 in a direction away from the substrate body 100.
  • any opening size of the recess 200 in the interlayer insulating layer 103 parallel to the substrate body 100 is larger than any opening size of the recess 200 in the gate insulating layer 102 parallel to the substrate body 100
  • the recess Any opening size of the groove 200 in the gate insulating layer 102 parallel to the substrate body 100 is larger than any opening size of the groove 200 in the buffer layer 101 parallel to the substrate body 100.
  • the portion of the fan-out signal line 300 located in the bending area 141 is disposed on the resin layer 210. Since the resin layer 210 is made of a flexible organic polymer material, the resin layer 210 is also filled in the groove 200 In the groove 200, the fan-out signal line 300 is in direct contact with the flexible organic polymer material layer. Through the setting of the resin layer 210, the depth of the groove 200 is reduced, and the fan-out area 140 is guaranteed. The effect of the flexibility of the fan-out signal line 300 at the bending region 141 of the fan-out region is reduced.
  • the resin layer 210 in the bent region 141 of the fan-out region 140, includes a portion located inside the groove 200, and further includes an insulation layer located outside the groove 200 and interposed with the interlayer. 103 direct contact.
  • the resin layer 210 covers the entire bending area of the fan-out area 140, so that the fan-out signal lines 300 of the entire bending area are disposed on the flexible organic polymer material layer to reduce the risk of fracture.
  • the implementation structure shown in FIG. 6 is the same.
  • the fan-out signal lines 300 and the data lines of the pixel area 110 are provided on the same layer and in the same material.
  • the grooves provided on the buffer layer 101, the gate insulation layer 102, and the interlayer insulation layer 103 are disposed on the same centerline, and the size of the grooves formed on the interlayer insulation layer 103 is larger than that of the gate.
  • the size of the grooves formed on the electrode insulation layer 102 and the size of the grooves formed on the gate insulation layer 102 are larger than the size of the grooves formed on the buffer layer 101.
  • the surfaces of the sidewalls of the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 forming the grooves are all formed as bevels, and the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are formed by bevels.
  • the surfaces of the side walls forming the interior of the groove are combined to form two opposing planes.
  • the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are sequentially formed on the bending region 141.
  • a through groove, and a resin layer 210 is deposited in the groove, so that the fan-out signal line 300 provided in the same layer and the same material as the data line is deposited on the resin layer 210.
  • the fan-out signal line 300 is in the recess.
  • the groove is deposited on the resin layer 210 and is in direct contact with the flexible organic polymer material layer.
  • the fan-out signal line 300 is sequentially provided with a passivation layer 104 and a flat layer 105. Due to the arrangement of the grooves, the thickness of the flexible flat layer 105 is increased, and the thickness of the brittle inorganic layer is reduced. It is small, and because the fan-out signal line 300 is deposited on the flexible organic polymer material layer, the flexibility of the fan-out signal line 300 at the bending area 141 of the fan-out area 140 can be ensured, and the risk of fracture is reduced.
  • FIG. 1 a schematic cross-sectional view of the fan-out area at AA ′ is shown in FIG. 8, and in the bent area 141 of the fan-out area 140.
  • Grooves are formed in the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103, and the grooves on the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 communicate with each other, and are formed as slave layers
  • the inter-insulating layer 103 penetrates to the groove 200 of the buffer layer 101.
  • grooves provided on the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are provided on the same centerline, and the interlayer insulating layer 103 is provided on the interlayer insulating layer 103.
  • the size of the opening groove is larger than the size of the opening groove on the gate insulating layer 102, and the size of the opening groove on the gate insulating layer 102 is larger than that of the buffer layer 101.
  • the distance between the first inorganic insulating layer and the substrate body 100 is greater than the distance between the second inorganic insulating layer and the substrate body 100.
  • the groove size on the first inorganic insulating layer is larger than the groove size on the second inorganic insulating layer.
  • the bottom opening size of the groove on the gate insulating layer 102 is larger than the top opening size of the groove on the buffer layer 101. That is, in the fan-out region 140, when a groove is provided on at least two inorganic insulating layers from top to bottom, and the first inorganic insulating layer provided with the groove is connected to the second inorganic insulating layer, the first A bottom opening size of the groove on the inorganic insulating layer is larger than a top opening size of the groove on the second inorganic insulating layer.
  • the surfaces of the inner sidewalls of the grooves formed in the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are all formed as slopes, and the gate insulating layer 102 and the interlayer insulating layer 103 are formed.
  • the two opposite first planes 801 formed by combining the surfaces of the inner side walls of the groove are different from the two opposite second planes 802 formed by the surface of the inner side wall of the groove formed by the buffer layer 101 flat.
  • the groove 200 penetrating from the interlayer insulating layer 103 to the buffer layer 101 includes a first groove portion 201 corresponding to the gate insulating layer 102 and the interlayer insulating layer 103 and a corresponding buffer layer.
  • the buffer layer 101 is formed in a stepped structure.
  • a resin layer 210 is deposited in the groove 200, and the resin layer 210 in the groove 200 is set according to the shape of the groove 200, and is located at the bottom of the groove 200.
  • the resin layer 210 is in direct contact with the substrate body 100.
  • the portion of the fan-out signal line 300 located in the bending area 141 is disposed on the resin layer 210. Since the resin layer 210 is made of a flexible material, the fan-out signal line 300 and the flexible organic polymer are in the groove 200. The material layer (ie, the resin layer 210) is in direct contact. In this implementation structure, since the groove 200 is formed in a stepped structure as shown in FIG. 8, compared with the implementation structure of FIG. 7, the steepness of the groove 200 in the bending region can be reduced, thereby reducing the fan-out signal line. Risk of breakage of 300.
  • the thickness of at least a portion of the resin layer 210 in the groove 200 is substantially the same, so that the surface of the portion of the resin layer 210 in the groove 200 facing the flat layer 105 is also the same.
  • a groove is formed, and the shape and orientation of the groove are substantially the same as those of the groove 200.
  • the resin layer 210 includes a portion located inside the groove 200 and a portion located outside the groove 200 and in direct contact with the interlayer insulating layer 103 so that the resin layer 210 covers the entire bent area of the fan-out area 140.
  • the fan-out signal line 300 may be provided on the same layer and the same material as the data line of the pixel area 110 over the entire fan-out area 140.
  • the thickness of the flexible flat layer 105 is increased, the thickness of the brittle inorganic layer is reduced, and the thickness of the brittle inorganic layer is reduced due to the arrangement of the groove 200.
  • 300 is deposited on the flexible organic polymer material layer, so that the flexibility of the fan-out signal line 300 at the bending region 141 of the fan-out region 140 can be ensured, and the risk of fracture is reduced.
  • the groove 200 is set to a stepped structure, so that the steepness of the groove 200 in the bending area is reduced, that is, the steepness of the groove 200 in the fan-out signal line 300 is reduced, thereby further reducing the fan-out. Risk of breakage of the signal line 300.
  • FIG. 9 a schematic cross-sectional view of the fan-out area at AA ′ is shown in FIG. 9, which is the same as the implementation structure shown in FIG. 8.
  • the bent region 141 of the fan-out region 140 grooves are formed in the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103, and the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are provided.
  • the grooves communicate with each other and are formed to penetrate from the interlayer insulating layer 103 to the groove 200 of the buffer layer 101.
  • the bottom opening size of the groove on the interlayer insulating layer 103 is larger than the top opening size of the groove on the gate insulating layer 102.
  • the surfaces of the inside walls of the grooves formed on the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are all formed as inclined surfaces, and the inside of the groove formed by the buffer layer 101 and the gate insulating layer 102 are The opposite two fourth planes 901 formed by combining the surfaces of the sidewalls are located on different planes from the opposite two third planes 902 formed by the surfaces of the sidewalls inside the groove formed by the interlayer insulating layer 103.
  • the groove 200 penetrating from the interlayer insulating layer 103 to the buffer layer 101 includes a third groove portion 203 corresponding to the buffer layer 101 and the gate insulating layer 102 and a corresponding interlayer insulating layer. Fourth groove portion 204 of 103. Therefore, inside the groove 200, the buffer layer 101 is formed in a step structure different from the implementation structure shown in FIG. 8, and the effect of reducing the steepness of the groove 200 in the bending region can also be achieved.
  • the arrangement manner of the fan-out signal line 300 and the arrangement manner of the resin layer 210 are the same as those of the implementation structure shown in FIG. 8, and are not repeated here.
  • the fan-out signal line 300 of the entire fan-out area 140 is provided at the same layer and the same material as the data line.
  • the present disclosure also provides an array substrate with the implementation structure shown in FIG. 10.
  • the fan-out signal line includes two circuit portions located in different material layers.
  • the buffer layer 101, the gate insulating layer 102, and the interlayer insulating layer 103 are all provided with grooves, and the buffer layer 101.
  • the grooves on the gate insulating layer 102 and the interlayer insulating layer 103 communicate with each other, and are formed to penetrate from the interlayer insulating layer 103 to the groove 200 of the buffer layer 101.
  • the surfaces of the sidewalls inside the grooves formed in the buffer layer 101, the gate insulation layer 102, and the interlayer insulation layer 103 are all formed as inclined surfaces. And the surfaces of the sidewalls inside the groove formed by the buffer layer 101 and the gate insulation layer 102 are combined to form two opposite planes, which are different from the surfaces of the sidewalls inside the groove formed by the interlayer insulation layer 103 flat. Therefore, the groove 200 penetrating from the interlayer insulating layer 103 to the buffer layer 101 includes a third groove portion 203 corresponding to the buffer layer 101 and the gate insulating layer 102 and a fourth groove portion 204 corresponding to the interlayer insulating layer 103.
  • a resin layer 210 is deposited in the groove 200, and the resin layer 210 in the groove 200 is provided according to the shape of the groove 200. At the bottom of 200, the resin layer 210 is in direct contact with the substrate body 100.
  • the fan-out signal line 300 and the pixel area 110 provided on the groove 200 are provided in the bent area 141 of the fan-out area 140.
  • the data lines are arranged in the same layer and the same material, that is, the fan-out signal lines 300 are deposited on the resin layer 210, that is, the first wiring portions are provided in the same layer and the same material as the data lines of the pixel unit.
  • the fan-out area 140 further includes a second line portion 310 of a gate line provided on the same layer as the gate line of the pixel area 110; wherein the fan-out signal line 300
  • the portion (ie, the first circuit portion) provided in the bending region 141 is connected to the second circuit portion 310 through the via hole 211.
  • the fan-out signal line 300 is connected to the signal line of the pixel region 110 by being connected to the second line portion 310.
  • the present disclosure also provides an array substrate of another implementation structure, as shown in FIG. 11.
  • this implementation structure compared to the implementation structure shown in FIG. 10, the interlayer insulating layer 103 and the flat layer are on the fan-out area 140. No passivation layer is provided between 105, and the arrangement structure of the other parts of the two implementation structures is the same.
  • no passivation layer is provided on the pixel region of the array substrate, and a flat layer is directly deposited on the fan-out signal line and connected to the fan-out signal line.
  • the fan-out signal line 300 is deposited on the resin layer 210, and the flat layer 105 is directly deposited on the fan-out signal line 300, thereby avoiding Compared with the array substrate of the implementation structure shown in FIG. 10, the arrangement of the brittle passivation layer further reduces the risk of fracture of the fan-out signal line 300 at the bending area.
  • the implementation structure of the other parts is the same except that the passivation layer is not provided above. Therefore, the other parts are not described here.
  • the detailed structural form is described. For details, please refer to the contents of the foregoing implementation structures.
  • the present disclosure also provides an array substrate of another implementation structure, as shown in FIG. 12.
  • the grid The electrode insulating layer 102 and the interlayer insulating layer 103 are both provided with a groove, and the buffer layer 101 is not provided with a groove.
  • the grooves formed on the gate insulating layer 102 and the interlayer insulating layer 103 communicate with each other, and are formed to penetrate from the interlayer insulating layer 103 to the groove 200 of the gate insulating layer 102.
  • the size of the grooves formed on the interlayer insulating layer 103 is larger than the size of the grooves formed on the gate insulating layer 102, and the inner sidewall of the groove formed by the interlayer insulating layer 103 and the gate insulating layer 102
  • the surfaces of are all inclined surfaces and are in different planes, so that the groove 200 is formed in a stepped structure.
  • the implementation structure of the other parts is the same except that the groove is not provided in the buffer layer described above.
  • the detailed structural forms of other parts are described. For details, refer to the contents of the foregoing implementation structures.
  • the surface of the sidewall of the groove 200 may be a stepped surface or a flat surface.
  • the two opposite sidewalls inside the groove 200 are both planes inclined with respect to the substrate body 100, while in the embodiments of FIGS. 8 to 12, the The two opposite side walls of the interior are stepped surfaces.
  • the array substrate shown in the implementation structure shown in FIG. 6 to FIG. 12 of the present disclosure is only the array substrate described in the embodiment of the present disclosure, and a recess is provided on the inorganic insulating layer in the fan-out area. Grooves to reduce the thickness of the inorganic insulating layer in the fan-out area, increase the thickness of the flat layer with better flexibility, and solve the problem of bending the fan-out area and easily break the signal line.
  • Several of the implementation structures are not specific. This is a limitation, and detailed description of each possible implementation structure is not provided here.
  • the gate, source, and drain electrodes may be made of metal materials such as Cu, Al, Mo, Ti, Cr, and W, or an alloy of these materials.
  • the layer structure may also adopt a multilayer structure, such as a multilayer structure formed as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, or Mo ⁇ Ti ⁇ Cu.
  • the active layer can be made of polysilicon-free or oxide (IGZO).
  • the buffer layer may be made of silicon nitride or silicon oxide; the buffer layer may be a single-layer structure or a multi-layer structure, such as a multi-layer structure formed of silicon oxide ⁇ silicon nitride.
  • the gate insulating layer may be made of silicon nitride or silicon oxide, and the gate insulating layer may be a single-layer structure or a multilayer structure, for example, formed as a multilayer of silicon oxide ⁇ silicon nitride structure.
  • the interlayer insulating layer may be made of silicon nitride or silicon oxide, and the interlayer insulating layer may be a single-layer structure or a multilayer structure, for example, formed as a multilayer of silicon oxide ⁇ silicon nitride structure.
  • the passivation layer may be made of silicon nitride or silicon oxide, and the passivation layer may be a single-layer structure or a multi-layer structure, for example, a multi-layer structure formed of silicon oxide ⁇ silicon nitride.
  • the flat layer may be made of a resin material
  • the pixel defining layer may be made of a resin material
  • the anode of the OLED may be made of indium tin oxide ITO, or ITO and Ag may be used to form an ITO / Ag / ITO structure.
  • the cathode of the OLED can be made of Al or Ag.
  • Another aspect of the embodiments of the present disclosure provides a display panel, which includes an array substrate having any of the above structures.
  • the present disclosure also provides a display device including the display panel as described above.
  • the fan-out signal line is arranged in the groove by opening a groove in the inorganic insulating layer of the fan-out area, thereby reducing the bending of the fan-out area.
  • the thickness of the inorganic insulating layer in the region increases the thickness of the flat layer with better flexibility, thereby solving the problem that the bending of the inorganic insulating layer in the bending region easily breaks the signal line.
  • the fan-out signal line is further deposited on the flexible organic polymer material layer, and / or the flexibility of the fan-out signal line at the bending area of the fan-out area is further ensured by reducing the steepness of the groove. To reduce the risk of fracture.

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Abstract

一种阵列基板、显示面板及显示装置。该阵列基板包括：基板本体（100），所述基板本体（100）上包括显示区域和非显示区域，所述非显示区域包括设置有扇出信号线（300）的扇出区域（140），且所述扇出信号线（300）连接所述显示区域内的信号线。所述扇出区域（140）包括设置于所述基板本体（100）与平坦层（105）之间的无机绝缘层，所述无机绝缘层上开设有第一凹槽（200），且所述扇出信号线（300）的至少一部分在所述基板本体（100）上的正投影位于所述第一凹槽（200）在所述基板本体（100）上的正投影内。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请主张在2018年9月27日在中国提交的中国专利申请No.201811130854.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其是指一种阵列基板、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diodes，OLED)显示器件，又称为有机电激光显示器件，因为具备自发光、轻薄和省电的特性，目前在显示设备上得到广泛应用。另外，当前OLED显示屏幕可以制成可弯曲的柔性屏幕，使所制成的显示产品更加多样化，具有广阔的市场应用前景。
为了简化柔性OLED显示器的结构，目前在制成显示区域的柔性基板上还直接制作驱动芯片IC，且柔性基板设置驱动电路的部分相较于设置显示区域的部分弯折，通常为弯折至设置显示区域的部分的背面，基于该设置结构，连接驱动电路和显示区域的信号线则设置在柔性基板的弯折区域上。
相关技术中，由于弯折区域上制作有多层的无机层，因此驱动电路与显示区域之间的信号线连接存在较高的断裂风险，从而影响柔性OLED显示器的使用性能。
发明内容
本公开技术方案的目的是提供一种阵列基板、显示面板及显示装置。
本公开提供一种阵列基板，包括：
基板本体，所述基板本体上包括显示区域和非显示区域，所述非显示区域包括设置有扇出信号线的扇出区域，且所述扇出信号线连接所述显示区域内的信号线；
其中，所述扇出区域包括设置于所述基板本体与平坦层之间的无机绝缘层，所述无机绝缘层上开设有第一凹槽，且所述扇出信号线的至少一部分在所述基板本体上的正投影位于所述第一凹槽在所述基板本体上的正投影内。
可选地，在所述的阵列基板中，所述平坦层沉积在所述扇出信号线上，与所述扇出信号线连接。
可选地，在所述的阵列基板中，所述第一凹槽的底部与所述第一凹槽的开口相对，所述基板本体的部分表面构成所述第一凹槽的底部，且所述扇出信号线的设置于所述第一凹槽的底部上的部分与所述基板本体直接接触。
可选地，所述第一凹槽的底部与所述第一凹槽的开口相对，所述基板本体的部分表面构成所述第一凹槽的底部，在所述第一凹槽内填充有有机高分子材料层，所述有机高分子材料层与所述第一凹槽的底部直接接触，所述扇出信号线设置于所述有机高分子材料层的远离所述基板本体的一侧，并与所述有机高分子材料层直接接触，且所述平坦层设置于所述扇出信号线的远离所述基板本体的一侧。
可选地，所述第一凹槽的底部与所述第一凹槽的开口相对，所述基板本体的部分表面构成所述第一凹槽的底部，所述有机高分子材料层与所述基板本体的部分表面直接接触。
可选地，在所述的阵列基板中，所述无机绝缘层包括依次设置于所述基板本体上的缓冲层、栅极绝缘层和层间绝缘层，所述第一凹槽的深度不大于所述缓冲层、所述栅极绝缘层和所述层间绝缘层的厚度之和，且所述扇出信号线设置于所述层间绝缘层上，其中一部分设置于所述第一凹槽内。
可选地，在所述的阵列基板中，所述第一凹槽贯穿所述缓冲层、所述栅极绝缘层和所述层间绝缘层以露出所述基板本体的部分表面，所述扇出信号线与所述基板本体的所述部分表面直接接触。
可选地，在所述的阵列基板中，所述无机绝缘层至少包括两层结构，所述第一凹槽平行于所述基板本体的开口尺寸在垂直于所述基板本体且沿远离所述基板本体的方向上逐渐增大。
可选地，在所述的阵列基板中，所述第一凹槽的侧壁的表面为阶梯面或平面。
可选地，在所述的阵列基板中，所述无机绝缘层包括互相直接接触的第一子无机绝缘层和第二子无机绝缘层。
可选地，在所述的阵列基板中，所述无机绝缘层包括依次设置于所述基板本体上的缓冲层、栅极绝缘层和层间绝缘层，所述第一凹槽在所述栅极绝缘层的开口尺寸大于所述第一凹槽在所述缓冲层的开口尺寸，且所述第一凹槽在所述层间绝缘层的开口尺寸大于所述第一凹槽在所述栅极绝缘层的开口尺寸。
可选地，在所述的阵列基板中，所述第一凹槽贯穿所述栅极绝缘层和所述层间绝缘层的部分的侧壁为第一平面，所述第一凹槽贯穿所述缓冲层的部分的侧壁为第二平面，且所述第一平面和第二平面位于不同平面。
可选地，在所述的阵列基板中，所述第一凹槽贯穿所述层间绝缘层的部分的侧壁为第三平面，所述第一凹槽贯穿所述栅极绝缘层和所述缓冲层的部分的侧壁为第四平面，且所述第三平面和第四平面位于不同平面。
可选地，在所述的阵列基板中，所述有机高分子材料层还包括位于所述第一凹槽的外部且与所述无机绝缘层贴合连接的部分。
可选地，在所述的阵列基板中，所述扇出信号线包括与所述像素单元的数据线同层同材料设置的第一线路部分和与所述像素单元的栅线同层同材料设置的第二线路部分；
其中，所述第一线路部分设置于所述第一凹槽内。
可选地，在所述的阵列基板中，所述基板本体为柔性基板本体。
可选地，在所述的阵列基板中，所述有机高分子材料层为柔性有机高分子材料层。
可选地，在所述的阵列基板中，在所述显示区域中设置有多个像素单元，在所述非显示区域或显示区域中还设置有驱动电路，所述驱动电路通过所述扇出信号线和所述显示区域内的信号线连接到所述多个像素单元。
本公开实施例还提供一种显示面板，包括如上任一项所述的阵列基板。
本公开实施例还提供一种显示装置，包括如上所述的显示面板。
附图说明
图1为本公开实施例所述阵列基板的平面示意图；
图2为本公开实施例所述阵列基板形成其中一种弯折状态的结构示意图；
图3为OLED显示器中，阵列基板上像素单元的驱动电路的电路结构示意图；
图4为所述阵列基板上像素单元的平面结构示意图；
图5为图4的B－B’处部分的剖面示意图；
图6为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的一种剖面示意图；
图7为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的另一种剖面示意图；
图8为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的又一种剖面示意图；
图9为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的又另一种剖面示意图；
图10为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的又另一种剖面示意图；
图11为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的又另一种剖面示意图；以及
图12为本公开实施例所述阵列基板的一些实施结构中，所述扇出区域在A-A’处的又另一种剖面示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
为解决阵列基板上驱动电路与显示区域之间的信号线容易断裂的问题，本公开实施例所述阵列基板，在扇出区域的无机绝缘层上设置凹槽，以减少扇出区域上无机绝缘层的厚度，增加柔韧性较好的平坦层的厚度，从而解决扇出区域弯折容易使信号线断裂的问题。
本公开实施例中，所述阵列基板包括：
柔性的基板本体，所述基板本体上包括：设置有多个像素单元的像素区域和设置有扇出信号线的扇出区域，所述扇出信号线连接所述像素区域的信号线；
其中，所述扇出区域包括设置于所述基板本体与平坦层之间的无机绝缘层，所述无机绝缘层上开设有凹槽，所述扇出信号线的至少一部分设置于所述凹槽内。
如图1所示为本公开实施例所述阵列基板的平面示意图。其中，该阵列基板的柔性的基板本体100上包括对应显示区域的像素区域110，且基板本体100上还制作有驱动电路120，驱动电路120通过扇出信号线连接像素区域110的信号线，因此扇出信号线在基板本体100上的布置区域，也即像素区域110与驱动电路120之间的区域形成为扇出区域140。如图1中所示，在显示区域中设置有多个像素单元11，驱动电路120通过扇出信号线300和显示区域内的栅线13和数据线12连接到多个像素单元11。本领域技术人员能够理解的是，图1中所示的像素单元、驱动电路、栅线和数据线等的数量和结构均仅是总体示意性的，并不代表阵列基板中这些元件的实际具体数量和结构。在下文中，将参照其他附图对像素单元、驱动电路、栅线和数据线等的示意性具体结构进行描述。此外，所述柔性的基板本体100例如可以由聚酰亚胺塑料、聚醚醚酮或透明导电涤纶等高分子材料制成，具有重量轻、厚度薄、柔软可弯曲的特点。
结合图2所示本公开实施例所述阵列基板形成其中一种弯折状态的结构示意图。其中，由于基板本体100采用柔性材料制成，扇出区域140能够弯折至像素区域110的背面，基于扇出区域140的该一弯折状态，使扇出区域140中的一部分形成弯折区域141，且弯折区域141将扇出区域140的其余部分划分为第一扇出区域142和第二扇出区域143，如图1所示。所述扇出区域140包括弯折区域141、第一扇出区域142和第二扇出区域143。
本公开实施例中，扇出区域140上包括设置于基板本体与平坦层之间的无机绝缘层，其中无机绝缘层上开设有凹槽，所述扇出信号线的至少一部分设置于所述凹槽内。
具体地，使扇出区域140上设置凹槽的部分形成为弯折区域141，通过在 弯折区域141的无机绝缘层上设置凹槽，以减少弯折区域141中无机绝缘层的厚度，增加柔韧性较好的平坦层的厚度，从而解决弯折区域141弯折容易使信号线断裂的问题。
可以理解的是，通常柔性的阵列基板应用于OLED显示器中，以下将以所述阵列基板应用于OLED显示器中为例，对本公开实施例所述阵列基板的实施结构进行详细说明。
如图3所示为OLED显示器中，阵列基板上像素单元的驱动电路的电路结构示意图，图4为所述阵列基板上像素单元的平面结构示意图。参阅图3和图4所示，阵列基板的像素单元包括用于实现OLED开关控制的薄膜晶体管(Thin Film Transistor，TFT)T1、用于实现OLED驱动的薄膜晶体管T2和存储电容Cs，其中开关TFT T1的栅极连接栅(Gate)线，源极连接数据(Data)线，漏极连接驱动TFT T2的栅极；驱动TFT T2的源极连接电源线(V dd)，漏极连接像素电极(OLED的阳极层1061)；存储电容Cs的一个电极连接至开关TFT T1的漏极和驱动TFT T2的栅极，另一个电极连接至TFT T2的源极。
以阵列基板上图4所示B－B’处部分的剖面为例，阵列基板的像素区域的各个像素单元中，如图5所示，分别包括：从下至上依次设置在基板本体100、缓冲层101、栅极绝缘层102、层间绝缘层103、钝化层104、平坦层105和像素界定层106，其中对应像素界定层106内设置有OLED的阳极层1061、有机发光层1062和阴极层1063。
进一步地，根据图5，缓冲层101上还设置有源层1011，栅极绝缘层102上设置有驱动TFT T2的栅极1021，穿透栅极绝缘层102与层间绝缘层103的过孔内设置有驱动TFT T2的源极1022和漏极1023，且层间绝缘层103上设置有Vdd线1和数据线2，结合图3，驱动TFT T2的漏极1023通过过孔与OLED的阳极层1061连接，驱动TFT T2的源极1022与Vdd线连接。
上述的图4和图5中展示了基板本体100上像素区域110的其中一实施结构示意图，可以理解的是，对应图1的扇出区域140设置有与像素区域110相对应且同层制作的缓冲层101、栅极绝缘层102、层间绝缘层103、钝化层104和平坦层105。
通常上述基板本体100上的缓冲层101、栅极绝缘层102、层间绝缘层103和钝化层104采用无机材料制作，多次弯折时存在较高的断裂风险，本公开实施例所述阵列基板，通过在扇出区域140的基板本体100上的无机绝缘层上开设凹槽，使扇出信号线的至少一部分设置于凹槽内，减少扇出区域140的弯折区域141中无机绝缘层的厚度，增加柔韧性较好的平坦层的厚度，从而解决弯折区域中的无机绝缘层弯折容易使信号线断裂的问题。
具体地，本公开实施例所述阵列基板，开设有凹槽的无机绝缘层可以为缓冲层101、栅极绝缘层102、层间绝缘层103和钝化层104中的任一个，或者为缓冲层101、栅极绝缘层102、层间绝缘层103和钝化层104中相邻的至少两个。其中，开设有凹槽200的无机绝缘层可以包括三个彼此直接接触的子无机绝缘层，如图6至图11中所示，无机绝缘层包括缓冲层101、栅极绝缘层102和层间绝缘层103；或者开设有凹槽200的无机绝缘层可以包括，如图12中所示无机绝缘层包括的栅极绝缘层102和层间绝缘层103。
可选地，本公开实施例所述阵列基板中，在所开设的凹槽内，扇出区域140的扇出信号线与一柔性有机高分子材料层直接接触，以增加信号线的柔韧性。其中，在凹槽内填充有柔性有机高分子材料层，所述扇出信号线与所述柔性有机高分子材料层直接接触；或者，所述扇出信号线与采用柔性有机高分子材料制作的所述基板本体直接接触。
可选地，该柔性有机高分子材料层可以采用树脂(例如环氧树脂)材料制作，具体也不限于仅能够采用该种材料。
本公开实施例所述阵列基板的一些实施结构中，结合图1所示，所述扇出区域在A-A’剖面示意图如图6所示，在扇出区域140的弯折区域141中，缓冲层101、栅极绝缘层102和层间绝缘层103上均开设有凹槽，且缓冲层101、栅极绝缘层102和层间绝缘层103上的凹槽相互连通，形成为从层间绝缘层103贯通至缓冲层101的凹槽200，也即缓冲层101、栅极绝缘层102和层间绝缘层103上的凹槽相互连通所组合形成的凹槽，其中扇出信号线300设置于层间绝缘层103上，在凹槽200内，扇出信号线300的一部分依次经过层间绝缘层103、栅极绝缘层102和缓冲层101上的凹槽后，沉积在基板本体100上。也即，在扇出区域140上，开设有凹槽的无机绝缘层的数量为 至少两个，且至少两个的无机绝缘层的凹槽上下连通，扇出信号线300设置于全部开设有凹槽的无机绝缘层上，其中的一部分依次经过每一无机绝缘层的凹槽。
由于基板本体100采用柔性材料制成，因此在凹槽200内，扇出信号线300与柔性有机高分子材料基板本体直接接触，以保证扇出区域140的弯折区域141处扇出信号线300的柔韧性，减小断裂的风险。
本公开实施例中，结合图1至图5，整个扇出区域140上，扇出信号线300与像素区域110的数据线同层同材料设置。可选地，扇出信号线300与数据线的引出线连接，通过数据线的引出线，扇出信号线300与像素区域110的信号线连接
另外，如图6所示，本公开实施例中，在缓冲层101、栅极绝缘层102和层间绝缘层103上所开设的凹槽同中心线设置，且层间绝缘层103上所开设凹槽的尺寸大于栅极绝缘层102上所开设凹槽的尺寸，栅极绝缘层102上所开设凹槽的尺寸大于缓冲层101上所开设凹槽的尺寸。也即，在扇出区域140中，当由上至下至少两个无机绝缘层上开设有凹槽，第一无机绝缘层与基板本体100的距离大于第二无机绝缘层与基板本体100的距离时，则第一无机绝缘层上的凹槽尺寸大于第二无机绝缘层上的凹槽尺寸，第一无绝缘层上的凹槽在第二无机绝缘层所在平面的正投影，覆盖整个的第二无机绝缘层上的凹槽。采用上述设置方式，使得在扇出区域140的弯折区域141处，多个无机绝缘层上凹槽相组合所形成的用于使扇出信号线300经过的整个凹槽200形成为上端开口大于下端开口的结构。
另外，可选地，如图6所示，缓冲层101、栅极绝缘层102和层间绝缘层103形成凹槽的内部的侧壁的表面均形成为斜面，且缓冲层101、栅极绝缘层102和层间绝缘层103所形成凹槽的内部的侧壁的表面相组合形成为相对的两个平面。也即，在扇出区域140中，当由上至下至少两个无机绝缘层上开设有凹槽时，每一无机绝缘层形成凹槽的内部的侧壁的表面均形成为斜面，且全部的无机绝缘层形成凹槽的内部的侧壁的表面相组合形成为相对的两个平面。
采用本公开实施例所述阵列基板的一些实施结构，在扇出区域140的弯 折区域141处，通过在缓冲层101、栅极绝缘层102和层间绝缘层103上形成依次贯通的凹槽，使与数据线同层同材料设置的扇出信号线300沉积于层间绝缘层103上时，在弯折区域处，扇出信号线300在凹槽内沉积于柔性的基板本体100上，与柔性有机高分子材料基板本体直接接触。
进一步地，如图6所示，扇出信号线300上依次设置有钝化层104和平坦层105，由于凹槽的设置，使柔性的平坦层105的厚度增加，脆性的无机层的厚度减小，又由于扇出信号线300沉积于柔性有机高分子材料基板本体上，从而能够保证扇出区域140的弯折区域141处扇出信号线300的柔韧性，减小断裂的风险。
本公开实施例所述阵列基板的一些实施结构中，结合图1所示，所述扇出区域在A-A’的剖面示意图如图7所示，在扇出区域140的弯折区域141中，缓冲层101、栅极绝缘层102和层间绝缘层103上均开设有凹槽，且缓冲层101、栅极绝缘层102和层间绝缘层103上的凹槽相互连通，形成为从层间绝缘层103贯通至缓冲层101的凹槽200。进一步地，该实施结构中，在扇出区域140的弯折区域141中，凹槽200内沉积有树脂层210，且凹槽200内的树脂层210依据凹槽200的形状设置，在凹槽200的底部，树脂层210与基板本体100直接接触。
进一步地，如图6所示，凹槽200的顶部开口位于所述层间绝缘层103的远离所述基板本体100的一侧的平面中，并且所述基板本体100的靠近所述平坦层105一侧的部分表面构成所述凹槽200的底部，从而在图6所示的实施例中所述凹槽200的深度(即从顶部开口到底部的距离)为缓冲层101、栅极绝缘层102和层间绝缘层103的厚度之和。在其他一些实施例中，所述凹槽200的深度也可以小于缓冲层101、栅极绝缘层102和层间绝缘层103的厚度之和(在这种情况下，凹槽200的顶部开口位置不变，而底部位置上移)，但不能大于缓冲层101、栅极绝缘层102和层间绝缘层103的厚度之和。
进一步地，如图6所示，凹槽200的平行于基板本体100的开口尺寸在垂直于所述基板本体100沿远离所述基板本体100的方向上逐渐增大。例如，凹槽200的位于层间绝缘层103中的平行于基板本体100的任一开口尺寸大于凹槽200的位于栅极绝缘层102中的平行于基板本体100的任一开口尺寸， 并且凹槽200的位于栅极绝缘层102中的平行于基板本体100的任一开口尺寸大于凹槽200的位于缓冲层101中的平行于基板本体100的任一开口尺寸。
基于该实施结构，扇出信号线300的位于弯折区域141中的部分设置于树脂层210上，由于树脂层210采用柔性有机高分子材料制成，树脂层210也就是填充在凹槽200内的柔性有机高分子材料层，因此在凹槽200内，扇出信号线300与柔性有机高分子材料层直接接触，通过树脂层210的设置，达到降低凹槽200的深度，保证扇出区域140的弯折区域141处扇出信号线300的柔韧性，减小断裂的风险的效果。
进一步，可选地，如图7所示，在扇出区域140的弯折区域141中，树脂层210包括位于凹槽200内部的部分，还包括位于凹槽200的外部且与层间绝缘层103直接接触的部分。采用该设置结构，树脂层210覆盖扇出区域140的整个弯折区域，使整个弯折区域的扇出信号线300均设置于柔性有机高分子材料层上，以减小断裂的风险。
另外，在图7所示的实施结构中，与图6所示的实施结构相同，整个扇出区域140上，扇出信号线300与像素区域110的数据线同层同材料设置。另外，如图7所示，在缓冲层101、栅极绝缘层102和层间绝缘层103上所开设的凹槽同中心线设置，且层间绝缘层103上所开设凹槽的尺寸大于栅极绝缘层102上所开设凹槽的尺寸，栅极绝缘层102上所开设凹槽的尺寸大于缓冲层101上所开设凹槽的尺寸。进一步地，缓冲层101、栅极绝缘层102和层间绝缘层103形成凹槽的内部的侧壁的表面均形成为斜面，且缓冲层101、栅极绝缘层102和层间绝缘层103所形成凹槽的内部的侧壁的表面相组合形成为相对的两个平面。
采用本公开实施例所述阵列基板的图7所示的实施结构，在扇出区域140的弯折区域141处，通过在缓冲层101、栅极绝缘层102和层间绝缘层103上形成依次贯通的凹槽，且在凹槽内沉积树脂层210，使与数据线同层同材料设置的扇出信号线300沉积于树脂层210上，在弯折区域处，扇出信号线300在凹槽内沉积于树脂层210上，与柔性有机高分子材料层直接接触。
进一步地，如图7所示，扇出信号线300上依次设置有钝化层104和平坦层105，由于凹槽的设置，使柔性的平坦层105的厚度增加，脆性的无机层 的厚度减小，又由于扇出信号线300沉积于柔性有机高分子材料层上，从而能够保证扇出区域140的弯折区域141处扇出信号线300的柔韧性，减小断裂的风险。
本公开实施例所述阵列基板的一些实施结构中，结合图1所示，所述扇出区域在A-A’的剖面示意图如图8所示，在扇出区域140的弯折区域141中，缓冲层101、栅极绝缘层102和层间绝缘层103上均开设有凹槽，且缓冲层101、栅极绝缘层102和层间绝缘层103上的凹槽相互连通，形成为从层间绝缘层103贯通至缓冲层101的凹槽200。
该实施结构中，如图8所示，可选地，在缓冲层101、栅极绝缘层102和层间绝缘层103上所开设的凹槽同中心线设置，且层间绝缘层103上所开设凹槽的尺寸大于栅极绝缘层102上所开设凹槽的尺寸，栅极绝缘层102上所开设凹槽的尺寸大于缓冲层101上所开设凹槽的尺寸。也即，在扇出区域140中，当由上至下至少两个无机绝缘层上开设有凹槽，第一无机绝缘层与基板本体100的距离大于第二无机绝缘层与基板本体100的距离时，则第一无机绝缘层上的凹槽尺寸大于第二无机绝缘层上的凹槽尺寸。
进一步地，如图8所示，栅极绝缘层102上凹槽的底部开口尺寸大于缓冲层101上凹槽的顶部开口尺寸。也即，当在扇出区域140中，当由上至下至少两个无机绝缘层上开设有凹槽，且开设有凹槽的第一无机绝缘层与第二无机绝缘层相连接时，第一无机绝缘层上凹槽的底部开口尺寸大于第二无机绝缘层上凹槽的顶部开口尺寸。
进一步地，缓冲层101、栅极绝缘层102和层间绝缘层103上所开设的凹槽的内部的侧壁的表面均形成为斜面，且栅极绝缘层102和层间绝缘层103所形成凹槽的内部的侧壁的表面相组合形成的相对的两个第一平面801，与缓冲层101所形成凹槽的内部的侧壁的表面所形成的相对的两个第二平面802位于不同平面。基于上述设置结构，如图8所示，从层间绝缘层103贯通至缓冲层101的凹槽200包括对应栅极绝缘层102和层间绝缘层103的第一凹槽部分201和对应缓冲层101的第二凹槽部分202。在凹槽200的内部，缓冲层101上形成为阶梯结构形式。
基于上述实施结构，在扇出区域140的弯折区域141中，凹槽200内沉 积有树脂层210，且凹槽200内的树脂层210依据凹槽200的形状设置，在凹槽200的底部，树脂层210与基板本体100直接接触。
另外，扇出信号线300的位于弯折区域141中的部分设置于树脂层210上，由于树脂层210采用柔性材料制成，因此在凹槽200内，扇出信号线300与柔性有机高分子材料层(即树脂层210)直接接触。该实施结构中，由于凹槽200形成为如图8所示的阶梯结构形式，相较于图7的实施结构，可降低弯折区域的凹槽200的陡度，从而减小扇出信号线300的断裂风险。在一个实施例中，所述树脂层210的至少在所述凹槽200内的部分的厚度基本相同，从而所述树脂层210在所述凹槽200内的部分的朝向平坦层105的表面也形成一个凹槽，该凹槽的形状和方位与凹槽200的形状和方位大致相同。
树脂层210包括位于凹槽200内部的部分，还包括位于凹槽200的外部且与层间绝缘层103直接接触的部分，以使树脂层210覆盖扇出区域140的整个弯折区域。
另外，在该实施结构中，与上述实施结构相同，整个扇出区域140上，扇出信号线300可以与像素区域110的数据线同层同材料设置。
采用本公开实施例所述阵列基板的图8所示的实施结构，通过凹槽200的设置，使柔性的平坦层105的厚度增加，脆性的无机层的厚度减小，又由于扇出信号线300沉积于柔性有机高分子材料层上，从而能够保证扇出区域140的弯折区域141处扇出信号线300的柔韧性，减小断裂的风险。另外，还将凹槽200设置为阶梯结构形式，使得弯折区域的凹槽200的陡度降低，也即使得扇出信号线300凹槽200内设置的陡度降低，从而进一步减小扇出信号线300的断裂风险。
本公开实施例所述阵列基板的一些实施结构中，结合图1所示，所述扇出区域在A-A’的剖面示意图如图9所示，与图8所示的实施结构相同，在扇出区域140的弯折区域141中，缓冲层101、栅极绝缘层102和层间绝缘层103上均开设有凹槽，且缓冲层101、栅极绝缘层102和层间绝缘层103上的凹槽相互连通，形成为从层间绝缘层103贯通至缓冲层101的凹槽200。
与图8所示的实施结构不同，层间绝缘层103上凹槽的底部开口尺寸大于栅极绝缘层102上凹槽的顶部开口尺寸。缓冲层101、栅极绝缘层102和 层间绝缘层103上所开设的凹槽的内部的侧壁的表面均形成为斜面，且缓冲层101和栅极绝缘层102所形成凹槽的内部的侧壁的表面相组合形成的相对的两个第四平面901，与层间绝缘层103所形成凹槽的内部的侧壁的表面所形成的相对的两个第三平面902位于不同平面。
基于上述设置结构，如图9所示，从层间绝缘层103贯通至缓冲层101的凹槽200包括对应缓冲层101和栅极绝缘层102的第三凹槽部分203和对应层间绝缘层103的第四凹槽部分204。因此，在凹槽200的内部，缓冲层101上形成为与图8所示实施结构不同的阶梯结构形式，也可以达到降低弯折区域的凹槽200的陡度的效果。
另外，图9所示的实施结构中，扇出信号线300的设置方式以及树脂层210的设置方式与图8所示的实施结构相同，在此不再赘述。
在上述图6所示的实施结构至图9所示的实施结构中，整个扇出区域140的扇出信号线300均与数据线同层同材料设置。另外本公开还提供图10所示的实施结构的阵列基板，在扇出区域140上，扇出信号线包括位于不同材料层的两个线路部分。
在图10所示的实施结构的阵列基板中，在扇出区域140的弯折区域141中，缓冲层101、栅极绝缘层102和层间绝缘层103上均开设有凹槽，且缓冲层101、栅极绝缘层102和层间绝缘层103上的凹槽相互连通，形成为从层间绝缘层103贯通至缓冲层101的凹槽200。
另外，与图9所示的实施结构相同，如图10所示，缓冲层101、栅极绝缘层102和层间绝缘层103上所开设的凹槽的内部的侧壁的表面均形成为斜面，且缓冲层101和栅极绝缘层102所形成凹槽的内部的侧壁的表面相组合形成相对的两个平面，与层间绝缘层103所形成凹槽的内部的侧壁的表面位于不同平面。因此，从层间绝缘层103贯通至缓冲层101的凹槽200包括对应缓冲层101和栅极绝缘层102的第三凹槽部分203和对应层间绝缘层103的第四凹槽部分204。
另外，如图10所示，在扇出区域140的弯折区域141中，凹槽200内沉积有树脂层210，且凹槽200内的树脂层210依据凹槽200的形状设置，在凹槽200的底部，树脂层210与基板本体100直接接触。
另外，与图9所示的实施结构不同，在图10所示的实施结构中，在扇出区域140的弯折区域141中，设置于凹槽200上的扇出信号线300与像素区域110的数据线同层同材料设置，也即扇出信号线300沉积于树脂层210上，也即包括与像素单元的数据线同层同材料设置的第一线路部分。
另外，如图10所示，并结合图1至图5，在扇出区域140上还包括与像素区域110的栅线同层设置的栅线的第二线路部分310；其中扇出信号线300的设置于弯折区域141中的部分(即第一线路部分)通过过孔211与第二线路部分310连接。基于该设置结构，通过与第二线路部分310连接，扇出信号线300与像素区域110的信号线连接。
对比图9和图10，除上述扇出区域140上扇出信号线300与像素区域110的信号线的连接方式不同，两个实施结构的其他部分的设置结构相同，其他部分的设置结构可以参阅以上的详细描述，在此不再赘述。
本公开还提供另一种实施结构的阵列基板，如图11所示，在该实施结构中，相较于图10所示的实施结构，扇出区域140上，层间绝缘层103与平坦层105之间未设置钝化层，两个实施结构的其他部分的设置结构相同。
可以理解的是，采用该实施结构，阵列基板的像素区域上也未设置钝化层，平坦层直接沉积在所述扇出信号线上，与扇出信号线连接。
基于上述的设置结构，根据图11所示，在扇出区域140的弯折区域141处，扇出信号线300沉积于树脂层210上，平坦层105直接沉积于扇出信号线300，避免了脆性的钝化层的设置，相较于图10所示的实施结构的阵列基板，进一步达到减小扇出信号线300在弯折区域处的断裂风险的效果。
由于图11所示的实施结构的阵列基板相较于图10所示的实施结构的阵列基板，除上述不设置钝化层之外，其他部分的实施结构相同，因此在此不再对其他部分的详细结构形式进行描述，具体可以参阅上述各实施结构的内容。
另外，本公开还提供另一种实施结构的阵列基板，如图12所示，在该实施结构中，与图11所示的实施结构不同，在扇出区域140的弯折区域141中，栅极绝缘层102和层间绝缘层103上均开设有凹槽，缓冲层101上未开设有凹槽。栅极绝缘层102和层间绝缘层103上所形成的凹槽相互连通，形成为 从层间绝缘层103贯通至栅极绝缘层102的凹槽200。
进一步地，层间绝缘层103上所开设凹槽的尺寸大于栅极绝缘层102上所开设凹槽的尺寸，且层间绝缘层103和栅极绝缘层102所形成凹槽的内部的侧壁的表面均为斜面，且处于不同平面，因此使凹槽200形成为阶梯结构形式。
基于上述的设置方式，也能够达到降低弯折区域的凹槽200的陡度的效果。
由于图12所示的实施结构的阵列基板相较于图11所示的实施结构的阵列基板，除上述未在缓冲层设置凹槽之外，其他部分的实施结构相同，因此在此不再对其他部分的详细结构形式进行描述，具体可以参阅上述各实施结构的内容。
进一步地，凹槽200的侧壁的表面可以为阶梯面或平面。例如在图6和图7的实施中，凹槽200的内部的两个相对的侧壁均为相对于基板本体100倾斜的平面，而在图8至图12的实施例中，凹槽200的内部的两个相对的侧壁均为阶梯面。
可以理解的是，以上本公开图6所示的实施结构至图12所示的实施结构的阵列基板，仅为本公开实施例所述阵列基板，通过在扇出区域的无机绝缘层上设置凹槽，达到减少扇出区域上无机绝缘层的厚度，增加柔韧性较好的平坦层的厚度，解决扇出区域弯折容易使信号线断裂问题技术效果的其中几种实施结构，具体并不以此为限，在此不再对可能的每一实施结构进行详细说明。
本公开实施例上述结构的阵列基板中，栅极、源极、漏极可以采用Cu、Al、Mo、Ti、Cr和W等金属材料制备，也可以采用该些材料的合金制备，可以是单层结构，也可以采用多层结构，如形成为Mo\Al\Mo、Ti\Cu\Ti或者Mo\Ti\Cu的多层结构。另外，有源层可以采用无多晶硅或氧化物(IGZO)制作。
本公开实施例中，缓冲层可以采用氮化硅或氧化硅制作；缓冲层可以是单层结构，可以是多层结构，例如形成为氧化硅\氮化硅的多层结构。
本公开实施例中，栅极绝缘层可以采用氮化硅或氧化硅制作，且栅极绝 缘层可以为单层结构，也可以为多层结构，例如形成为氧化硅\氮化硅的多层结构。
本公开实施例中，层间绝缘层可以采用氮化硅或氧化硅制作，且层间绝缘层可以为单层结构，也可以为多层结构，例如形成为氧化硅\氮化硅的多层结构。
本公开实施例中，钝化层可以采用氮化硅或氧化硅制作，且钝化层可以为单层结构，也可以为多层结构，例如形成为氧化硅\氮化硅的多层结构。
进一步，平坦层可以采用树脂材料制备，像素界定层可以采用树脂材料制备，OLED的阳极可以采用氧化铟锡ITO制备，或者采用ITO和Ag制备为ITO/Ag/ITO结构。另外，OLED的阴极可以采用Al或Ag制备。
结合图1至图12，并根据以上本公开实施例所述阵列基板的详细说明，本领域技术人员应该能够了解本公开实施例所述阵列基板的具体制作过程，在此不再详细说明。
本公开实施例另一方面还提供一种显示面板，其中，包括如上任一结构的阵列基板。
另外，本公开还提供一种显示装置，包括如上所述的显示面板。
结合图1至图12，并参阅以上的详细描述。本领域技术人员应该能够了解采用本公开实施例所述阵列基板的显示面板和显示装置的具体结构，在此不再详细说明。
本公开实施例所述阵列基板、显示面板及显示装置，通过在扇出区域的无机绝缘层上开设凹槽，使扇出信号线的至少一部分设置于凹槽内，减少扇出区域的弯折区域中无机绝缘层的厚度，增加柔韧性较好的平坦层的厚度，从而解决弯折区域中的无机绝缘层弯折容易使信号线断裂的问题。此外，又进一步地使扇出信号线沉积于柔性有机高分子材料层上，和/或通过降低凹槽的陡度的方式，进一步保证扇出区域的弯折区域处扇出信号线的柔韧性，减小断裂的风险。
以上所述的是本公开的优选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本公开所述原理前提下，还可以作出若干改进有机高分子材料和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种阵列基板，包括：
    基板本体，所述基板本体上包括显示区域和非显示区域，所述非显示区域包括设置有扇出信号线的扇出区域，且所述扇出信号线连接所述显示区域内的信号线；
    其中，所述扇出区域包括设置于所述基板本体与平坦层之间的无机绝缘层，所述无机绝缘层上开设有第一凹槽，且所述扇出信号线的至少一部分在所述基板本体上的正投影位于所述第一凹槽在所述基板本体上的正投影内。
  2. 根据权利要求1所述的阵列基板，其中，所述平坦层沉积在所述扇出信号线上，与所述扇出信号线连接。
  3. 根据权利要求1所述的阵列基板，其中，所述第一凹槽的底部与所述第一凹槽的开口相对，所述基板本体的部分表面构成所述第一凹槽的底部，且所述扇出信号线的设置于所述第一凹槽的底部上的部分与所述基板本体直接接触。
  4. 根据权利要求1所述的阵列基板，其中，所述第一凹槽的底部与所述第一凹槽的开口相对，所述基板本体的部分表面构成所述第一凹槽的底部，在所述第一凹槽内填充有有机高分子材料层，所述有机高分子材料层与所述第一凹槽的底部直接接触，所述扇出信号线设置于所述有机高分子材料层的远离所述基板本体的一侧，并与所述有机高分子材料层直接接触，且所述平坦层设置于所述扇出信号线的远离所述基板本体的一侧。
  5. 根据权利要求4所述的阵列基板，其中，所述第一凹槽的底部与所述第一凹槽的开口相对，所述基板本体的部分表面构成所述第一凹槽的底部，所述有机高分子材料层与所述基板本体的部分表面直接接触。
  6. 根据权利要求1至5任一项所述的阵列基板，其中，所述无机绝缘层包括依次设置于所述基板本体上的缓冲层、栅极绝缘层和层间绝缘层，所述第一凹槽的深度不大于所述缓冲层、所述栅极绝缘层和所述层间绝缘层的厚度之和，且所述扇出信号线设置于所述层间绝缘层上，其中一部分设置于所述第一凹槽内。
  7. 根据权利要求6所述的阵列基板，其中，所述第一凹槽贯穿所述缓冲层、所述栅极绝缘层和所述层间绝缘层以露出所述基板本体的部分表面，所述扇出信号线与所述基板本体的所述部分表面直接接触。
  8. 根据权利要求1所述的阵列基板，其中，所述无机绝缘层至少包括两层结构，所述第一凹槽平行于所述基板本体的开口尺寸在垂直于所述基板本体且沿远离所述基板本体的方向上逐渐增大。
  9. 根据权利要求8所述的阵列基板，其中，所述第一凹槽的侧壁的表面为阶梯面或平面。
  10. 根据权利要求9所述的阵列基板，其中，所述无机绝缘层包括互相直接接触的第一子无机绝缘层和第二子无机绝缘层。
  11. 根据权利要求8所述的阵列基板，其中，所述无机绝缘层包括依次设置于所述基板本体上的缓冲层、栅极绝缘层和层间绝缘层，所述第一凹槽在所述栅极绝缘层的开口尺寸大于所述第一凹槽在所述缓冲层的开口尺寸，且所述第一凹槽在所述层间绝缘层的开口尺寸大于所述第一凹槽在所述栅极绝缘层的开口尺寸。
  12. 根据权利要求11所述的阵列基板，其中，所述第一凹槽贯穿所述栅极绝缘层和所述层间绝缘层的部分的侧壁为第一平面，所述第一凹槽贯穿所述缓冲层的部分的侧壁为第二平面，且所述第一平面和第二平面位于不同平面。
  13. 根据权利要求11所述的阵列基板，其中，所述第一凹槽贯穿所述层间绝缘层的部分的侧壁为第三平面，所述第一凹槽贯穿所述栅极绝缘层和所述缓冲层的部分的侧壁为第四平面，且所述第三平面和第四平面位于不同平面。
  14. 根据权利要求3或5所述的阵列基板，其中，所述有机高分子材料层还包括位于所述第一凹槽的外部且与所述无机绝缘层贴合连接的部分。
  15. 根据权利要求1所述的阵列基板，其中，所述扇出信号线包括与所述像素单元的数据线同层同材料设置的第一线路部分和与所述像素单元的栅线同层同材料设置的第二线路部分；
    其中，所述第一线路部分设置于所述第一凹槽内。
  16. 根据权利要求1所述的阵列基板，其中，所述基板本体为柔性基板本体。
  17. 根据权利要求1所述的阵列基板，其中，在所述显示区域中设置有多个像素单元，在所述非显示区域或显示区域中还设置有驱动电路，所述驱动电路通过所述扇出信号线和所述显示区域内的信号线连接到所述多个像素单元。
  18. 根据权利要求3或5所述的阵列基板，其中，所述有机高分子材料层为柔性有机高分子材料层。
  19. 一种显示面板，包括权利要求1至18任一项所述的阵列基板。
  20. 一种显示装置，包括权利要求19所述的显示面板。
PCT/CN2019/099787 2018-09-27 2019-08-08 阵列基板、显示面板及显示装置 WO2020063128A1 (zh)

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