WO2024021117A1 - 一种阵列基板、显示面板、显示装置和拼接显示装置 - Google Patents

一种阵列基板、显示面板、显示装置和拼接显示装置 Download PDF

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Publication number
WO2024021117A1
WO2024021117A1 PCT/CN2022/109236 CN2022109236W WO2024021117A1 WO 2024021117 A1 WO2024021117 A1 WO 2024021117A1 CN 2022109236 W CN2022109236 W CN 2022109236W WO 2024021117 A1 WO2024021117 A1 WO 2024021117A1
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Prior art keywords
layer
substrate
wiring layer
array substrate
electrodes
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PCT/CN2022/109236
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English (en)
French (fr)
Inventor
孙双
张方振
王新星
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/109236 priority Critical patent/WO2024021117A1/zh
Priority to CN202280002469.1A priority patent/CN117795683A/zh
Publication of WO2024021117A1 publication Critical patent/WO2024021117A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a display panel, a display device and a spliced display device.
  • Micro Light Emitting Diode (Micro LED for short) is called the third generation display technology. Micro LED display devices are unable to achieve the production of oversized products due to technical pressures such as massive transfer and repair of dead pixels. Therefore, for products with such large displays, the best solution currently is small-size display splicing.
  • some embodiments of the present disclosure provide an array substrate.
  • the array substrate includes: a base, a wiring layer, a plurality of second electrodes and a protective layer.
  • the wiring layer is provided on the substrate; a plurality of second electrodes are provided on a side of the substrate away from the wiring layer, and the wiring layer is electrically connected to the plurality of second electrodes; a protective layer is provided between the substrate and the wiring layer and/or between the substrate and the plurality of second electrodes.
  • the protective layer includes a reflective layer, and the reflective layer is disposed between the substrate and the wiring layer and/or between the substrate and the plurality of second electrodes.
  • the reflective layer includes at least two film layers stacked in a stack, wherein the reflective layer includes two materials with different refractive indexes, and the materials of two adjacent film layers are different.
  • two materials with different refractive indexes include a first material.
  • the wavelength of the laser to be reflected by the reflective layer is determined.
  • the product of the thickness of the film layer formed by the first material and the refractive index of the first material is the product to be reflected. 1/4 times the wavelength of light.
  • two materials with different refractive indexes include a second material.
  • the wavelength of the laser to be reflected by the reflective layer is determined.
  • the product of the thickness of the film layer formed by the second material and the refractive index of the second material is the product to be reflected. 1/4 times the wavelength of light.
  • the two materials with different refractive indexes include a first material, the first material is titanium dioxide, and a film layer formed of the first material is disposed on the substrate.
  • the second material is silicon dioxide.
  • the protective layer includes an energy absorption layer, and the energy absorption layer is disposed between the substrate and the wiring layer and/or between the substrate and the plurality of second electrodes.
  • the energy absorbing layer has a bandgap width less than 3.5 eV.
  • the material of the energy absorbing layer is titanium dioxide.
  • the wiring layer includes a plurality of connection traces, the plurality of connection traces are electrically connected to the plurality of second electrodes, and the orthographic projection of the multiple connection traces on the substrate is located at the orthographic projection of the protective layer on the substrate. internal.
  • the wiring layer includes a driving circuit layer
  • the driving circuit layer includes: an active layer and a gate layer, wherein the active layer is provided on the substrate or protective layer, and the gate layer is provided on the active layer away from the substrate. side.
  • the orthographic projection of the active layer on the substrate is located inside the orthographic projection of the protective layer on the substrate.
  • the display panel includes: the array substrate as described in any of the above embodiments and a plurality of light-emitting devices.
  • the array substrate includes a base and a driving circuit layer disposed on the base, and a plurality of light-emitting devices are arranged in an array on the driving circuit layer one layer away from the base.
  • some embodiments of the present disclosure provide a display device.
  • the display device includes: the display panel and the driving circuit board of the above embodiment.
  • the display panel includes a substrate and a wiring layer.
  • the wiring layer is provided on the substrate.
  • the driving circuit board is disposed on a side of the substrate away from the wiring layer.
  • the driving circuit board is electrically connected to the wiring layer through the flexible circuit board.
  • the spliced display device includes: a plurality of display devices as described in the above embodiments, and the plurality of display devices are spliced and assembled.
  • Figure 1 is a structural diagram of a display device provided by some embodiments of the present disclosure.
  • Figure 2 is a front structural view of a display device provided by some embodiments of the present disclosure.
  • Figure 3 is a rear structural view of a display device provided by some embodiments of the present disclosure.
  • Figure 4 is a structural diagram of a display panel provided by some embodiments of the present disclosure.
  • Figure 5 is a front structural view of a display panel provided by some embodiments of the present disclosure.
  • Figure 6 is a structural diagram of a lamp area and a driver chip of a display panel provided by some embodiments of the present disclosure
  • Figure 7 is a structural diagram of another display panel provided by some embodiments of the present disclosure.
  • Figure 8 is a structural diagram of a first display panel with a protective layer provided by some embodiments of the present disclosure.
  • Figure 9 is a structural diagram of a second display panel with a protective layer provided by some embodiments of the present disclosure.
  • Figure 10 is a structural diagram of a third display panel with a protective layer provided by some embodiments of the present disclosure.
  • Figure 11 is a structural diagram of a fourth display panel with a protective layer provided by some embodiments of the present disclosure.
  • Figure 12 is a structural diagram of a first display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 13 is a structural diagram of a second display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 14 is a structural diagram of a third display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 15 is a structural diagram of a reflective layer provided by some embodiments of the present disclosure.
  • Figure 16 is a structural diagram of a fourth display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 17 is a structural diagram of a fifth display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 18 is a structural diagram of a sixth display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 19 is a structural diagram of a seventh display panel with a reflective layer provided by some embodiments of the present disclosure.
  • Figure 20 is a structural diagram of a first display panel with an energy absorption layer provided by some embodiments of the present disclosure
  • Figure 21 is a structural diagram of a second display panel with an energy absorption layer provided by some embodiments of the present disclosure.
  • Figure 22 is a structural diagram of a third display panel with an energy absorption layer provided by some embodiments of the present disclosure.
  • Figure 23 is a structural diagram of a first display panel with an energy absorption layer and an absorption layer provided by some embodiments of the present disclosure
  • Figure 24 is a structural diagram of a second display panel with an energy absorption layer and an absorption layer provided by some embodiments of the present disclosure
  • Figure 25 is a structural diagram of a third display panel with an energy absorption layer and an absorption layer provided by some embodiments of the present disclosure
  • Figure 26 is a structural diagram of a fourth display panel with an energy absorption layer and an absorption layer provided by some embodiments of the present disclosure
  • Figure 27 is a structural diagram of a fifth display panel with an energy absorption layer and an absorption layer provided by some embodiments of the present disclosure
  • Figure 28 is a structural diagram of a sixth display panel with an energy absorption layer and an absorption layer provided by some embodiments of the present disclosure
  • Figure 29 is a structural diagram of a splicable display device provided by some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the display device 1000 includes a display panel 100 and a driving circuit board 200 .
  • the drive circuit board 200 may be disposed on the non-display surface O side of the display panel 100.
  • the drive circuit board 200 is configured as a drive integrated circuit (IC, Integrated Circuit) that drives the display panel 100 to display.
  • the drive circuit board 200 includes, for example, a gate.
  • the drive circuit board 200 is electrically connected to the display panel 100 and is configured to output corresponding signals to control the display panel 100 to display.
  • the display panel 100 includes a display area AA and a peripheral area BB provided at least on one side of the display area AA.
  • the peripheral area BB may be located on one side, both sides, or both sides of the display area AA.
  • Three sides, or peripheral areas BB, may be provided around the display area AA.
  • a plurality of pixels P and a plurality of signal lines 60 arranged in an array are provided in the display area AA, and the plurality of signal lines 60 are electrically connected to the plurality of pixels P.
  • Each pixel P includes a plurality of sub-pixels SP.
  • the sub-pixel SP is the smallest unit of the display panel 100 for picture display.
  • Each sub-pixel SP can display a single color, such as red (R), green (G) or blue ( B), adjust the brightness (gray scale) of the sub-pixels SP of different colors, and realize the display of multiple colors through color combination and superposition, thereby realizing the full-color display of the display panel 100.
  • Each sub-pixel SP includes at least one light-emitting device, which may be an inorganic light-emitting diode.
  • the light-emitting device is a sub-millimeter light-emitting diode (Mini Light Emitting Diode, Mini LED) and/or a micro light-emitting diode (Micro Light Emitting Diode). , Micro LED).
  • the size of sub-millimeter light-emitting diodes is greater than or equal to 100 ⁇ m and less than 500 ⁇ m, and the size of micro-light-emitting diodes is less than 100 ⁇ m.
  • each pixel P receives the electrical signal transmitted by the corresponding signal line 60 and emits light. Under the control of different electrical signals, the pixel P generates different brightness (gray scale), so that all pixels P on the display panel 100 Generate screen.
  • multiple pixels P are scanned line by line and are provided with a set of data signals by the corresponding signal lines 60, thereby displaying a picture under the control of the data signals. After the multiple pixels P are scanned again During progressive scanning, when each pixel P receives a new set of data signals provided by the signal line 60 that is electrically connected to it, it displays a new picture, thereby refreshing the display picture, and successively refreshing multiple display pictures to form a display image.
  • the light-emitting device uses sub-millimeter light-emitting diodes and/or micro-light-emitting diodes. Under the pressure of existing process capabilities and cost factors, large-size display panels cannot be directly produced. The current solution is to use multiple small-sized display panels.
  • the display panel is spliced to achieve large size. As shown in FIG. 1 , the driving circuit board 200 of the display device 1000 is bound to the non-display surface O side of the display panel, which can reduce the width of the peripheral area and facilitate the splicing of the display panels 100 into a large-size display device.
  • Figure 1 is a cross-sectional view along the A-A direction in Figure 2
  • Figure 2 is a structural diagram of the display surface side of the display device 1000
  • Figure 3 is a display Structural diagram of the non-display surface O side of the device 1000.
  • the display panel 100 includes an array substrate 10 , a light emitting device layer 20 , a plurality of first electrodes 30 , a plurality of side traces 40 and a plurality of second electrodes 50 .
  • the array substrate 10 includes a first surface 10a, a second surface 10b opposite the first surface 10a, and a plurality of side surfaces 10c connecting the first surface 10a and the second surface 10b, wherein the second surface 10b of the array substrate 10 is also The non-display surface O side of the display device.
  • a light emitting device layer 20 and a plurality of first electrodes 30 are provided on the first surface 10a of the array substrate 10, wherein the plurality of first electrodes 30 are close to the selected side.
  • the plurality of side traces 40 include part of the traces provided on the first surface 10a, part of the traces provided on the selected side and part of the traces provided on the second surface 10b.
  • the driving circuit board 200 and a plurality of second electrodes 50 are disposed on the second surface 10b of the array substrate 10, wherein the plurality of second electrodes 50 are close to selected side surfaces.
  • the plurality of first electrodes 30 are electrically connected to the light emitting device layer 20 and the corresponding side traces 40; the plurality of second electrodes 50 are connected to the drive circuit board 200/flexible circuit board 70 (Flexible Printed Circuit, FPC) and the corresponding side traces. 40 is electrically connected, wherein the flexible circuit board 70 can electrically connect the second electrode 50 and the driving circuit board 200 .
  • the driving circuit board 200 is electrically connected to the second electrode 50 , the side wiring 40 and the first electrode 30 in sequence, and transmits the electrical signal to the light emitting device layer 20 .
  • the first electrode 30 located on the first surface 10a of the array substrate 10 and the second electrode 50 located on the second surface 10b of the array substrate 10 are formed by electroplating, evaporation, pad printing silver paste or wet etching. It is prepared by etching and other processes.
  • a metal plating layer can be prepared on the first surface 10a, the selected side surface and the second surface 10b of the array substrate 10, and the metal plating layer can be etched and patterned using a laser to obtain multiple side traces.
  • the array substrate 10 includes a substrate 11 and a wiring layer 12 disposed on the substrate 11 .
  • the substrate 11 may include a base 111 and a buffer layer (Buffer) 112.
  • the base 111 may be a silicon substrate
  • the buffer layer 112 is disposed on the base 111
  • the wiring layer 12 is disposed on the side of the buffer layer 112 away from the base 111.
  • the wiring layer 12 may include a plurality of connecting wirings
  • the light-emitting device layer 20 may include a plurality of light-emitting devices 21 and a plurality of driving chips 22 arranged in an array.
  • the array substrate includes a plurality of lamp areas Q arranged in an array. Each lamp area Q is provided with a number of series and/or parallel light-emitting devices 21 and at least one driver chip 22, wherein several series and/or parallel light-emitting devices 21 located in the same lamp area Q are arranged. Or the light-emitting device 21 connected in parallel is electrically connected to the driving chip 22 .
  • the plurality of connection traces include a first power supply voltage signal line VLED, a second power supply voltage signal line PWR, a third power supply voltage signal line GND, an addressing signal line Addr, and a feedback signal line FB.
  • One lamp area Q may include several light-emitting devices 21, for example, the number of light-emitting devices may be four, six or eight.
  • a lamp area Q includes four light-emitting devices 21 connected in series, wherein the first end of the series-connected light-emitting devices 21 is electrically connected to the first power supply voltage signal line VLED, and the second end of the series-connected light-emitting devices 21 It is electrically connected to the driver chip 22 in the same lamp area Q.
  • each driver chip 22 may include four pins: a signal input pin In, an output pin Out, a first power supply pin Vdd, and a second power supply pin Vss.
  • the first power pin Vdd of each driver chip 22 is electrically connected to the second power voltage signal line PWR, and the second power voltage signal line PWR is configured to transmit a second level signal, such as a second voltage signal, to the driver chip 22 .
  • the flat signal can be a high level signal.
  • the second power pin Vss of each driver chip 22 is electrically connected to the third power voltage signal line GND.
  • the third power voltage signal line GND is configured to transmit a first level signal, such as a first level signal, to the driver chip 22 Can be a low level signal.
  • the driver chips 22 in several lamp areas Q can be cascaded.
  • the output pin Out of the upper-level driver chip 22 is electrically connected to the signal input pin In of the lower-level driver chip 22.
  • the cascaded driver The input pin In of the first driver chip 22 in the chip 22 is electrically connected to the addressing signal line Addr, and the addressing signal line Addr is configured to transmit the addressing signal to the driver chip 22; the last driver chip 22 in the cascade
  • An output pin Out of a driver chip 22 is electrically connected to the feedback signal line FB, and the feedback signal line FB is configured to transmit the feedback signal.
  • the laser when laser etching some side traces on the second surface, the laser may be irradiated through the substrate to the trace layer, and the residual energy of the laser may cause some of the connection traces to break, thereby causing the display panel to Some light areas cannot illuminate properly.
  • the wiring layer 12 may include a driving circuit layer, and the driving circuit layer includes functional layers and insulation layers located between adjacent functional layers.
  • the functional layer may include an active layer 121, a gate layer 122, a first source and drain metal layer 123 and a second source and drain metal layer 124, etc., wherein the active layer 121, the gate layer 122 and the first source and drain metal layer Layer 123 is used to form a plurality of pixel driving circuits of the display panel 100 .
  • the light-emitting device layer 20 is disposed on the side of the driving circuit layer away from the substrate 11 , and the light-emitting devices located in the light-emitting device layer 20 are electrically connected to the corresponding pixel driving circuit.
  • the pixel driving circuit may include a plurality of transistors and capacitors.
  • the transistor may be a thin film transistor (TFT), a field effect transistor (such as an oxide thin film transistor), or other switching devices with the same characteristics.
  • TFT thin film transistor
  • field effect transistor such as an oxide thin film transistor
  • thin film transistors are used as examples.
  • the active layer 121 may be polysilicon (P-Si).
  • the active layer 121 includes active layer patterns of each transistor.
  • the gate layer 122 includes a plurality of gate lines that pass through the active layer patterns of the corresponding transistors.
  • the part of the active layer pattern of the transistor that overlaps with the gate line is the channel region sg of the transistor.
  • the part of the gate line that overlaps with the active layer pattern of the transistor may be the gate terminal of the transistor.
  • the first source-drain metal layer 123 is provided with Through a plurality of via holes penetrating the gate layer 122, the active layer patterns of the transistors located on both sides of the channel region sg are electrically connected to the traces and/or connection terminals located in the first source-drain metal layer 123, located at The traces and/or connection terminals that electrically connect the first source-drain metal layer 123 to the active layer patterns of the transistors on both sides of the channel region sg may be the source or drain of the transistor.
  • the active layer pattern of the transistor, the gate line portion overlapping the active layer pattern of the transistor, the wiring and/or connection terminal in the first source-drain metal layer 123 that is electrically connected to the active layer pattern of the transistor can be is a thin film transistor TFT.
  • passing through means that the orthographic projection of the former on the substrate overlaps with the orthographic projection of the latter on the substrate.
  • a gate line passes through the active layer pattern of the corresponding transistor, it means that the orthographic projection of a gate located in the gate layer on the substrate can overlap with the orthographic projection of the active layer patterns of multiple transistors on the substrate.
  • connection end of the first source-drain metal layer can be used as a signal output end of the pixel driving circuit, and the connection end of the first source-drain metal layer can receive a driving signal provided by the pixel driving circuit.
  • the connection end located in the second source-drain metal layer can be electrically connected to the connection end located in the first source-drain metal layer through a via hole penetrating the insulating layer.
  • the connection end located in the second source-drain metal layer can be used as an anode electrode of the light-emitting device. connect.
  • the first source-drain metal layer or the second source-drain metal layer may include a cathode wiring, and the cathode of the light-emitting device is electrically connected to the cathode wiring through a via hole penetrating the first source-drain metal layer or the second source-drain metal layer.
  • the laser when laser etching some side traces on the second surface, the laser may be irradiated through the substrate to the active layer.
  • the polysilicon in the active layer absorbs energy, it may cause serious deterioration in the characteristics of the thin film transistor.
  • Deterioration such as threshold voltage shift or increase in leakage current, etc., causes the pixel drive circuit to be unable to accurately control the voltage or current of the output drive signal, and then the brightness of the light-emitting device is inaccurate, and the image formed by the display panel has color shift, The problem of uneven brightness.
  • the array substrate 10 includes: a base 111, a wiring layer 12, a plurality of second electrodes 50 and a protection layer.
  • Layer 80 the substrate 111, the wiring layer 12 and the plurality of second electrodes 50 are consistent with the substrate 111, the wiring layer and the second electrodes mentioned in the display panel of the above embodiment in terms of structure, function and arrangement position.
  • the protective layer 80 is disposed between the substrate 111 and the wiring layer 12 and/or between the substrate 111 and the plurality of second electrodes 50 , wherein the protective layer 80 is configured to absorb or reflect laser light.
  • the protective layer 80 is disposed between the substrate 111 and the wiring layer 12 .
  • the protective layer 80 is disposed between the substrate 111 and the plurality of second electrodes 50 .
  • the protective layer 80 is disposed between the substrate 111 and the wiring layer 12 , and between the substrate 111 and the plurality of second electrodes 50 .
  • the protective layer 80 can absorb or reflect the laser light, so that the laser light cannot be directly irradiated to the wiring layer 12 . That is to say, the laser cannot cause damage to the connection wiring or the active layer in the wiring layer 12, which improves the product yield of the display panel.
  • the array substrate 10 further includes a buffer layer 112 disposed on a side of the substrate close to the wiring layer 12 , and the protective layer 80 is disposed between the substrate 111 and the buffer layer 112 .
  • the array substrate 10 includes a substrate.
  • the substrate includes a base 111 and a buffer layer 112 disposed on the base 111 .
  • the buffer layer 112 is provided with a wiring layer 12 on a side away from the base 111 .
  • the protective layer 80 is disposed on the side of the substrate 111 close to the wiring layer 12 , the protective layer 80 is located between the substrate 111 and the buffer layer 112 .
  • the orthographic projection of the plurality of connection traces on the substrate 111 is located inside the orthographic projection of the protective layer 80 on the substrate 111.
  • the laser when the laser is etching the metal plating layer located on the second surface, the laser is vertically irradiated onto the metal plating layer.
  • the protective layer 80 In order to prevent part of the laser from penetrating the substrate 111 and causing damage to the wiring layer 12, the protective layer 80 should be In a direction parallel to the second surface, the laser is completely isolated from the wiring layer 12 to prevent the laser from irradiating onto the wiring layer 12 and to prevent the laser from causing damage to the wiring layer 12 .
  • the wiring layer includes multiple connecting traces.
  • the laser When the laser is etching the metal plating layer, the laser may penetrate through the substrate 111 from the gap between the two side traces and irradiate one of the multiple connecting traces.
  • laser energy On the wire, laser energy may cause breakage of connecting traces. Breaks in the connection traces may cause problems such as the failure of some light areas on the display panel to emit light normally.
  • the protective layer 80 completely covers multiple connection traces, which can prevent the laser from irradiating the connection traces, prevent the connection traces from being disconnected due to laser, and improve the product yield.
  • the wiring layer includes the driver circuit layer.
  • the laser When the laser is etching the metal coating, the laser is vertically irradiated to the wiring layer. Part of the active layer may be irradiated by the laser. Under the action of the laser energy, the characteristics of some thin film transistors will be affected. Serious deterioration, such as threshold voltage shift and or increase in leakage current.
  • the protective layer In order to avoid laser damage to the driving circuit layer, the protective layer should completely cover the active layer in a direction parallel to the second surface, so that the laser will not cause changes to the characteristics of part of the active layer, and the image quality of the display panel will be stable. , the product yield is higher.
  • the protective layer 80 includes a reflective layer 81 , which is disposed between the substrate 111 and the wiring layer 12 and/or between the substrate 111 and the plurality of second electrodes 50 between.
  • the protective layer 80 may be a reflective layer 81 , wherein the reflective layer 81 is disposed between the substrate 111 and the wiring layer 12 .
  • part of the laser may pass through the substrate 111 and be irradiated onto the wiring layer 12.
  • the reflective layer 81 is located between the substrate 111 and the wiring layer 12. The reflective layer 81 can Part of the laser light transmitted through the substrate 111 is reflected to prevent part of the laser light transmitted through the substrate 111 from irradiating onto the wiring layer 12 , thereby achieving the purpose of protecting the wiring layer 12 .
  • the protective layer 80 may be a reflective layer 81 , wherein the reflective layer 81 is disposed between the substrate 111 and the plurality of second electrodes 50 .
  • the reflective layer 81 is located between the substrate 111 and the plurality of second electrodes 50.
  • the laser irradiates the reflective layer 81 through the gaps between the side traces 40.
  • the reflective layer 81 can reflect part of the laser light, that is to say, part of the laser light cannot penetrate the substrate 111 and reach the wiring layer, thereby achieving the purpose of protecting the wiring layer 12 .
  • the protective layer 80 may be a reflective layer 81 , wherein the reflective layer 81 is disposed between the substrate 111 and the wiring layer 12 , and between the substrate 111 and the plurality of second electrodes 50 .
  • the reflective layer 81 is located between the substrate 111 and the plurality of second electrodes 50.
  • the laser irradiates the reflective layer 81 through the gaps between the side traces 40.
  • the reflective layer 81 can reflect part of the laser, and the remaining small part of the laser can be irradiated through the substrate 111 to the reflective layer 81 between the substrate 111 and the wiring layer 12, and can further reflect the remaining small part of the laser so that it can be irradiated to the wiring layer.
  • the laser energy on 12 is small, so the wiring layer will not be broken or the characteristics of the active layer will change.
  • the reflective layer 81 includes at least two film layers stacked in a stack, wherein the reflective layer 81 includes two materials with different refractive indexes.
  • the two materials with different refractive indexes include a first material, the first material is titanium dioxide, and a film layer formed of the first material is disposed between the substrate and a film layer formed of the second material.
  • the second material is silicon dioxide.
  • the reflective layer 81 includes at least two film layers, and the at least two film layers are stacked in sequence.
  • the two adjacent film layers are made of materials with different refractive indexes.
  • the at least two film layers can improve the laser light of a specific wavelength. Reflectivity.
  • the reflective layer 81 includes at least two film layers: a first film layer 811 and a second film layer 812.
  • the first film layer 811 is made of a first material. That is to say, the first film layer 811 can be titanium dioxide.
  • the refractive index of the layer 811 is 2.55;
  • the second film layer 812 is made of a second material, that is to say, the second film layer 812 can be silicon dioxide, and the refractive index of the second film layer 812 is 1.45.
  • the reflective layer 81 is disposed between the substrate 111 and the wiring layer 12 .
  • the reflective layer 81 includes a first film layer 811 and the first film layer 811 is located away from the substrate 111 A second film layer 812 on one side.
  • the first film layer 811 is disposed on the side of the substrate 111 close to the wiring layer 12
  • the wiring layer 12 is disposed on the side of the second film layer 812 away from the substrate 111 .
  • Part of the laser light transmitted through the substrate 111 is reflected after being irradiated to the first film layer 811 and the second film layer 812, preventing part of the laser light from directly irradiating the wiring layer 12, which can avoid the breakage of a certain connection trace or the threshold of a certain thin film transistor. Problems such as voltage offset occur and the product yield is improved.
  • the reflective layer 81 may include three film layers: two first film layers 811 and a second film layer 812 located between the two first film layers 811 .
  • the first first film layer 811 is disposed on the side of the substrate 111 close to the wiring layer 12
  • the second first film layer 812 is disposed on the side of the first first film layer 811 away from the substrate 111
  • the second first film layer 811 The wiring layer 12 is disposed on the side of the second film layer 812 away from the base 111
  • the wiring layer 12 is disposed on the side of the second first film layer 811 away from the base 111 .
  • the first film layer 811 can be titanium dioxide
  • the second film layer 812 can be silicon dioxide.
  • Part of the laser light transmitted through the substrate 111 is irradiated to the first first film layer 811, the second film layer 812 and the second second film layer 811.
  • One film layer 811 can be reflected between the interfaces of two adjacent film layers, preventing the laser from directly irradiating the wiring layer, and avoiding problems such as breakage of a certain connecting trace or shift of the threshold voltage of a certain thin film transistor. , improve product yield.
  • the reflective layer 81 is disposed between the substrate 111 and the plurality of second electrodes 50 .
  • the reflective layer 81 includes a first film layer 811 and a second film layer 812 .
  • the first film layer 811 is disposed on the side of the base 111 away from the wiring layer 12
  • the second film layer 812 is disposed on the side of the first film layer 811 away from the base 111
  • a plurality of second electrodes 50 are disposed on the second film layer 812 away from the base 111 side.
  • part of the laser passes through the gap between two adjacent side traces and irradiates the first film layer 811 and the second film layer 812 before being reflected, preventing the laser from directly irradiating the wiring layer 12 , which can avoid problems such as breakage of a certain connection trace or deviation of the threshold voltage of a certain thin film transistor, and improve product yield.
  • the reflective layer 81 may include three film layers: two first film layers 811 and a second film layer 812 located between the two first film layers 811 .
  • the first first film layer 811 is disposed on one side of the base 111
  • the second film layer 812 is disposed on the side of the first film layer 811 away from the base 111
  • the second first film layer 811 is disposed on the side of the second film layer away from the base 111 .
  • a plurality of second electrodes 50 are disposed on the side of the second first film layer 811 away from the substrate 111 .
  • the first film layer 811 may be titanium dioxide.
  • Part of the laser passes through the gap between two adjacent side traces and irradiates the first first film layer 811, the second film layer 812 and the second first film.
  • Layer 811 reflection can occur between the interfaces of two adjacent film layers, preventing the laser from directly irradiating the wiring layer, and avoiding problems such as breakage of a certain connecting trace or shift of the threshold voltage of a certain thin film transistor, improving Product yield.
  • the reflective layer may also include four film layers, five film layers, or more film layers.
  • the first film layer 811 is disposed on a side of the substrate 111 close to the wiring layer 12 , or away from the wiring layer 12 On one side of the film, the first film layer is titanium dioxide, the second film layer is silicon dioxide, the third film layer is titanium dioxide, and so on, and the materials of the two adjacent film layers are titanium dioxide and silicon dioxide respectively.
  • the wavelength of the laser to be reflected by the reflective layer is ⁇ , where the product of the thickness d1 of the film layer formed of the first material and the refractive index of the first material is 1/4 times the wavelength of the light to be reflected. .
  • the first material is titanium dioxide.
  • the refractive index n1 of titanium dioxide is 2.55.
  • the wavelength of the laser to be reflected by the reflective layer is ⁇ .
  • the wavelength ⁇ of the laser used for etching is 355 nm.
  • the film thickness of titanium dioxide is d1, where:
  • the thickness of the film layer using titanium dioxide is 35.3nm, that is to say, the thickness of the odd-numbered film layers such as the first film layer, the third film layer and the fifth film layer is 35.3nm.
  • the product of the thickness d2 of the film layer formed of the second material and the refractive index of the second material is 1/4 times the wavelength of the light to be reflected.
  • the second material is silicon dioxide
  • the refractive index n2 of silicon dioxide is 1.45
  • the wavelength of the laser to be reflected by the reflective layer is ⁇ .
  • the wavelength ⁇ of the laser used for etching is 355 nm.
  • the thickness of the silicon dioxide layer is d2, where:
  • the thickness of the film layer using silicon dioxide is 59.2nm, that is to say, the thickness of the even-numbered film layers such as the second film layer and the fourth film layer is 59.2nm.
  • the first material is titanium dioxide, and the thickness of the film layer formed by the first material is 35.3 nm.
  • the second material is silicon dioxide, and the thickness of the film layer formed by the second material is 59.2 nm.
  • the corresponding film thicknesses of different materials can produce total reflection of laser light with a wavelength ⁇ of 355nm.
  • the above-mentioned film layer thickness has a high reflection efficiency for laser light with a wavelength ⁇ of 355 nm.
  • the protective layer 80 includes an energy absorption layer 82 .
  • the energy absorption layer 82 is disposed between the substrate 111 and the wiring layer 12 and/or between the substrate 111 and a plurality of strips. between the second electrodes 50 .
  • the protective layer 80 includes an energy absorption layer 82 disposed between the substrate 111 and the wiring layer 12 .
  • the energy absorption layer 82 is provided on the side of the substrate 111 close to the wiring layer 12
  • the buffer layer 112 is provided on the side of the energy absorption layer 82 away from the substrate 111
  • the wiring layer 12 is provided on the side of the buffer layer 112 away from the substrate 111 .
  • the protective layer 80 includes an energy absorption layer 82 disposed between the substrate 111 and the plurality of second electrodes 50 .
  • the energy absorption layer 82 is provided on the side of the substrate 111 away from the wiring layer 12
  • a plurality of second electrodes 50 are provided on the side of the energy absorption layer 82 away from the substrate 111 .
  • the protective layer 80 includes an energy absorption layer 82 disposed between the substrate 111 and the wiring layer 12 , and between the substrate 111 and the plurality of second electrodes 50 .
  • the energy absorption layer 82 is provided on the side of the substrate 111 close to the wiring layer 12
  • the buffer layer 112 is provided on the side of the energy absorption layer 82 away from the substrate 111
  • the wiring layer 12 is provided on the side of the buffer layer 112 away from the substrate 111 .
  • an energy absorption layer 82 is provided on the side of the base 111 away from the wiring layer 12
  • a plurality of second electrodes 50 are provided on the side of the energy absorption layer 82 away from the base 111 .
  • the protective layer 80 includes a reflective layer 81 and an energy absorbing layer 82 , which are disposed between the substrate 111 and the wiring layer 12 .
  • the energy absorption layer 82 is provided on the side of the substrate 111 close to the wiring layer 12
  • the reflective layer 81 is provided on the side of the energy absorption layer away from the substrate 111
  • the wiring layer 12 is provided on the reflective layer. 81 away from the base 111 side.
  • a reflective layer 81 is provided on the side of the substrate 111 close to the wiring layer 12
  • the energy absorbing layer 82 is provided on the side of the reflective layer 81 away from the substrate 111
  • the wiring layer 12 is provided on the side away from the energy absorbing layer 82 .
  • the protective layer 80 includes a reflective layer 81 and an energy absorbing layer 82 disposed between the substrate 111 and the plurality of second electrodes 50 .
  • the energy absorption layer 82 is provided on the side of the substrate 111 away from the wiring layer 12
  • the reflective layer 81 is provided on the side of the energy absorption layer 82 away from the substrate 111
  • a plurality of second electrodes 50 Disposed on the side of the reflective layer 81 away from the substrate 111 .
  • FIG. 25 the energy absorption layer 82 is provided on the side of the substrate 111 away from the wiring layer 12
  • the reflective layer 81 is provided on the side of the energy absorption layer 82 away from the substrate 111
  • a plurality of second electrodes 50 Disposed on the side of the reflective layer 81 away from the substrate 111 .
  • a reflective layer 81 is provided on the side of the substrate 111 away from the wiring layer 12 , an energy absorption layer 82 is provided on a side of the reflective layer 81 away from the substrate 111 , and a plurality of second electrodes 50 are provided on the energy absorption layer.
  • Layer 82 is on the side away from the substrate 111 .
  • the protective layer 80 includes a reflective layer 81 and an energy absorbing layer 82 .
  • the energy absorbing layer 82 is disposed between the substrate 111 and the wiring layer 12 .
  • the reflective layer 81 is disposed between the substrate 111 and the wiring layer 12 . between the second electrodes 50 .
  • the energy absorption layer 82 is provided on the side of the substrate 111 close to the wiring layer 12
  • the wiring layer 12 is provided on the side of the energy absorption layer 82 away from the substrate 111 ;
  • the substrate 111 is provided with a reflective layer on the side away from the wiring layer 12 81.
  • a plurality of second electrodes 50 are disposed on the side of the reflective layer 81 away from the substrate 111.
  • the protective layer 80 includes a reflective layer 81 and an energy absorbing layer 82 .
  • the energy absorbing layer 82 is disposed between the substrate 111 and the plurality of second electrodes 50 .
  • the reflective layer 81 is disposed on the substrate 111 and wiring layer 12.
  • a reflective layer 81 is provided on the side of the substrate 111 away from the wiring layer 12
  • a plurality of second electrodes 50 are provided on the side of the energy absorption layer 82 away from the substrate 111
  • a reflective layer 81 is provided on the side of the substrate 111 close to the wiring layer 12
  • the wiring layer 12 is disposed on the side of the reflective layer 81 away from the substrate 111 .
  • the reflective layer 81 in the above-mentioned first example, second example, third example, fourth example, fifth example, sixth example and seventh film layer may include two film layers or three film layers. Or five film layers or more. The specific arrangement of the film layers will not be described in detail here.
  • the material of the energy absorbing layer has a bandgap width less than 3.5 eV.
  • the wavelength ⁇ of the laser to be absorbed is 355 nm
  • the photon energy of the laser with the wavelength ⁇ of 355 nm is 3.5 eV.
  • the material of the energy absorption layer has a forbidden band width less than 3.5 eV.
  • the material of energy absorbing layer 82 is titanium dioxide.
  • the bandgap Eg of titanium dioxide is 3.2eV
  • the photon energy of a laser with a wavelength ⁇ of 355nm is 3.5eV, which is greater than the bandgap Eg of titanium dioxide.
  • Titanium dioxide can absorb laser energy with a wavelength ⁇ of 355nm, thereby blocking laser energy transfer. to the wiring layer to avoid the negative impact of the laser on the connection wiring or active layer.
  • the energy absorption layer 82 can absorb the energy of a laser with a wavelength ⁇ of 355 nm. That is to say, when a laser with a wavelength ⁇ of 355 nm passes through the energy absorption layer 82 , it can absorb the energy of the laser. , reduce the laser intensity. After the laser is irradiated to the wiring layer, the low-intensity laser may not cause damage to the connecting traces or active layers in the wiring layer 12 . Of course, combined with the reflective layer 81 , the laser can be further reflected and irradiated to the wiring layer 12 The laser intensity is negligible.
  • the display panel 100 includes: a plurality of light-emitting devices and the array substrate 10 as described in any of the above embodiments.
  • the array substrate 10 includes a substrate 111 and a wiring layer provided on the substrate 111 . Among them, a plurality of light-emitting device arrays are arranged on the wiring layer 12 one layer away from the substrate 111, and the wiring layer 12 is electrically connected to the plurality of light-emitting devices.
  • the display panel includes a protective layer 80 , and the protective layer 80 may include a reflective layer 81 and/or an energy absorbing layer 82 . Therefore, the display panel has the same beneficial effects as the above-mentioned array substrate, which will not be described again here.
  • some embodiments of the present disclosure provide a display device.
  • the display device includes a drive circuit board and a display panel as described in the above embodiments.
  • the display panel includes a substrate and a wiring layer provided on the substrate.
  • a plurality of second electrodes are provided on a side of the substrate away from the wiring layer.
  • the driving circuit board is disposed on a side of the substrate away from the wiring layer, and the driving circuit board can be electrically connected to the plurality of second electrodes through the flexible circuit board.
  • the display device adopts the display panel provided in the above embodiment and has the same beneficial effects as the display panel, which will not be described again here.
  • the spliced display device 2000 includes: a plurality of display devices 1000 as described in the above embodiments, the plurality of display devices 1000 are spliced and assembled,
  • the splicing display device 2000 provided in this embodiment adopts the display device 1000 provided in the above embodiment, and has the same beneficial effects as the display device 1000, which will not be described again here.

Abstract

一种阵列基板（10）、显示面板（100）、显示装置（1000）和拼接显示装置（2000）。阵列基板（10）包括：基底（111）、走线层（12）、多个第二电极（50）和保护层（80）。其中，走线层（12）设置于基底（111）上；多个第二电极（50），设置于基底（111）远离走线层（12）一侧，走线层（12）与多个第二电极（50）电连接；保护层（80），设置于基底（111）与走线层（12）之间和/或基底（111）与多个第二电极（50）之间。

Description

一种阵列基板、显示面板、显示装置和拼接显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板、显示装置和拼接显示装置。
背景技术
微型发光二极管(Micro Light Emitting Diode，简称Micro LED)被称为第三代显示技术。Micro LED显示装置在巨量转移与坏点修复等技术压力下，无法实现超大尺寸产品的制作。因此对于此类超大显示屏的产品，目前最佳方案是小尺寸显示屏拼接。
公开内容
一方面，本公开的一些实施例提供一种阵列基板。所述阵列基板包括：基底、走线层、多个第二电极和保护层。其中，走线层设置于基底上；多个第二电极，设置于基底远离走线层一侧，走线层与多个第二电极电连接；保护层，设置于基底与走线层之间和/或基底与多个第二电极之间。
在一些实施例中，保护层包括反射层，反射层设置于基底与走线层之间和/或基底与多个第二电极之间。
在一些实施例中，反射层包括层叠设置的至少两个膜层，其中，反射层包括两种折射率不同的材质，相邻两个膜层的材质不同。
在一些实施例中，两种折射率不同的材质包括第一材质，反射层待反射的激光的波长确定，第一材质形成膜层的厚度与第一材质的折射率的乘积，是待反射的光的波长的1/4倍。
在一些实施例中，两种折射率不同的材质包括第二材质，反射层待反射的激光的波长确定，第二材质形成膜层的厚度与第二材质的折射率的乘积，是待反射的光的波长的1/4倍。
在一些实施例中，两种折射率不同的材质包括第一材质，第一材质为二氧化钛，第一材质形成的膜层设置于基底上。
在一些实施例中，第二材质为二氧化硅。
在一些实施例中，保护层包括能量吸收层，能量吸收层设置于基底与走线层之间和/或基底与多个第二电极电之间。
在一些实施例中，能量吸收层的禁带宽度小于3.5eV。
在一些实施例中，能量吸收层的材料为二氧化钛。
在一些实施例中，走线层包括多条连接走线，多条连接走线与多个第二电极电连接，多条连接走线在基底上的正投影位于保护层在基底上的正投影内 部。
在一些实施例中，走线层包括驱动电路层，驱动电路层包括：有源层和栅极层，其中，有源层设置于基底或保护层上，栅极层设置于有源层远离基底的一侧。有源层在基底上的正投影位于保护层在基底上的正投影内部。
另一方面，本公开的一些实施例提供一种显示面板。所述显示面板包括：如上述任一项实施例所述的阵列基板和多个发光器件。其中，阵列基板包括基底和设置于基底上的驱动电路层，多个发光器件整列布置于驱动电路层远离基底一层。
又一方面，本公开的一些实施例提供一种显示装置。所述显示装置包括：如上述实施例的所述显示面板和驱动电路板。其中，显示面板包括基底和走线层，基底上设置有走线层，驱动电路板设置于基底远离走线层一侧，驱动电路板通过柔性线路板和走线层电连接。
再一方面，本公开的一些实施例提供一种拼接显示装置，所述拼接显示装置包括：多个如上述实施例所述的显示装置，多个显示装置拼接组装。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开的一些实施例提供的一种显示装置的结构图；
图2为本公开的一些实施例提供的一种显示装置的正面结构图；
图3为本公开的一些实施例提供的一种显示装置的反面结构图；
图4为本公开的一些实施例提供的一种显示面板的结构图；
图5为本公开的一些实施例提供的一种显示面板的正面结构图；
图6为本公开的一些实施例提供的一种显示面板的一个灯区和驱动芯片的结构图；
图7为本公开的一些实施例提供的另一种显示面板的结构图；
图8为本公开的一些实施例提供的第一种具有保护层的显示面板的结构图；
图9为本公开的一些实施例提供的第二种具有保护层的显示面板的结构图；
图10为本公开的一些实施例提供的第三种具有保护层的显示面板的结构 图；
图11为本公开的一些实施例提供的第四种具有保护层的显示面板的结构图；
图12为本公开的一些实施例提供的第一种具有反射层的显示面板的结构图；
图13为本公开的一些实施例提供的第二种具有反射层的显示面板的结构图；
图14为本公开的一些实施例提供的第三种具有反射层的显示面板的结构图；
图15为本公开的一些实施例提供的一种反射层的结构图；
图16为本公开的一些实施例提供的第四种具有反射层的显示面板的结构图；
图17为本公开的一些实施例提供的第五种具有反射层的显示面板的结构图；
图18为本公开的一些实施例提供的第六种具有反射层的显示面板的结构图；
图19为本公开的一些实施例提供的第七种具有反射层的显示面板的结构图；
图20为本公开的一些实施例提供的第一种具有能量吸收层的显示面板的结构图；
图21为本公开的一些实施例提供的第二种具有能量吸收层的显示面板的结构图；
图22为本公开的一些实施例提供的第三种具有能量吸收层的显示面板的结构图；
图23为本公开的一些实施例提供的第一种具有能量吸收层和吸收层的显示面板的结构图；
图24为本公开的一些实施例提供的第二种具有能量吸收层和吸收层的显示面板的结构图；
图25为本公开的一些实施例提供的第三种具有能量吸收层和吸收层的显示面板的结构图；
图26为本公开的一些实施例提供的第四种具有能量吸收层和吸收层的显示面板的结构图；
图27为本公开的一些实施例提供的第五种具有能量吸收层和吸收层的显 示面板的结构图；
图28为本公开的一些实施例提供的第六种具有能量吸收层和吸收层的显示面板的结构图；
图29为本公开的一些实施例提供的可拼接显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供一种显示装置，如图1所示，显示装置1000包括显示面板100和驱动电路板200。其中，驱动电路板200可以设置于显示面板100的非显示面O一侧，驱动电路板200被配置为驱动显示面板100显示的驱动集成电路(IC，Integrated Circuit)，驱动电路板200例如包括栅极驱动电路、源极驱动电路、时序控制器以及电源电路等，驱动电路板200与显示面板100电连接，被配置为输出相应的信号，以控制显示面板100进行显示。
在一些实施例中，如图2所示，显示面板100包括显示区AA和至少设置于显示区AA一侧的周边区BB，例如：周边区BB可以位于显示区AA的一侧、两侧或三侧，或者，周边区BB可以围绕显示区AA设置。在显示区AA中设置有阵列排列的多个像素P和多条信号线60，多条信号线60与多个像素P电连接。每个像素P包括多个子像素SP，子像素SP是显示面板100进行画面显示的最小单元，每个子像素SP可显示一种单一的颜色，例如红色(R)、 绿色(G)或蓝色(B)，调节不同颜色子像素SP的亮度(灰阶)，通过颜色组合和叠加可以实现多种颜色的显示，从而实现显示面板100的全彩化显示。每个子像素SP包括至少一个发光器件，该发光器件可以为无机发光二极管，示例性地，发光器件为次毫米发光二极管(Mini Light Emitting Diode，Mini LED)和/或微型发光二极管(Micro Light Emitting Diode，Micro LED)。其中，次毫米发光二极管的尺寸大于或等于100μm，且小于500μm，微型发光二极管的尺寸小于100μm。
在一些示例中，每个像素P接收对应的信号线60传输的电信号而发光，在不同电信号的控制下，像素P生成不同的亮度(灰阶)，如此所有像素P在显示面板100上生成画面。
显示面板100在显示过程中，多个像素P被逐行扫描，被对应的信号线60提供的一组数据信号，从而在数据信号的控制下，显示一幅画面，在多个像素P被再次逐行扫描，各像素P接收与其电连接的信号线60提供的新一组数据信号时，显示新的一幅画面，从而显示画面刷新，连续多个显示画面逐次刷新形成显示影像。
在一些实施例中，发光器件采用次毫米发光二极管和/或微型发光二极管，在现有的工艺能力和成本因素等压力下，无法直接制作大尺寸显示面板，目前的方案是采用多个小尺寸显示面板拼接的方式来实现大尺寸。如图1所示，显示装置1000的驱动电路板200绑定至显示面板的非显示面O一侧，可以降低周边区的宽度，利于显示面板100拼接为大尺寸的显示装置。
在一些实施例中，如图1、图2和图3所示，其中，图1为图2中A-A方向的剖视图，图2为显示装置1000的显示面一侧的结构图，图3为显示装置1000的非显示面O一侧的结构图。显示面板100包括阵列基板10、发光器件层20、多个第一电极30、多条侧面走线40和多个第二电极50。其中，阵列基板10包括第一表面10a、与第一表面10a相对的第二表面10b以及连接第一表面10a和第二表面10b的多个侧面10c，其中，阵列基板10的第二表面10b也是显示装置的非显示面O一侧。
以多个侧面10c中的一个侧面为选定侧面，阵列基板10的第一表面10a上设置有发光器件层20和多个第一电极30，其中，多个第一电极30靠近选定侧面。多条侧面走线40包括设置于第一表面10a的部分走线，设置于选定侧面的部分走线和设置于第二表面10b的部分走线。阵列基板10的第二表面10b上设置有驱动电路板200和多个第二电极50，其中，多个第二电极50靠近选定侧面。多个第一电极30与发光器件层20和对应的侧面走线40电连 接；多个第二电极50与驱动电路板200/柔性线路板70(Flexible Printed Circuit，FPC)和对应的侧面走线40电连接，其中，柔性线路板70可以将第二电极50和驱动电路板200电连接。如此，驱动电路板200依次与第二电极50、侧面走线40和第一电极30电连接，将电信号传输至发光器件层20。
在一些实施例中，位于阵列基板10的第一表面10a的第一电极30和位于阵列基板10的第二表面10b的第二电极50采用通过电镀、蒸镀、移印银胶或者湿法刻蚀等工艺制备得到。侧面走线40可以在阵列基板10的第一表面10a、选定侧表面和第二表面10b制备金属镀层，利用激光对金属镀层进行刻蚀以图案化，得到多条侧面走线。
在一些实施例中，如图4和图7所示，阵列基板10包括衬底11和设置于衬底11上的走线层12。其中，衬底11可以包括基底111和缓冲层(Buffer)112。其中，基底111可以为硅衬底，在基底111上设置缓冲层112，在缓冲层112远离基底111一侧设置走线层12。
在一些实施例中，结合图4和图5所示，走线层12可以包括多条连接走线，发光器件层20可以包括阵列布置的多个发光器件21和多个驱动芯片22。阵列基板包括阵列布置的多个灯区Q，每个灯区Q内设置有若干串联和/或并联的发光器件21和至少一个驱动芯片22，其中，位于同一灯区Q内的若干串联和/或并联的发光器件21与驱动芯片22电连接。
在一些示例中，多条连接走线包括第一电源电压信号线VLED、第二电源电压信号线PWR、第三电源电压信号线GND、寻址信号线Addr和反馈信号线FB。一个灯区Q内可以包括若干个发光器件21，例如发光器件的数量可以为四个、六个或八个。示例性地，一个灯区Q内包括四个依次串联的发光器件21，其中，串联的发光器件21的第一端与第一电源电压信号线VLED电连接，串联的发光器件21的第二端与同一灯区Q内的驱动芯片22电连接。
在一些示例中，如图6所示，每个驱动芯片22可以包括四个引脚：信号输入引脚In、输出引脚Out、第一电源引脚Vdd和第二电源引脚Vss。其中，每个驱动芯片22的第一电源引脚Vdd与第二电源电压信号线PWR电连接，第二电源电压信号线PWR被配置为向驱动芯片22传输第二电平信号，例如第二电平信号可以为高电平信号。每个驱动芯片22的第二电源引脚Vss与第三电源电压信号线GND电连接，第三电源电压信号线GND被配置为向驱动芯片22传输第一电平信号，例如第一电平信号可以为低电平信号。
若干个灯区Q内的驱动芯片22可以级联，在级联的驱动芯片22中，上级驱动芯片22的输出引脚Out与下级驱动芯片22的信号输入引脚In电连 接，级联的驱动芯片22中的第一个驱动芯片22的输入引脚In与寻址信号线Addr电连接，寻址信号线Addr被配置为向驱动芯片22传输寻址信号；级联的驱动芯片22中的最后一个驱动芯片22的输出引脚Out与反馈信号线FB电连接，反馈信号线FB被配置为传输反馈信号。
在一些实施例中，激光刻蚀第二表面上的部分侧面走线时，可能存在激光透过基底照射至走线层，激光残余能量可能造成部分连接走线断裂的情况，进而造成显示面板上的部分灯区不能正常发光。
在另一些实施例中，如图7所示，走线层12可以包括驱动电路层，驱动电路层包括功能层以及位于相邻功能层之间的绝缘层。其中，功能层可以包括有源层121、栅极层122、第一源漏金属层123和第二源漏金属层124等，其中，有源层121、栅极层122和第一源漏金属层123用于形成显示面板100的多个像素驱动电路。发光器件层20则设置于驱动电路层远离衬底11的一侧，位于发光器件层20的发光器件与对应的像素驱动电路电连接。
像素驱动电路可以包括多个晶体管和电容器。示例性地，晶体管可以为薄膜晶体管(Thin Film Transistor，TFT)、场效应晶体管(例如氧化物薄膜晶体管)或其他特性相同的开关器件，本公开所述的实施例中均以薄膜晶体管为例。
有源层121可以采用多晶硅(P-Si)，有源层121包括各晶体管的有源层图案，栅极层122包括多条栅线，栅线经过对应的晶体管的有源层图案。与栅线重叠的晶体管的有源层图案的部分为晶体管的沟道区sg，与晶体管的有源层图案重叠的栅线部分可以为晶体管的栅极端，第一源漏金属层123上设置有多个贯穿栅极层122的过孔，位于沟道区sg两侧的晶体管的有源层图案通过过孔，与位于第一源漏金属层123的走线和/或连接端电连接，位于第一源漏金属层123与沟道区sg两侧的晶体管的有源层图案电连接的走线和/或连接端可以为晶体管的源极或漏极。也就是说，晶体管的有源层图案、与晶体管的有源层图案重叠的栅线部分、第一源漏金属层123中与晶体管的有源层图案电连接的走线和/或连接端可以为一个薄膜晶体管TFT。
需要说明的是，本公开所述的“经过”是指，前者在衬底上的正投影与后者在衬底上的正投影有重叠。例如栅线经过对应的晶体管的有源层图案，是指位于栅极层中的一条栅极在衬底上正投影，可以与多个晶体管的有源层图案在衬底上的正投影有重叠。
在一些示例中，位于第一源漏金属层的连接端可以作为像素驱动电路的信号输出端，所述第一源漏金属层的连接端可以接收像素驱动电路提供的驱动信号。位于第二源漏金属层的连接端可以通过贯穿绝缘层的过孔，与位于第 一源漏金属层的连接端电连接，位于第二源漏金属层的连接端可作为发光器件的阳极电连接。第一源漏金属层或第二源漏金属层可以包括阴极走线，发光器件的阴极通过贯穿至第一源漏金属层或第二源漏金属层的过孔，与阴极走线电连接。
在一些实施例中，激光刻蚀第二表面上的部分侧面走线时，可能存在激光透过衬底照射至有源层，有源层的多晶硅吸收能量后，可能引起薄膜晶体管的特性的严重恶化，如阈值电压的偏移和或漏电流增加等，造成像素驱动电路不能准确控制输出的驱动信号的电压或电流的大小，进而发光器件的亮度不准确，显示面板形成的图像存在色偏、亮度不均等问题。
基于此，一方面，本公开的一些实施例提供一种阵列基板，如图8和图9所示，所述阵列基板10包括：基底111、走线层12、多条第二电极50和保护层80。其中，基底111、走线层12和多条第二电极50，与上述实施例的显示面板提及的基底111、走线层和第二电极在结构、功能和布置位置上一致，在此不再赘述。保护层80设置于基底111与走线层12之间和/或基底111与多条第二电极50之间，其中，保护层80被配置为吸收或反射激光。
在一些示例中，如图8所示，保护层80设置于基底111与走线层12之间。
在另一些示例中，如图9所示，保护层80设置于基底111与多条第二电极50之间。
在又一些示例中，如图10所示，保护层80设置于基底111与走线层12之间，以及基底111与多条第二电极50之间。
在对多条第二电极50采用激光刻蚀工艺加工时，部分激光穿过基底111照射至保护层80上，保护层80可以吸收或者反射激光，使得激光无法直接照射至走线层12，也就是说，激光无法对走线层12中的连接走线或者有源层造成损害，提高了显示面板的产品良率。
在一些实施例中，阵列基板10还包括缓冲层112，缓冲层112设置于所述基底靠近走线层12一侧，且所述保护层80设置于基底111和缓冲层112之间。
在一些示例中，阵列基板10包括衬底，衬底包括基底111和设置于基底111上的缓冲层112，缓冲层112远离基底111一侧设置有走线层12。保护层80设置于基底111靠近走线层12一侧时，保护层80位于基底111和缓冲层112之间。
在一些实施例中，多条连接走线在基底111上的正投影位于保护层80在 基底111上的正投影内部。
在一些示例中，激光对位于第二表面上的金属镀层进行刻蚀加工时，激光垂直照射至金属镀层上，为避免部分激光透过基底111对走线层12造成损害，因此保护层80应在平行于第二表面的方向上，将激光与走线层12完全隔离，实现激光不会照射至走线层12上，避免激光对走线层12造成损害。
示例性地，走线层包括多条连接走线，激光对金属镀层进行刻蚀加工时，激光可能从两条侧面走线的间隙中透过基底111，照射至多条连接走线中一条连接走线上，激光能量可能造成连接走线的断裂。连接走线的断裂可能会导致显示面板上部分灯区无法正常发光等问题。
保护层80完全覆盖多条连接走线，可避免激光对连接走线的照射，避免因激光造成连接走线断路的情况发生，提高产品良率。
示例性地，走线层包括驱动电路层，激光对金属镀层进行刻蚀加工时，激光垂直照射至走线层，部分有源层可能受到激光照射，在激光能量作用下，部分薄膜晶体管的特性的严重恶化，如阈值电压的偏移和或漏电流增加等。为避免激光对驱动电路层造成损害，因此保护层应在平行于第二表面的方向上将有源层完全覆盖，使激光不会对部分有源层的特性引起变化，显示面板的图像质量稳定，产品良率较高。
在一些实施例中，如图12至图14所示，保护层80包括反射层81，反射层81设置于基底111与走线层12之间和/或基底111与多条第二电极50之间。
在一些示例中，如图12所示，保护层80可以为反射层81，其中，反射层81设置于基底111与走线层12之间。
在对多条侧面走线40采用激光刻蚀工艺加工时，部分激光可能穿过基底111照射至走线层12上，反射层81位于基底111和走线层12之间，反射层81可以将透射过基底111的部分激光反射，避免透射过基底111的部分激光照射至走线层12上，实现保护走线层12的目的。
在另一些示例中，如图13所示，保护层80可以为反射层81，其中，反射层81设置于基底111与多条第二电极50之间。
反射层81位于基底111和多条第二电极50之间，在对多条侧面走线40采用激光刻蚀工艺加工时，激光透过侧面走线40之间的间隙照射至反射层81上。反射层81可以将部分激光反射，也就是说，部分激光无法透过基底111照射至走线层上，实现保护走线层12的目的。
在又一些示例中，如图14所示，保护层80可以为反射层81，其中，反 射层81设置于基底111与走线层12之间，以及基底111与多条第二电极50之间。
反射层81位于基底111和多条第二电极50之间，在对多条侧面走线40采用激光刻蚀工艺加工时，激光透过侧面走线40之间的间隙照射至反射层81上。反射层81可以将部分激光反射，剩余小部分激光透过基底111照射至位于基底111与走线层12之间的反射层81上，可对剩余小部分激光进一步反射，使照射至走线层12上的激光能量较小，走线层不会因此发生走线断裂或有源层特性变化的情况。
在一些实施例中，如图15所示，反射层81包括层叠设置的至少两个膜层，其中，反射层81包括两种折射率不同的材质。
在一些实施例中，两种折射率不同的材质包括第一材质，第一材质为二氧化钛，第一材质形成的膜层设置于衬底和第二材质形成的膜层之间。
在一些实施例中第二材质为二氧化硅。
在一些示例中，反射层81包括至少两个膜层，且至少两个膜层依次层叠设置，相邻两个膜层是折射率不同的材质，至少两个膜层可以提高对特定波长的激光反射率。
反射层81包括至少两个膜层：第一膜层811和第二膜层812，其中，第一膜层811采用第一材质，也就是说，第一膜层811可以为二氧化钛，第一膜层811的折射率为2.55；第二膜层812采用第二材质，也就是说，第二膜层812可以为二氧化硅，第二膜层812的折射率为1.45。
在一些示例中，反射层81设置于基底111与走线层12之间，示例性地，如图16所示，反射层81包括一个第一膜层811和位于第一膜层811远离基底111一侧的一个第二膜层812。其中，第一膜层811设置于基底111的靠近走线层12一侧，走线层12设置于第二膜层812远离基底111一侧。透过基底111的部分激光照射至第一膜层811和第二膜层812后发生反射，避免部分激光直接照射至走线层12，可避免某条连接走线断裂或者某个薄膜晶体管的阈值电压偏移等问题发生，提高产品良率。
或者，如图17所示，反射层81可以包括三个膜层：两个第一膜层811和位于两个第一膜层811之间的一个第二膜层812。第一个第一膜层811设置于基底111的靠近走线层12一侧，第二膜层812设置于第一个第一膜层811远离基底111一侧，第二个第一膜层811设置于第二膜层812远离基底111一侧，走线层12设置于第二个第一膜层811远离基底111一侧。其中，第一膜层811可以为二氧化钛，第二膜层812可以为二氧化硅，透过基底111的部 分激光照射至第一个第一膜层811、第二膜层812和第二个第一膜层811，在相邻两个膜层界面之间均可发生反射，避免激光直接照射至走线层，可避免某条连接走线断裂或者某个薄膜晶体管的阈值电压偏移等问题发生，提高产品良率。
在另一些示例中，反射层81设置于基底111与多条第二电极50之间，示例性地，如图18所示，反射层81包括第一膜层811和第二膜层812。其中，第一膜层811设置于基底111远离走线层12一侧，第二膜层812设置于第一膜层811远离基底111一侧，多条第二电极50设置于第二膜层812远离基底111一侧。部分激光在刻蚀侧面走线时，透过相邻两个侧面走线之间的间隙，照射至第一膜层811和第二膜层812后发生反射，避免激光直接照射至走线层12，可避免某条连接走线断裂或者某个薄膜晶体管的阈值电压偏移等问题发生，提高产品良率。
或者，图19所示，反射层81可以包括三个膜层：两个第一膜层811和位于两个第一膜层811之间的一个第二膜层812。第一个第一膜层811设置于基底111的一侧，第二膜层812设置于第一膜层811远离基底111一侧，第二个第一膜层811设置于第二膜层远离基底111一侧，多条第二电极50设置于第二个第一膜层811远离基底111一侧。其中，第一膜层811可以为二氧化钛，部分激光透过相邻两个侧面走线之间的间隙，照射至第一个第一膜层811、第二膜层812和第二个第一膜层811，在相邻两个膜层界面之间均可发生反射，避免激光直接照射至走线层，可避免某条连接走线断裂或者某个薄膜晶体管的阈值电压偏移等问题发生，提高产品良率。
可以理解的是，反射层还可以包括四个膜层、五个膜层或者更多膜层，第一膜层811设置于基底111靠近走线层12的一侧面上，或者远离走线层12的一侧面上，第一膜层为二氧化钛，第二膜层为二氧化硅，第三膜层为二氧化钛，依次类推，相邻两个膜层的材质分别为二氧化钛和二氧化硅。
在一些实施例中，反射层待反射的激光的波长为λ，其中，第一材质形成膜层的厚度d1与第一材质的折射率的乘积，是待反射的光的波长的1/4倍。
在一些示例中，第一材质为二氧化钛，二氧化钛的折射率n1为2.55，反射层待反射的激光的波长为λ，在本公开中，用于刻蚀的激光波长λ为355nm，为了实现对波长为λ的激光的全反射，采用二氧化钛的膜层厚度为d1，其中：
Figure PCTCN2022109236-appb-000001
可以知道的是，采用二氧化钛的膜层厚度为35.3nm，也就是说，第一膜 层、第三膜层以及第五膜层等奇数膜层的厚度为35.3nm。
在一些实施例中，第二材质形成膜层的厚度d2与第二材质的折射率的乘积，是待反射的光的波长的1/4倍。
在一些示例中，第二材质为二氧化硅，二氧化硅的折射率n2为1.45，反射层待反射的激光的波长为λ，在本公开中，用于刻蚀的激光波长λ为355nm，为了实现对波长为λ的激光的全反射，采用二氧化硅的膜层厚度为d2，其中：
Figure PCTCN2022109236-appb-000002
可以知道的是，采用二氧化硅的膜层厚度为59.2nm，也就是说，第二膜层和第四膜层等偶数膜层的厚度为59.2nm。
第一材质为二氧化钛，第一材质形成的膜层的厚度为35.3nm，第二材质为二氧化硅，第二材质形成的膜层的厚度为59.2nm。不同材质的对应的膜层厚度可以波长λ为355nm的激光发生全反射。也就是说，上述膜层厚度，对波长λ为355nm的激光的反射效率较高。
在一些实施例中，如图20、图21和图22所示，保护层80包括能量吸收层82，能量吸收层82设置于基底111与走线层12之间和/或基底111与多条第二电极50之间。
在第一示例中，如图20所示，保护层80包括能量吸收层82，能量吸收层82设置于基底111与走线层12之间。示例性地，基底111靠近走线层12一侧面上设置有能量吸收层82，缓冲层112设置于能量吸收层82远离基底111一侧，走线层12设置于缓冲层112远离基底111一侧。
在第二示例中，如图21所示，保护层80包括能量吸收层82，能量吸收层82设置于基底111与多条第二电极50之间。示例性地，基底111远离走线层12一侧面上设置有能量吸收层82，多条第二电极50设置于能量吸收层82远离基底111一侧。
在第三示例中，如图22所示，保护层80包括能量吸收层82，能量吸收层82设置于基底111与走线层12之间，以及基底111与多条第二电极50之间。示例性地，基底111靠近走线层12一侧面上设置有能量吸收层82，缓冲层112设置于能量吸收层82远离基底111一侧，走线层12设置于缓冲层112远离基底111一侧。且，基底111远离走线层12一侧面上设置有能量吸收层82，多条第二电极50设置于能量吸收层82远离基底111一侧。
在第四示例中，如图23和图24所示，保护层80包括反射层81和能量吸收层82，反射层和能量吸收层设置于基底111与走线层12之间。示例性 地，如图23所示，基底111的靠近走线层12一侧面上设置有能量吸收层82，反射层81设置于能量吸收层远离基底111一侧，走线层12设置于反射层81远离基底111一侧。或者，如图24所示，基底111靠近走线层12一侧面上设置有反射层81，能量吸收层82设置于反射层81远离基底111一侧，走线层12设置于能量吸收层82远离基底111一侧。
在第五示例中，如图25和图26所示，保护层80包括反射层81和能量吸收层82，反射层81和能量吸收层82设置于基底111与多条第二电极50之间。示例性地，如图25所示，基底111远离走线层12的一侧面上设置有能量吸收层82，反射层81设置于能量吸收层82远离基底111的一侧，多条第二电极50设置于反射层81远离基底111的一侧。或者，如图26所示，基底111远离走线层12一侧上设置有反射层81，能量吸收层82设置于反射层81远离基底111的一侧，多条第二电极50设置于能量吸收层82远离基底111一侧。
在第六示例中，如图27所示，保护层80包括反射层81和能量吸收层82，能量吸收层82设置于基底111与走线层12之间，反射层81设置于基底111与多条第二电极50之间。示例性地，基底111靠近走线层12一侧上设置有能量吸收层82，走线层12设置于能量吸收层82远离基底111一侧；基底111远离走线层12一侧设置有反射层81，多条第二电极50设置于反射层81远离基底111一侧。
在第七示例中，如图28所示，保护层80包括反射层81和能量吸收层82，能量吸收层82设置于基底111与多条第二电极50之间，反射层81设置于基底111与走线层12之间。示例性地，基底111远离走线层12一侧设置有反射层81，多条第二电极50设置于能量吸收层82远离基底111一侧；基底111靠近走线层12一侧上设置有反射层81，走线层12设置于反射层81远离基底111一侧。
可以理解的是，上述第一示例、第二示例、第三示例、第四示例、第五示例、第六示例和第七膜层中的反射层81可以包括两个膜层、三个膜层或者五个膜层等更多膜层，具体膜层的排列在此不做赘述。
在一些实施例中，能量吸收层的材料的禁带宽度小于3.5eV。示例性地，待吸收的激光的波长λ为355nm，波长λ为355nm的激光的光子能量为3.5eV。为了能够吸收波长λ为355nm的激光的能量，能量吸收层的材料的禁带宽度小于3.5eV。
在一些实施例中，能量吸收层82的材料为二氧化钛。示例性地，二氧化 钛的禁带宽度Eg为3.2eV，波长λ为355nm的激光的光子能量为3.5eV大于二氧化钛的禁带宽度Eg，二氧化钛能够吸收波长λ为355nm激光能量，从而能够阻挡激光能量传递到走线层，避免激光对连接走线或有源层造成负面影响。
示例性地，如图20至图28所示，能量吸收层82可以吸收波长λ为355nm的激光的能量，也就是说，波长λ为355nm的激光经过能量吸收层82时，可以吸收激光的能量，降低激光强度。在激光照射至走线层后，低强度的激光可能无法对走线层12中的连接走线或有源层造成损害，当然，结合反射层81可以进一步将激光反射，照射至走线层12的激光强度可忽略不计。
另一方面，如图8至图28所示，本公开的一些实施例提供一种显示面板100。其中，所述显示面板100包括：多个发光器件和如上述任一项实施例所述的阵列基板10，阵列基板10包括基底111和设置于基底111上的走线层。其中，多个发光器件阵列布置于走线层12远离基底111一层，走线层12与多个发光器件电连接。
在一些示例中，显示面板包括保护层80，且保护层80可以包括反射层81和/或能量吸收层82。因此，该显示面板具有和上述阵列基板相同的有益效果，在此不做赘述。
又一方面，本公开的一些实施例提供一种显示装置。其中，显示装置包括驱动电路板和如上述实施例所述的显示面板，显示面板包括基底和设置于基底上的走线层，基底远离走线层一侧设置有多个第二电极。其中，驱动电路板设置于基底远离走线层一侧，驱动电路板可以通过柔性线路板和多个第二电极电连接。
显示装置采用上述实施例提供的显示面板，具有和显示面板相同的有益效果，在此不做赘述。
再一方面，如图29所示，本公开的一些实施例提供一种拼接显示装置2000。所述一种拼接显示装置2000包括：多个如上述实施例所述的显示装置1000，多个显示装置1000拼接组装，
本实施例提供的拼接显示装置2000采用上述实施例提供的显示装置1000，具有和显示装置1000相同的有益效果，在此不做赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，包括：
    基底，
    走线层，设置于所述基底上；
    多个第二电极，设置于所述基底远离所述走线层一侧，所述走线层与所述多个第二电极电连接；
    保护层，设置于所述基底与所述走线层之间和/或所述基底与所述多个第二电极之间。
  2. 根据权利要求1所述的阵列基板，其中，所述保护层包括反射层，所述反射层设置于所述基底与所述走线层之间和/或所述基底与所述多个第二电极之间。
  3. 根据权利要求2所述的阵列基板，其中，所述反射层包括层叠设置的至少两个膜层；
    其中，所述反射层包括两种折射率不同的材质，相邻两个膜层的材质不同。
  4. 根据权利要求3所述的阵列基板，其中，所述两种折射率不同的材质包括第一材质，所述反射层待反射的激光的波长确定，
    所述第一材质形成膜层的厚度与所述第一材质的折射率的乘积，是所述待反射的光的波长的1/4倍。
  5. 根据权利要求3或4所述的阵列基板，其中，所述两种折射率不同的材质包括第二材质，所述反射层待反射的激光的波长确定，
    所述第二材质形成膜层的厚度与所述第二材质的折射率的乘积，是所述待反射的光的波长的1/4倍。
  6. 根据权利要求5所述的阵列基板，其中，所述两种折射率不同的材质包括第一材质，所述第一材质为二氧化钛，所述第一材质形成的膜层设置于所述基底上。
  7. 根据权利要求5或6所述的阵列基板，其中，所述第二材质为二氧化硅。
  8. 根据权利要求1至7任一项所述的阵列基板，其中，所述保护层包括能量吸收层，所述能量吸收层设置于所述基底与所述走线层之间和/或所述基底与所述多个第二电极电之间。
  9. 根据权利要求8所述的阵列基板，其中，所述能量吸收层的禁带宽度小于3.5eV。
  10. 根据权利要求9所述的阵列基板，其中，所述能量吸收层的材料为二氧化钛。
  11. 根据权利要求1至10任一项所述的阵列基板，其中，所述走线层包括多条连接走线，所述多条连接走线与所述多个第二电极电连接；
    所述多条连接走线在所述基底上的正投影位于所述保护层在所述基底上的正投影内部。
  12. 根据权利要求1至10任一项所述的阵列基板，其中，所述走线层包括驱动电路层，所述驱动电路层包括：
    有源层，设置于所述基底或所述保护层上；
    栅极层，设置于所述有源层远离所述基底的一侧；
    所述有源层在所述基底上的正投影位于所述保护层在所述基底上的正投影内部。
  13. 一种显示面板，包括：
    如权利要求1至12任一项所述的阵列基板，所述阵列基板包括基底和设置于基底上的驱动电路层；
    多个发光器件，所述多个发光器件整列布置于所述驱动电路层远离所述基底一层。
  14. 一种显示装置，包括：
    如权利要求13所述的显示面板，所述显示面板包括基底和走线层，所述基底上设置有走线层；
    驱动电路板，所述驱动电路板设置于所述基底远离走线层一侧上，所述驱动电路板通过柔性线路板和所述走线层电连接。
  15. 一种拼接显示装置，包括：多个如权利要求14所述的显示装置，所述多个显示装置拼接组装。
PCT/CN2022/109236 2022-07-29 2022-07-29 一种阵列基板、显示面板、显示装置和拼接显示装置 WO2024021117A1 (zh)

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