WO2020087588A1 - 显示面板电路结构 - Google Patents

显示面板电路结构 Download PDF

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Publication number
WO2020087588A1
WO2020087588A1 PCT/CN2018/116284 CN2018116284W WO2020087588A1 WO 2020087588 A1 WO2020087588 A1 WO 2020087588A1 CN 2018116284 W CN2018116284 W CN 2018116284W WO 2020087588 A1 WO2020087588 A1 WO 2020087588A1
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WO
WIPO (PCT)
Prior art keywords
electrically connected
pad
connection line
bonding
metal layer
Prior art date
Application number
PCT/CN2018/116284
Other languages
English (en)
French (fr)
Inventor
聂晓辉
张嘉伟
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/343,782 priority Critical patent/US10852606B2/en
Publication of WO2020087588A1 publication Critical patent/WO2020087588A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technology, and particularly to a circuit structure of a display panel.
  • LCD liquid crystal displays
  • other flat display devices have been widely used in mobile phones, TVs, and individuals due to their advantages of high image quality, power saving, thin body, and wide application range.
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates.
  • the liquid crystal molecules can be controlled to change the direction by turning on or off, and the light of the backlight module Refracted to produce a picture.
  • a liquid crystal display panel is composed of a color filter substrate (CF, Color), a thin film transistor substrate (TFT, Thin Film Transistor), a liquid crystal (LC, Liquid) and a sealant frame sandwiched between the color filter substrate and the thin film transistor substrate Sealant), the molding process generally includes: front-end Array process (thin film, yellow light, etching and stripping), middle-stage cell (Cell) process (TFT substrate and CF substrate bonding) and rear-end module assembly Process (drive IC and printed circuit board pressed together).
  • CF color filter substrate
  • TFT Thin Film Transistor
  • LC liquid crystal
  • Sealant a sealant frame sandwiched between the color filter substrate and the thin film transistor substrate Sealant
  • the molding process generally includes: front-end Array process (thin film, yellow light, etching and stripping), middle-stage cell (Cell) process (TFT substrate and CF substrate bonding) and rear-end module assembly Process (drive IC and printed circuit board pressed together).
  • the front-stage Array process is mainly to form a TFT substrate to facilitate the control of the movement of liquid crystal molecules;
  • the middle-stage Cell process is mainly to add liquid crystal between the TFT substrate and the CF substrate;
  • the integration of the board then drives the liquid crystal molecules to rotate and display images.
  • the existing liquid crystal display panel includes a display area 1 ', an output bonding (IC) Output area 2', a test control (Cricuit) area 3 'and an output bonding (IC input) ) Area 4 ', in which the structure of the output bonding (IC Output Pin) area 2' is shown in FIG.
  • first bonding pads 30 ' located at each first bonding pad 30 'A plurality of first connection lines 31', a plurality of second bonding pads 40 'respectively located between the first connection lines 31' and the display area 1 ', respectively located in the plurality of first A second connection line 32 'between the bonding pad 30' and the display area 1 ', a third connection line 33' between the plurality of second bonding pads 40 'and the display area 1', and A fourth connection line 34 'between the plurality of first bonding pads 30' and the test control area 3 'respectively; as shown in FIG.
  • the fixed pads 40 ' all include: a bottom pad 301', a middle pad 302 'above the bottom pad 301' and electrically connected to the bottom pad 301 ', and a middle solder A top pad 303 'above 302' and electrically connected to the middle pad 302 ', the bottom pad 301', the second connection line 32 'and the third connection line 33' are all located in the first metal layer, the The middle pad 302 ', the first connection line 31' and the fourth connection line 34 'are located in the second metal layer, the top pad 303' is located in the transparent conductive layer, between the first metal layer and the second metal layer Having an interlayer insulating layer 94 ', and a passivation layer 95' between the second metal layer and the transparent conductive layer; the bottom pad 301 'of the first bonding pad 30' passes through the second connection line 32 ' Electrically connected to the display area 1 ', the middle pad 302' of the
  • the first bonding pad 30 'and the second bonding pad 40' are both used for bonding driver chips.
  • the first bonding pad 30 'and the second bonding pad 40' are both used for bonding driver chips.
  • the distance between a connection line 31 ' is very small, and the first connection line 31' is only covered with a passivation layer 95 '.
  • the passivation layer 95 ' is likely to be broken, which causes the driver chip to connect the first bonding pad 30' and the first connection line 31 'together, thereby causing an abnormal drive signal input to the display area , Causing poor display.
  • the purpose of the present invention is to provide a circuit structure of a display panel, which can avoid the problem of short circuit between the bonding pins and the bonding pins when the chips are pressed together, improve the process yield, and ensure product quality.
  • the present invention provides a display panel circuit structure, including a display area and an output bonding area located on one side of the display area;
  • the output bonding area includes: a plurality of first bonding pads arranged in parallel and spaced apart, and a plurality of first connection lines between each first bonding pad;
  • Each first bonding pad includes: a first bottom pad, a first middle pad located above the first bottom pad and electrically connected to the first bottom pad, and located on the first A first top pad above the middle pad and electrically connected to the first middle pad;
  • Both the first bottom pad and the first connection line are located in the first metal layer, the first middle pad is located in the second metal layer, and the first top pad is located in the transparent conductive layer, the The first metal layer, the second metal layer and the transparent conductive layer are sequentially stacked, and an interlayer insulating layer is provided between the first metal layer and the second metal layer.
  • the second metal layer and the transparent conductive layer There is a passivation layer.
  • the circuit structure of the display panel further includes a plurality of second connection lines respectively located between the plurality of first bonding pins and the display area, and the second connection lines are located in the first metal layer;
  • each second connecting wire is electrically connected to the first conductive portion of the corresponding first bonding pin, and the other end is electrically connected to the display area.
  • the display panel circuit structure further includes: a plurality of second bonding pads respectively located between the plurality of first connection lines and the display area, respectively located in the plurality of first connection lines and a plurality of first bonding lines Multiple third connection lines between the two bonding pads and multiple fourth connection lines respectively located between the multiple second bonding pads and the display area;
  • Each second bonding pad includes a second bottom pad, a second middle pad located above and electrically connected to the second bottom pad, and located in the second middle A second top pad above the pad and electrically connected to the second middle pad;
  • the second bottom pad and the fourth connection line are located in the first metal layer, the second middle pad and the third connection line are located in the second metal layer, and the second top pad is located in the transparent conductive layer;
  • each third connection line is electrically connected to the corresponding first connection line, the other end is electrically connected to the second middle pad of the corresponding second bonding pad, and one end of each fourth connection line
  • the second bottom pad of the corresponding second bonding pad is electrically connected to each other, and the other end is electrically connected to the display area.
  • the circuit structure of the display panel further includes a test control area located on a side of the output bonding area away from the display area, and a third position between the plurality of first bonding pads and the test control area, respectively Five connection lines and sixth connection lines respectively located between the plurality of first connection lines and the test control area;
  • the fifth connection line and the sixth connection line are both located in the second metal layer
  • each fifth connecting line is electrically connected to the first middle pad of the corresponding first bonding pad, and the other end is electrically connected to the test control area;
  • each sixth connection line is electrically connected to the corresponding first connection line, and the other end is electrically connected to the test control area.
  • the test control area includes multiple first thin film transistors, multiple second thin film transistors, multiple seventh connection lines, multiple eighth connection lines, and a signal input section;
  • each first thin film transistor is electrically connected to the signal input part, the source corresponds to the other end of a fifth connection line, and the drain corresponds to the one end of a seventh connection line;
  • each second thin film transistor corresponds to an electrical connection with the gate of a second thin film transistor
  • the source corresponds to the other end of a sixth connection line
  • the drain corresponds to an eighth connection line End of
  • each seventh connection line and the other end of each eighth connection line are both electrically connected to the signal input section;
  • the gate of the first thin film transistor, the gate of the second thin film transistor, the seventh connection line and the eighth connection line are all located in the first metal layer, the source and drain of the first thin film transistor, and the second thin film The source and drain of the transistor and the signal input portion are located in the second metal layer.
  • the signal input section includes first data signal lines, second data signal lines, and third data signal lines and control signal lines arranged in parallel at intervals;
  • each first thin film transistor is electrically connected to the control signal line, and the other end of each seventh connection line and the other end of each eighth connection line are electrically connected and connected to a data signal line
  • the adjacent seventh connection line and the eighth connection line are electrically connected to different data signal lines.
  • the first bottom pad and the first middle pad are electrically connected through a first via penetrating the interlayer insulating layer, and the first middle pad and the first top pad are passed through a passivation layer
  • the second via is electrically connected.
  • the second bottom pad and the second middle pad are electrically connected through a third via penetrating the interlayer insulating layer, and the second middle pad and the second top pad are passed through a passivation layer
  • the third via is electrically connected, and the third connection line and the first connection line are electrically connected by a fifth via penetrating the interlayer insulating layer.
  • each first thin film transistor is electrically connected to the signal input portion through a sixth via penetrating the interlayer insulating layer, and the drain of each first thin film transistor passes through the interlayer insulating layer
  • the seventh via is electrically connected to the seventh connection line
  • each seventh connection line is electrically connected to the signal input portion through an eighth via penetrating the interlayer insulating layer
  • each of the second thin film transistors The drain electrodes are electrically connected to the eighth connection line through a ninth via hole penetrating the interlayer insulating layer
  • each eighth connection line is connected to a signal input through a tenth via hole penetrating the interlayer insulating layer
  • Each sixth connection line is electrically connected to its corresponding first connection line through an eleventh via that penetrates the interlayer insulating layer.
  • An input bonding area located on a side of the test control area away from the output bonding area, and a plurality of input bonding pads arranged at intervals are arranged in the input bonding area.
  • the present invention provides a circuit structure of a display panel, which includes a display area and an output bonding area located on one side of the display area; the output bonding area includes: a plurality of first arrays arranged in parallel and spaced apart Bonding pads and a plurality of first connecting lines between each first bonding pad; each first bonding pad includes: a first bottom pad, which is located above the first bottom pad and A first middle pad electrically connected to the first bottom pad and a first top pad located above the first middle pad and electrically connected to the first middle pad; the first bottom solder Both the disk and the first connection line are located in the first metal layer, the first middle pad is located in the second metal layer, the first top pad is located in the transparent conductive layer, and the first metal layer is second A metal layer and a transparent conductive layer are sequentially stacked, and an interlayer insulating layer is provided between the first metal layer and the second metal layer, and a passivation layer is provided between the second metal layer and the transparent conductive layer ,
  • FIG. 1 is a structural diagram of an existing liquid crystal display panel
  • FIG. 2 is a structural diagram of an input bonding area in an existing liquid crystal display panel
  • Figure 3 is a cross-sectional view at A'-A 'in Figure 2;
  • Figure 4 is a cross-sectional view at B'-B 'in Figure 2;
  • FIG. 5 is a top view of the circuit structure of the display panel of the present invention.
  • FIG. 6 is a cross-sectional view at A-A in FIG. 5;
  • FIG. 7 is a cross-sectional view at B-B in FIG. 5;
  • FIG. 8 is a cross-sectional view at D-D in FIG. 5;
  • FIG. 9 is a cross-sectional view at C-C in FIG. 5;
  • FIG. 10 is a film structure diagram of the circuit structure of the display panel of the present invention.
  • the present invention provides a circuit structure of a display panel, including a display area 1 and an output bonding area 2 located on one side of the display area 1;
  • the output bonding area 2 includes: a plurality of first bonding pads 30 arranged in parallel and spaced apart, and a plurality of first connection lines 31 between each first bonding pad 30;
  • each first bonding pad 30 includes: a first bottom pad 301, a first located above the first bottom pad 301 and electrically connected to the first bottom pad 301
  • the middle pad 302 and the first top pad 303 located above the first middle pad 302 and electrically connected to the first middle pad 302.
  • the first bottom pad 301 and the first connection line 31 are both located in the first metal layer 91
  • the first middle pad 302 is located in the second metal layer 92
  • the first A top pad 303 is located on the transparent conductive layer 93
  • the first metal layer 91, the second metal layer 92 and the transparent conductive layer 93 are stacked in this order
  • the first metal layer 91 and the second metal layer 92 are An interlayer insulating layer 94 is provided therebetween
  • a passivation layer 95 is provided between the second metal layer 92 and the transparent conductive layer 93.
  • the first connection line 31 between the first bonding pins 30 is located in the first metal layer 91, which is covered with an interlayer insulating layer 94 and a passivation layer 95. Even if an error occurs in the manufacturing process, The broken interlayer insulating layer 94 is still covered with a passivation layer 95, which will not cause the first connecting wire 31 to short-circuit with the first bonding pin 30, which can improve the process yield and ensure product quality.
  • the circuit structure of the display panel further includes a plurality of second connection wires 32 respectively located between the plurality of first bonding pins 30 and the display area 1, the second connection wires 32 being located in the first metal Layer 91;
  • Each second connection line 32 is electrically connected to the first conductive portion 301 of the corresponding first bonding pin 30 at one end, and is electrically connected to the display area 2 at the other end.
  • the circuit structure of the display panel further includes: a plurality of second bonding pads 40 respectively located between the plurality of first connection lines 31 and the display area 2, and respectively located on the plurality of first bonding wires 40 A plurality of third connection lines 33 between the connection line 31 and the plurality of second bonding pads 40 and a plurality of fourth connection lines respectively located between the plurality of second bonding pads 40 and the display area 2 Connecting line 34;
  • each second bonding pad 40 includes a second bottom pad 401, which is located above the second bottom pad 301 and is electrically connected to the second bottom pad 401 A second middle pad 402 and a second top pad 403 located above the second middle pad 402 and electrically connected to the second middle pad 402;
  • the second bottom pad 401 and the fourth connection line 34 are located in the first metal layer 91, the second middle pad 402 and the third connection line 33 are located in the second metal layer 92, and the second top pad 403 Located in the transparent conductive layer 93;
  • each third connection line 33 is electrically connected to its corresponding first connection line 31, and the other end is electrically connected to the second middle pad 402 of its corresponding second bonding pad 40, and each fourth One end of the connecting wire 34 is electrically connected to the second bottom pad 401 of the corresponding second bonding pad 40, and the other end is electrically connected to the display area 2.
  • the display panel circuit structure further includes a test control area 3 located on a side of the output bonding area 2 away from the display area 1, respectively located on the plurality of first bonding pads 30 and the A fifth connection line 35 between the test control area 3 and a sixth connection line 36 between the plurality of first connection lines 31 and the test control area 3, respectively;
  • the fifth connection line 35 and the sixth connection line 36 are both located in the second metal layer 92;
  • each fifth connection line 35 is electrically connected to the corresponding first middle pad 302 of the first bonding pad 30, and the other end is electrically connected to the test control area 3;
  • each sixth connection line 36 is electrically connected to the corresponding first connection line 31, and the other end is electrically connected to the test control area 3.
  • test control area 3 is used to receive test signals
  • the input bonding area 2 is used to transmit test signals to the display area 1
  • the display area 1 is used to emit light when the test signal is driven to complete Picture test of a display panel
  • the test signal includes at least a data signal (Data) for driving each sub-pixel in the display area 3 to emit light.
  • test control area 3, the input bonding area 2 and the display area 1 are all formed on a base substrate 100, preferably the base substrate 100 is a glass substrate.
  • the second connection line 32, the first bonding pin 30, and the fifth connection line 35 are connected in series to form a first transmission channel
  • the third connection line 33, the first connection line 31, and the sixth connection line 36 are sequentially connected in series to form a second transmission channel, the first transmission channel and the second transmission channel are alternately and repeatedly arranged, and each of the first transmission channel and the second transmission channel
  • the channels are electrically connected to a row of sub-pixels in the display area 3, and receive data signals from the test control area 1 to transmit to the corresponding sub-pixels to light up the sub-pixels for testing.
  • the test control area 3 includes a plurality of first thin film transistors 51, a plurality of second thin film transistors 52, a plurality of seventh connection lines 37, a plurality of eighth connection lines 38, and a signal input portion 53;
  • each first thin film transistor 51 is electrically connected to the signal input part 53, the source is electrically connected to the other end of a fifth connection line 35, and the drain is electrically connected to a seventh connection line 37 End of
  • each second thin film transistor 51 corresponds to an electrical connection with the gate of a second thin film transistor 52, the source corresponds to the other end of a sixth connection line 36, and the drain corresponds to an Eight one end of the connecting line 38;
  • each seventh connection line 37 and the other end of each eighth connection line 38 are both electrically connected to the signal input portion 53;
  • the gate of the first thin film transistor 51, the gate of the second thin film transistor 52, the seventh connection line 37 and the eighth connection line 38 are all located in the first metal layer 91, the source of the first thin film transistor 51 and The drain, the source and drain of the second thin film transistor 52, and the signal input portion 53 are all located in the second metal layer 92.
  • each of the first thin-film transistor 51 and the second thin-film transistor 52 further includes an active layer 96, the active layer 96 is located under the gate thereof, and a gate is provided between the active layer 96 and the gate Insulation layer 97.
  • the signal input part 53 includes a first data signal line 61, a second data signal line 62, a third data signal line 63 and a control signal line 64 arranged in parallel at intervals;
  • each first thin film transistor 51 is electrically connected to the control signal line 64, and the other end of each seventh connection line 37 and the other end of each eighth connection line 38 are electrically connected to a data signal line
  • the data signal lines that are electrically connected and that the adjacent seventh and third connection lines 37 and 38 are electrically connected are different.
  • the drain of the first first thin film transistor 51 is electrically connected to the first data signal line 61
  • the drain of the first second thin film transistor 52 is electrically connected to the second data signal line 62
  • the drain of the second first thin film transistor 52 is electrically connected to the third data signal line 63
  • the drain of the second second thin film transistor 52 is connected to the first data signal line 61
  • the third The drain is connected to the second data signal line 62
  • the drain of the third second thin film transistor 52 is connected to the third data signal line 63, and so on.
  • the first data signal line 61, the second data signal line 62 and the second The three data signal lines 63 respectively correspond to the red, green and blue sub-pixels in the display area 3, and are used to transmit data signals of the red, green and blue sub-pixels, respectively.
  • the control signal line 64 is used to transmit a control signal to control the opening and closing of the first thin film transistor 51 and the second thin film transistor 52.
  • first bottom pad 301 and the first middle pad 302 are electrically connected by a first via 71 penetrating the interlayer insulating layer 94, and the first middle pad 302 and the first top solder
  • the discs 303 are electrically connected by second vias 72 penetrating the passivation layer 95.
  • connection between the different film layers is as follows.
  • the second bottom pad 401 and the second middle pad 402 are electrically connected by a third via 73 penetrating through the interlayer insulating layer 94.
  • the second middle solder The pad 402 and the second top pad 403 are electrically connected by a third via 73 penetrating the passivation layer 95, and the third connection line 33 and the first connection line 31 are penetrating the interlayer insulating layer 94.
  • the fifth via 35 is electrically connected.
  • each first thin film transistor 51 is electrically connected to the signal input portion 53 through a sixth via 76 that penetrates the interlayer insulating layer 94, and the drain of each first thin film transistor 51 passes through
  • the seventh via 77 penetrating through the interlayer insulating layer 94 is electrically connected to the seventh connecting line 37, and each seventh connecting line 37 passes through the eighth via 48 penetrating through the interlayer insulating layer 94 and
  • the signal input portion 53 is electrically connected, and the drain of each second thin film transistor 52 is electrically connected to the eighth connection line 38 through a ninth via 79 penetrating the interlayer insulating layer 94, each eighth
  • the connecting wires 38 are electrically connected to the signal input portion 53 through the tenth via 710 passing through the interlayer insulating layer 94, and each sixth connecting wire 36 passes through the eleventh passing through the interlayer insulating layer 94.
  • the hole 711 is electrically connected to the corresponding first connecting wire 31.
  • the first metal layer 91 is also used to form the gate and gate lines of the pixel driving TFT in the display area 1
  • the first metal layer 92 is also used to form the display area
  • the pixels in 1 drive the source, drain, and source lines of the TFT
  • the transparent conductive layer 93 is also used for the pixel electrodes of each sub-pixel in the display area 1.
  • an input bonding area 4 located on a side of the test control area 3 away from the output bonding area 2 is provided with a plurality of input bonding pads 80 arranged at intervals.
  • the external first data signal, second data signal, and third data signal are applied to the first data signal line 61, the second data signal line 62, and the third data signal line 63, respectively, and the control signal is applied.
  • the control signal line 64 To the control signal line 64, the first thin film transistor 51 and the second thin film transistor 52 and the first transmission channel and the second transmission channel are transmitted to the display area to drive the sub-pixels in the display area to emit light.
  • the input pin of the driving chip is bonded to the input bonding pin 80, and the output pin is bonded to the first bonding pin 30 and the second bonding pin 40 to Together, so that external signals can be input into the driver chip from the input pins of the driver chip, and after being processed by the driver chip, output from the output pins of the driver chip to the first bonding pin 30 and the second bonding pin 40, It is then transmitted to the display area 3 to drive the sub-pixels in the display area 3 to emit light.
  • the present invention provides a display panel circuit structure including a display area and an output bonding area located on one side of the display area; the output bonding area includes: a plurality of first states arranged in parallel and spaced apart Fixed pads and a plurality of first connection lines between each first bonding pad; each first bonding pad includes: a first bottom pad, located above the first bottom pad and A first middle pad electrically connected to the first bottom pad and a first top pad located above the first middle pad and electrically connected to the first middle pad; the first bottom pad Both the first connection line and the first connection layer are located in the first metal layer, the first middle pad is located in the second metal layer, the first top pad is located in the transparent conductive layer, and the first metal layer is the second metal The layers and the transparent conductive layer are sequentially stacked, and an interlayer insulating layer is provided between the first metal layer and the second metal layer, and a passivation layer is provided between the second metal layer and the transparent conductive layer.

Abstract

一种显示面板电路结构，包括显示区(1)及位于显示区(1)的一侧的输出邦定区(2)；输出邦定区(2)包括：平行间隔排列的多个第一邦定焊盘(30)以及位于各个第一邦定焊盘(30)之间的多条第一连接线(31)；每一个第一邦定焊盘(30)均包括：第一底焊盘(301)、第一中焊盘(302)以及第一顶焊盘(303)；第一底焊盘(301)与第一连接线(31)均位于第一金属层(91)，第一中焊盘(302)位于第二金属层(92)，第一顶焊盘(303)位于透明导电层(93)，第一金属层(91)、第二金属层(92)及透明导电层(93)依次层叠设置，且第一金属层(91)与第二金属层(92)之间设有层间绝缘层(94)，第二金属层(92)与透明导电层(93)之间设有钝化层(95)，通过将第一连接线(31)设置于第一金属层(91)，能够避免在芯片压合时出现第一邦定引脚(30)之间的第一连接线(31)与第一邦定引脚(30)短路的问题，提升制程良率，保证产品质量。

Description

显示面板电路结构 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板电路结构。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜基板(CF，Color Filter)、薄膜晶体管基板(TFT，Thin Film Transistor)、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
如图1所示，现有的液晶显示面板包括依次排列的显示区1’、输出邦定(IC Output Pin)区2’、测试控制(Test Cricuit)区3’及输出邦定(IC input Pin)区4’，其中输出邦定(IC Output Pin)区2’的结构如图2所示，包括平行间隔排列的多个第一邦定焊盘30’、位于各个第一邦定焊盘30’之间的多条第一连接线31’、分别位于所述第一连接线31’和显示区1’之间的多个第二邦定焊盘40’、分别位于所述多个第一邦定焊盘30’与显示区1’之间的第二连接线32’、分别位于所述多个第二邦定焊盘40’和显示区1’之间的第三连接线33’以及分别位于所述多个第一邦定焊盘30’与测试控制区3’之间的第四连接线34’；如图3所示，所述第一邦定焊盘30’和第二邦定焊盘40’ 均包括：底焊盘301’、位于所述底焊盘301’上方并与所述底焊盘301’电性连接的中焊盘302’以及位于所述中焊盘302’上方并与中焊盘302’电性连接的顶焊盘303’，所述底焊盘301’、第二连接线32’及第三连接线33’均位于第一金属层，所述中焊盘302’、第一连接线31’及第四连接线34’位于第二金属层，所述顶焊盘303’位于透明导电层，所述第一金属层与第二金属层之间具有层间绝缘层94’，所述第二金属层与透明导电层之间具有钝化层95’；所述第一邦定焊盘30’的底焊盘301’通过第二连接线32’与显示区1’电性连接，所述第一邦定焊盘30’的中焊盘302’通过第四连接线34’与测试控制区3’电性连接，所述第二邦定焊盘40’的底焊盘301’通过第三连接线33’与显示区1’电性连接，所述第二邦定焊盘40’的中焊盘302’通过第一连接线31’与测试控制区3’电性连接。
其中，所述第一邦定焊盘30’和第二邦定焊盘40’均用于邦定(Bonding)驱动芯片，然而如图4所示，由于第一邦定焊盘30’与第一连接线31’之间的间距很小，而第一连接线31’上方仅覆盖一层钝化层95’，在邦定时，由于连接线制程工艺不佳、钝化层覆盖不佳及邦定工艺精度不良等原因，容易出现钝化层95’被破裂，导致驱动芯片将第一邦定焊盘30’与第一连接线31’连接到一起，进而造成向显示区输入的驱动信号异常，引起显示不良。
发明内容
本发明的目的在于提供一种显示面板电路结构，能够避免在芯片压合时出现邦定引脚之间的连接线与邦定引脚短路的问题，提升制程良率，保证产品质量。
为实现上述目的，本发明提供了一种显示面板电路结构，包括显示区及位于所述显示区的一侧的输出邦定区；
所述输出邦定区包括：平行间隔排列的多个第一邦定焊盘以及位于各个第一邦定焊盘之间的多条第一连接线；
每一个第一邦定焊盘均包括：第一底焊盘、位于所述第一底焊盘上方并与所述第一底焊盘电性连接的第一中焊盘以及位于所述第一中焊盘上方并与第一中焊盘电性连接的第一顶焊盘；
所述第一底焊盘与所述第一连接线均位于第一金属层，所述第一中焊盘位于第二金属层、所述第一顶焊盘位于所述透明导电层，所述第一金属层第二金属层及透明导电层依次层叠设置，且所述第一金属层与第二金属层之间设有层间绝缘层，所述第二金属层与所述透明导电层之间设有钝化层。
所述显示面板电路结构还包括分别位于所述多个第一邦定引脚与显示区之间的多条第二连接线，所述第二连接线位于第一金属层；
每一条第二连接线一端均电性连接其对应的第一邦定引脚的第一导电部，另一端均电性连接显示区。
所述显示面板电路结构还包括：分别位于所述多条第一连接线与所述显示区之间的多个第二邦定焊盘、分别位于所述多条第一连接线和多个第二邦定焊盘之间的多条第三连接线以及分别位于所述多个第二邦定焊盘与所述显示区之间的多条第四连接线；
每一个第二邦定焊盘均包括第二底焊盘、位于所述第二底焊盘上方并与所述第二底焊盘电性连接的第二中焊盘以及位于所述第二中焊盘上方并与第二中焊盘电性连接的第二顶焊盘；
所述第二底焊盘和第四连接线位于第一金属层，所述第二中焊盘和第三连接线位于第二金属层，所述第二顶焊盘位于透明导电层；
每一条第三连接线的一端均电性连接其对应的第一连接线，另一端均电性连接其对应的第二邦定焊盘的第二中焊盘，每一条第四连接线的一端均电性连接其对应的第二邦定焊盘的第二底焊盘，另一端电性连接显示区。
所述显示面板电路结构还包括位于所述输出邦定区远离所述显示区的一侧的测试控制区、分别位于所述多个第一邦定焊盘与所述测试控制区之间的第五连接线以及分别位于所述多条第一连接线与所述测试控制区之间的第六连接线；
所述第五连接线和第六连接线均位于第二金属层；
每一条第五连接线的一端均与其对应的第一邦定焊盘的第一中焊盘电性连接，另一端电性连接测试控制区；
每一条第六连接线的一端均与其对应的第一连接线电性连接，另一端电性连接测试控制区。
所述测试控制区包括多个第一薄膜晶体管、多个第二薄膜晶体管、多条第七连接线、多条第八连接线及信号输入部；
每一个第一薄膜晶体管的栅极均与所述信号输入部电性连接，源极对应电性连接一条第五连接线的另一端，漏极对应电性连接一条第七连接线的一端；
每一个第二薄膜晶体管的栅极均对应与一个第二薄膜晶体管的栅极电性连接，源极对应电性连接一条第六连接线的另一端，漏极对应电性连接一条第八连接线的一端；
每一条第七连接线的另一端和每一条第八连接线的另一端均电性连接 所述信号输入部；
所述第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第七连接线及第八连接线均位于第一金属层，所述第一薄膜晶体管的源极和漏极、第二薄膜晶体管的源极和漏极及信号输入部均位于第二金属层。
所述信号输入部包括平行间隔排列的第一数据信号线、第二数据信号线及第三数据信号线和控制信号线；
每一个第一薄膜晶体管的栅极均与所述控制信号线电性连接，每一条第七连接线的另一端和每一条第八连接线的另一端均与一条数据信号线电性连接且相邻的第七连接线和第八连接线电性连接的数据信号线不同。
所述第一底焊盘和第一中焊盘之间通过贯穿层间绝缘层的第一过孔电性连接，所述第一中焊盘和第一顶焊盘之间通过贯穿钝化层的第二过孔电性连接。
所述第二底焊盘和第二中焊盘之间通过贯穿层间绝缘层的第三过孔电性连接，所述第二中焊盘和第二顶焊盘之间通过贯穿钝化层的第三过孔电性连接，所述第三连接线和第一连接线之间通过贯穿层间绝缘层的第五过孔电性连接。
每一个第一薄膜晶体管的栅极均通过贯穿所述层间绝缘层的第六过孔与信号输入部电性连接，每一个第一薄膜晶体管的漏极均通过贯穿所述层间绝缘层的第七过孔与所述第七连接线电性连接，每一条第七连接线均通过贯穿所述层间绝缘层的第八过孔与信号输入部电性连接，每一个第二薄膜晶体管的漏极均通过贯穿所述层间绝缘层的第九过孔与所述第八连接线电性连接，每一条第八连接线均通过贯穿所述层间绝缘层的第十过孔与信号输入部电性连接，每一条第六连接线均通过贯穿所述层间绝缘层的第十一过孔与其对应的第一连接线电性连接。
位于所述测试控制区远离所述输出邦定区的一侧的输入邦定区，所述输入邦定区内设有多个间隔排列的输入邦定焊盘。
本发明的有益效果：本发明提供一种显示面板电路结构，包括显示区及位于所述显示区的一侧的输出邦定区；所述输出邦定区包括：平行间隔排列的多个第一邦定焊盘以及位于各个第一邦定焊盘之间的多条第一连接线；每一个第一邦定焊盘均包括：第一底焊盘、位于所述第一底焊盘上方并与所述第一底焊盘电性连接的第一中焊盘以及位于所述第一中焊盘上方并与第一中焊盘电性连接的第一顶焊盘；所述第一底焊盘与所述第一连接线均位于第一金属层，所述第一中焊盘位于第二金属层、所述第一顶焊盘位于所述透明导电层，所述第一金属层第二金属层及透明导电层依次层叠 设置，且所述第一金属层与第二金属层之间设有层间绝缘层，所述第二金属层与所述透明导电层之间设有钝化层，通过将所述第一连接线设置于第一金属层，能够避免在芯片压合时出现第一邦定引脚之间的第一连接线与第一邦定引脚短路的问题，提升制程良率，保证产品质量。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的液晶显示面板的结构图；
图2为现有的液晶显示面板中输入邦定区的结构图；
图3为图2中A’-A’处的剖面图；
图4为图2中B’-B’处的剖面图；
图5为本发明的显示面板电路结构的俯视图；
图6为图5中A-A处的剖面图；
图7为图5中B-B处的剖面图；
图8为图5中D-D处的剖面图；
图9为图5中C-C处的剖面图；
图10为本发明的显示面板电路结构的膜层结构图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5至图10，本发明提供一种显示面板电路结构，包括显示区1及位于所述显示区1的一侧的输出邦定区2；
所述输出邦定区2包括：平行间隔排列的多个第一邦定焊盘30以及位于各个第一邦定焊盘30之间的多条第一连接线31；
请参阅图7，每一个第一邦定焊盘30均包括：第一底焊盘301、位于所述第一底焊盘301上方并与所述第一底焊盘301电性连接的第一中焊盘302以及位于所述第一中焊盘302上方并与第一中焊盘302电性连接的第一顶焊盘303。
请参阅图6及图10，所述第一底焊盘301与所述第一连接线31均位于第一金属层91，所述第一中焊盘302位于第二金属层92，所述第一顶焊盘 303位于所述透明导电层93，所述第一金属层91、第二金属层92及透明导电层93依次层叠设置，且所述第一金属层91与第二金属层92之间设有层间绝缘层94，所述第二金属层92与所述透明导电层93之间设有钝化层95。
在芯片邦定时，位于第一邦定引脚30之间的第一连接线31位于第一金属层91，其上覆盖有层间绝缘层94和钝化层95，即便在制程出现误差，压破层间绝缘层94，其上仍有钝化层95覆盖，不会导致第一连接线31与第一邦定引脚30短路，能够提升制程良率，保证产品质量。
具体地，所述显示面板电路结构还包括分别位于所述多个第一邦定引脚30与显示区1之间的多条第二连接线32，所述第二连接线32位于第一金属层91；
每一条第二连接线32一端均电性连接其对应的第一邦定引脚30的第一导电部301，另一端均电性连接显示区2。
具体地，所述显示面板电路结构还包括：分别位于所述多条第一连接线31与所述显示区2之间的多个第二邦定焊盘40、分别位于所述多条第一连接线31和多个第二邦定焊盘40之间的多条第三连接线33以及分别位于所述多个第二邦定焊盘40与所述显示区2之间的多条第四连接线34；
请参阅图8及图9，每一个第二邦定焊盘40均包括第二底焊盘401、位于所述第二底焊盘301上方并与所述第二底焊盘401电性连接的第二中焊盘402以及位于所述第二中焊盘402上方并与第二中焊盘402电性连接的第二顶焊盘403；
所述第二底焊盘401和第四连接线34位于第一金属层91，所述第二中焊盘402和第三连接线33位于第二金属层92，所述第二顶焊盘403位于透明导电层93；
每一条第三连接线33的一端均电性连接其对应的第一连接线31，另一端均电性连接其对应的第二邦定焊盘40的第二中焊盘402，每一条第四连接线34的一端均电性连接其对应的第二邦定焊盘40的第二底焊盘401，另一端电性连接显示区2。
具体地，所述显示面板电路结构还包括位于所述输出邦定区2远离所述显示区1的一侧的测试控制区3、分别位于所述多个第一邦定焊盘30与所述测试控制区3之间的第五连接线35以及分别位于所述多条第一连接线31与所述测试控制区3之间的第六连接线36；
所述第五连接线35和第六连接线36均位于第二金属层92；
每一条第五连接线35的一端均与其对应的第一邦定焊盘30的第一中焊盘302电性连接，另一端电性连接测试控制区3；
每一条第六连接线36的一端均与其对应的第一连接线31电性连接，另一端电性连接测试控制区3。
其中，所述测试控制区3用于接收测试信号，所述输入邦定区2用于将测试信号传输至显示区1，所述显示区1用于在测试信号在驱动下发光，以完成对显示面板的画面测试，其中所述测试信号至少包括用于驱动所述显示区3内的各个子像素发光的数据信号(Data)。
具体地，所述测试控制区3、输入邦定区2及显示区1均形成于一衬底基板100上，优选地所述衬底基板100为玻璃基板。
需要说明的是，所述第二连接线32、第一邦定引脚30及第五连接线35依次串联形成第一传输通道，所述第四连接线34、第二邦定引脚40、第三连接线33、第一连接线31、第六连接线36依次串联形成第二传输通道，所述第一传输通道和第二传输通道交替重复排列，每一个第一传输通道和第二传输通道均电性连接所述显示区3内的一列子像素，并从所述测试控制区1接收数据信号传输至对应的子像素，以点亮所述子像素进行测试。
具体地，所述测试控制区3包括多个第一薄膜晶体管51、多个第二薄膜晶体管52、多条第七连接线37、多条第八连接线38及信号输入部53；
每一个第一薄膜晶体管51的栅极均与所述信号输入部53电性连接，源极对应电性连接一条第五连接线35的另一端，漏极对应电性连接一条第七连接线37的一端；
每一个第二薄膜晶体管51的栅极均对应与一个第二薄膜晶体管52的栅极电性连接，源极对应电性连接一条第六连接线36的另一端，漏极对应电性连接一条第八连接线38的一端；
每一条第七连接线37的另一端和每一条第八连接线38的另一端均电性连接所述信号输入部53；
所述第一薄膜晶体管51的栅极、第二薄膜晶体管52的栅极、第七连接线37及第八连接线38均位于第一金属层91，所述第一薄膜晶体管51的源极和漏极、第二薄膜晶体管52的源极和漏极及信号输入部53均位于第二金属层92。
此外，所述第一薄膜晶体管51和第二薄膜晶体管52均还包括一有源层96，所述有源层96位于其栅极下方，且有源层96与栅极之间设有栅极绝缘层97。
进一步地，所述信号输入部53包括平行间隔排列的第一数据信号线61、第二数据信号线62及第三数据信号线63和控制信号线64；
每一个第一薄膜晶体管51的栅极均与所述控制信号线64电性连接， 每一条第七连接线37的另一端和每一条第八连接线38的另一端均与一条数据信号线电性连接且相邻的第七连接线37和第八连接线38电性连接的数据信号线不同。
具体连接关系例如图4所示，第一个第一薄膜晶体管51的漏极电性连接第一数据信号线61，第一个第二薄膜晶体管52的漏极电性连接第二数据信号线62，第二个第一薄膜晶体管52的漏极电性连接第三数据信号线63，第二个第二薄膜晶体管52的漏极连接第一数据信号线61，第三个第一薄膜晶体管51的漏极连接第二数据信号线62，第三个第二薄膜晶体管52的漏极连接第三数据信号线63，依次类推，其中所述第一数据信号线61、第二数据信号线62及第三数据信号线63分别对应所述显示区3内的红色子像素、绿色子像素及蓝色子像素设置，分别用于传输红色子像素、绿色子像素及蓝色子像素的数据信号，而所述控制信号线64用于传输控制信号控制所述第一薄膜晶体管51和第二薄膜晶体管52的开闭。
具体地，所述第一底焊盘301和第一中焊盘302之间通过贯穿层间绝缘层94的第一过孔71电性连接，所述第一中焊盘302和第一顶焊盘303之间通过贯穿钝化层95的第二过孔72电性连接。
不同膜层之间的连接方式如下，所述第二底焊盘401和第二中焊盘402之间通过贯穿层间绝缘层94的第三过孔73电性连接，所述第二中焊盘402和第二顶焊盘403之间通过贯穿钝化层95的第三过孔73电性连接，所述第三连接线33和第一连接线31之间通过贯穿层间绝缘层94的第五过孔35电性连接。
具体地，每一个第一薄膜晶体管51的栅极均通过贯穿所述层间绝缘层94的第六过孔76与信号输入部53电性连接，每一个第一薄膜晶体管51的漏极均通过贯穿所述层间绝缘层94的第七过孔77与所述第七连接线37电性连接，每一条第七连接线37均通过贯穿所述层间绝缘层94的第八过孔48与信号输入部53电性连接，每一个第二薄膜晶体管52的漏极均通过贯穿所述层间绝缘层94的第九过孔79与所述第八连接线38电性连接，每一条第八连接线38均通过贯穿所述层间绝缘层94的第十过孔710与信号输入部53电性连接，每一条第六连接线36均通过贯穿所述层间绝缘层94的第十一过孔711与其对应的第一连接线31电性连接。
值得一提的是，所述第一金属层91还用于形成所述显示区1内的像素驱动TFT的栅极及栅极线，所述第一金属层92还用于形成所述显示区1内的像素驱动TFT的源极、漏极及源极线，所述透明导电层93还用于所述所述显示区1内的各个子像素的像素电极。
具体地，位于所述测试控制区3远离所述输出邦定区2的一侧的输入邦定区4，所述输入邦定区4内设有多个间隔排列的输入邦定焊盘80。
进行点亮测试时，外部的第一数据信号、第二数据信号及第三数据信号分别施加至第一数据信号线61、第二数据信号线62及第三数据信号线63上，控制信号施加至控制信号线64上，经由第一薄膜晶体管51和第二薄膜晶体管52以及第一传输通道和第二传输通道传输至显示区内驱动显示区内的子像素发光。
进行驱动芯片邦定时，驱动芯片的输入引脚与所述输入邦定引脚80邦定至一起，输出引脚与所述第一邦定引脚30和第二邦定引脚40邦定至一起，从而外部信号能够从驱动芯片的输入引脚输入至驱动芯片中，经过驱动芯片的处理后从驱动芯片的输出引脚输出至第一邦定引脚30和第二邦定引脚40，再传输至显示区3中驱动显示区3中的子像素发光。
综上所述，本发明提供一种显示面板电路结构，包括显示区及位于所述显示区的一侧的输出邦定区；所述输出邦定区包括：平行间隔排列的多个第一邦定焊盘以及位于各个第一邦定焊盘之间的多条第一连接线；每一个第一邦定焊盘均包括：第一底焊盘、位于所述第一底焊盘上方并与所述第一底焊盘电性连接的第一中焊盘以及位于所述第一中焊盘上方并与第一中焊盘电性连接的第一顶焊盘；所述第一底焊盘与所述第一连接线均位于第一金属层，所述第一中焊盘位于第二金属层、所述第一顶焊盘位于所述透明导电层，所述第一金属层第二金属层及透明导电层依次层叠设置，且所述第一金属层与第二金属层之间设有层间绝缘层，所述第二金属层与所述透明导电层之间设有钝化层，通过将所述第一连接线设置于第一金属层，能够避免在芯片压合时出现第一邦定引脚之间的第一连接线与第一邦定引脚短路的问题，提升制程良率，保证产品质量。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方
案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种显示面板电路结构，包括显示区及位于所述显示区的一侧的输出邦定区；
    所述输出邦定区包括：平行间隔排列的多个第一邦定焊盘以及位于各个第一邦定焊盘之间的多条第一连接线；
    每一个第一邦定焊盘均包括：第一底焊盘、位于所述第一底焊盘上方并与所述第一底焊盘电性连接的第一中焊盘以及位于所述第一中焊盘上方并与第一中焊盘电性连接的第一顶焊盘；
    所述第一底焊盘与所述第一连接线均位于第一金属层，所述第一中焊盘位于第二金属层，所述第一顶焊盘位于所述透明导电层，所述第一金属层、第二金属层及透明导电层依次层叠设置，且所述第一金属层与第二金属层之间设有层间绝缘层，所述第二金属层与所述透明导电层之间设有钝化层。
  2. 如权利要求1所述的显示面板电路结构，还包括分别位于所述多个第一邦定引脚与显示区之间的多条第二连接线，所述第二连接线位于第一金属层；
    每一条第二连接线一端均电性连接其对应的第一邦定引脚的第一导电部，另一端均电性连接显示区。
  3. 如权利要求1所述的显示面板电路结构，还包括：分别位于所述多条第一连接线与所述显示区之间的多个第二邦定焊盘、分别位于所述多条第一连接线和多个第二邦定焊盘之间的多条第三连接线以及分别位于所述多个第二邦定焊盘与所述显示区之间的多条第四连接线；
    每一个第二邦定焊盘均包括第二底焊盘、位于所述第二底焊盘上方并与所述第二底焊盘电性连接的第二中焊盘以及位于所述第二中焊盘上方并与第二中焊盘电性连接的第二顶焊盘；
    所述第二底焊盘和第四连接线位于第一金属层，所述第二中焊盘和第三连接线位于第二金属层，所述第二顶焊盘位于透明导电层；
    每一条第三连接线的一端均电性连接其对应的第一连接线，另一端均电性连接其对应的第二邦定焊盘的第二中焊盘，每一条第四连接线的一端均电性连接其对应的第二邦定焊盘的第二底焊盘，另一端电性连接显示区。
  4. 如权利要求1所述的显示面板电路结构，还包括位于所述输出邦定区远离所述显示区的一侧的测试控制区、分别位于所述多个第一邦定焊盘 与所述测试控制区之间的第五连接线以及分别位于所述多条第一连接线与所述测试控制区之间的第六连接线；
    所述第五连接线和第六连接线均位于第二金属层；
    每一条第五连接线的一端均与其对应的第一邦定焊盘的第一中焊盘电性连接，另一端电性连接测试控制区；
    每一条第六连接线的一端均与其对应的第一连接线电性连接，另一端电性连接测试控制区。
  5. 如权利要求4所述的显示面板电路结构，其中，所述测试控制区包括多个第一薄膜晶体管、多个第二薄膜晶体管、多条第七连接线、多条第八连接线及信号输入部；
    每一个第一薄膜晶体管的栅极均与所述信号输入部电性连接，源极对应电性连接一条第五连接线的另一端，漏极对应电性连接一条第七连接线的一端；
    每一个第二薄膜晶体管的栅极均对应与一个第二薄膜晶体管的栅极电性连接，源极对应电性连接一条第六连接线的另一端，漏极对应电性连接一条第八连接线的一端；
    每一条第七连接线的另一端和每一条第八连接线的另一端均电性连接所述信号输入部；
    所述第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第七连接线及第八连接线均位于第一金属层，所述第一薄膜晶体管的源极和漏极、第二薄膜晶体管的源极和漏极及信号输入部均位于第二金属层。
  6. 如权利要求5所述的显示面板电路结构，其中，所述信号输入部包括平行间隔排列的第一数据信号线、第二数据信号线及第三数据信号线和控制信号线；
    每一个第一薄膜晶体管的栅极均与所述控制信号线电性连接，每一条第七连接线的另一端和每一条第八连接线的另一端均与一条数据信号线电性连接且相邻的第七连接线和第八连接线电性连接的数据信号线不同。
  7. 如权利要求1所述的显示面板电路结构，其中，所述第一底焊盘和第一中焊盘之间通过贯穿层间绝缘层的第一过孔电性连接，所述第一中焊盘和第一顶焊盘之间通过贯穿钝化层的第二过孔电性连接。
  8. 如权利要求3所述的显示面板电路结构，其中，所述第二底焊盘和第二中焊盘之间通过贯穿层间绝缘层的第三过孔电性连接，所述第二中焊盘和第二顶焊盘之间通过贯穿钝化层的第三过孔电性连接，所述第三连接线和第一连接线之间通过贯穿层间绝缘层的第五过孔电性连接。
  9. 如权利要求5所述的显示面板电路结构，其中，每一个第一薄膜晶体管的栅极均通过贯穿所述层间绝缘层的第六过孔与信号输入部电性连接，每一个第一薄膜晶体管的漏极均通过贯穿所述层间绝缘层的第七过孔与所述第七连接线电性连接，每一条第七连接线均通过贯穿所述层间绝缘层的第八过孔与信号输入部电性连接，每一个第二薄膜晶体管的漏极均通过贯穿所述层间绝缘层的第九过孔与所述第八连接线电性连接，每一条第八连接线均通过贯穿所述层间绝缘层的第十过孔与信号输入部电性连接，每一条第六连接线均通过贯穿所述层间绝缘层的第十一过孔与其对应的第一连接线电性连接。
  10. 如权利要求4所述的显示面板电路结构，还包括位于所述测试控制区远离所述输出邦定区的一侧的输入邦定区，所述输入邦定区内设有多个间隔排列的输入邦定焊盘。
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