WO2024040877A1 - 拼接显示面板及其拼接方法、显示装置 - Google Patents

拼接显示面板及其拼接方法、显示装置 Download PDF

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Publication number
WO2024040877A1
WO2024040877A1 PCT/CN2023/074880 CN2023074880W WO2024040877A1 WO 2024040877 A1 WO2024040877 A1 WO 2024040877A1 CN 2023074880 W CN2023074880 W CN 2023074880W WO 2024040877 A1 WO2024040877 A1 WO 2024040877A1
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WO
WIPO (PCT)
Prior art keywords
backplane
substrate
binding
layer
display
Prior art date
Application number
PCT/CN2023/074880
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English (en)
French (fr)
Inventor
沈海燕
张乐
鲜于文旭
张春鹏
黄灿
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024040877A1 publication Critical patent/WO2024040877A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Definitions

  • the present application relates to the field of display technology, and in particular to a splicing display panel, a splicing method thereof, and a display device.
  • the splicing screen is made up of multiple display screens, which allows it to be large enough to meet the large-size needs in fields such as outdoor displays.
  • Existing splicing screens mostly use Printed Circuit Board (PCB)-based splicing.
  • PCB Printed Circuit Board
  • This splicing method is relatively simple, but the PCB-based wiring width and wiring accuracy are poorer than those of glass-based ones, making it difficult to meet high-precision splicing. Require.
  • glass-based splicing is required for splicing screens that apply Mini-LED or Micro-LED technology.
  • glass-based splicing is mostly used to use a set of driver ICs corresponding to one splicing unit, so that each splicing unit has a frame. The existence of the frame of each splicing unit will lead to large splicing seams at the splicing joints of the splicing screen, which will affect the display taste.
  • This application provides a splicing display panel, its splicing method, and a display device to alleviate the technical problem of large splicing seams at the splicing locations of existing splicing screens.
  • Embodiments of the present application provide a spliced display panel, which includes a driving backplane and a plurality of display components arranged in an array on the driving backplane;
  • Each of the display components includes a display substrate, a plurality of first binding terminals disposed on one side of the display substrate, and a plurality of LED chips disposed on the other side of the display substrate.
  • the first binding terminals are connected to corresponding The LED chip is electrically connected;
  • the driving backplane includes a stacked first backplane and a second backplane.
  • the first backplane is located on a side of the second backplane away from the display component.
  • the second backplane is provided with A plurality of second binding terminals, a plurality of third binding terminals and driving elements electrically connected to the third binding terminals are provided on the first backplane, and the second binding terminals are electrically connected to corresponding the first binding terminal and the corresponding third binding terminal.
  • the driving element array is arranged on a side of the first backplane away from the second backplane.
  • the first backplane includes a first substrate and a first barrier layer located on a side of the first substrate close to the second backplane, and the third The binding terminal is located on the first substrate, and the first barrier layer is provided with a gap at a position corresponding to the third binding terminal to expose the third binding terminal; the first substrate A first opening is provided at a position corresponding to the third binding terminal, and the driving element is electrically connected to the third binding terminal through the first opening.
  • the first backplane further includes a first auxiliary conductive layer filled in the first opening, and the driving element passes through the first auxiliary conductive layer.
  • the first auxiliary conductive layer is electrically connected to the third binding terminal.
  • the second backplane includes a second substrate, a connecting trace and a second barrier layer located on a side of the second substrate close to the display component, and the The second barrier layer covers the connecting traces, the second binding terminals are located on the second barrier layer, and the connecting traces are connected to the corresponding second binding terminals and the third Bind terminals.
  • the second backplane includes a second substrate, a driving function layer and a second barrier layer located on a side of the second substrate close to the display component, and the The second barrier layer covers the driving function layer, the second binding terminal is located on the second barrier layer, and the driving function layer is connected to the corresponding second binding terminal and the third Bind terminals.
  • the display substrate includes: base substrate; A drive circuit layer provided on the side of the base substrate away from the drive backplane; the drive circuit layer is electrically connected to the first binding terminal; The LED chip is located on a side of the driving circuit layer away from the base substrate and is electrically connected to the driving circuit layer.
  • the base substrate includes a third substrate and a third barrier layer located on a side of the third substrate away from the driving circuit layer, and the first binding layer
  • the terminal is located on a side of the third barrier layer away from the third substrate, and the third barrier layer is provided with a second opening at a position corresponding to the first binding terminal. The terminal is located in the second opening.
  • the driving circuit layer includes a planarization layer and a first electrode and a second electrode provided on a side of the planarization layer away from the base substrate;
  • the LED chip It has a first pole and a second pole, the first pole is electrically connected to the first electrode, and the second pole is electrically connected to the second electrode.
  • the driving circuit layer further includes a pixel definition layer covering the planarization layer, the pixel definition layer corresponding to the first electrode and the second electrode.
  • An opening is provided at the position, and the LED chip is arranged in the opening.
  • An embodiment of the present application also provides a splicing display panel splicing method, which includes: Provide a transfer substrate on which a plurality of LED chips are arranged in an array; A plurality of display components are provided, each of the display components includes a display substrate and a plurality of first binding terminals disposed on one side of the display substrate, and the LED chips on the transfer substrate are sequentially transferred to each of the The other side of the display substrate of the display component electrically connects the first binding terminal to the corresponding LED chip; A driving backplane is provided, the driving backplane includes a first backplane and a second backplane arranged in a stack, the first backplane is located on a side of the second backplane away from the display assembly, and the second backplane A plurality of second binding terminals are provided on the backplane, and a plurality of third binding terminals and driving elements electrically connected to the third binding terminals are provided on the first backplane.
  • the terminal is also electrically connected to the corresponding second binding terminal; Splice a plurality of the display components on the driving backplane so that each second binding terminal is electrically connected to the corresponding first binding terminal, so that the driving element passes through the third binding terminal.
  • the terminal transmits signals to the second binding terminal, the first binding terminal and the LED chip in sequence to drive the LED chip to emit light.
  • An embodiment of the present application also provides a display device, which includes: A housing is formed with an accommodation cavity; and a splicing display panel as in one of the previous embodiments, the splicing display panel is disposed in the accommodation cavity.
  • the spliced display panel includes a driving backplane and a plurality of display components arranged in an array on the driving backplane, and each of the display components includes a display panel.
  • the driving backplane is provided with a second binding terminal bound to the first binding terminal and a third binding terminal electrically connected to the driving element and the second binding terminal, and the driving element passes through the third binding terminal.
  • the three binding terminals transmit signals to the second binding terminal, the first binding terminal and the LED chip in sequence to drive the LED chip to emit light.
  • the driving element is arranged on the driving backplane, which can Reducing or eliminating the frame of each display component reduces or eliminates the splicing seams at the splicing joints after multiple display components are spliced, thus solving the problem of large splicing seams at the splicing joints of existing splicing screens.
  • FIG. 1 is a schematic top structural view of a spliced display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional structural diagram of a spliced display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic cross-sectional structural diagram of a driving backplane provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the arrangement of driving elements on the first backplane according to an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional structural diagram of a display component provided by an embodiment of the present application.
  • FIG. 6 is another schematic cross-sectional structural diagram of a driving backplane provided by an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a splicing display panel splicing method provided by an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional structural diagram of a display device provided by an embodiment of the present application.
  • Figure 1 is a schematic structural diagram of a top view of a splicing display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional structural view of a spliced display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a spliced display panel provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of the arrangement of the driving elements on the first backplane provided by the embodiment of the application.
  • Figure 5 is a schematic diagram of a display assembly provided by the embodiment of the application.
  • the spliced display panel 100 includes a display area AA and a non-display area NA located outside the display area AA.
  • the spliced display panel 100 further includes a driving backplane 1 and a plurality of display components 2 arranged in an array on the driving backplane 1 .
  • a plurality of the display components 2 are located in the display area AA.
  • Each of the display components 2 includes a display substrate 20, a plurality of first binding terminals 10 provided on one side of the display substrate 20, and a plurality of first binding terminals 10 provided on one side of the display substrate 20.
  • a plurality of LED chips 30 on the other side of the display substrate 20 are displayed, and the first binding terminals 10 are electrically connected to the corresponding LED chips 30 .
  • the LED chip 30 includes a Mini-LED chip or a Micro-LED chip.
  • the one side of the display substrate 20 and the other side of the display substrate 20 refer to two opposite sides of the display substrate 20 .
  • the driving backplane 1 is provided with a plurality of second binding terminals 40 and driving elements 50 electrically connected to the second binding terminals 40. Each of the second binding terminals 40 is connected to the corresponding third binding terminal.
  • a binding terminal 10 is electrically connected, thereby electrically connecting the LED chip 30 on the display substrate 20 and the driving element 50 on the driving backplane 1 .
  • the driving element 50 sequentially transmits signals to the first binding terminal 10 and the LED chip 30 through the second binding terminal 40 to drive the LED chip 30 on the display substrate 20 to emit light.
  • the driving element 50 includes a driving device such as an integrated circuit (IC).
  • the driving element 50 is disposed on a side of the driving backplane 1 away from the display assembly 2 .
  • IC integrated circuit
  • the driving backplane 1 includes a stacked first backplane 11 and a second backplane 12.
  • the first backplane 11 is located on the side of the second backplane 12 away from the display assembly 2.
  • the second backplane 12 is provided with a plurality of second binding terminals 40
  • the first backplane 11 is provided with a plurality of third binding terminals 60 and are electrically connected to the third binding terminals 60
  • the driving element 50 , the second binding terminal 40 is electrically connected to the corresponding first binding terminal 10 and the corresponding third binding terminal 60 .
  • the first backplane 11 includes a first substrate 111 and a first barrier layer 112 located on a side of the first substrate 111 close to the second backplane 12.
  • the third binding terminal 60 is located on the first substrate 111 , and the first barrier layer 112 is provided with a notch at a position corresponding to the third binding terminal 60 to expose the third binding terminal 60 .
  • the first substrate 111 is provided with a first opening 1110 at a position corresponding to the third binding terminal 60.
  • the driving element 50 electrically communicates with the third binding terminal 60 through the first opening 1110. connect.
  • the first backplane 11 further includes a first auxiliary conductive layer 1111.
  • the first auxiliary conductive layer 1111 is filled in the first opening 1110.
  • the driving element 50 passes through the first auxiliary conductive layer 1111.
  • Layer 1111 is electrically connected to the third bonding terminal 60 .
  • the material of the first auxiliary conductive layer 1111 includes one or more of conductive film, conductive adhesive, metal solder, solder paste, liquid metal, etc., wherein the conductive adhesive includes polymer Physical conductive adhesive or conductive adhesive doped with conductive particles.
  • the third binding terminal 60 can be made of a metal or alloy with strong oxidation resistance and low resistivity, or a metal laminate structure, metal oxide, conductive oxide, etc., such as MO, AL and other metals.
  • the second backplane 12 includes a second substrate 121 and a connecting trace 123 located on a side of the second substrate 121 close to the display component 2 and a second barrier layer 122 .
  • the layer 122 covers the connecting traces 123, the second binding terminals 40 are located on the second barrier layer 122, and the connecting traces 123 are connected to the corresponding second binding terminals 40 and all the connecting traces 123.
  • the third binding terminal 60 is described.
  • the second binding terminal 40 can also be made of a metal or alloy with strong oxidation resistance and low resistivity, or a metal stack structure, metal oxide, conductive oxide, etc., such as MO, AL and other metals.
  • the second binding terminal 40 is also electrically connected to the corresponding first binding terminal 10 .
  • the driving element 50 sequentially transmits signals to the second binding terminal 40 , the first binding terminal 10 and the display substrate 20 through the third binding terminal 60 to drive the LED.
  • the first barrier layer 112 and the second barrier layer 122 may be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., to prevent undesired Impurities or contaminants (eg, moisture, oxygen, etc.) diffuse from the first substrate 111 or the second substrate 121 into devices that may be damaged by these impurities or contaminants.
  • the materials of the first substrate 111 and the second substrate 121 include flexible film materials such as polyimide (PI).
  • the driving elements 50 are arranged in an array on the side of the first back plate 11 away from the second back plate 12 so that the driving elements 50 are evenly distributed on the first back plate 11, such as As shown in Figure 4.
  • the frame of each display component 2 can be reduced or eliminated, so that the splicing seams at the splicing points after multiple display components 2 are spliced are reduced or eliminated.
  • the driving elements 50 are distributed at equal intervals on the first backplane 11 and are arranged corresponding to the display area of the display panel, which can prevent the driving elements 50 from being concentrated on the lower frame or side frame and causing the wiring to be too long. IR drop problem.
  • the display assembly 2 includes a display substrate 20 and a plurality of first binding terminals 10 and a plurality of LED chips 30 disposed on opposite sides of the display substrate.
  • the display substrate 20 includes a base substrate 13 and a driving circuit layer 21 provided on the base substrate 13.
  • the LED chip 30 is electrically connected to the driving circuit layer 21.
  • the driving circuit layer 21 is used for driving.
  • the LED chip 30 emits light.
  • the first binding terminal 10 can be prepared using metals or alloys with strong oxidation resistance and low resistivity, metal laminated structures, metal oxides, conductive oxides, etc., such as MO, AL and other metals, to ensure that the first The stability of a binding terminal 10 and the reliability of connection with the driving backplane 1 are ensured.
  • the base substrate 13 includes a stacked third barrier layer 132, a third substrate 131, a fourth barrier layer 133 and a buffer layer 134.
  • the first binding terminal 10 and the third barrier layer 132 are both located on a side of the third substrate 131 away from the driving circuit layer 21 .
  • the first binding terminal 10 is disposed on The third barrier layer 132 is on a side away from the third substrate 131 .
  • the third barrier layer 132 is provided with a second opening 1321 at a position corresponding to the first binding terminal 10 .
  • the first The binding terminal 10 is located in the second opening 1321 , and the second opening 1321 exposes the first binding terminal 10 .
  • the fourth barrier layer 133 and the buffer layer 134 are both located on the side of the third substrate 131 close to the driving circuit layer 21. Specifically, the fourth barrier layer 133 covers the third On the substrate 131 , the buffer layer 134 covers the fourth barrier layer 133 .
  • the third barrier layer 132 , the fourth barrier layer 133 and the buffer layer 134 may be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. , to prevent undesired impurities or contaminants (such as moisture, oxygen, etc.) from diffusing from the third substrate 131 into devices that may be damaged by these impurities or contaminants.
  • the material of the third substrate 131 includes flexible film materials such as polyimide (PI).
  • the buffer layer 134 can also provide a flat top surface to facilitate the preparation of other film structures on the buffer layer 134 .
  • the base substrate 13 of the present application is not limited thereto.
  • the base substrate 13 of the present application may include more or less base film layers and barrier film layers.
  • the driving circuit layer 21 is provided on the buffer layer 134.
  • the driving circuit layer 21 includes a first semiconductor layer 22, a first gate electrode 23, a second gate electrode 24, a first source electrode 251, and a first drain electrode. 252 and the insulating layer between each layer, specifically, including the first gate insulating layer 17 between the first semiconductor layer 22 and the first gate 23, 23 and the second gate electrode 24, and the first interlayer insulating layer 19 between the second gate electrode 24 and the first source electrode 251.
  • the first semiconductor layer 22 is disposed on the buffer layer 134 , and the first semiconductor layer 22 includes a channel region and source and drain regions located on opposite sides of the channel region.
  • the first gate insulating layer 17 covers the first semiconductor layer 22 and the buffer layer 134 .
  • the first gate 23 is disposed on the first gate insulating layer 17 , and the first gate 23 is disposed corresponding to the channel region of the first semiconductor layer 22 .
  • the second gate insulating layer 18 covers the first gate 23 and the first gate insulating layer 17 .
  • the second gate electrode 24 is disposed on the second gate insulating layer 18 , and the second gate electrode 24 is disposed corresponding to the first gate electrode 23 .
  • the first interlayer insulating layer 19 covers the second gate 24 and the second gate insulating layer 18 .
  • the source electrode 251 and the drain electrode 252 are disposed on the first interlayer insulating layer 19 , and the source electrode 251 and the drain electrode 252 are respectively connected to the corresponding source regions of the first semiconductor layer 22 electrically connected to the drain region.
  • the driving circuit layer 21 also includes a plurality of signal lines.
  • the signal lines include data lines 253, gate scanning lines, etc., wherein the data lines 253 are in contact with the source electrode 251 and the drain electrode. 252 are arranged on the same layer, and the gate scanning line and the first gate electrode 23 or the second gate electrode 24 are arranged on the same layer.
  • this application is not limited to this.
  • the signal lines in this application may also include VSS, VDD power lines and other various signal lines for display or non-display, and different signal lines are connected to different first Bind the terminals 10 electrically to obtain different signals.
  • the data line 253 is electrically connected to the corresponding first bonding terminal 10 to obtain a source driving signal and provide it to the source 251;
  • the gate scan line is electrically connected to the corresponding first bonding terminal 10.
  • the fixed terminal 10 is electrically connected to obtain the gate scanning signal and provide it to the first gate 23 .
  • This embodiment takes the electrical connection between the data line 253 and the first binding terminal 10 as an example to illustrate: Specifically, continuing to refer to FIG. 5 , the first interlayer insulating layer 19 is patterned with deep holes, and the deep holes penetrate the first interlayer insulating layer 19 , the second gate insulating layer 18 , and the The first gate insulating layer 17, the buffer layer 134, the fourth barrier layer 133, the third substrate 131, the third barrier layer 132 and the first bonding terminal 10 are exposed to partially The first binding terminal 10.
  • the data line 253 is electrically connected to the first binding terminal 10 through the deep hole, and at the same time, the data line 253 is also electrically connected to the source electrode 251 or the drain electrode 252, that is, the data line 253 It is also electrically connected to the driving circuit layer 21 to realize the electrical connection between the first binding terminal 10 and the driving circuit layer 21 .
  • This application takes the electrical connection between the data line 253 and the drain electrode 252 as an example.
  • “same layer arrangement” in this application means that in the preparation process, film layers formed of the same material are patterned to obtain at least two different features, then the at least two different features are the same. Layer settings. For example, if the data line 253 and the source electrode 251 in this embodiment are obtained by patterning the same conductive film layer, then the data line 253 and the source electrode 251 are arranged in the same layer.
  • the driving circuit layer 21 also includes a planarization layer covering the source electrode 251 , the drain electrode 252 and the first interlayer insulating layer 19 27.
  • the structure of the driving circuit layer 21 in this application is not limited to that illustrated in this embodiment.
  • the driving circuit layer 21 in this application may also include more or less film layers, and the positional relationship of each film layer is not limited to this embodiment.
  • a single gate structure may also be used in this application, and the single gate structure may also be located below the first semiconductor layer 22 to form a bottom gate structure.
  • the driving circuit layer 21 further includes a first electrode 261 located on the planarization layer 27 .
  • the first electrode 261 communicates with the source electrode 251 and the source electrode 251 through a via hole of the planarization layer 27 .
  • the drain electrode 252 is electrically connected.
  • the first electrode 261 and the source electrode 251 are electrically connected as an example.
  • the LED chip 30 is electrically connected to the first electrode 261 to realize the electrical connection between the LED chip and the driving circuit layer 21.
  • the driving circuit layer 21 is also connected to the corresponding first binding terminal. 10 is electrically connected, thereby achieving electrical connection between the first binding terminal 10 and the corresponding LED chip 30 .
  • the driving circuit layer 21 also includes a second electrode 262.
  • the second electrode 262 and the first electrode 261 are arranged in the same layer.
  • the LED chip 30 has a first pole 31 and a second pole 32.
  • the first pole 31 is electrically connected to the first electrode 261, and the second pole 32 is electrically connected to the second electrode 262. connect.
  • the first electrode 261 is an anode
  • the second electrode 262 is a cathode.
  • the application is not limited thereto.
  • the first electrode 261 of the application may also be a cathode.
  • the second electrode 262 can also be disposed on a side of the LED chip 30 away from the driving circuit layer 21 , when the first pole 31 and the second pole 32 of the LED chip 30 are located there. opposite sides of the LED chip 30 .
  • the driving circuit layer 21 may further include a pixel definition layer 28 covering the planarization layer 27 , and the pixel definition layer 28 is located at a position corresponding to the first electrode 261 An opening is provided at the position of the second electrode 262 , and the LED chip 30 can be placed in the opening and electrically connected to the driving circuit layer 21 .
  • the display component 2 further includes an encapsulation layer 29 covering the LED chip 30 and the pixel definition layer 28 .
  • FIG. 6 is another schematic cross-sectional structural diagram of a drive backplane provided in an embodiment of the present application.
  • the second backplane 12 includes a second substrate 121 and a driving function layer 80 and a second barrier layer 122 located on the side of the second substrate 121 close to the display component 2.
  • the second barrier layer 122 covers the driving function layer 80, the second binding terminal 40 is located on the second barrier layer 122, and the driving function layer 80 is connected to the corresponding second binding terminal. fixed terminal 40 and the third binding terminal 60.
  • the driving function layer 80 includes a plurality of driving transistors with a double-gate structure.
  • the driving function layer 80 includes a second semiconductor layer 81 formed on the second substrate 121, a third gate covering the second semiconductor layer 81 and the second substrate 121.
  • the fourth gate 83 formed on the fourth gate insulating layer 63, the second interlayer insulating layer 64 covering the fourth gate 83 and the fourth gate insulating layer 63,
  • a second source electrode 85 and a second drain electrode 84 are formed on the second interlayer insulating layer 64 .
  • the second barrier layer 122 covers the second source electrode 85 , the second drain electrode 84 and the second interlayer insulating layer 64 .
  • the third gate electrode 82 and the fourth gate electrode 83 are both arranged corresponding to the channel region of the second semiconductor layer 81 , and the second source electrode 85 and the second drain electrode 84 are electrically connected respectively.
  • the source region and the drain region of the second semiconductor layer 81 are electrically connected to the second binding terminal 40 through the via hole of the second barrier layer 122 .
  • the second drain 84 is electrically connected to the third binding terminal 60 through the first signal transfer line 86 , and the third binding terminal 60 is also connected to the driving element 50 through the first auxiliary conductive layer 1111 Electrical connection.
  • the driving function layer 80 may further include a driving transistor having a single gate structure.
  • the driving element 50 is disposed on a side of the first backplane 11 away from the second backplane 12 , and the driving signal from the driving element 50 passes through the third binding in turn.
  • the terminal 60, the first signal transfer line 86, the second drain electrode 84, the second semiconductor layer 81, the second source electrode 85, the second binding terminal 40 and the first binding The fixed terminal 10 is transmitted to the display substrate 20 to drive the LED chip 30 on the display substrate 20 to emit light.
  • the driving function layer 80 can also be used to make a GOA circuit, so that there is no need to provide a driving element 50 for driving the gate, which can save costs. Moreover, by fabricating the GOA circuit on the second backplane 12, the frame of the spliced display panel 100 can also be reduced.
  • the structure of the driving function layer 80 is not limited to the structure described above. Please refer to the above embodiment for other descriptions, which will not be described again here.
  • the embodiment of the present application also provides a splicing display panel splicing method. Please refer to FIGS. 1 to 7 in combination.
  • FIG. 7 is a schematic flow chart of the splicing display panel splicing method provided by the embodiment of the present application.
  • the splicing The method includes the following steps: S301: Provide a transfer substrate on which a plurality of LED chips 30 are arranged in an array; S302: Provide multiple display components 2, each of which includes a display substrate 20 and a plurality of first binding terminals 10 disposed on one side of the display substrate 20, and transfer the LEDs on the transfer substrate
  • the chip 30 is transferred to the other side of the display substrate 20 of each display component 2 in turn, so that the first binding terminal 10 is electrically connected to the corresponding LED chip 30;
  • the other side of the display substrate 20 refers to the side opposite to the first binding terminal 10 .
  • the first binding terminal 10 is located on one side of the display substrate 20 .
  • the LED chip 30 is located on the other side of the display substrate 20 , and the first binding terminal 10 and the LED chip 30 are located on opposite sides of the display substrate 20 .
  • the driving backplane 1 includes a stacked first backplane 11 and a second backplane 12.
  • the first backplane 11 is located away from the second backplane 12 and away from the display assembly. 2
  • a plurality of second binding terminals 40 are provided on the second back plate 12
  • a plurality of third binding terminals 60 are provided on the first back plate 11 and are connected with the third binding terminals 60.
  • the terminal 60 is electrically connected to the driving element 50, and the third binding terminal 60 is also electrically connected to the corresponding second binding terminal 40;
  • the LED chip 30 on the transfer substrate is first transferred to a single small-sized display component 2, and then multiple display components 2 are spliced to the driving backplane 1. This eliminates the need to use large-scale and large-volume transfers, and can improve the transfer yield.
  • FIG. 8 is a schematic cross-sectional structural diagram of a display device according to an embodiment of the present application.
  • the display device 1000 includes a housing 200 and a spliced display panel 100 of one of the above embodiments.
  • the housing 200 is formed with an accommodation cavity 201 , and the display panel 100 is disposed in the accommodation cavity 201 .
  • the present application provides a splicing display panel, a splicing method thereof, and a display device.
  • the splicing display panel includes a driving backplane and a plurality of display components arranged in an array on the driving backplane.
  • Each of the display components includes A display substrate, a plurality of first binding terminals provided on one side of the display substrate, and a plurality of LED chips provided on the other side of the display substrate.
  • the first binding terminals are electrically connected to the corresponding LED chips.
  • On the driving backplane There is a second binding terminal bound to the first binding terminal and a third binding terminal electrically connected to the driving element and the second binding terminal.
  • the driving element transmits the signal in sequence through the third binding terminal.
  • the frame of the component reduces or eliminates the splicing seams at the splicing joints after multiple display components are spliced, thus solving the problem of large splicing seams at the splicing joints of existing splicing screens.

Abstract

提供一种拼接显示面板及其拼接方法、显示装置。拼接显示面板（100）的驱动背板（1）上的驱动元件（50）与显示组件（2）上的LED芯片（30）电连接，以驱动LED芯片（30）发光，如此把驱动元件（50）设置在驱动背板（1）上，能够减小或消除每个显示组件（2）的边框，使得多个显示组件（2）拼接后拼接处的拼接缝减小或消除，从而解决了现有拼接屏的拼接处存在较大拼接缝的问题。

Description

拼接显示面板及其拼接方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种拼接显示面板及其拼接方法、显示装置。
 背景技术
拼接屏由多个显示屏拼接而成，这使其尺寸可以足够大，从而满足户外显示等领域对于大尺寸的需求。现有的拼接屏多采用印制电路板（Printed Circuit Board，PCB）基拼接，该拼接方法较为简单，但PCB基走线宽度、走线精度相比玻璃基差，很难满足高精度的拼接要求。
随着显示技术的更新迭代，小间距（pitch）、高分辨率的Mini‑LED或Micro‑LED显示产品逐渐推向市场。而为了满足高精度的拼接需求，对于应用Mini‑LED或Micro‑LED技术的拼接屏，需要采用玻璃基拼接。目前玻璃基拼接用的较多的是采用一组驱动IC对应一个拼接单元的方式，使得每个拼接单元均会有边框存在。而每个拼接单元边框的存在会导致拼接屏的拼接处存在较大的拼接缝，影响显示品味。
 技术问题
本申请提供一种拼接显示面板及其拼接方法、显示装置，以缓解现有拼接屏的拼接处存在较大拼接缝的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种拼接显示面板，其包括驱动背板以及阵列排布在所述驱动背板上的多个显示组件；
每个所述显示组件包括显示基板、设置所述显示基板一侧的多个第一绑定端子以及设置在所述显示基板另一侧的多个LED芯片，所述第一绑定端子与对应的所述LED芯片电连接；
所述驱动背板包括层叠设置的第一背板和第二背板，所述第一背板位于所述第二背板远离所述显示组件的一侧，所述第二背板上设置有多个第二绑定端子，所述第一背板上设置有多个第三绑定端子及与所述第三绑定端子电连接的驱动元件，所述第二绑定端子电连接于对应的所述第一绑定端子和对应的所述第三绑定端子。
在本申请实施例提供的拼接显示面板中，所述驱动元件阵列排布在所述第一背板远离所述第二背板的一侧。
在本申请实施例提供的拼接显示面板中，所述第一背板包括第一衬底以及位于所述第一衬底靠近所述第二背板一侧的第一阻挡层，所述第三绑定端子位于所述第一衬底上，且所述第一阻挡层在对应所述第三绑定端子的位置设置有缺口以暴露出所述第三绑定端子；所述第一衬底在对应所述第三绑定端子的位置设置有第一开孔，所述驱动元件通过所述第一开孔与所述第三绑定端子电连接。
在本申请实施例提供的拼接显示面板中，所述第一背板还包括第一辅助导电层，所述第一辅助导电层填充在所述第一开孔内，所述驱动元件通过所述第一辅助导电层与所述第三绑定端子电连接。
在本申请实施例提供的拼接显示面板中，所述第二背板包括第二衬底以及位于所述第二衬底靠近所述显示组件一侧的连接走线以及第二阻挡层，所述第二阻挡层覆于所述连接走线上，所述第二绑定端子位于所述第二阻挡层上，所述连接走线连接于对应的所述第二绑定端子和所述第三绑定端子。
在本申请实施例提供的拼接显示面板中，所述第二背板包括第二衬底以及位于所述第二衬底靠近所述显示组件一侧的驱动功能层以及第二阻挡层，所述第二阻挡层覆于所述驱动功能层上，所述第二绑定端子位于所述第二阻挡层上，所述驱动功能层连接于对应的所述第二绑定端子和所述第三绑定端子。
在本申请实施例提供的拼接显示面板中，所述显示基板包括：
衬底基板；
设置于所述衬底基板的远离所述驱动背板一侧的驱动电路层；所述驱动电路层与所述第一绑定端子电连接；
所述LED芯片位于所述驱动电路层远离所述衬底基板的一侧，并与所述驱动电路层电连接。
在本申请实施例提供的拼接显示面板中，所述衬底基板包括第三衬底以及位于所述第三衬底远离所述驱动电路层一侧的第三阻挡层，所述第一绑定端子位于所述第三阻挡层远离所述第三衬底的一侧，且所述第三阻挡层在对应所述第一绑定端子的位置设置有第二开孔，所述第一绑定端子位于所述第二开孔内。
在本申请实施例提供的拼接显示面板中，所述驱动电路层包括平坦化层以及设置在所述平坦化层远离所述衬底基板一侧的第一电极和第二电极；所述LED芯片具有第一极和第二极，所述第一极与所述第一电极电连接，所述第二极与所述第二电极电连接。
在本申请实施例提供的拼接显示面板中，所述驱动电路层还包括覆于所述平坦化层上的像素定义层，所述像素定义层在对应所述第一电极和所述第二电极的位置设置有开口，所述LED芯片设置在所述开口内。
本申请实施例还提供一种拼接显示面板拼接方法，其包括：
提供转移基板，所述转移基板上阵列排布有多个LED芯片；
提供多个显示组件，每个所述显示组件包括显示基板以及设置所述显示基板一侧的多个第一绑定端子，把所述转移基板上的所述LED芯片依次转移到每个所述显示组件的所述显示基板的另一侧，使所述第一绑定端子与对应的所述LED芯片电连接；
提供驱动背板，所述驱动背板包括层叠设置的第一背板和第二背板，所述第一背板位于所述第二背板远离所述显示组件的一侧，所述第二背板上设置有多个第二绑定端子，所述第一背板上设置有多个第三绑定端子及与所述第三绑定端子电连接的驱动元件，所述第三绑定端子还与对应的所述第二绑定端子电连接；
把多个所述显示组件拼接在所述驱动背板上，使每个所述第二绑定端子与对应的所述第一绑定端子电连接，以使所述驱动元件通过第三绑定端子将信号依次传输到所述第二绑定端子、所述第一绑定端子及所述LED芯片，以驱动所述LED芯片发光。
本申请实施例还提供一种显示装置，其包括：
壳体，形成有容纳腔；以及
如前述实施例其中之一的拼接显示面板，所述拼接显示面板设置在所述容纳腔内。
有益效果
本申请提供的拼接显示面板及其拼接方法、显示装置中，所述拼接显示面板包括驱动背板以及阵列排布在所述驱动背板上的多个显示组件，每个所述显示组件包括显示基板、设置在所述显示基板一侧的多个第一绑定端子以及设置在所述显示基板另一侧的多个LED芯片，所述第一绑定端子与对应的所述LED芯片电连接，所述驱动背板上设置有与第一绑定端子绑定的第二绑定端子以及电连接于驱动元件与所述第二绑定端子的第三绑定端子，所述驱动元件通过第三绑定端子将信号依次传输到所述第二绑定端子、所述第一绑定端子及所述LED芯片，以驱动所述LED芯片发光，如此把驱动元件设置在驱动背板上，能够减小或消除每个显示组件的边框，使得多个显示组件拼接后拼接处的拼接缝减小或消除，从而解决了现有拼接屏的拼接处存在较大拼接缝的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的拼接显示面板的一种俯视结构示意图。
图2为本申请实施例提供的拼接显示面板的一种剖面结构示意图。
图3为本申请实施例提供的驱动背板的一种剖面结构示意图。
图4为本申请实施例提供的驱动元件在第一背板上的排布示意图。
图5为本申请实施例提供的显示组件的一种剖面结构示意图。
图6为本申请实施例提供的驱动背板的另一种剖面结构示意图。
图7为本申请实施例提供的拼接显示面板拼接方法的流程示意图。
图8为本申请实施例提供的显示装置的一种剖面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请参照图1至图4，图1为本申请实施例提供的拼接显示面板的一种俯视结构示意图，图2为本申请实施例提供的拼接显示面板的一种剖面结构示意图，图3为本申请实施例提供的驱动背板的一种剖面结构示意图，图4为本申请实施例提供的驱动元件在第一背板上的排布示意图，图5为本申请实施例提供的显示组件的一种剖面结构示意图。所述拼接显示面板100包括显示区AA及位于所述显示区AA外侧的非显示区NA。所述拼接显示面板100还包括驱动背板1以及阵列排布在所述驱动背板1上的多个显示组件2。多个所述显示组件2位于所述显示区AA内，每个所述显示组件2包括显示基板20、设置在所述显示基板20一侧的多个第一绑定端子10以及设置在所述显示基板20另一侧的多个LED芯片30，所述第一绑定端子10与对应的所述LED芯片30电连接。所述LED芯片30包括Mini‑LED芯片或Micro‑LED芯片。其中所述显示基板20的一侧和所述显示基板20的另一侧是指所述显示基板20上相对的两侧。
所述驱动背板1上设置有多个第二绑定端子40及与所述第二绑定端子40电连接的驱动元件50，每个所述第二绑定端子40与对应的所述第一绑定端子10电连接，进而使所述显示基板20上的所述LED芯片30与所述驱动背板1上的驱动元件50电连接。所述驱动元件50通过所述第二绑定端子40将信号依次传输到所述第一绑定端子10及所述LED芯片30，以驱动所述显示基板20上的所述LED芯片30发光。
所述驱动元件50包括驱动集成电路（integrated circuit，IC）等驱动器件。所述驱动元件50设置在所述驱动背板1远离所述显示组件2的一侧。如此把驱动元件50设置在驱动背板1上，能够减小或消除每个显示组件2的边框，使得多个显示组件2拼接后拼接处的拼接缝减小或消除，从而解决了现有拼接屏的拼接处存在较大拼接缝的问题。
下面将具体阐述所述拼接显示面板100的所述显示组件2和所述驱动背板1的膜层结构：
参照图3，所述驱动背板1包括层叠设置的第一背板11和第二背板12，所述第一背板11位于所述第二背板12远离所述显示组件2的一侧，所述第二背板12上设置有多个第二绑定端子40，所述第一背板11上设置有多个第三绑定端子60及与所述第三绑定端子60电连接的驱动元件50，所述第二绑定端子40电连接于对应的所述第一绑定端子10和对应的所述第三绑定端子60。
具体而言，所述第一背板11包括第一衬底111以及位于所述第一衬底111靠近所述第二背板12一侧的第一阻挡层112，所述第三绑定端子60位于所述第一衬底111上，且所述第一阻挡层112在对应所述第三绑定端子60的位置设置有缺口以暴露出所述第三绑定端子60。所述第一衬底111在对应所述第三绑定端子60的位置设置有第一开孔1110，所述驱动元件50通过所述第一开孔1110与所述第三绑定端子60电连接。
进一步地，所述第一背板11还包括第一辅助导电层1111，所述第一辅助导电层1111填充在所述第一开孔1110内，所述驱动元件50通过所述第一辅助导电层1111与所述第三绑定端子60电连接。
可选地，所述第一辅助导电层1111的材料包括导电胶膜、导电胶黏剂、金属焊料、锡膏、液态金属等中的一种或多种，其中所述导电胶黏剂包括聚合物导电胶黏剂或掺杂导电粒子的导电胶黏剂。另外，所述第三绑定端子60可使用抗氧化性强且电阻率低的金属或合金或金属叠层结构、金属氧化物、导电氧化物等制备，如MO、AL等金属。
进一步地，所述第二背板12包括第二衬底121以及位于所述第二衬底121靠近所述显示组件2一侧的连接走线123以及第二阻挡层122，所述第二阻挡层122覆于所述连接走线123上，所述第二绑定端子40位于所述第二阻挡层122上，所述连接走线123连接于对应的所述第二绑定端子40和所述第三绑定端子60。
可选地，所述第二绑定端子40也可使用抗氧化性强且电阻率低的金属或合金或金属叠层结构、金属氧化物、导电氧化物等制备，如MO、AL等金属。
同时所述第二绑定端子40还电连接于对应的所述第一绑定端子10。如此，所述驱动元件50通过所述第三绑定端子60将信号依次传输到所述第二绑定端子40、所述第一绑定端子10及所述显示基板20，以驱动所述LED芯片发光。
可选地，所述第一阻挡层112、所述第二阻挡层122均可由氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料形成，以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一衬底111或所述第二衬底121扩散至可能因这些杂质或污染物而受损的器件中。而所述第一衬底111和所述第二衬底121的材料包括聚酰亚胺（Polyimide，PI）等柔性薄膜材料。
进一步地，所述驱动元件50阵列排布在所述第一背板11远离所述第二背板12的一侧，使所述驱动元件50均匀分布在所述第一背板11上，如图4所示。如此通过把所述驱动元件50设置在所述第一背板11上，能够减小或消除每个显示组件2的边框，使得多个显示组件2拼接后拼接处的拼接缝减小或消除。同时所述驱动元件50在所述第一背板11上等间距分布，并对应所述显示面板的显示区设置，能够避免驱动元件50集中放置于下边框或侧边框导致走线过长而引起的IR drop问题。
接着阐述所述显示组件2的具体结构：
参照图5，所述显示组件2包括显示基板20以及设置所述显示基板相对两侧的多个第一绑定端子10和多个LED芯片30。所述显示基板20包括衬底基板13以及设置在所述衬底基板13上的驱动电路层21，所述LED芯片30与所述驱动电路层21电连接，所述驱动电路层21用于驱动所述LED芯片30发光。所述第一绑定端子10可使用抗氧化性强且电阻率低的金属或合金或金属叠层结构、金属氧化物、导电氧化物等制备，如MO、AL等金属，以保证所述第一绑定端子10的稳定性以及与所述驱动背板1连接的可靠性。
可选地，所述衬底基板13包括层叠设置的第三阻挡层132、第三衬底131、第四阻挡层133以及缓冲层134。所述第一绑定端子10和所述第三阻挡层132均位于所述第三衬底131远离所述驱动电路层21的一侧，具体而言，所述第一绑定端子10设置在所述第三阻挡层132远离所述第三衬底131的一侧，所述第三阻挡层132在对应所述第一绑定端子10的位置设置有第二开孔1321，所述第一绑定端子10位于所述第二开孔1321内，且所述第二开孔1321暴露出所述第一绑定端子10。
所述第四阻挡层133和所述缓冲层134均位于所述第三衬底131靠近所述驱动电路层21的一侧，具体而言，所述第四阻挡层133覆于所述第三衬底131上，所述缓冲层134覆于所述第四阻挡层133上。
可选地，所述第三阻挡层132、所述第四阻挡层133以及所述缓冲层134均可由氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料形成，以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第三衬底131扩散至可能因这些杂质或污染物而受损的器件中。而所述第三衬底131的材料包括聚酰亚胺（Polyimide，PI）等柔性薄膜材料。同时所述缓冲层134还可以提供平坦的顶表面，以利于在所述缓冲层134上制备其他膜层结构。当然地，本申请的所述衬底基板13不限于此，本申请的所述衬底基板13可包括更多或更少的衬底膜层以及阻隔膜层。
所述驱动电路层21设置在所述缓冲层134上，所述驱动电路层21包括第一半导体层22、第一栅极23、第二栅极24、第一源极251、第一漏极252以及位于各层之间的绝缘层，具体而言，包括位于所述第一半导体层22与所述第一栅极23之间的第一栅极绝缘层17、位于所述第一栅极23与所述第二栅极24之间的第二栅极绝缘层18、位于所述第二栅极24与所述第一源极251之间的第一层间绝缘层19。
具体地，所述第一半导体层22设置于所述缓冲层134上，所述第一半导体层22包括沟道区以及位于所述沟道区相对两侧的源极区和漏极区。所述第一栅极绝缘层17覆于所述第一半导体层22及所述缓冲层134上。所述第一栅极23设置于所述第一栅极绝缘层17上，所述第一栅极23与所述第一半导体层22的沟道区对应设置。所述第二栅极绝缘层18覆于所述第一栅极23及所述第一栅极绝缘层17上。所述第二栅极24设置在所述第二栅极绝缘层18上，所述第二栅极24与所述第一栅极23对应设置。
所述第一层间绝缘层19覆于所述第二栅极24及所述第二栅极绝缘层18上。所述源极251和所述漏极252设置于所述第一层间绝缘层19上，所述源极251和所述漏极252分别与对应的所述第一半导体层22的源极区和漏极区电连接。需要说明的是，所述驱动电路层21还包括多个信号线，所述信号线包括数据线253、栅极扫描线等，其中所述数据线253与所述源极251和所述漏极252同层设置，所述栅极扫描线与所述第一栅极23或所述第二栅极24同层设置。但本申请不限于此，本申请的所述信号线还可包括VSS、VDD电源线以及其他用于显示或非显示的各种信号线，且不同的所述信号线与不同的所述第一绑定端子10电连接，以获取不同的信号。比如，所述数据线253与对应的所述第一绑定端子10电连接，以获取源极驱动信号并提供给所述源极251；所述栅极扫描线与对应的所述第一绑定端子10电连接，以获取栅极扫描信号并提供给所述第一栅极23。
本实施例以所述数据线253与所述第一绑定端子10电连接为例说明：
具体地，继续参照图5，所述第一层间绝缘层19图案化形成有深孔，所述深孔贯穿所述第一层间绝缘层19、所述第二栅极绝缘层18、所述第一栅极绝缘层17、所述缓冲层134、所述第四阻挡层133、所述第三衬底131、第三阻挡层132直至所述第一绑定端子10，以裸露出部分所述第一绑定端子10。所述数据线253通过所述深孔与所述第一绑定端子10电连接，同时所述数据线253还与所述源极251或所述漏极252电连接，即所述数据线253还与所述驱动电路层21电连接，以实现所述第一绑定端子10与所述驱动电路层21的电连接。本申请以所述数据线253与所述漏极252电连接为例说明。
需要说明的是，本申请中的“同层设置”是指在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征，则所述至少两个不同的特征同层设置。比如，本实施例的所述数据线253与所述源极251由同一导电膜层进行图案化处理后得到，则所述数据线253与所述源极251同层设置。
同时为了给所述驱动电路层21提供平坦的表面，所述驱动电路层21还包括覆于所述源极251、所述漏极252以及所述第一层间绝缘层19上的平坦化层27。当然地，本申请中驱动电路层21的结构不限于本实施例示意的，本申请的驱动电路层21还可包括更多或更少的膜层，且各膜层的位置关系也不限于本实施例示意的，比如本申请还可采用单栅结构，且所述单栅结构还可位于所述第一半导体层22的下方，形成底栅结构。
进一步地，所述驱动电路层21还包括位于所述平坦化层27上的第一电极261，所述第一电极261通过所述平坦化层27的过孔与所述源极251和所述漏极252电连接，本实施例以所述第一电极261与所述源极251电连接为例说明。所述LED芯片30与所述第一电极261电连接，以实现所述LED芯片与所述驱动电路层21的电连接，同时所述驱动电路层21还与对应的所述第一绑定端子10电连接，从而实现所述第一绑定端子10与对应的所述LED芯片30电连接。当然地，为了驱动所述LED芯片30发光，所述驱动电路层21还包括第二电极262，可选地，所述第二电极262与所述第一电极261同层设置。
具体而言，所述LED芯片30具有第一极31和第二极32，所述第一极31与所述第一电极261电连接，所述第二极32与所述第二电极262电连接。其中，所述第一电极261为阳极，所述第二电极262为阴极，但本申请不限于此，本申请的所述第一电极261也可为阴极，相应地，所述第二电极262为阳极。另外所述第二电极262还可设置在所述LED芯片30远离所述驱动电路层21的一侧，此时所述LED芯片30的所述第一极31和所述第二极32位于所述LED芯片30的相对两侧。
为了限定所述LED芯片30的绑定位置，所述驱动电路层21还可包括覆于所述平坦化层27上的像素定义层28，所述像素定义层28在对应所述第一电极261和所述第二电极262的位置设置有开口，所述LED芯片30可放置在所述开口内，并与所述驱动电路层21电连接。而为了提高所述LED芯片30的可靠性，避免水氧入侵导致LED芯片30失效，所述显示组件2还包括覆于所述LED芯片30以及所述像素定义层28上的封装层29。
在一种实施例中，请结合参照图1至图6，图6为本申请实施例提供的驱动背板的另一种剖面结构示意图。与上述实施例不同的是，所述第二背板12包括第二衬底121以及位于所述第二衬底121靠近所述显示组件2一侧的驱动功能层80以及第二阻挡层122，所述第二阻挡层122覆于所述驱动功能层80上，所述第二绑定端子40位于所述第二阻挡层122上，所述驱动功能层80连接于对应的所述第二绑定端子40和所述第三绑定端子60。
具体地，所述驱动功能层80包括多个具有双栅结构的驱动晶体管。具体地，所述驱动功能层80包括形成在所述第二衬底121上的第二半导体层81、覆于所述第二半导体层81以及所述第二衬底121上的第三栅极绝缘层62、形成在所述第三栅极绝缘层62上的第三栅极82、覆于所述第三栅极82以及所述第三栅极绝缘层62上的第四栅极绝缘层63、形成在所述第四栅极绝缘层63上的第四栅极83、覆于所述第四栅极83以及所述第四栅极绝缘层63上的第二层间绝缘层64、形成在所述第二层间绝缘层64上的第二源极85和第二漏极84。所述第二阻挡层122覆于所述第二源极85和所述第二漏极84以及所述第二层间绝缘层64上。
其中，所述第三栅极82和所述第四栅极83均对应所述第二半导体层81的沟道区设置，所述第二源极85和所述第二漏极84分别电连接所述第二半导体层81的源极区和漏极区。所述第二绑定端子40通过所述第二阻挡层122的过孔电连接所述第二源极85。所述第二漏极84通过第一信号转接线86与所述第三绑定端子60电连接，所述第三绑定端子60还通过所述第一辅助导电层1111与所述驱动元件50电连接。
在其他实施例中，所述驱动功能层80还可以包括具有单栅结构的驱动晶体管。
在本实施例中，所述驱动元件50设置在所述第一背板11远离所述第二背板12的一侧，来自于所述驱动元件50的驱动信号依次通过所述第三绑定端子60、所述第一信号转接线86、所述第二漏极84、所述第二半导体层81、所述第二源极85、所述第二绑定端子40及所述第一绑定端子10传输至所述显示基板20内，以驱动显示基板20上的LED芯片30发光。
在一种实施例中，所述驱动功能层80还可用于制作GOA电路，从而无需设置用于驱动栅极的驱动元件50，可节约成本。而且把GOA电路制作在所述第二背板12上，还能够减小所述拼接显示面板100的边框。
在其他实施例中，所述驱动功能层80的结构并不局限于如上所述的结构。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，本申请实施例还提供一种拼接显示面板拼接方法，请结合参照图1至图7，图7为本申请实施例提供的拼接显示面板拼接方法的流程示意图，该拼接方法包括以下步骤：
S301：提供转移基板，所述转移基板上阵列排布有多个LED芯片30；
S302：提供多个显示组件2，每个所述显示组件2包括显示基板20以及设置在所述显示基板20一侧的多个第一绑定端子10，把所述转移基板上的所述LED芯片30依次转移到每个所述显示组件2的所述显示基板20的另一侧，使所述第一绑定端子10与对应的所述LED芯片30电连接；
其中所述显示基板20的另一侧是指与所述第一绑定端子10相对的一侧，具体而言，所述第一绑定端子10位于所述显示基板20的一侧，所述LED芯片30位于所述显示基板20的另一侧，所述第一绑定端子10和所述LED芯片30位于所述显示基板20的相对两侧。
S303：提供驱动背板1，所述驱动背板1包括层叠设置的第一背板11和第二背板12，所述第一背板11位于所述第二背板12远离所述显示组件2的一侧，所述第二背板12上设置有多个第二绑定端子40，所述第一背板11上设置有多个第三绑定端子60及与所述第三绑定端子60电连接的驱动元件50，所述第三绑定端子60还与对应的所述第二绑定端子40电连接；
S304：把多个所述显示组件2拼接在所述驱动背板1上，使每个所述第二绑定端子40与对应的所述第一绑定端子10电连接，以使所述驱动元件50通过第三绑定端子60将信号依次传输到所述第二绑定端子40、所述第一绑定端子10及所述LED芯片30，以驱动所述LED芯片30发光。
可以理解的是，在LED芯片30转移制程中，通常采用巨量转移技术，而巨量转移技术受限于单次转移面积，对于大尺寸拼接显示需要多次转移以完成整个转移制程，但多次转移会存在偏位累积导致良率较低的问题。而在本实施例中，通过先把转移基板上的LED芯片30转移到单个小尺寸的所述显示组件2上，然后再把多个所述显示组件2拼接到所述驱动背板1上。如此无需采用大尺寸巨量转移，能够提高转移的良率。
在一种实施例中，请参照图8，图8为本申请实施例提供的显示装置的剖面结构示意图。所述显示装置1000包括壳体200和上述实施例其中之一的拼接显示面板100，所述壳体200形成有容纳腔201，所述显示面板100设置在所述容纳腔201内。
根据上述实施例可知：
本申请提供一种拼接显示面板及其拼接方法、显示装置中，所述拼接显示面板包括驱动背板以及阵列排布在所述驱动背板上的多个显示组件，每个所述显示组件包括显示基板、设置在显示基板一侧的多个第一绑定端子以及设置在显示基板另一侧的多个LED芯片，第一绑定端子与对应的LED芯片电连接，所述驱动背板上设置有与第一绑定端子绑定的第二绑定端子以及电连接于驱动元件与所述第二绑定端子的第三绑定端子，所述驱动元件通过第三绑定端子将信号依次传输到所述第二绑定端子、所述第一绑定端子及所述LED芯片，以驱动所述LED芯片发光，如此把驱动元件设置在驱动背板上，能够减小或消除每个显示组件的边框，使得多个显示组件拼接后拼接处的拼接缝减小或消除，从而解决了现有拼接屏的拼接处存在较大拼接缝的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种拼接显示面板，其包括驱动背板以及阵列排布在所述驱动背板上的多个显示组件；
    所述显示组件包括显示基板、设置在所述显示基板一侧的多个第一绑定端子以及设置在所述显示基板另一侧的多个LED芯片，所述第一绑定端子与对应的所述LED芯片电连接；
    所述驱动背板包括层叠设置的第一背板和第二背板，所述第一背板位于所述第二背板远离所述显示组件的一侧，所述第二背板上设置有多个第二绑定端子，所述第一背板上设置有多个第三绑定端子及与所述第三绑定端子电连接的驱动元件，所述第二绑定端子电连接于对应的所述第一绑定端子和对应的所述第三绑定端子。
  2. 如权利要求1所述的拼接显示面板，其中，所述驱动元件阵列排布在所述第一背板远离所述第二背板的一侧。
  3. 如权利要求2所述的拼接显示面板，其中，所述第一背板包括第一衬底以及位于所述第一衬底靠近所述第二背板一侧的第一阻挡层，所述第三绑定端子位于所述第一衬底上，且所述第一阻挡层在对应所述第三绑定端子的位置设置有缺口以暴露出所述第三绑定端子；所述第一衬底在对应所述第三绑定端子的位置设置有第一开孔，所述驱动元件通过所述第一开孔与所述第三绑定端子电连接。
  4. 如权利要求3所述的拼接显示面板，其中，所述第一背板还包括第一辅助导电层，所述第一辅助导电层填充在所述第一开孔内，所述驱动元件通过所述第一辅助导电层与所述第三绑定端子电连接。
  5. 如权利要求3所述的拼接显示面板，其中，所述第二背板包括第二衬底以及位于所述第二衬底靠近所述显示组件一侧的连接走线以及第二阻挡层，所述第二阻挡层覆于所述连接走线上，所述第二绑定端子位于所述第二阻挡层上，所述连接走线连接于对应的所述第二绑定端子和所述第三绑定端子。
  6. 如权利要求3所述的拼接显示面板，其中，所述第二背板包括第二衬底以及位于所述第二衬底靠近所述显示组件一侧的驱动功能层以及第二阻挡层，所述第二阻挡层覆于所述驱动功能层上，所述第二绑定端子位于所述第二阻挡层上，所述驱动功能层连接于对应的所述第二绑定端子和所述第三绑定端子。
  7. 如权利要求1所述的拼接显示面板，其中，所述显示基板包括：
    衬底基板；
    设置于所述衬底基板的远离所述驱动背板一侧的驱动电路层；所述驱动电路层与所述第一绑定端子电连接；
    所述LED芯片位于所述驱动电路层远离所述衬底基板的一侧，并与所述驱动电路层电连接。
  8. 如权利要求7所述的拼接显示面板，其中，所述衬底基板包括第三衬底以及位于所述第三衬底远离所述驱动电路层一侧的第三阻挡层，所述第一绑定端子位于所述第三阻挡层远离所述第三衬底的一侧，且所述第三阻挡层在对应所述第一绑定端子的位置设置有第二开孔，所述第一绑定端子位于所述第二开孔内。
  9. 如权利要求7所述的拼接显示面板，其中，所述驱动电路层包括平坦化层以及设置在所述平坦化层远离所述衬底基板一侧的第一电极和第二电极；所述LED芯片具有第一极和第二极，所述第一极与所述第一电极电连接，所述第二极与所述第二电极电连接。
  10. 如权利要求9所述的拼接显示面板，其中，所述驱动电路层还包括覆于所述平坦化层上的像素定义层，所述像素定义层在对应所述第一电极和所述第二电极的位置设置有开口，所述LED芯片设置在所述开口内。
  11. 一种拼接显示面板拼接方法，其包括：
    提供转移基板，所述转移基板上阵列排布有多个LED芯片；
    提供多个显示组件，每个所述显示组件包括显示基板以及设置所述显示基板一侧的多个第一绑定端子，把所述转移基板上的所述LED芯片依次转移到每个所述显示组件的所述显示基板的另一侧，使所述第一绑定端子与对应的所述LED芯片电连接；
    提供驱动背板，所述驱动背板包括层叠设置的第一背板和第二背板，所述第一背板位于所述第二背板远离所述显示组件的一侧，所述第二背板上设置有多个第二绑定端子，所述第一背板上设置有多个第三绑定端子及与所述第三绑定端子电连接的驱动元件，所述第三绑定端子还与对应的所述第二绑定端子电连接；
    把多个所述显示组件拼接在所述驱动背板上，使每个所述第二绑定端子与对应的所述第一绑定端子电连接，以使所述驱动元件通过第三绑定端子将信号依次传输到所述第二绑定端子、所述第一绑定端子及所述LED芯片，以驱动所述LED芯片发光。
  12. 一种显示装置，其包括：
    壳体，形成有容纳腔；以及
    拼接显示面板，所述拼接显示面板设置在所述容纳腔内，所述拼接显示面板包括驱动背板以及阵列排布在所述驱动背板上的多个显示组件；
    所述显示组件包括显示基板、设置在所述显示基板一侧的多个第一绑定端子以及设置在所述显示基板另一侧的多个LED芯片，所述第一绑定端子与对应的所述LED芯片电连接；
    所述驱动背板包括层叠设置的第一背板和第二背板，所述第一背板位于所述第二背板远离所述显示组件的一侧，所述第二背板上设置有多个第二绑定端子，所述第一背板上设置有多个第三绑定端子及与所述第三绑定端子电连接的驱动元件，所述第二绑定端子电连接于对应的所述第一绑定端子和对应的所述第三绑定端子。
  13. 如权利要求12所述的显示装置，其中，所述驱动元件阵列排布在所述第一背板远离所述第二背板的一侧。
  14. 如权利要求13所述的显示装置，其中，所述第一背板包括第一衬底以及位于所述第一衬底靠近所述第二背板一侧的第一阻挡层，所述第三绑定端子位于所述第一衬底上，且所述第一阻挡层在对应所述第三绑定端子的位置设置有缺口以暴露出所述第三绑定端子；所述第一衬底在对应所述第三绑定端子的位置设置有第一开孔，所述驱动元件通过所述第一开孔与所述第三绑定端子电连接。
  15. 如权利要求14所述的显示装置，其中，所述第一背板还包括第一辅助导电层，所述第一辅助导电层填充在所述第一开孔内，所述驱动元件通过所述第一辅助导电层与所述第三绑定端子电连接。
  16. 如权利要求14所述的显示装置，其中，所述第二背板包括第二衬底以及位于所述第二衬底靠近所述显示组件一侧的连接走线以及第二阻挡层，所述第二阻挡层覆于所述连接走线上，所述第二绑定端子位于所述第二阻挡层上，所述连接走线连接于对应的所述第二绑定端子和所述第三绑定端子。
  17. 如权利要求14所述的显示装置，其中，所述第二背板包括第二衬底以及位于所述第二衬底靠近所述显示组件一侧的驱动功能层以及第二阻挡层，所述第二阻挡层覆于所述驱动功能层上，所述第二绑定端子位于所述第二阻挡层上，所述驱动功能层连接于对应的所述第二绑定端子和所述第三绑定端子。
  18. 如权利要求12所述的显示装置，其中，所述显示基板包括：
    衬底基板；
    设置于所述衬底基板的远离所述驱动背板一侧的驱动电路层；所述驱动电路层与所述第一绑定端子电连接；
    所述LED芯片位于所述驱动电路层远离所述衬底基板的一侧，并与所述驱动电路层电连接。
  19. 如权利要求18所述的显示装置，其中，所述衬底基板包括第三衬底以及位于所述第三衬底远离所述驱动电路层一侧的第三阻挡层，所述第一绑定端子位于所述第三衬底上，所述第三阻挡层覆于所述第一绑定端子上，且所述第三阻挡层在对应所述第一绑定端子的位置设置有第二开孔，所述第二开孔暴露出所述第一绑定端子。
  20. 如权利要求18所述的显示装置，其中，所述驱动电路层包括平坦化层以及设置在所述平坦化层远离所述衬底基板一侧的第一电极和第二电极；所述LED芯片具有第一极和第二极，所述第一极与所述第一电极电连接，所述第二极与所述第二电极电连接。
PCT/CN2023/074880 2022-08-22 2023-02-08 拼接显示面板及其拼接方法、显示装置 WO2024040877A1 (zh)

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