WO2020253734A1 - 显示基板及其制作方法、显示面板、显示装置 - Google Patents

显示基板及其制作方法、显示面板、显示装置 Download PDF

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Publication number
WO2020253734A1
WO2020253734A1 PCT/CN2020/096616 CN2020096616W WO2020253734A1 WO 2020253734 A1 WO2020253734 A1 WO 2020253734A1 CN 2020096616 W CN2020096616 W CN 2020096616W WO 2020253734 A1 WO2020253734 A1 WO 2020253734A1
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Prior art keywords
base substrate
signal line
electrically connected
electrode
forming
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PCT/CN2020/096616
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English (en)
French (fr)
Inventor
姚琪
柳在一
刘英伟
狄沐昕
顾仁权
梁志伟
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京东方科技集团股份有限公司
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Priority to US17/264,925 priority Critical patent/US20210327995A1/en
Publication of WO2020253734A1 publication Critical patent/WO2020253734A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, a display panel, and a display device.
  • the embodiment of the present disclosure provides a display substrate having a display area and a frame area surrounding the display area, wherein the display substrate includes:
  • the base substrate includes a first surface and a second surface disposed oppositely;
  • the driving circuit is located on a side of the first surface of the base substrate and is arrayed in the display area;
  • Binding electrodes located on the side of the second surface of the base substrate and distributed in the display area
  • the signal line is located in the display area, one end of the signal line is electrically connected to the binding electrode, and the other end is electrically connected to the drive circuit;
  • the conductive structure is filled in at least the through hole penetrating the base substrate, and the conductive structure is configured to conduct the signal line, the driving circuit and the binding electrode.
  • the display substrate provided by the embodiment of the present disclosure, it further includes: a connecting electrode located on a side of the first surface of the base substrate and electrically connected to the driving circuit;
  • the signal line includes a first type signal line, and the first type signal line is located on a side of the second surface of the base substrate and is electrically connected to the bonding electrode;
  • the through hole is located in an overlapping area between the first type signal line and the connection electrode, and the first type signal line and the connection electrode are electrically connected through the conductive structure.
  • the signal line includes a second type signal line, and the second type signal line is located on the side of the first surface of the base substrate and is connected to the The drive circuit is electrically connected;
  • the through hole is located in an overlapping area between the second type signal line and the binding electrode, and the second type signal line and the binding electrode are electrically connected through the conductive structure.
  • the first type signal line is a data line
  • the bonding electrode is a data line bonding electrode
  • the connecting electrode is electrically connected to the driving circuit.
  • the first type of signal line is a scan line
  • the bonding electrode is a scan line bonding electrode
  • the connecting electrode is electrically connected to the gate of the thin film transistor in the driving circuit.
  • the second type signal line is a data line
  • the bonding electrode is a data line bonding electrode
  • the data line is electrically connected to the driving circuit The source of the thin film transistor; and/or,
  • the second type of signal line is a scan line
  • the bonding electrode is a scan line bonding electrode
  • the scan line is electrically connected to the gate of the thin film transistor in the driving circuit.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes: a scan driving circuit located on a side of the second surface of the base substrate and electrically connected to the scan line binding electrode.
  • the display substrate provided by the embodiment of the present disclosure, it further includes: an electroluminescent device located on a side of the first surface of the base substrate and electrically connected to the driving circuit.
  • the base substrate is a flexible base substrate.
  • an embodiment of the present disclosure also provides a method for manufacturing the above-mentioned display substrate, including:
  • a signal line is formed in the display area, one end of the signal line is electrically connected to the binding electrode, and the other end is electrically connected to the driving circuit, and the conductive structure is configured to conduct the signal line and drive Circuit and binding electrodes.
  • forming a through hole at least penetrating the base substrate from the second surface side of the base substrate specifically includes:
  • the hard mask layer is removed.
  • forming a conductive structure in the through hole specifically includes:
  • Metal filling is performed in the through hole by an electroplating process to form the conductive structure.
  • the material of the seed layer is titanium, molybdenum, tantalum, aluminum, copper, silver metal simple substance or molybdenum alloy, copper alloy, aluminum alloy.
  • forming a signal line in the display area specifically includes:
  • a first-type signal line electrically connected to the bonding electrode is formed in the display area on the second surface side of the base substrate.
  • the first-type signal line when the first-type signal line includes both data lines and scan lines, they are formed in the display area of the second surface of the base substrate and
  • the first type of signal line that is electrically connected to the binding electrode includes:
  • forming a signal line in the display area specifically includes:
  • a second type signal line electrically connected to the driving circuit is formed in the display area on the first surface side of the base substrate.
  • the embodiments of the present disclosure also provide another method for manufacturing the above-mentioned display substrate, including:
  • a signal line is formed in the display area, one end of the signal line is electrically connected to the binding electrode, and the other end is electrically connected to the driving circuit, and the conductive structure is configured to conduct the signal line and drive Circuits and binding electrodes;
  • the rigid substrate and the buffer sacrificial layer are removed.
  • an embodiment of the present disclosure also provides a display panel, including the above-mentioned display substrate, and a driving circuit connected to at least part of the bound electrodes.
  • an embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • 4A to 4F are respectively schematic diagrams of a manufacturing process of a display substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a flowchart of another method for manufacturing a display substrate according to an embodiment of the disclosure.
  • scan lines and data lines are provided on display substrates such as organic electroluminescence display panels (OLED).
  • GOA and integrated circuit (IC) are electrically connected to the scan lines and data lines in the frame area, respectively.
  • the scan lines and data lines need to be provided with leads at the edge of the display substrate to be connected to the GOA and the integrated circuit in the frame area. This requires a certain width of the frame at the edge of the display substrate, so that the display device cannot achieve a narrow frame or no frame.
  • the frame design is not conducive to achieving a full screen.
  • the present disclosure provides a display substrate having a display area and a frame area surrounding the display area. In FIGS. 1 and 2, only a part of the structure of the display area is shown.
  • the display substrate includes:
  • the base substrate 1 includes a first surface A and a second surface B that are arranged oppositely;
  • the driving circuit 2 is located on the side of the first surface A of the base substrate 1 and the array is distributed in the display area; specifically, the driving circuit 2 generally includes one or more thin film transistors, and one thin film transistor is shown in FIGS. 1 and 2 Take an example to illustrate;
  • the binding electrode 3 is located on the side of the second surface B of the base substrate 1 and distributed in the display area;
  • the signal line 4 is located in the display area, one end of the signal line is electrically connected to the binding electrode 3, and the other end is electrically connected to the driving circuit 2;
  • the conductive structure 5 is filled in at least the through hole penetrating the base substrate 1, and the conductive structure 5 is configured to conduct the signal line 4, the driving circuit 2 and the binding electrode 3.
  • the bonding electrode 3 since the bonding electrode 3 is disposed on the side of the base substrate 1 away from the driving circuit 2, it can be disposed in the display area without affecting the front surface of the display substrate (ie The normal display of the first surface A).
  • Drive components such as integrated circuits or GOA can be electrically connected to the bonding electrode 3 on the side of the base substrate 1 away from the drive circuit 2 and are arranged in the display area. Therefore, the edge of the display substrate does not need to be reserved for the drive circuit. The width of the frame, and then realize the narrow frame or no frame design.
  • the location of the signal line 4 may be located on the side of the first surface A of the base substrate 1 or on the side of the second surface B of the base substrate 1.
  • the signal line 4 may include any signal line that needs to be connected to the drive circuit or GOA and other drive components, such as data lines, scan lines, and other signal lines. According to the different signals that the signal line 4 needs to transmit, it is designed to be different from those in the drive circuit 2. The connection relationship between the corresponding parts. A detailed introduction will be given below through specific embodiments.
  • the signal line 4 when the signal line 4 is located on the second surface B of the base substrate 1 and is electrically connected to the bonding electrode 3, the signal line 4 and the correspondingly connected bonding electrode 3 may be in the same film layer
  • the graphics can also be made in different layers, which is not limited here.
  • this type of signal line 4 can be referred to as a first type signal line 41.
  • the bonding electrode 3 since the bonding electrode 3 is generally designed in a concentrated manner to facilitate the pin connection of the driving circuit that needs to be bonded, a lead can be provided between the first type signal line 41 and the bonding electrode 3 connected to it. It is convenient to connect the two, and each lead connected to each first type signal line 41 can form a fan-out area similar in shape to a fan.
  • a connecting electrode 6 electrically connected to the driving circuit 2 can also be provided on the side of the first surface A of the base substrate 1.
  • the connecting electrode 6 and the first-type signal line 41 have an overlapping area, and a through hole penetrating the base substrate 1 is provided in the overlapping area, so that the first-type signal line 41 and the connecting electrode 6 can be electrically connected through the conductive structure 5.
  • each drive circuit 2 provided on the side of the first surface A of the base substrate 1 can be electrically connected to the first type signal line 41 through the conductive structure 5, it is necessary to provide a one-to-one correspondence with each drive circuit 2
  • the number of through holes and the number of connection electrodes 6. Specifically, the connecting electrode 6 and the corresponding components to be connected in the driving circuit 2 can be patterned in the same film layer.
  • the bonding electrode 3 can be considered to be used for bonding with a driver IC (Driver IC).
  • the data line is bound to the electrode 31, and the connecting electrode 6 is generally electrically connected to the source 23 of a thin film transistor in the driving circuit 2.
  • a connecting electrode 6 electrically connected to the source electrode 23 and a conductive structure 5 electrically connected to the connecting electrode 6 need to be provided.
  • connection electrode 6 a part of the extended source electrode 23 can be used as the connection electrode 6, or a connection electrode 6 can be provided on a certain film layer (such as a gate metal layer) between the film layer where the source electrode 23 is located and the base substrate 1. Not limited. In FIG. 1, the connection electrode 6 and the source electrode 23 are formed in the same film layer as an example for illustration.
  • the bonding electrode 3 can be considered as a scan line bonding for connecting with GOA
  • the electrode 32 and the connecting electrode 6 are generally electrically connected to the gate 22 of a thin film transistor in the driving circuit 2.
  • a connecting electrode 6 electrically connected to the gate 22 and a conductive structure 5 electrically connected to the connecting electrode 6 need to be provided.
  • a part of the gate electrode 22 may be used as the connecting electrode 6, or a connecting electrode 6 may be provided on a film layer (such as a light-shielding layer) between the film layer where the gate electrode 22 is located and the base substrate 1. limited.
  • the connection electrode 6 and the gate electrode 22 are formed in the same film as an example for illustration.
  • the data line and the scan line can be designed with the first-type signal line 41 at the same time. Since the extension directions of the data lines and scan lines cross each other, it is necessary to arrange the data lines and scan lines in different layers on the side of the second surface B of the base substrate 1, for example, as shown in FIG. An insulating layer 7 is provided between the first-type signal line 41 and the first-type signal line 41 as a scanning line.
  • the signal line 4 when the signal line 4 is located on the first surface A of the base substrate 1 and is electrically connected to the drive circuit 2, the signal line 4 and the corresponding connected components of the drive circuit 2 can be in the same film layer
  • the graphics can also be made in different layers, which is not limited here.
  • this type of signal line 4 may be referred to as a first type signal line 42.
  • the bonding electrode 3 since the bonding electrode 3 is generally designed in a concentrated manner to facilitate the pin connection of the driving circuit to be bonded, a lead can be provided between the second-type signal line 42 and the bonding electrode 3 connected to it. It is convenient to connect the two, and each lead connected to each second type signal line 42 can form a fan-out area similar in shape to a fan.
  • the lead wires can be patterned in the same film layer as the second type signal line 42, or patterns can be made in the same film layer as the bonding electrode 3, which is not limited here.
  • each drive circuit 2 of one row or one column can be electrically connected to the same second-type signal line 42, and then a through substrate is provided in the overlapping area between the second-type signal line 42 and the bonding electrode 3
  • the through holes of the substrate 1 can electrically connect the second type signal line 42 and the binding electrode 3 through the conductive structure 5.
  • the bonding electrode 3 is a data line bonding electrode 31, and one data line is electrically connected to the source electrode 23 of the thin film transistor in each driving circuit 2 in one column.
  • the bonding electrode 3 is a scan line bonding electrode 32, and one scan line is electrically connected to the gate 22 of the thin film transistor in each driving circuit 2 of a row.
  • the base substrate 1 can be provided with through holes corresponding to the second type signal lines 42 one-to-one.
  • multiple second type signal lines 42 are connected to one bonding electrode 3 through one through hole at the same time, and one The second type of signal line 42 is connected to one bonding electrode 3 through multiple through holes at the same time.
  • the thin film transistor in the driving circuit 2 may be a bottom gate thin film transistor as shown in FIG. 2 or a top gate thin film transistor as shown in FIG. 1.
  • a top-gate thin film transistor, as shown in FIG. 1 generally includes a gate 22, a gate insulating layer 25, an active layer 21, a source 23, and a drain 24 on a base substrate 1.
  • a bottom-gate thin film transistor, as shown in FIG. 2 generally includes an active layer 21, a gate insulating layer 25, a gate 22, an interlayer insulating layer 26, a source 23 and a drain 24 on the base substrate 1.
  • the source 23 of the thin film transistor in each drive circuit 2 in a column is used to receive the data signal provided by the same data line
  • the gate 22 of the thin film transistor in each drive circuit 2 in a row is used to receive the data signal provided by the same scan line.
  • the drain 24 of the thin film transistor is generally electrically connected to the anode 8 (or pixel electrode).
  • a buffer layer 9 can be provided between the driver circuit 2 and the base substrate 1, a flat layer 10 can be provided between the driver circuit 2 and the anode 8, and a pixel defining layer 11 can be provided on the anode 8 so that the base substrate 1
  • An electroluminescent device electrically connected to the drive circuit 2 is provided on the side of the first surface A, and specifically, the electroluminescent display panel is electrically connected to the anode 8.
  • a micro LED can also be used to bind on the anode 8.
  • the scan line binding electrode 32 when the scan line binding electrode 32 is provided on the side of the second surface B of the base substrate 1, it may be on the side of the second surface B of the base substrate 2.
  • the scan driving circuit electrically connected to the scan line binding electrode 32 is directly fabricated, that is, a GOA circuit.
  • the base substrate 1 may be a flexible base substrate.
  • the present disclosure also provides a method for manufacturing the above-mentioned display substrate, as shown in FIG. 3, the specific steps are as follows:
  • S203 Reverse the base substrate, and form a through hole at least penetrating the base substrate from the second surface side of the base substrate;
  • a signal line is formed in the display area. One end of the signal line is electrically connected to the binding electrode, and the other end is electrically connected to the driving circuit.
  • the conductive structure is configured to conduct the signal line, the driving circuit and the binding electrode.
  • the conductive structure is then fabricated with binding electrodes on the second surface side of the base substrate.
  • the binding electrodes can be arranged in the display area without affecting the normal display on the front surface (ie, the first surface) of the display substrate.
  • Driving components such as integrated circuits or GOA can be electrically connected to the bonding electrode on the side of the second surface of the base substrate and are arranged in the display area. Therefore, the edge of the display substrate does not need to reserve a certain width of frame for the driving circuit , And then realize narrow frame or frameless design.
  • the selected signal line type it is possible to determine in which specific process step the above step S206 is performed to form the signal line in the display area. For example, when the first type of signal line is selected, after the conductive structure is formed in the through hole in step S204, the first type of signal electrically connected to the bonding electrode may be formed in the display area on the second surface side of the base substrate. It is possible to perform step 206 while performing step S205 to form a binding electrode on the second surface side of the base substrate.
  • the second type of signal line that is electrically connected to the driving circuit can be formed in the display area on the side of the first surface of the base substrate before the base substrate is reversed in step S203 , And step 206 may be performed while performing step S202 to form drive circuits distributed in an array in the display area on the first surface side of the base substrate.
  • step S202 when part of the first type of signal line is selected and part of the second type of signal line is selected, for example, when the first type of signal line is selected as the data line and the second type of signal line is used as the scan line, it is possible to perform step S202 simultaneously. The production of the second type of scan line is realized, and when step S205 is executed, the production of the first type of scan line is realized.
  • the first type of signal line includes data lines and scan lines at the same time, since the extension directions of the data lines and scan lines cross each other, they cannot be fabricated on the same film layer. Therefore, they are in the display area on the second surface of the base substrate.
  • Forming the first type of signal lines electrically connected to the bonding electrode may be provided with through holes corresponding to the data lines and through holes corresponding to the scan lines, which may specifically include:
  • the data line is formed in the display area on the second surface side of the base substrate;
  • an insulating layer is formed on the film layer where the data line is located;
  • step S201 may specifically include: as shown in FIG. 4A, forming a base substrate 1 on the first rigid substrate 01.
  • the thin film transistor of the driving circuit 2 may include a gate electrode 22, a gate insulating layer 25, an active layer 21, an interlayer insulating layer 26, a source electrode 23, and a drain electrode 24 which are sequentially stacked.
  • a buffer layer 2 may also be provided between the thin film transistor and the base substrate 1.
  • a flat layer 10, an anode 8 and a pixel defining layer 11, and an electroluminescent device can also be fabricated on the thin film transistor, and the electroluminescent device can also be packaged.
  • the base substrate 1 is reversed, and the second rigid substrate 02 is bonded to the second rigid substrate 02 from the first surface A side of the base substrate 1 through the bonding material 12, wherein a vacuum bonding equipment is used for bonding
  • the bonding material 12 can be a thermosetting glue.
  • the first rigid substrate 01 is removed.
  • a through hole penetrating through the base substrate 1 is formed from the second surface B side of the base substrate 1, and a conductive structure 5 is formed in the through hole, and the through hole extends to the connection electrode connected to the source 23 At six places, specifically, the through hole penetrates the base substrate 1, the buffer layer 9, and the gate insulating layer 25.
  • a second type signal line 41 as a data line and a data line binding electrode 31 connected thereto are formed.
  • an insulating layer 7 is formed on the second surface B side of the base substrate 1.
  • a through hole penetrating through the base substrate 1 is formed from the second surface B side of the base substrate 1 and a conductive structure 5 is formed in the through hole, and the through hole extends to the connection electrode connected to the gate 22 At 6 locations, specifically, the through holes penetrate the base substrate 1 and the buffer layer 9.
  • second-type signal lines 42 are formed on the side of the second surface B of the base substrate 1 as scan lines, scan line binding electrodes 32 connected thereto, and GOA.
  • the bonding material 12 and the second rigid substrate 02 are removed. Since the bonding material 12 is a thermal curing adhesive, the thermal curing adhesive achieves a decrease in viscosity at 200-300° C., which can separate the display substrate from the second rigid substrate B. Finally, the driving circuit (IC device) is bound to the data line binding electrode 31, and the back film is attached to the second surface B side.
  • the above-mentioned step S203 forms a through hole at least penetrating the base substrate from the second surface side of the base substrate.
  • the specific steps may be:
  • a patterned hard mask layer is formed on the second surface side of the base substrate
  • the above-mentioned step S204 forms a conductive structure in the through hole.
  • the specific steps may be:
  • a seed layer is formed on the bottom of the through hole and the surface of the hole wall;
  • metal filling is performed in the through hole by an electroplating process to form a conductive structure.
  • the seed layer formed on the surface of the hole bottom and the hole wall of the through hole can reduce the difficulty of subsequent electroplating and filling, and can prevent the conductive structure from being broken and affecting signal transmission.
  • the material of the seed layer is titanium, molybdenum, tantalum, aluminum, copper, silver metal simple substance or molybdenum alloy, copper alloy, aluminum alloy.
  • the present disclosure also provides another method for manufacturing the above-mentioned display substrate, as shown in FIG. 5, the specific steps include:
  • a signal line is formed in the display area, one end of the signal line is electrically connected to the binding electrode, and the other end is electrically connected to the driving circuit, and the conductive structure is configured to conduct the signal line, the driving circuit and the binding electrode; specifically, Making the first type of signal line while executing step S403, and making the second type of signal line while executing step S405;
  • embodiments of the present disclosure also provide a display panel, including the above-mentioned display substrate, and a driving circuit (IC circuit) connected to at least part of the bonding electrodes (data line bonding electrodes).
  • the display panel may be an organic electroluminescence display panel or a micro LED display panel.
  • embodiments of the present disclosure also provide a display device including the above-mentioned display panel.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板及其制作方法、显示面板、显示装置，该显示基板包括衬底基板（1）、位于衬底基板（1）的第一表面（A）一侧的显示区域内呈阵列方式分布的驱动电路（2），位于衬底基板（1）的第二表面（B）一侧且分布于显示区域内的绑定电极（3），位于显示区域内的信号线（4），信号线（4）一端与绑定电极（3）电连接，另一端与驱动电路（2）电连接，填充于至少贯穿衬底基板（1）的通孔内的导电结构（5），导电结构（5）被配置为导通信号线（4）、驱动电路（2）和绑定电极（3）。该显示基板，可以将驱动电路设置在衬底基板（1）的第二表面（B）与绑定电极（3）电连接，显示面板可以实现窄边框或无边框设计。

Description

显示基板及其制作方法、显示面板、显示装置
相关申请的交叉引用
本公开要求在2019年06月18日提交中国专利局、申请号为201910526074.1、申请名称为“一种阵列基板及其制作方法、显示面板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及其制作方法、显示面板、显示装置。
背景技术
全面屏技术逐渐成为手机等手持设备的主流技术，目前采用显示基板行驱动(GOA，Gate Driver On Array)技术实现左右边框的窄型化，采用覆晶薄膜(COF，Chip On Film)技术实现下边框的窄型化。
发明内容
本公开实施例提供了一种显示基板，具有显示区域和包围所述显示区域的边框区域，其中，所述显示基板包括：
衬底基板，包括相对设置的第一表面和第二表面；
驱动电路，位于所述衬底基板的第一表面一侧且阵列分布于所述显示区域内；
绑定电极，位于所述衬底基板的第二表面一侧且分布于所述显示区域内；
信号线，位于所述显示区域内，所述信号线的一端与所述绑定电极电连接，另一端与所述驱动电路电连接；
导电结构，填充于至少贯穿所述衬底基板的通孔内，所述导电结构被配置为导通所述信号线、驱动电路和绑定电极。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述衬底基板的第一表面一侧且与所述驱动电路电连接的连接电极；
所述信号线包括第一类信号线，所述第一类信号线位于所述衬底基板的第二表面一侧且与所述绑定电极电连接；
所述通孔位于所述第一类信号线与所述连接电极之间的交叠区域，所述第一类信号线与所述连接电极通过所述导电结构电连接。
可选地，在本公开实施例提供的上述显示基板中，所述信号线包括第二类信号线，所述第二类信号线位于所述衬底基板的第一表面一侧且与所述驱动电路电连接；
所述通孔位于所述第二类信号线与所述绑定电极之间的交叠区域，所述第二类信号线与所述绑定电极通过所述导电结构电连接。
可选地，在本公开实施例提供的上述显示基板中，所述第一类信号线为数据线，所述绑定电极为数据线绑定电极，所述连接电极电连接所述驱动电路中薄膜晶体管的源极；和/或，
所述第一类信号线为扫描线，所述绑定电极为扫描线绑定电极，所述连接电极电连接所述驱动电路中薄膜晶体管的栅极。
可选地，在本公开实施例提供的上述显示基板中，所述第二类信号线为数据线，所述绑定电极为数据线绑定电极，所述数据线电连接所述驱动电路中薄膜晶体管的源极；和/或，
所述第二类信号线为扫描线，所述绑定电极为扫描线绑定电极，所述扫描线电连接所述驱动电路中薄膜晶体管的栅极。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述衬底基板的第二表面一侧且与所述扫描线绑定电极电连接的扫描驱动电路。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述衬底基板的第一表面一侧且与所述驱动电路电连接的电致发光器件。
可选地，在本公开实施例提供的上述显示基板中，所述衬底基板为柔性衬底基板。
另一方面，本公开实施例还提供了一种上述显示基板的制作方法中，包括：
形成衬底基板；
在所述衬底基板的第一表面一侧的显示区域内形成呈阵列分布的驱动电路；
将所述衬底基板反置，从所述衬底基板的第二表面一侧形成至少贯穿所述衬底基板的通孔；
在所述通孔内形成导电结构；
在所述衬底基板的第二表面一侧形成绑定电极；
在所述显示区域内形成信号线，所述信号线的一端与所述绑定电极电连接，另一端与所述驱动电路电连接，所述导电结构被配置为导通所述信号线、驱动电路和绑定电极。
可选地，在本公开实施例提供的上述制作方法中，从所述衬底基板的第二表面一侧形成至少贯穿所述衬底基板的通孔，具体包括：
在所述衬底基板的第二表面一侧形成一层图案化的硬掩膜层；
采用图案化的硬掩膜层作为遮挡，对所述衬底基板进行干刻形成所述通孔；
去除所述硬掩膜层。
可选地，在本公开实施例提供的上述制作方法中，在所述通孔内形成导电结构，具体包括：
在所述通孔的孔底和孔壁表面形成一层种子层；
利用电镀工艺在所述通孔内进行金属填充，形成所述导电结构。
可选地，在本公开实施例提供的上述制作方法中，所述种子层的材料为钛、钼、钽、铝、铜、银金属单质或者为钼合金、铜合金、铝合金。
可选地，在本公开实施例提供的上述制作方法中，在所述显示区域内形成信号线，具体包括：
在所述通孔内形成导电结构之后，在所述衬底基板的第二表面一侧的显 示区域内形成与所述绑定电极电连接的第一类信号线。
可选地，在本公开实施例提供的上述制作方法中，所述第一类信号线同时包括数据线和扫描线时，在所述衬底基板的第二表面的显示区域内形成与所述绑定电极电连接的第一类信号线，具体包括：
在对应于数据线的所述通孔内形成导电结构之后，在所述衬底基板的第二表面的显示区域内形成数据线；
在所述数据线所在膜层之上形成绝缘层；
在从所述衬底基板的第二表面一侧形成对应于扫描线的贯穿所述衬底基板和所述绝缘层的通孔，并在所述通孔内形成导电结构之后，在所述衬底基板的第二表面一侧的显示区域内形成扫描线。
可选地，在本公开实施例提供的上述制作方法中，在所述显示区域内形成信号线，具体包括：
在所述衬底基板的第一表面一侧的显示区域内形成与所述驱动电路电连接的第二类信号线。
另一方面，本公开实施例还提供了另一种上述显示基板的制作方法，包括：
在刚性基板上形成缓冲牺牲层；
在所述缓冲牺牲层背离所述刚性基板的一侧形成绑定电极；
在所述绑定电极背离所述缓冲牺牲层的一侧形成衬底基板；
形成贯穿所述衬底基板的通孔，在所述通孔内形成导电结构；
在所述衬底基板上形成呈阵列分布的驱动电路；
在所述显示区域内形成信号线，所述信号线的一端与所述绑定电极电连接，另一端与所述驱动电路电连接，所述导电结构被配置为导通所述信号线、驱动电路和绑定电极；
去除所述刚性基板以及缓冲牺牲层。
另一方面，本公开实施例还提供了一种显示面板，包括上述显示基板，以及与至少部分绑定电极连接驱动电路。
另一方面，本公开实施例还提供了一种显示装置，包括上述显示面板。
附图说明
图1为本公开实施例提供的一种显示基板的结构示意图；
图2为本公开实施例提供的另一种显示基板的结构示意图；
图3为本公开实施例提供的一种显示基板的制作方法的流程图；
图4A至图4F分别为本公开实施例提供的一种显示基板的制作过程示意图；
图5为本公开实施例提供的另一种显示基板的制作方法的流程图。
具体实施方式
目前，在诸如有机电致发光显示面板(OLED)的显示基板上设置有扫描线和数据线，GOA和集成电路(IC，integrated circuit)在边框区分别与扫描线和数据线电连接，向扫描线和数据线输出控制信号。扫描线和数据线需要在显示基板的边缘设置引线，与边框区的GOA和集成电路导通，这就需要在显示基板的边缘留设一定宽度的边框，从而无法使显示装置实现窄边框或者无边框设计，不利于实现全面屏。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
请参考图1和图2，本公开提供了一种显示基板，具有显示区域和包围显示区域的边框区域，在图1和图2中仅示出显示区域的部分结构，显示基板包括：
衬底基板1，包括相对设置的第一表面A和第二表面B；
驱动电路2，位于衬底基板1的第一表面A一侧且阵列分布于显示区域内；具体地，驱动电路2一般包含一个或多个薄膜晶体管，图1和图2中是 以一个薄膜晶体管为例进行说明；
绑定电极3，位于衬底基板1的第二表面B一侧且分布于显示区域内；
信号线4，位于显示区域内，信号线的一端与绑定电极3电连接，另一端与驱动电路2电连接；
导电结构5，填充于至少贯穿衬底基板1的通孔内，导电结构5被配置为导通信号线4、驱动电路2和绑定电极3。
具体地，在本公开施例提供的上述显示基板中，由于绑定电极3设置于衬底基板1背离驱动电路2的一侧，可以将其设置于显示区域内而不影响显示基板正面(即第一表面A)的正常显示。集成电路或GOA等驱动部件可以在衬底基板1背离驱动电路2的一侧与绑定电极3电连接，且设置在显示区域内，因此，显示基板的边缘可以不需要为驱动电路预留一定宽度的边框，进而实现窄边框或者无边框设计。
可选地，在本公开实施例提供上述显示基板中，信号线4的设置位置可以位于衬底基板1的第一表面A一侧，也可以位于衬底基板1的第二表面B一侧。并且，信号线4可以包括需要和驱动电路或GOA等驱动部件连接任何信号线，例如数据线、扫描线等信号线，根据信号线4所需传输的信号不同，设计其与驱动电路2中的相应部件之间的连接关系。下面通过具体实施例进行详细的介绍。
具体地，如图1所示，当信号线4位于衬底基板1的第二表面B且与绑定电极3电连接时，信号线4与对应连接的绑定电极3可以在同一膜层内制作图形，也可以在不同膜层内制作，在此不做限定。并且，可以将这类信号线4称为第一类信号线41。此外，由于绑定电极3一般较为集中设计，以便于所需绑定的驱动电路的引脚连接，因此，在第一类信号线41与其连接的绑定电极3之间可以设置一段引线，以方便两者连接，且与各第一类信号线41连接的各条引线可以构成形状类似于扇面的扇出区。
为了保证驱动电路2中相应部件与第一类信号线41可以通过导电结构5电连接，还可以在衬底基板1的第一表面A一侧设置与驱动电路2电连接的 连接电极6。连接电极6与第一类信号线41具有交叠区域，在该交叠区域设置贯穿衬底基板1的通孔，可以使第一类信号线41与连接电极6通过导电结构5电连接。
并且，为了保证在衬底基板1的第一表面A一侧设置的每个驱动电路2均可以与第一类信号线41通过导电结构5电连接，则需要设置与各驱动电路2一一对应的通孔数量和连接电极6数量。具体地，连接电极6可以和驱动电路2中所需连接的相应部件在同一膜层内制作图形。
例如，在第一类信号线41具体为数据线时，即数据线设置在衬底基板的第二表面B一侧，则绑定电极3可以认为是用于和驱动芯片(Driver IC)绑定的数据线绑定电极31，连接电极6一般电连接驱动电路2中某个薄膜晶体管的源极23。对应每个驱动电路2中均需要设置与源极23电连接的连接电极6以及与连接电极6导通的导通结构5。具体可以将源极23延伸出的一部分作为连接电极6，也可以在源极23所在膜层与衬底基板1之间的某个膜层(例如栅极金属层)设置连接电极6，在此不做限定。图1中是以连接电极6与源极23在同一膜层内制作图形为例进行说明的。
又如，在第一类信号线41具体为扫描线时，即扫描线设置在衬底基板的第二表面B一侧，则绑定电极3可以认为是用于和GOA连接的扫描线绑定电极32，连接电极6一般电连接驱动电路2中某个薄膜晶体管的栅极22。对应每个驱动电路2中均需要设置与栅极22电连接的连接电极6以及与连接电极6导通的导通结构5。具体可以将栅极22延伸出的一部分作为连接电极6，也可以在栅极22所在膜层与衬底基板1之间的某个膜层(例如遮光层)设置连接电极6，在此不做限定。图1中是以连接电极6与栅极22在同一膜层内制作图形为例进行说明的。
并且，在本发明实施例提供的上述显示基板中，可以将数据线和扫描线同时采用第一类信号线41的设计方式。由于数据线和扫描线的延伸方向相互交叉，因此，需要在衬底基板1的第二表面B一侧的不同膜层设置数据线和扫描线，例如图1中所示，在作为数据线的第一类信号线41和作为扫描线的 第一类信号线41之间设置绝缘层7。
具体地，如图2所示，当信号线4位于衬底基板1的第一表面A且与驱动电路2电连接时，信号线4与驱动电路2中对应连接的部件可以在同一膜层内制作图形，也可以在不同膜层内制作，在此不做限定。并且，可以将这类信号线4称为第一类信号线42。此外，由于绑定电极3一般较为集中设计，以便于所需绑定的驱动电路的引脚连接，因此，在第二类信号线42与其连接的绑定电极3之间可以设置一段引线，以方便两者连接，且与各第二类信号线42连接的各条引线可以构成形状类似于扇面的扇出区。引线可以与第二类信号线42在同一膜层内制作图形，也可以与绑定电极3在同一膜层内制作图形，在此不做限定。
具体地，一行或者一列的各驱动电路2中相应部件可以与同一条第二类信号线42电连接，之后在第二类信号线42与绑定电极3之间的交叠区域设置贯穿衬底基板1的通孔，可以使第二类信号线42与绑定电极3通过导电结构5电连接。例如，在第二类信号线42为数据线时，绑定电极3为数据线绑定电极31，一条数据线电连接一列的各驱动电路2中薄膜晶体管的源极23。又如，第二类信号线42为扫描线时，绑定电极3为扫描线绑定电极32，一条扫描线电连接一行的各驱动电路2中薄膜晶体管的栅极22。在衬底基板1中可以设置与第二类信号线42一一对应的通孔，当然不排除多条第二类信号线42同时通过一个通孔与一个绑定电极3连接的情况，以及一条第二类信号线42同时通过多个通孔与一个绑定电极3连接的情况。
可选地，在本公开实施例提供上述显示基板中，驱动电路2中的薄膜晶体管可以如图2所示采用底栅型薄膜晶体管，也可以如图1所示采用顶栅型薄膜晶体管。顶栅型薄膜晶体管，如图1所示，一般包括位于衬底基板1上的栅极22、栅绝缘层25、有源层21、源极23和漏极24。底栅型薄膜晶体管，如图2所示，一般包括位于衬底基板1上的有源层21、栅绝缘层25、栅极22、层间绝缘层26、源极23和漏极24。一般一列的各驱动电路2中的薄膜晶体管的源极23用于接收同一条数据线提供的数据信号，一行的各驱动电路2中 的薄膜晶体管的栅极22用于接收同一条扫描线提供的扫描信号，薄膜晶体管的漏极24一般与阳极8(或像素电极)电连接。在驱动电路2与衬底基板1之间可以设置缓冲层9，在驱动电路2与阳极8之间可以设置平坦层10，在阳极8之上可以设置像素限定层11，以便在衬底基板1的第一表面A一侧设置与驱动电路2电连接的电致发光器件，具体电致发光显示面板与阳极8电连接。或者，也可以采用微LED绑定于阳极8之上。
可选地，在本公开实施例提供上述显示基板中，当在衬底基板1的第二表面B一侧设置扫描线绑定电极32时，可以在衬底基板2的第二表面B一侧直接制作与扫描线绑定电极32电连接的扫描驱动电路，即GOA电路。
具体地，在本公开实施例提供上述显示基板中，衬底基板1可以为柔性衬底基板。
基于同一发明构思，本公开还提供了一种上述显示基板的制作方法，如图3所示，具体步骤如下：
S201、形成衬底基板；
S202、在衬底基板的第一表面一侧的显示区域内形成呈阵列分布的驱动电路；
S203、将衬底基板反置，从衬底基板的第二表面一侧形成至少贯穿衬底基板的通孔；
S204、在通孔内形成导电结构；
S205、在衬底基板的第二表面一侧形成绑定电极；
S206、在显示区域内形成信号线，信号线的一端与绑定电极电连接，另一端与驱动电路电连接，导电结构被配置为导通信号线、驱动电路和绑定电极。
具体地，本公开实施例提供的上述制作方法中，在制作完成衬底基板的第一表面一侧的驱动电路后，从衬底基板的第二表面一侧开通孔，并在通孔内填充导电结构，之后在衬底基板的第二表面一侧制作绑定电极，绑定电极可以设置在显示区域而不影响显示基板正面(即第一表面)的正常显示。集 成电路或GOA等驱动部件可以在衬底基板的第二表面一侧与绑定电极电连接，且设置在显示区域内，因此，显示基板的边缘可以不需要为驱动电路预留一定宽度的边框，进而实现窄边框或者无边框设计。
具体地，在本公开实施例提供的上述制作方法中，可以根据选择的信号线类型，确定在具体哪个工序步骤执行上述步骤S206在显示区域内形成信号线。例如，在选用第一类信号线时，可以在步骤S204在通孔内形成导电结构之后，在衬底基板的第二表面一侧的显示区域内形成与绑定电极电连接的第一类信号线，并且可以在执行步骤S205在衬底基板的第二表面一侧形成绑定电极的同时执行步骤206。又如，在选用第二类信号线时，可以在步骤S203将衬底基板反置之前，在衬底基板的第一表面一侧的显示区域内形成与驱动电路电连接的第二类信号线，并且可以在执行步骤S202在衬底基板的第一表面一侧的显示区域内形成呈阵列分布的驱动电路的同时执行步骤206。又如，在部分选用第一类信号线，部分选用第二类信号线时，例如选用第一类信号线作为数据线、第二类信号线作为扫描线时，可以分别在执行步骤S202的同时实现第二类扫描线的制作，在执行步骤S205时，实现第一类扫描线的制作。
并且，在第一类信号线同时包括数据线和扫描线时，由于数据线和扫描线的延伸方向相互交叉，不能在同一膜层制作，因此，在衬底基板的第二表面的显示区域内形成与所述绑定电极电连接的第一类信号线，可以分别设置对应于数据线的通孔和对应于扫描线的通孔，可以具体包括：
首先，在对应于数据线的通孔内形成导电结构之后，在衬底基板的第二表面一侧的显示区域内形成数据线；
之后，在数据线所在膜层之上形成绝缘层；
接着，在从衬底基板的第二表面一侧形成对应于扫描线的贯穿衬底基板和绝缘层的通孔，并在通孔内形成导电结构之后，在衬底基板的第二表面一侧的显示区域内形成扫描线。
具体地，在本公开实施例提供的上述显示基板的制作方法中，步骤S201可以具体包括：如图4A所示，在第一刚性基板01上形成衬底基板1。
以图1所示的结构为例，之后在第一刚性基板01作为承载体的基础上，如图4B所示，在衬底基板1的第一表面A一侧的显示区域内形成呈阵列分布的驱动电路2和连接电极6。具体地，驱动电路2的薄膜晶体管可以包括依次层叠设置的栅极22、栅绝缘层25、有源层21、层间绝缘层26、源极23和漏极24。薄膜晶体管与衬底基板1之间还可以设置有缓冲层2。在薄膜晶体管之上还可以制作平坦层10，阳极8和像素限定层11，以及电致发光器件等，还可以对电致发光器件进行封装。
之后，如图4C所示，将衬底基板1反置，从衬底基板1的第一表面A一侧通过贴合材料12贴合第二刚性基板02，其中，采用真空贴合设备进行贴合，贴合材料12可以为热固化胶。
接着，如图4D所示，去除第一刚性基板01。如图4E所示，从衬底基板1的第二表面B一侧形成贯穿衬底基板1的通孔并在通孔内形成导电结构5，通孔一直延伸至与源极23连接的连接电极6处，具体地，通孔贯穿衬底基板1、缓冲层9、栅绝缘层25。在衬底基板1的第二表面B一侧形成作为数据线的第二类信号线41和与其连接的数据线绑定电极31。
然后，在衬底基板1的第二表面B一侧形成绝缘层7。如图4F所示，从衬底基板1的第二表面B一侧形成贯穿衬底基板1的通孔并在通孔内形成导电结构5，通孔一直延伸至与栅极22连接的连接电极6处，具体地，通孔贯穿衬底基板1、缓冲层9。在衬底基板1的第二表面B一侧形成作为扫描线的第二类信号线42和与其连接的扫描线绑定电极32，以及GOA。
最后，去除贴合材料12以及第二刚性基板02。由于贴合材料12为热固化胶，热固化胶在200～300℃实现粘性下降，可使显示基板与第二刚性基板B分离。最后，将驱动电路(IC器件)绑定于数据线绑定电极31，并在第二表面B一侧进行背膜贴附。
具体地，在本公开实施例提供的上述显示基板的制作方法中，上述步骤S203从衬底基板的第二表面一侧形成至少贯穿衬底基板的通孔，具体步骤可以为：
首先，在衬底基板的第二表面一侧形成一层图案化的硬掩膜层；
之后，通过图案化后的硬掩膜层作为遮挡，对衬底基板进行干刻形成通孔；
最后，去除硬掩膜层。
具体地，在本公开实施例提供的上述显示基板的制作方法中，上述步骤S204在通孔内形成导电结构，具体步骤可以为：
首先，在通孔的孔底和孔壁表面形成一层种子层；
之后，利用电镀工艺在通孔内进行金属填充，形成导电结构。
上述制作方法中，先在通孔的孔底和孔壁表面形成的种子层能够降低后续电镀填充的难度，且能够避免导电结构断裂，影响信号的传输。
可选地，种子层的材料为钛、钼、钽、铝、铜、银金属单质或者为钼合金、铜合金、铝合金。
基于同一发明构思，本公开还提供了另一种上述显示基板的制作方法，如图5所示，具体步骤包括：
S401、在刚性基板上形成缓冲牺牲层；
S402、在缓冲牺牲层背离刚性基板的一侧形成绑定电极；
S403、在绑定电极背离缓冲牺牲层的一侧形成衬底基板；
S404、形成贯穿衬底基板的通孔，在通孔内形成导电结构；
S405、在衬底基板上形成呈阵列分布的驱动电路；
S406、在显示区域内形成信号线，信号线的一端与绑定电极电连接，另一端与驱动电路电连接，导电结构被配置为导通信号线、驱动电路和绑定电极；具体地，可以在执行步骤S403的同时制作第一类信号线，在执行步骤S405的同时制作第二类信号线；
S407、去除刚性基板以及缓冲牺牲层。
基于同一发明构思，本公开实施例还提供一种显示面板，包括上述显示基板，以及与至少部分绑定电极(数据线绑定电极)连接的驱动电路(IC电路)。其中，显示面板可以为有机电致发光显示面板或微LED显示面板。
基于同一发明构思，本公开实施例还提供一种显示装置，包括上述显示面板。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种显示基板，具有显示区域和包围所述显示区域的边框区域，其中，所述显示基板包括：
    衬底基板，包括相对设置的第一表面和第二表面；
    驱动电路，位于所述衬底基板的第一表面一侧且阵列分布于所述显示区域内；
    绑定电极，位于所述衬底基板的第二表面一侧且分布于所述显示区域内；
    信号线，位于所述显示区域内，所述信号线的一端与所述绑定电极电连接，另一端与所述驱动电路电连接；
    导电结构，填充于至少贯穿所述衬底基板的通孔内，所述导电结构被配置为导通所述信号线、驱动电路和绑定电极。
  2. 根据权利要求1所述的显示基板，其中，还包括：位于所述衬底基板的第一表面一侧且与所述驱动电路电连接的连接电极；
    所述信号线包括第一类信号线，所述第一类信号线位于所述衬底基板的第二表面一侧且与所述绑定电极电连接；
    所述通孔位于所述第一类信号线与所述连接电极之间的交叠区域，所述第一类信号线与所述连接电极通过所述导电结构电连接。
  3. 根据权利要求1所述的显示基板，其中，所述信号线包括第二类信号线，所述第二类信号线位于所述衬底基板的第一表面一侧且与所述驱动电路电连接；
    所述通孔位于所述第二类信号线与所述绑定电极之间的交叠区域，所述第二类信号线与所述绑定电极通过所述导电结构电连接。
  4. 根据权利要求2所述的显示基板，其中，所述第一类信号线为数据线，所述绑定电极为数据线绑定电极，所述连接电极电连接所述驱动电路中薄膜晶体管的源极；和/或，
    所述第一类信号线为扫描线，所述绑定电极为扫描线绑定电极，所述连 接电极电连接所述驱动电路中薄膜晶体管的栅极。
  5. 根据权利要求3所述的显示基板，其中，所述第二类信号线为数据线，所述绑定电极为数据线绑定电极，所述数据线电连接所述驱动电路中薄膜晶体管的源极；和/或，
    所述第二类信号线为扫描线，所述绑定电极为扫描线绑定电极，所述扫描线电连接所述驱动电路中薄膜晶体管的栅极。
  6. 根据权利要求4或5所述的显示基板，其中，还包括：位于所述衬底基板的第二表面一侧且与所述扫描线绑定电极电连接的扫描驱动电路。
  7. 根据权利要求1-5任一项所述的显示基板，其中，还包括：位于所述衬底基板的第一表面一侧且与所述驱动电路电连接的电致发光器件。
  8. 根据权利要求1-5任一项所述的显示基板，其中，所述衬底基板为柔性衬底基板。
  9. 一种如权利要求1-8任一项所述的显示基板的制作方法，其中，包括：
    形成衬底基板；
    在所述衬底基板的第一表面一侧的显示区域内形成呈阵列分布的驱动电路；
    将所述衬底基板反置，从所述衬底基板的第二表面一侧形成至少贯穿所述衬底基板的通孔；
    在所述通孔内形成导电结构；
    在所述衬底基板的第二表面一侧形成绑定电极；
    在所述显示区域内形成信号线，所述信号线的一端与所述绑定电极电连接，另一端与所述驱动电路电连接，所述导电结构被配置为导通所述信号线、驱动电路和绑定电极。
  10. 根据权利要求9所述的制作方法，其中，从所述衬底基板的第二表面一侧形成至少贯穿所述衬底基板的通孔，具体包括：
    在所述衬底基板的第二表面一侧形成一层图案化的硬掩膜层；
    采用图案化的硬掩膜层作为遮挡，对所述衬底基板进行干刻形成所述通 孔；
    去除所述硬掩膜层。
  11. 根据权利要求9所述的制作方法，其中，在所述通孔内形成导电结构，具体包括：
    在所述通孔的孔底和孔壁表面形成一层种子层；
    利用电镀工艺在所述通孔内进行金属填充，形成所述导电结构。
  12. 根据权利要求11所述的制作方法，其中，所述种子层的材料为钛、钼、钽、铝、铜、银金属单质或者为钼合金、铜合金、铝合金。
  13. 一种如权利要求9所述的制作方法，其中，在所述显示区域内形成信号线，具体包括：
    在所述通孔内形成导电结构之后，在所述衬底基板的第二表面一侧的显示区域内形成与所述绑定电极电连接的第一类信号线。
  14. 一种如权利要求13所述的制作方法，其中，所述第一类信号线同时包括数据线和扫描线时，在所述衬底基板的第二表面的显示区域内形成与所述绑定电极电连接的第一类信号线，具体包括：
    在对应于数据线的所述通孔内形成导电结构之后，在所述衬底基板的第二表面的显示区域内形成数据线；
    在所述数据线所在膜层之上形成绝缘层；
    在从所述衬底基板的第二表面一侧形成对应于扫描线的贯穿所述衬底基板和所述绝缘层的通孔，并在所述通孔内形成导电结构之后，在所述衬底基板的第二表面一侧的显示区域内形成扫描线。
  15. 一种如权利要求9所述的制作方法，其中，在所述显示区域内形成信号线，具体包括：
    在所述衬底基板的第一表面一侧的显示区域内形成与所述驱动电路电连接的第二类信号线。
  16. 一种如权利要求1-8任一项所述的显示基板的制作方法，其中，包括：
    在刚性基板上形成缓冲牺牲层；
    在所述缓冲牺牲层背离所述刚性基板的一侧形成绑定电极；
    在所述绑定电极背离所述缓冲牺牲层的一侧形成衬底基板；
    形成贯穿所述衬底基板的通孔，在所述通孔内形成导电结构；
    在所述衬底基板上形成呈阵列分布的驱动电路；
    在所述显示区域内形成信号线，所述信号线的一端与所述绑定电极电连接，另一端与所述驱动电路电连接，所述导电结构被配置为导通所述信号线、驱动电路和绑定电极；
    去除所述刚性基板以及缓冲牺牲层。
  17. 一种显示面板，其中，包括如权利要求1-8任一项所述的显示基板，以及与至少部分绑定电极连接驱动电路。
  18. 一种显示装置，其中，包括如权利要求17所述的显示面板。
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