WO2022052218A1 - 一种阵列基板及其制备方法以及显示面板 - Google Patents

一种阵列基板及其制备方法以及显示面板 Download PDF

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Publication number
WO2022052218A1
WO2022052218A1 PCT/CN2020/122191 CN2020122191W WO2022052218A1 WO 2022052218 A1 WO2022052218 A1 WO 2022052218A1 CN 2020122191 W CN2020122191 W CN 2020122191W WO 2022052218 A1 WO2022052218 A1 WO 2022052218A1
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Prior art keywords
substrate
array substrate
flexible substrate
thin film
film transistor
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PCT/CN2020/122191
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English (en)
French (fr)
Inventor
刘俊领
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/056,616 priority Critical patent/US20220308376A1/en
Publication of WO2022052218A1 publication Critical patent/WO2022052218A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display panel.
  • borderless displays have become the mainstream of high-end products in the display market.
  • the two major advantages of borderless displays are that they are beautiful in appearance and more fashionable.
  • the display with borderless technology can well realize display splicing, realizing double screen, triple screen and even multi-screen.
  • the borderless display can bring users a wider visual experience, eliminating the sense of restraint of the original thick bezel display.
  • borderless or narrow borders There are two existing implementations of borderless or narrow borders, one of which is the side bonding method: that is, the lines originally bound by the peripheral (bonding) traces are shortened or shrunk into the plane, and printed on the side of the array substrate. Nano-silver (Ag) glue is connected to the circuit, and then the chip-on-chip (Chip) On Film, COF) is bound to the side of the array substrate, so as to achieve a narrow border or no border effect.
  • the other is the backside bonding method, which shortens or shrinks the lines originally bound by the peripheral lines into the plane, and uses the backside technology to design the corresponding peripheral lines on the backside.
  • the side-printed nano-silver glue is also used to connect the lines correspondingly, so that the binding traces on the front and the peripheral circuits on the back are correspondingly connected, and finally COF binding is performed on the back to achieve the effect of narrow or no border.
  • both of the above two bonding methods need to print nano-silver paste on the side of the array substrate, and the printing accuracy is limited.
  • silver ions often cause short circuits in the substrate due to diffusion and penetration of silver ions or abnormal alignment of the nano-silver paste.
  • the product yield rate is low, and the cost remains high, resulting in the inability to widely adopt and popularize the borderless technology.
  • the present application provides an array substrate, a preparation method thereof, and a display panel, so as to alleviate the technical problem of low yield caused by using nano-silver glue in the existing array substrate bonding process.
  • An embodiment of the present application provides an array substrate.
  • the array substrate is divided into a display area and a bending area.
  • the bending area is located on one side of the display area.
  • the array substrate includes a glass substrate and a flexible substrate.
  • the glass substrate Corresponding to the display area, the flexible substrate corresponds to the bending area, and the flexible substrate extends from the bending area to the upper surface of one side of the glass substrate covering the display area.
  • the display area further includes: a buffer layer, a thin film transistor, a plurality of signal lines and pixel electrodes.
  • the buffer layer is disposed on the glass substrate and is in contact with the flexible substrate.
  • the thin film transistor is disposed above the buffer layer and the flexible substrate.
  • the plurality of signal lines are arranged in the same layer as the gate electrode of the thin film transistor.
  • the pixel electrode is disposed on the thin film transistor and connected to the thin film transistor.
  • the bending area further includes a plurality of binding wires, the plurality of binding wires are arranged on the flexible substrate, and the plurality of binding wires are respectively connected to the plurality of binding wires in the display area. Multiple signal lines are connected.
  • the flexible substrate in the bending area is suitable for bending along the side edge of the glass substrate to the side of the glass substrate away from the thin film transistor.
  • the material of the flexible substrate includes polyimide.
  • the thickness of the flexible substrate is 3 micrometers to 100 micrometers.
  • the buffer layer and the flexible substrate have the same film thickness.
  • the structure of the thin film transistor includes a back channel etch type, an etch stop type and a top gate structure type.
  • the thin film transistor further includes an active layer and a source and drain electrode, the active layer is disposed under the gate electrode, and the source and drain electrode are disposed under the gate electrode on both sides.
  • the material of the active layer includes one of amorphous silicon, low temperature polysilicon or metal oxide semiconductor.
  • the material of the pixel electrode includes indium tin oxide.
  • An embodiment of the present application further provides a display panel, which includes the array substrate of the foregoing embodiment and a chip-on-film disposed under the array substrate, and the chip-on film is bound to the plurality of bonding wires.
  • the display panel is a liquid crystal display panel
  • the liquid crystal display panel further includes a color filter substrate disposed opposite to the array substrate, and a color filter substrate located between the array substrate and the color filter Multiple liquid crystal molecules between substrates.
  • the display panel is an OLED display panel
  • the OLED display panel further includes a light-emitting functional layer disposed on the array substrate, and an encapsulation disposed on the light-emitting functional layer Floor.
  • Embodiments of the present application further provide a method for fabricating an array substrate, which includes the following steps: Step S10, providing a glass substrate, the glass substrate is divided into a display area and a bending area, and a buffer layer is prepared on one side of the glass substrate and preparing a flexible substrate on the other side of the glass substrate, wherein the buffer layer and part of the flexible substrate are arranged corresponding to the display area, and another part of the flexible substrate is arranged corresponding to the bending area.
  • Step S20 preparing a thin film transistor and a pixel electrode on the buffer layer and the flexible substrate in the display area, preparing a plurality of signal lines in the display area while preparing the thin film transistor, and preparing a plurality of signal lines in the bending area.
  • a plurality of bonding wires are prepared on the flexible substrate in the folding area, and the plurality of signal wires are respectively connected with the plurality of bonding wires.
  • Step S30 removing the glass substrate corresponding to the bending area, bending the exposed flexible substrate to the side of the glass substrate away from the thin film transistor, and fixing it.
  • the material of the flexible substrate includes polyimide.
  • the thickness of the flexible substrate is 3 micrometers to 100 micrometers.
  • the buffer layer and the flexible substrate have the same film thickness.
  • the structure of the thin film transistor includes a back channel etching type, an etching barrier type and a top gate structure type.
  • the thin film transistor further includes an active layer and a source and drain electrodes, the active layer is disposed below the gate electrode, and the source and drain electrodes are disposed on the both sides of the gate.
  • the material of the active layer includes one of amorphous silicon, low temperature polysilicon or metal oxide semiconductor.
  • step S30 the method for removing the glass substrate corresponding to the bending region includes at least one of substrate thinning technology, cutting, and laser burning.
  • the fixing material for fixing the exposed flexible substrate includes at least one of double-sided tape or glue.
  • a flexible substrate is prepared on the glass substrate side of the array substrate, and then the thin film transistors are prepared on the glass substrate and the bonding wires are prepared on the flexible substrate.
  • the glass substrate corresponding to the bending area is removed, and the flexible substrate prepared with the binding traces is bent to the back of the glass substrate for COF binding to achieve a borderless design.
  • the use of nano-silver glue in the bonding process is avoided.
  • the problem of low yield caused by the use of nano-silver glue in the bonding process of the existing array substrates to achieve narrow borders or no borders is solved.
  • FIG. 1 is a schematic side view of the film layer structure before the bending region of the array substrate provided by the embodiment of the present application.
  • FIG. 2 is a schematic diagram of a film layer structure of a thin film transistor according to an embodiment of the present application.
  • FIG. 3 is a schematic top view of a partial structure of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a film layer structure after the bending region of the array substrate provided by the embodiment of the present application is bent.
  • FIG. 5 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 6 to FIG. 7 are schematic diagrams of structures of film layers prepared in each step in the method for fabricating an array substrate provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a first structure of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a second structure of a display panel according to an embodiment of the present application.
  • an array substrate 100 is provided. As shown in FIG. 1 , the array substrate 100 is divided into a display area AA and a bending area BA, and the bending area BA is located at one side of the display area AA.
  • the array substrate 100 includes a glass substrate 10 and a flexible substrate 60.
  • the glass substrate 10 corresponds to the display area AA
  • the flexible substrate 60 corresponds to the bending area BA
  • the flexible substrate 60 extends from the The bending area BA extends to the upper surface of the side 11 of the glass substrate 10 covering the display area AA.
  • the display area AA further includes: a buffer layer 20 , a thin film transistor 40 , a plurality of signal lines 30 , and a pixel electrode 50 .
  • the buffer layer 20 is disposed on the glass substrate 10 and is in contact with the flexible substrate 60 .
  • the thin film transistor 40 is disposed above the buffer layer 20 and the flexible substrate 60 .
  • the plurality of signal lines 30 are disposed in the same layer as the gate electrode 42 of the thin film transistor 40 .
  • the pixel electrode 50 is disposed on the thin film transistor 40 and connected to the thin film transistor 40 .
  • the bending area BA also includes a plurality of bonding wires 70 disposed on the flexible substrate 60 (FIG. 1 is a schematic diagram of the film layer structure of the array substrate, and the bonding wires 70 and the signal wires 30 are shown.
  • FIG. 3 is a schematic top view of a partial structure of the array substrate, showing that a plurality of binding wires 70 and a plurality of signal wires 30 are electrically connected).
  • the plurality of binding wires 70 are respectively connected to the plurality of signal wires 30 in the display area AA.
  • the flexible substrate 60 in the bending area BA is suitable for bending along the side edge 11 of the glass substrate 10 to the side of the glass substrate 10 away from the thin film transistor 40 , as shown in FIG. 4 shown.
  • the structure of the thin film transistor includes a back channel etch (BCE) type, an etch stop layer (ESL) and a top gate (Top gate) structure type, etc.
  • BCE back channel etch
  • ESL etch stop layer
  • Top gate top gate
  • the thin film transistor 40 shown in FIG. 1 and FIG. 2 is described by taking the top gate structure as an example.
  • the thin film transistor 40 includes an active layer 41 , a gate electrode 42 , and a source and drain electrode 43 .
  • the gate 42 is disposed above the active layer 41 .
  • the source and drain electrodes 43 are disposed on both sides of the gate electrode 42 , and the source and drain electrodes 43 include a source electrode 431 and a drain electrode 432 .
  • the active layer 41 includes a doped region 411 and a channel region 412 , and the source electrode 431 and the drain electrode 432 are respectively connected to the doped region 411 of the active layer 41 .
  • the active layer 41 can be made of amorphous silicon (Amorphous Silicon, a-Si), low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or metal oxide semiconductors, such as Indium Gallium Zinc Oxide (IGZO), etc.
  • amorphous silicon Amorphous Silicon, a-Si
  • low temperature polysilicon Low Temperature Poly Silicon, LTPS
  • metal oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), etc.
  • a plurality of signal lines 30 are also prepared in the display area AA, and the plurality of signal lines 30 are arranged in the same layer as the gate electrode 42 of the thin film transistor 40 .
  • the signal line 30 is connected to the binding wire 70 of the bending area BA.
  • the film layer between the bonding wire 70 and the flexible substrate 60 may include the insulating layer 80 in the normal manufacturing process of the thin film transistor, such as a gate insulating layer and the like.
  • the connection method between the signal line and the binding line of the present application is not limited to that shown in FIG. 1 , the binding line may be formed at the same time as the signal line, and the binding line is an extension of the signal line.
  • the signal lines can also be connected to the bonding traces by arranging vias in the gate insulating layer.
  • the signal line is directly disposed on the surface of the buffer layer 20 and the flexible substrate 60, and is directly connected to the binding line.
  • FIG. 3 a schematic top view of a partial structure in which the plurality of signal lines 30 and the plurality of binding wires 70 are connected is shown in FIG. 3 .
  • FIG. 3 only shows the signal line 30 , the bonding wire 70 , the glass substrate 10 and the flexible substrate 60 .
  • a plurality of signal lines 30 are disposed above the glass substrate 10, and fan out to the bending area BA at the junction of the display area AA and the bending area BA, which are respectively connected with the multiple signal lines 30 on the flexible substrate 60 in the bending area BA.
  • a bond trace 70 is connected.
  • the plurality of signal lines include signal lines such as gate lines and data lines.
  • the signal lines shown in FIG. 1 and FIG. 2 are gate lines.
  • the array substrate 100 further includes a pixel electrode 50 located above the thin film transistor 40 .
  • the pixel electrode 50 may be connected to the source electrode 431 or the drain electrode 432 through a via hole. 1 and 2 show that the pixel electrode 50 is connected to the drain electrode 432 .
  • the array substrate also includes multiple insulating layers between each film layer of the thin film transistor and the pixel electrodes, but the insulating layer is the prior art and is not the focus of this application, so it is not particularly marked in the figure or drawing, which will not be repeated here.
  • the material of the pixel electrode includes a transparent conductive electrode material such as indium tin oxide (Indium Tin Oxide, ITO).
  • a transparent conductive electrode material such as indium tin oxide (Indium Tin Oxide, ITO).
  • the buffer layer 20 of the display area AA is disposed on the glass substrate 10 and is the same layer as the flexible substrate 60 , and the upper surfaces of the two are at the same level, that is, the film layers of the two are at the same level. Same thickness. In this way, the height difference between the plurality of binding wires 70 and the plurality of signal wires 30 can be well balanced, and a breakage can be avoided.
  • the film thicknesses of the buffer layer and the flexible substrate can also be different.
  • the material of the flexible substrate 60 in the bending area BA includes a bendable flexible material such as polyimide (PI).
  • PI polyimide
  • the thickness of the flexible substrate 60 can be set in the range of 3 microns to 100 microns according to actual process requirements.
  • the flexible substrate 60 can be bent to the back of the glass substrate 10 and fixed on the back of the glass substrate by other fixing methods such as double-sided tape or glue, so as to facilitate COF binding.
  • the substrate of the array substrate is a combination of a glass substrate and a flexible substrate, and the bonding wires are prepared on the flexible substrate.
  • the flexible substrate prepared with the bonding traces can be bent to the back of the glass substrate and bound by COF to achieve a borderless design. Avoid the problem of low yield caused by the use of nano-silver glue.
  • a method for fabricating an array substrate is provided, as shown in FIG. 5 , which includes the following steps:
  • Step S10 providing a glass substrate, the glass substrate is divided into a display area and a bending area, a buffer layer is prepared on one side of the glass substrate, and a flexible substrate is prepared on the other side of the glass substrate, wherein the The buffer layer and part of the flexible substrate are disposed corresponding to the display area, and another part of the flexible substrate is disposed corresponding to the bending area.
  • a deposition process such as chemical vapor deposition (CVD) is used to deposit an inorganic film layer on one side of the glass substrate 10 as the buffer layer 20 , and on the other side of the glass substrate 10 , an inorganic film layer is deposited.
  • a flexible film layer is deposited on one side as a flexible substrate 60, the flexible substrate 60 extends from the bending area BA to the display area AA, and is in contact with the buffer layer 20, as shown in FIG. 6 .
  • the material of the flexible substrate 60 includes bendable flexible materials such as polyimide.
  • the thickness of the flexible substrate 60 can be set according to actual process requirements, and the thickness ranges from 3 micrometers to 100 micrometers.
  • the buffer layer 20 of the display area AA is disposed on the glass substrate 10 and is the same layer as the flexible substrate 60 , which can well balance the multiple binding wires and the multiple binding wires. The height difference of each signal line is avoided to avoid breakage.
  • Step S20 preparing a thin film transistor and a pixel electrode on the buffer layer and the flexible substrate in the display area, preparing a plurality of signal lines in the display area while preparing the thin film transistor, and preparing a plurality of signal lines in the bending area.
  • a plurality of bonding wires are prepared on the flexible substrate in the folding area, and the plurality of signal wires are respectively connected with the plurality of bonding wires.
  • a buffer layer 20 and a part of the flexible substrate 60 are prepared on the glass substrate 10 in the display area AA.
  • Thin film transistors 40 and pixel electrodes 50 are fabricated on the buffer layer 20 and part of the flexible substrate 60 .
  • the thin film transistor 40 includes an active layer 41 , a gate electrode 42 , and a source and drain electrode 43 .
  • the gate 42 is disposed above the active layer 41 .
  • the source and drain electrodes 43 are disposed on both sides of the gate electrode 42 , and the source and drain electrodes 43 include a source electrode 431 and a drain electrode 432 .
  • the active layer 41 includes a doped region 411 and a channel region 412 , and the source electrode 431 and the drain electrode 432 are respectively connected to the doped region 411 of the active layer 41 .
  • the active layer 41 can be made of amorphous silicon (Amorphous Silicon, a-Si), low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or metal oxide semiconductors, such as Indium Gallium Zinc Oxide (IGZO), etc.
  • amorphous silicon Amorphous Silicon, a-Si
  • low temperature polysilicon Low Temperature Poly Silicon, LTPS
  • metal oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), etc.
  • a plurality of signal lines 30 are prepared in the display area AA, and the flexible substrate in the bending area BA
  • a plurality of binding wires 70 are prepared on the bottom 60
  • an insulating layer 80 is also arranged between the plurality of binding wires 70 and the flexible substrate 60
  • the plurality of signal wires 30 are respectively connected with the plurality of binding wires 70 , as shown in Figure 7.
  • the pixel electrode 50 is connected to the source electrode or the drain electrode through a via hole.
  • the array substrate further includes a plurality of insulating layers between each film layer of the thin film transistor and the pixel electrode, which will not be repeated here.
  • the material of the pixel electrode includes a transparent conductive electrode material such as indium tin oxide (Indium Tin Oxide, ITO).
  • a transparent conductive electrode material such as indium tin oxide (Indium Tin Oxide, ITO).
  • Step S30 removing the glass substrate corresponding to the bending area, bending the exposed flexible substrate to the side of the glass substrate away from the thin film transistor, and fixing it.
  • the glass substrate 10 corresponding to the bending area BA is removed by adopting at least one of the substrate thinning technology, cutting, laser burning and other processes to form the structure shown in FIG. 1 .
  • the flexible substrate 60 prepared with a plurality of binding wires 70 is bent to the back of the glass substrate 10 . (that is, the side away from the thin film transistor 40).
  • the flexible substrate bent to the back of the glass substrate is fixed on the glass substrate using double-sided tape or glue or other fixing methods.
  • a display panel which includes the array substrate in the foregoing embodiment and a chip-on-film disposed under the array substrate, the chip-on film is bound to the plurality of bonding wires Certainly.
  • the display panel is a liquid crystal display panel.
  • the liquid crystal display panel 1000 includes an array substrate 100 , a color filter substrate 300 disposed opposite to the array substrate 100 , and a color filter substrate 300 located between the array substrate 100 and the array substrate 100 .
  • the liquid crystal display panel 1000 further includes a chip on film 400 , and the chip on film 400 is bound to a plurality of bonding wires 70 on the flexible substrate 60 .
  • the display panel is an OLED display panel.
  • the OLED display panel 1001 includes an array substrate 100 , a light-emitting functional layer 500 disposed on the array substrate 100 , and a light-emitting functional layer disposed on the light-emitting functional layer. Encapsulation layer 600 on 500 .
  • the OLED display panel 1001 further includes a chip on film 400 , and the chip on film 400 is bound to a plurality of bonding wires 70 on the flexible substrate 60 .
  • the present application adopts the method of combining the glass substrate and the flexible substrate to prepare the binding wires on the flexible substrate. Then, the flexible substrate prepared with the bonding traces is bent to the back of the glass substrate, and the chip-on-film COF bonding is performed to realize the frameless design method, which is not limited to the array substrate provided in the embodiments of the present application.
  • the borderless design method is also applicable to GOA (Gate Driver on Array, row driver of array substrate) substrates or COA (Color-filter on Array, color filter on array) substrates, etc., which will not be repeated here.
  • the present application provides an array substrate, a preparation method thereof, and a display panel.
  • a flexible substrate is prepared on one side of a glass substrate of the array substrate, and then a thin film transistor is prepared on the glass substrate and binding wires are prepared on the flexible substrate.
  • the glass substrate under the flexible substrate is removed, and the flexible substrate is bent to the back of the glass substrate for COF binding to achieve a borderless design.
  • the use of nano-silver glue in the bonding process is avoided.
  • the problem of low yield caused by the use of nano-silver glue in the bonding process of the existing array substrates to achieve narrow-sided models or no borders is solved.

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Abstract

本申请提供一种阵列基板及其制备方法以及显示面板。阵列基板划分为显示区及弯折区，阵列基板包括玻璃基板和柔性衬底，玻璃基板对应显示区设置，柔性衬底对应弯折区设置。弯折区的多条绑定走线分别与显示区内的多条信号线连接。柔性衬底弯折到阵列基板的背面进行COF绑定，避免使用纳米银胶导致良率较低的问题。

Description

一种阵列基板及其制备方法以及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法以及显示面板。
 背景技术
随着显示技术的发展，无边框显示器成为现在显示市场中高端产品的主流。无边框显示器的两大优点，一是外形美观，更有时尚感。其二采用无边框技术的显示器可以很好的实现显示器拼接，实现两联屏、三联屏甚至多联屏。此外，无边框显示器能给用户带来更宽广的视觉体验，消除了原先厚边框显示器的束缚感。
现有无边框或窄边框的实现方式有两种，其中一种为侧面绑定方式：即采用将原本外围绑定（bonding）走线的线路缩短或缩到面内，并在阵列基板侧面印刷纳米银（Ag）胶与线路连接，然后把覆晶薄膜（Chip On Film，COF）绑定在阵列基板的侧面，从而实现窄边框或无边框效果。另外一种为背面绑定方式，将原本外围绑定走线的线路缩短或缩到面内，并采用背面工艺技术在背面进行对应的外围线路设计。然后同样采用侧面印刷纳米银胶与线路对应连接，使正面的绑定走线与背面的外围线路对应连接起来，最后在背面进行COF 绑定，从而实现窄边框或无边框的效果。然而以上这两种绑定方式均需在阵列基板侧面印刷纳米银胶，而且受限印刷精度，制程工艺中经常会有银离子因扩散渗透或纳米银胶对位异常导致基板内线路发生短路。进而导致产品良率较低，成本高居不下，导致无边框技术无法广泛采用及普及。
因此，现有阵列基板绑定工艺中使用纳米银胶导致良率较低的问题需要解决。
 技术问题
本申请提供一种阵列基板及其制备方法以及显示面板，以缓解现有阵列基板绑定工艺中使用纳米银胶导致良率较低的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，阵列基板划分为显示区及弯折区，所述弯折区位于所述显示区一侧，所述阵列基板包括玻璃基板和柔性衬底，所述玻璃基板对应所述显示区，所述柔性衬底对应所述弯折区，且所述柔性衬底从所述弯折区延伸到覆盖所述显示区的所述玻璃基板的一侧边的上表面。其中所述显示区还包括：缓冲层、薄膜晶体管、多条信号线及像素电极。所述缓冲层设置于所述玻璃基板上，且与所述柔性衬底接触。所述薄膜晶体管设置于所述缓冲层及所述柔性衬底上方。所述多条信号线与所述薄膜晶体管的栅极同层设置。所述像素电极，设置于所述薄膜晶体管上，且与所述薄膜晶体管连接。所述弯折区还包括多条绑定走线，所述多条绑定走线设置于所述柔性衬底上，且所述多条绑定走线分别与所述显示区内的所述多条信号线连接。其中，所述弯折区内的所述柔性衬底适于沿着所述玻璃基板的所述一侧边弯折到所述玻璃基板远离所述薄膜晶体管的一面。
在本申请实施例提供的阵列基板中，所述柔性衬底的材料包括聚酰亚胺。
在本申请实施例提供的阵列基板中，所述柔性衬底的厚度为3微米至100微米。
在本申请实施例提供的阵列基板中，所述缓冲层和所述柔性衬底的膜层厚度相同。
在本申请实施例提供的阵列基板中，所述薄膜晶体管的结构包括背沟道蚀刻型、刻蚀阻挡型及顶栅结构型。
在本申请实施例提供的阵列基板中，所述薄膜晶体管还包括有源层及源漏极，所述有源层设置于所述栅极的下方，所述源漏极设置于所述栅极的两侧。
在本申请实施例提供的阵列基板中，所述有源层的材料包括非晶硅、低温多晶硅或金属氧化物半导体中的一种。
在本申请实施例提供的阵列基板中，所述像素电极的材料包括氧化铟锡。
本申请实施例还提供一种显示面板，其包括前述实施例的阵列基板及设置于所述阵列基板下的覆晶薄膜，所述覆晶薄膜与所述多条绑定走线绑定。
在本申请实施例提供的显示面板中，所述显示面板为液晶显示面板，所述液晶显示面板还包括与所述阵列基板相对设置的彩膜基板、及位于所述阵列基板与所述彩膜基板之间的多个液晶分子。
在本申请实施例提供的显示面板中，所述显示面板为OLED显示面板，所述OLED显示面板还包括设置于所述阵列基板上的发光功能层、及设置于所述发光功能层上的封装层。
本申请实施例还提供一种阵列基板制备方法，其包括以下步骤：步骤S10、提供一玻璃基板，所述玻璃基板划分为显示区和弯折区，在所述玻璃基板的一侧制备缓冲层，在所述玻璃基板的另一侧制备柔性衬底，其中所述缓冲层和部分所述柔性衬底对应所述显示区设置，另一部分所述柔性衬底对应所述弯折区设置。步骤S20、在所述显示区的所述缓冲层及所述柔性衬底上制备薄膜晶体管和像素电极，在制备所述薄膜晶体管的同时在所述显示区制备多条信号线，在所述弯折区的所述柔性衬底上制备多条绑定走线，所述多条信号线分别与所述多条绑定走线连接。步骤S30、去除对应所述弯折区的所述玻璃基板，把裸露出的所述柔性衬底弯折到所述玻璃基板远离所述薄膜晶体管的一面并固定。
在本申请实施例提供的阵列基板制备方法中，所述柔性衬底的材料包括聚酰亚胺。
在本申请实施例提供的阵列基板制备方法中，所述柔性衬底的厚度为3微米至100微米。
在本申请实施例提供的阵列基板制备方法中，所述缓冲层和所述柔性衬底的膜层厚度相同。
在本申请实施例提供的阵列基板制备方法中，所述薄膜晶体管的结构包括背沟道蚀刻型、刻蚀阻挡型及顶栅结构型。
在本申请实施例提供的阵列基板制备方法中，所述薄膜晶体管还包括有源层及源漏极，所述有源层设置于所述栅极的下方，所述源漏极设置于所述栅极的两侧。
在本申请实施例提供的阵列基板制备方法中，所述有源层的材料包括非晶硅、低温多晶硅或金属氧化物半导体中的一种。
在本申请实施例提供的阵列基板制备方法中，在步骤S30中，去除对应所述弯折区的所述玻璃基板的方法包括基板减薄技术、切割、激光烧灼中的至少一种。
在本申请实施例提供的阵列基板制备方法中，在步骤S30中，固定裸露出的所述柔性衬底的固定材料包括双面胶或胶水中的至少一种。
 有益效果
本申请提供的阵列基板及其制备方法以及显示面板中，在阵列基板的玻璃基板一侧制备柔性衬底，然后在玻璃基板上制备薄膜晶体管的同时在柔性衬底上制备绑定走线。阵列基板的阵列工艺完成后，去掉对应弯折区的玻璃基板，把制备有绑定走线的柔性衬底弯折到玻璃基板的背面进行COF绑定，以实现无边框设计。避免了在绑定工艺中使用纳米银胶。解决了现有阵列基板为实现窄边框或无边框在绑定工艺中使用纳米银胶导致良率较低的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的弯折区弯折前的膜层结构侧视示意图。
图2为本申请实施例提供的薄膜晶体管的膜层结构示意图。
图3为本申请实施例提供的阵列基板的部分结构上视示意图。
图4为本申请实施例提供的阵列基板的弯折区弯折后的膜层结构示意图。
图5为本申请实施例提供的阵列基板制备方法的流程示意图。
图6至图7为本申请实施例提供的阵列基板制备方法中各步骤制得膜层结构示意图。
图8为本申请实施例提供的显示面板的第一种结构示意图。
图9为本申请实施例提供的显示面板的第二种结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了理解和便于描述，夸大了一些组件的尺寸和厚度。
参照图1和图2，在一种实施例中，提供一种阵列基板100，如图1所示，所述阵列基板100划分为显示区AA及弯折区BA，所述弯折区BA位于所述显示区AA一侧。所述阵列基板100包括玻璃基板10和柔性衬底60，所述玻璃基板10对应所述显示区AA，所述柔性衬底60对应所述弯折区BA，且所述柔性衬底60从所述弯折区BA延伸到覆盖所述显示区AA的所述玻璃基板10的一侧边11的上表面。其中所述显示区AA还包括：缓冲层20、薄膜晶体管40、多条信号线30、及像素电极50。所述缓冲层20设置于所述玻璃基板10上，且与所述柔性衬底60接触。所述薄膜晶体管40设置于所述缓冲层20及所述柔性衬底60上方。所述多条信号线30与所述薄膜晶体管40的栅极42同层设置。所述像素电极50，设置于所述薄膜晶体管40上，且与所述薄膜晶体管40连接。所述弯折区BA还包括设置于所述柔性衬底60上的多条绑定走线70（图1为阵列基板的膜层结构示意图，示出的为绑定走线70和信号线30的截面示意图，如图3所示为阵列基板的部分结构上视示意图，示出多条绑定走线70和多条信号线30电性连接）。所述多条绑定走线70分别与所述显示区AA内的所述多条信号线30连接。其中，所述弯折区BA的所述柔性衬底60适于沿着所述玻璃基板10的所述一侧边11弯折到所述玻璃基板10远离所述薄膜晶体管40的一面，如图4所示。
具体的，所述薄膜晶体管的结构包括背沟道蚀刻（Back Channel Etch, BCE）型、刻蚀阻挡型（Etch Stop Layer, ESL）及顶栅（Top gate）结构型等。
具体的，如图1和图2所示的薄膜晶体管40以顶栅结构为例说明。具体的如图2所示，所述薄膜晶体管40包括有源层41、栅极42、源漏极43。栅极42设置于有源层41的上方。源漏极43设置于所述栅极42的两侧，所述源漏极43包括源极431和漏极432。有源层41包括掺杂区411和沟道区412，源极431和漏极432分别与有源层41的掺杂区411连接。
具体的，所述有源层41可以采用非晶硅（Amorphous Silicon，a-Si）、低温多晶硅（Low Temperature Poly Silicon，LTPS）或金属氧化物半导体，如铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）等。
具体的，请参照图1和图2，所述显示区AA内还制备有多条信号线30，所述多条信号线30与所述薄膜晶体管40的栅极42同层设置。且所述信号线30与弯折区BA的绑定走线70连接。绑定走线70与柔性衬底60之间的膜层可以包括薄膜晶体管正常制程中的绝缘层80，如栅极绝缘层等。当然本申请信号线与绑定走线之间的连接方式不限于图1示出的，绑定走线可以与信号线同时形成，且绑定走线即是信号线的延伸。或者信号线也可以通过在栅极绝缘层设置过孔连接到绑定走线。或者薄膜晶体管采用底栅时，信号线直接设置在缓冲层20及所述柔性衬底60的表面，并直接连接绑定走线。
进一步的，所述多条信号线30与所述多条绑定走线70连接的部分结构上视示意图如图3所示。为了便于描述，图3仅绘示信号线30、绑定走线70、玻璃基板10及柔性衬底60。多条信号线30设置在所述玻璃基板10的上方，且在显示区AA和弯折区BA的交界处扇出到弯折区BA，分别与弯折区BA内柔性衬底60上的多条绑定走线70连接。
具体的，所述多条信号线包括栅极线、数据线等信号线，如图1和图2示出的信号线即为栅极线。
进一步的，所述阵列基板100还包括位于薄膜晶体管40上方的像素电极50。所述像素电极50可通过过孔与所述源极431或所述漏极432连接。图1和图2示为像素电极50与所述漏极432连接。当然的，所述阵列基板还包括位于所述薄膜晶体管各膜层及与像素电极之间的多层绝缘层，但绝缘层为现有技术且非本申请重点，因此并未特别在图中标示或绘示，在此不再赘述。
具体的，所述像素电极的材料包括氧化铟锡（Indium Tin Oxide，ITO）等透明导电电极材料。
具体的，所述显示区AA的所述缓冲层20设置在所述玻璃基板10上，与所述柔性衬底60同层，且两者的上表面在同一水平面，也即两者的膜层厚度相同。如此可以很好的平衡所述多条绑定走线70与所述多条信号线30的高度差，避免产生断差。当然的，根据实际工艺需求，缓冲层和柔性衬底的膜层厚度也可以不同。
进一步的，所述弯折区BA的柔性衬底60的材料包括聚酰亚胺（Polyimide，PI）等可弯折的柔性材料。
进一步的，所述柔性衬底60的厚度可以根据实际工艺需求，设置范围为3微米至100微米。
进一步的，所述柔性衬底60可以弯折到玻璃基板10的背面，并用双面胶或胶水等其他固定方式固定在所述玻璃基板的背面，以方便进行COF绑定。
在本实施例中，阵列基板的衬底采用玻璃基板与柔性衬底相结合的方式，把绑定走线制备在柔性衬底上。制备有绑定走线的柔性衬底可以弯折到玻璃基板的背面，并进行COF绑定，实现无边框设计。避免使用纳米银胶导致良率较低的问题。
在一种实施例中，提供一种阵列基板制备方法，如图5所示，其包括以下步骤：
步骤S10、提供一玻璃基板，所述玻璃基板划分为显示区和弯折区，在所述玻璃基板的一侧制备缓冲层，在所述玻璃基板的另一侧制备柔性衬底，其中所述缓冲层和部分所述柔性衬底对应所述显示区设置，另一部分所述柔性衬底对应所述弯折区设置。
具体的，根据实际工艺需求，采用化学气相沉积（Chemical Vapor Deposition, CVD）等沉积工艺在所述玻璃基板10的一侧沉积一层无机膜层作为缓冲层20，在所述玻璃基板10的另一侧沉积一层柔性膜层作为柔性衬底60，所述柔性衬底60由所述弯折区BA延伸到所述显示区AA，与所述缓冲层20接触，如图6所示。
进一步的，所述柔性衬底60的材料包括聚酰亚胺等可弯折的柔性材料。
进一步的，所述柔性衬底60的厚度可以根据实际工艺需求进行设置，厚度范围为3微米至100微米。
具体的，所述显示区AA的所述缓冲层20设置在所述玻璃基板10上，与所述柔性衬底60同层，可以很好的平衡所述多条绑定走线与所述多条信号线的高度差，避免产生断差。
步骤S20、在所述显示区的所述缓冲层及所述柔性衬底上制备薄膜晶体管和像素电极，在制备所述薄膜晶体管的同时在所述显示区制备多条信号线，在所述弯折区的所述柔性衬底上制备多条绑定走线，所述多条信号线分别与所述多条绑定走线连接。
具体的，如图7所示，所述显示区AA内的所述玻璃基板10上，制备有缓冲层20及部分所述柔性衬底60。在所述缓冲层20及部分所述柔性衬底60上制备薄膜晶体管40和像素电极50。
具体的，如图2所示，所述薄膜晶体管40包括有源层41、栅极42、源漏极43。栅极42设置于有源层41的上方。源漏极43设置于所述栅极42的两侧，所述源漏极43包括源极431和漏极432。有源层41包括掺杂区411和沟道区412，源极431和漏极432分别与有源层41的掺杂区411连接。
具体的，所述有源层41可以采用非晶硅（Amorphous Silicon，a-Si）、低温多晶硅（Low Temperature Poly Silicon，LTPS）或金属氧化物半导体，如铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）等。
进一步的，在所述缓冲层20及部分所述柔性衬底60上制备薄膜晶体管40的同时，在所述显示区AA制备多条信号线30，在所述弯折区BA的所述柔性衬底60上制备多条绑定走线70，多条绑定走线70与所述柔性衬底60之间还设置有绝缘层80，多条信号线30分别与多条绑定走线70连接，如图7所示。
进一步的，所述像素电极50通过过孔与所述源极或所述漏极连接。当然的，所述阵列基板还包括位于所述薄膜晶体管各膜层及与像素电极之间的多层绝缘层，在此不再赘述。
具体的，所述像素电极的材料包括氧化铟锡（Indium Tin Oxide，ITO）等透明导电电极材料。
步骤S30、去除对应所述弯折区的所述玻璃基板，把裸露出的所述柔性衬底弯折到所述玻璃基板远离所述薄膜晶体管的一面并固定。
具体的，采用基板减薄技术、切割、激光烧灼等工艺中的至少一种，去除对应所述弯折区BA的所述玻璃基板10，形成如图1所示的结构。
进一步的，如图4所示，去除对应所述弯折区的所述玻璃基板后，把制备有多条绑定走线70的所述柔性衬底60弯折到所述玻璃基板10的背面（也即远离所述薄膜晶体管40的一面）。
进一步的，使用双面胶或胶水或其他固定方式把弯折到所述玻璃基板背面的所述柔性衬底固定在所述玻璃基板上。
在一种实施例中，提供一种显示面板，其包括前述实施例中的阵列基板及设置于所述阵列基板下的覆晶薄膜，所述覆晶薄膜与所述多条绑定走线绑定。
具体的，所述显示面板为液晶显示面板，如图8所示，所述液晶显示面板1000包括阵列基板100、与所述阵列基板100相对设置的彩膜基板300以及位于所述阵列基板100和彩膜基板300之间的多个液晶分子200。所述液晶显示面板1000还包括覆晶薄膜400，所述覆晶薄膜400与所述柔性衬底60上的多条绑定走线70绑定。
具体的，所述显示面板为OLED显示面板，如图9所示，所述OLED显示面板1001包括阵列基板100、设置于所述阵列基板100上的发光功能层500及设置于所述发光功能层500上的封装层600。所述OLED显示面板1001还包括覆晶薄膜400，所述覆晶薄膜400与所述柔性衬底60上的多条绑定走线70绑定。
需要说明的是，本申请采用玻璃基板与柔性衬底相结合的方式，把绑定走线制备在柔性衬底上。然后把制备有绑定走线的柔性衬底弯折到玻璃基板的背面，并进行覆晶薄膜COF绑定，实现无边框设计的方法，不限于本申请实施例提供的阵列基板。该无边框设计方法同样适用于GOA（Gate Driver on Array，阵列基板行驱动）基板或COA（Color-filter on Array，阵列上彩色滤光片）基板等，在此不再赘述。
根据上述实施例可知：
本申请提供一种阵列基板及其制备方法以及显示面板，在阵列基板的玻璃基板一侧制备柔性衬底，然后在玻璃基板上制备薄膜晶体管的同时在柔性衬底上制备绑定走线。阵列基板的阵列工艺完成后，去掉柔性衬底下方的玻璃基板，把柔性衬底弯折到玻璃基板的背面进行COF绑定，以实现无边框设计。避免了在绑定工艺中使用纳米银胶。解决了现有阵列基板为实现窄边款或无边框在绑定工艺中使用纳米银胶导致良率较低的问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其划分为显示区及弯折区，所述弯折区位于所述显示区一侧，所述阵列基板包括玻璃基板和柔性衬底，所述玻璃基板对应所述显示区，所述柔性衬底对应所述弯折区，且所述柔性衬底从所述弯折区延伸到覆盖所述显示区的所述玻璃基板的一侧边的上表面；其中所述显示区还包括：
    缓冲层，设置于所述玻璃基板上，且与所述柔性衬底接触；
    薄膜晶体管，设置于所述缓冲层及所述柔性衬底上方；
    多条信号线，与所述薄膜晶体管的栅极同层设置；以及
    像素电极，设置于所述薄膜晶体管上，且与所述薄膜晶体管连接；
    所述弯折区还包括多条绑定走线，所述多条绑定走线设置于所述柔性衬底上，且所述多条绑定走线分别与所述显示区内的所述多条信号线连接；
    其中，所述弯折区的所述柔性衬底适于沿着所述玻璃基板的所述一侧边弯折到所述玻璃基板远离所述薄膜晶体管的一面。
  2. 根据权利要求1所述的阵列基板，其中，所述柔性衬底的材料包括聚酰亚胺。
  3. 根据权利要求1所述的阵列基板，其中，所述柔性衬底的厚度为3微米至100微米。
  4. 根据权利要求1所述的阵列基板，其中，所述缓冲层和所述柔性衬底的膜层厚度相同。
  5. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管的结构包括背沟道蚀刻型、刻蚀阻挡型及顶栅结构型。
  6. 根据权利要求5所述的阵列基板，其中，所述薄膜晶体管还包括有源层及源漏极，所述有源层设置于所述栅极的下方，所述源漏极设置于所述栅极的两侧。
  7. 根据权利要求6所述的阵列基板，其中，所述有源层的材料包括非晶硅、低温多晶硅或金属氧化物半导体中的一种。
  8. 根据权利要求1所述的阵列基板，其中，所述像素电极的材料包括氧化铟锡。
  9. 一种显示面板，其包括如权利要求1所述的阵列基板及设置于所述阵列基板下的覆晶薄膜，所述覆晶薄膜与所述多条绑定走线绑定。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板为液晶显示面板，所述液晶显示面板还包括与所述阵列基板相对设置的彩膜基板、及位于所述阵列基板与所述彩膜基板之间的多个液晶分子。
  11. 根据权利要求9所述的显示面板，其中，所述显示面板为OLED显示面板，所述OLED显示面板还包括设置于所述阵列基板上的发光功能层、及设置于所述发光功能层上的封装层。
  12. 一种阵列基板制备方法，其包括以下步骤：
    步骤S10、提供一玻璃基板，所述玻璃基板划分为显示区和弯折区，在所述玻璃基板的一侧制备缓冲层，在所述玻璃基板的另一侧制备柔性衬底，其中所述缓冲层和部分所述柔性衬底对应所述显示区设置，另一部分所述柔性衬底对应所述弯折区设置；
    步骤S20、在所述显示区的所述缓冲层及所述柔性衬底上制备薄膜晶体管和像素电极，在制备所述薄膜晶体管的同时在所述显示区制备多条信号线，在所述弯折区的所述柔性衬底上制备多条绑定走线，所述多条信号线分别与所述多条绑定走线连接；以及
    步骤S30、去除对应所述弯折区的所述玻璃基板，把裸露出的所述柔性衬底弯折到所述玻璃基板远离所述薄膜晶体管的一面并固定。
  13. 根据权利要求12所述的阵列基板制备方法，其中，所述柔性衬底的材料包括聚酰亚胺。
  14. 根据权利要求12所述的阵列基板制备方法，其中，所述柔性衬底的厚度为3微米至100微米。
  15. 根据权利要求12所述的阵列基板制备方法，其中，所述缓冲层和所述柔性衬底的膜层厚度相同。
  16. 根据权利要求12所述的阵列基板制备方法，其中，所述薄膜晶体管的结构包括背沟道蚀刻型、刻蚀阻挡型及顶栅结构型。
  17. 根据权利要求16所述的阵列基板制备方法，其中，所述薄膜晶体管还包括有源层及源漏极，所述有源层设置于所述栅极的下方，所述源漏极设置于所述栅极的两侧。
  18. 根据权利要求17所述的阵列基板制备方法，其中，所述有源层的材料包括非晶硅、低温多晶硅或金属氧化物半导体中的一种。
  19. 根据权利要求12所述的阵列基板制备方法，其中，在步骤S30中，去除对应所述弯折区的所述玻璃基板的方法包括基板减薄技术、切割、激光烧灼中的至少一种。
  20. 根据权利要求12所述的阵列基板制备方法，其中，在步骤S30中，固定裸露出的所述柔性衬底的固定材料包括双面胶或胶水中的至少一种。
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