WO2019000912A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2019000912A1
WO2019000912A1 PCT/CN2018/072560 CN2018072560W WO2019000912A1 WO 2019000912 A1 WO2019000912 A1 WO 2019000912A1 CN 2018072560 W CN2018072560 W CN 2018072560W WO 2019000912 A1 WO2019000912 A1 WO 2019000912A1
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WIPO (PCT)
Prior art keywords
substrate
disposed
layer
conductive
display panel
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PCT/CN2018/072560
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English (en)
French (fr)
Inventor
孙乐
张伟
唐乌力吉白尔
潘正文
石天雷
王晓杰
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/080,119 priority Critical patent/US11237437B2/en
Publication of WO2019000912A1 publication Critical patent/WO2019000912A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H10K59/1275—Electrical connections of the two substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/48—Flattening arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0215—Bonding to the substrate
    • H01S5/0216—Bonding to the substrate using an intermediate compound, e.g. a glue or solder
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • At least one embodiment of the present disclosure is directed to a display panel, a method of fabricating the same, and a display device.
  • Touch screens also known as touch panels, have been widely used in various electronic products and are widely accepted by consumers.
  • the embedded capacitive touch screen integrates the touch electrode structure into the display screen, has the advantages of simple structure, lightness, thinness and low cost, and is increasingly becoming the mainstream technology of the touch screen, and is more and more widely used in various portable intelligent terminals (such as a mobile phone).
  • the in-cell capacitive touch screen can be divided into On-Cell touch screen and In-Cell touch screen.
  • the In-Cell touch screen can be divided into Hybrid In-Cell (HIC) capacitive touch screen and fully in-line (Full In- Cell, FIC) capacitive touch screen.
  • HIC Hybrid In-Cell
  • FIC Full In- Cell
  • At least one embodiment of the present disclosure provides a display panel, a method of manufacturing the same, and a display device.
  • a display panel including a first substrate and a second substrate disposed opposite to each other, wherein the first substrate includes a display area and a peripheral area, and is disposed in a peripheral area of the first substrate The conductive portion is electrically connected to the ground portion.
  • the second substrate includes a display area and a peripheral area, wherein a black matrix is disposed at least in a peripheral area of the second substrate, and the black matrix is electrically connected to the conductive part.
  • the conductive portion includes at least one first conductive layer, and the first conductive layer is respectively disposed in the same layer as the conductive layer in the first substrate display region.
  • a thickness of the first conductive layer in a peripheral region of the first substrate is larger than a layer disposed in a same layer as the first conductive layer in the first substrate display region. a thickness of the conductive layer, and the first conductive layer is electrically connected to the black matrix.
  • the conductive layer in the display area of the first substrate includes a light shielding layer, and the first conductive layer is disposed in the same layer as the light shielding layer.
  • a thin film transistor is disposed in a display region of the first substrate, the thin film transistor includes a gate and a source/drain, the first conductive layer and the The gate or the metal layer to which the source/drain belongs is disposed in the same layer.
  • the conductive portion further includes an insulating layer and a second conductive layer, wherein the insulating layer covers the first conductive layer, and the second conductive layer passes the At least one via in the insulating layer is electrically connected to the first conductive layer, and the second conductive layer is electrically connected to the black matrix.
  • the first substrate further includes a pixel electrode, and the second conductive layer is disposed in the same layer as the pixel electrode.
  • the first substrate further includes a common electrode, and the second conductive layer is disposed in the same layer as the common electrode.
  • the black matrix is further disposed in a display area of the second substrate, and a thickness of a black matrix disposed in a peripheral area of the second substrate is greater than The second substrate displays the thickness of the black matrix in the region.
  • the conductive portion is disposed around a peripheral region of the first substrate and encloses a circle, and the black matrix is disposed at a portion of the peripheral region of the second substrate. Enclosed in a circle, and the conductive portion is in contact with the black matrix.
  • the second substrate further includes a flat layer disposed in the display area of the second substrate, the flat layer covering black in the display area of the second substrate a matrix, and a thickness of the black matrix disposed in the peripheral region of the second substrate is equal to a sum of a thickness of a black matrix disposed in the display region of the second substrate and a thickness of the flat layer.
  • a display panel according to an embodiment of the present disclosure further includes a sealant, and the sealant is disposed on a side of the conductive portion facing the display area of the first substrate.
  • a display panel according to an embodiment of the present disclosure further includes a conductive paste, and the conductive portion is electrically connected to the ground portion through the conductive paste.
  • a display panel provided by an embodiment of the present disclosure is a fully in-cell capacitive touch screen.
  • At least one embodiment of the present disclosure also provides a display device including the display panel of any of the embodiments of the present disclosure.
  • a display device further includes a metal frame, wherein the ground portion is the metal frame.
  • an embodiment of the present disclosure further provides a method of manufacturing a display panel, including providing a first substrate, and providing a second substrate such that the second substrate is disposed opposite to the first substrate.
  • the first substrate includes a display area and a peripheral area, and a conductive portion is disposed in a peripheral area of the first substrate, the conductive portion is electrically connected to the ground portion;
  • the second substrate includes a display area and a peripheral area
  • the black matrix is disposed at least in a peripheral region of the second substrate, and the black matrix is electrically connected to the conductive portion.
  • FIG. 1A is a top plan view of a display panel adopting a GOA mode according to an embodiment of the present disclosure
  • FIG. 1B is a schematic top plan view of a display panel adopting a COF mode according to an embodiment of the present disclosure
  • Figure 2 is a cross-sectional view taken along line II' of Figure 1A;
  • FIG. 3A is a top plan view corresponding to FIG. 1A in the case of including a frame sealant;
  • FIG. 3B is a top plan view corresponding to FIG. 1B in the case of including a frame sealant
  • Figure 4 is a cross-sectional view taken along line II-II' of Figure 3A;
  • FIG. 5 is a schematic view showing a manner of setting a thickness of a black matrix and a conductive portion
  • FIG. 6 is a cross-sectional view of a first substrate in a display panel according to an embodiment of the present disclosure
  • FIG. 7 is a cross-sectional view showing another first substrate in a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view showing still another first substrate in a display panel according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural view of a conductive adhesive in contact with a surface of a metal frame according to an embodiment of the present disclosure.
  • the FIC uses a single-layer touch trace design and uses the self-capacitance principle.
  • the touch function is realized by means of a finger and a metal layer of the touch function inside the panel to form a capacitor. Based on this, the surface of the color film substrate can no longer be plated with any metal layer, so as not to affect or even completely shield the touch function. Therefore, at present, the surface of the color film substrate of the FIC product has no way to release static electricity, and its anti-ESD (Electro-Static Discharge) ability is weak, and static electricity is difficult to be exported. However, ESD can cause poor device performance and even break down the device and cause permanent damage to the device.
  • ESD Electro-Static Discharge
  • the black matrix material on the side of the color filter substrate has a low resistivity, the resistance is in the mega-ohm range, and the static electricity is generally concentrated on the black matrix, which may cause the panel to display an abnormality.
  • static electricity is easily introduced in the gap between the color filter substrate and the array substrate, thereby puncturing the circuit on the side of the array substrate, resulting in abnormal display of the panel.
  • At least one embodiment of the present disclosure provides a display panel.
  • the display panel includes a first substrate and a second substrate disposed opposite to each other, the first substrate includes a display area and a peripheral area, and a conductive portion is disposed in a peripheral area of the first substrate, and the conductive portion and the ground portion are electrically connection.
  • the second substrate includes a display area and a peripheral area, wherein a black matrix is disposed at least in a peripheral area of the second substrate, and the black matrix is electrically connected to the conductive portion.
  • At least one embodiment of the present disclosure also provides a method of manufacturing the above display panel and a display device including the above display panel.
  • the display panel provided by the embodiment of the present disclosure can derive the static electricity accumulated by the black matrix layer, thereby preventing static electricity from affecting the display effect of the display panel or even damaging the display panel (for example, a fully in-cell capacitive touch screen).
  • the display area and the peripheral area of the first substrate are the areas on the side of the first substrate facing the second substrate, and the display area and the peripheral area of the second substrate are the second substrate. An area on a side facing the first substrate.
  • the conductive adhesive is an adhesive having certain conductive properties after curing or drying, and generally the composition thereof may include a matrix resin, conductive particles, a dispersing additive, an auxiliary agent, etc., and the conductive adhesive passes through the substrate. The bonding of the resin bonds the conductive particles together to form a conductive path to achieve electrical connection of the material to be bonded.
  • embodiments of the present disclosure do not limit the position and connection relationship between the ground portion and the first substrate or the second substrate, as long as the static electricity on the conductive portion electrically connected to the black matrix can be led out in the display panel to release the static electricity.
  • the components can all be used as the grounding portion in the embodiment of the present disclosure. It should be noted that the grounding portion is not limited to be connected to the ground.
  • the metal frame of the display device is discharged when the static electricity is led to the metal frame.
  • the metal frame is connected to Earth, static electricity can also be guided through the earth.
  • the embodiments of the present disclosure can be applied to various display panels such as a liquid crystal display panel and an OLED (Organic Light Emitting Diode) display panel.
  • OLED Organic Light Emitting Diode
  • the following embodiments mainly describe a liquid crystal display panel.
  • the packaging method of the liquid crystal display panel may include COG (chip on glass, connecting the chip and the glass substrate by a conductor), COB (chip on board, directly connecting the bare chip to the printed circuit board with a wire), COF (chip on
  • the film driving method of the liquid crystal display device may be a GOA (gate driver on array) or the like. Embodiments of the present disclosure are not limited to the manner in which these driver chips or driver circuits are arranged.
  • FIG. 1A is a top plan view of a display panel adopting a GOA mode according to an embodiment of the present disclosure
  • FIG. 1B is a schematic top view of a display panel adopting a COF mode according to an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display panel, as shown in FIGS. 1A and 2 (wherein FIG. 2 is a cross-sectional view taken along line II' of FIG. 1A), the display panel includes a first substrate 100 and an oppositely disposed The second substrate 200.
  • the first substrate 100 may be an array substrate, and the side of the first substrate 100 facing the second substrate 200 includes the display region 110 and the peripheral region 120.
  • a conductive portion 30 and a ground portion are provided in the peripheral region 120 of the first substrate 100, and the conductive portion 30 is electrically connected to the ground portion.
  • the first substrate 100 may further include other film layers such as TFTs (Thin Film Transistors). Not specifically shown.
  • the second substrate 200 is an opposite substrate, which may be, for example, a color film substrate, and the side of the second substrate 200 facing the first substrate 100 includes a display region 210 and a peripheral region 220.
  • the orthographic projection of the display region 210 of the second substrate 200 on the first substrate 100 coincides with the display region 110 of the first substrate 100.
  • the black matrix is disposed at least in the peripheral region 220 of the second substrate 200. As shown by 41 in FIG. 2, the black matrix 41 is electrically connected to the conductive portion 30, for example, can be electrically connected by direct contact, and disposed in the peripheral region 220 of the second substrate.
  • the black matrix 41 in the middle can function to block ambient light.
  • the black matrix may also be disposed in the display area 210 of the second substrate 200, as shown by reference numeral 42 in FIG. 2, and may be used to block the scattered light of the liquid crystal layer, prevent color mixing between sub-pixels and prevent Ambient light illuminates the TFT channel.
  • the black matrix 42 disposed in the display region 210 of the second substrate 200 is not shown in FIGS. 1A and 1B, and the material of the black matrix may be an organic material, for example, a black acrylic resin (mainly through Incorporating carbon black).
  • a film layer such as a color filter layer 21 and a flat layer 22 may be disposed in the display region 210 of the second substrate 200.
  • the color filter layer 21 generally includes a plurality of red sub-pixels R. a plurality of green sub-pixels G and a plurality of blue sub-pixels B. It should be noted that only a part of the sub-pixels of the second substrate are shown in FIG. 1A, FIG. 1B and FIG.
  • the conductive portion 30 and the black matrix 41 disposed in the peripheral region 220 of the second substrate can be electrically connected by direct contact, for example, the direct bonding of the conductive portion 30 and the black matrix 41 in a process of a cassette process can be performed. Tight fit for electrical connection.
  • the conductive portion 30 includes at least one first conductive layer disposed in the same layer as the conductive layer in the display region 110 of the first substrate 100, and the thickness of the first conductive layer The thickness of the conductive layer disposed in the same layer as the first conductive layer in the display region 110 of the first substrate 100 is larger.
  • the first conductive layer is electrically connected to the black matrix 41 in the peripheral region of the second substrate, for example, electrical connection can be achieved by direct contact.
  • a light shielding layer 115 is disposed on the glass substrate of the display region of the first substrate 100.
  • the light shielding layer 115 may be directly disposed on the display of the first substrate 100.
  • the glass substrate of region 110 can be used to shield the channel region and prevent the backlight from affecting the channel region.
  • the light shielding layer 115 is obtained by using a metal material, for example, metal molybdenum, and the embodiment includes but is not limited thereto.
  • the first conductive layer may be simultaneously formed in the first substrate peripheral region 120 by one patterning process.
  • the gray mask process may be formed at one time, such that the thickness of the first conductive layer disposed in the first substrate peripheral region 120 is greater than the thickness of the light shielding layer 115 disposed in the first substrate display region 110, where the light shielding is performed.
  • the layer 115 may serve as a corresponding conductive layer of the first conductive layer in the display region 110 of the first substrate 100.
  • FIGS. 1A and 1B are plan views. Since the conductive portion 30 is below the black matrix 41, it cannot be shown, and a region where the conductive portion 30 can be disposed is indicated by a broken line frame in FIGS. 1A and 1B.
  • the conductive portion in this embodiment may be disposed at least in a region where one side of the peripheral region of the first substrate is located. For example, the conductive portion may be disposed only in one side region of the peripheral region of the first substrate, and for example, the conductive portion may be in the periphery. Two or more side regions of the region are disposed, that is, as long as the conductive portion is provided in the peripheral region of the first substrate to achieve electrical connection with the black matrix.
  • the data signal input side of the first substrate 100 is provided with a printed circuit board 60, and the end of the signal line provided on the first substrate 100 passes through the electrode.
  • a pin 62 and a flexible circuit film 61 are connected to the printed circuit board 60. It should be noted that the connection relationship between the signal lines and the electrode pins is not shown in FIGS. 1A and 1B. Since the static electricity on the black matrix can be released through the printed circuit board 60, the ground portion can be the printed circuit board 60.
  • the conductive portion 30 can be electrically connected through the conductive paste 80 and the wires 91 and the printed circuit board 60. Electrical connection of the conductive portion 30 and the wire 91 is achieved by dropping the conductive paste 80 between the conductive portion 30 and the wire 91.
  • the conductive paste 80 can be dropped by an automatic dispensing device. Due to the surface tension, the conductive paste 80 is formed into an elliptical shape and is infiltrated into the conductive portion 30 and the wire 91, thereby realizing the electricity of the conductive portion 30 and the wire 91. connection.
  • the wire 91 is connected to the electrode lead 62 to finally achieve electrical connection of the conductive portion 30 and the printed circuit board 60. Since the static electricity on the black matrix can be released by the printed circuit board 60 electrically connected to the conductive portion 30, the ground portion can be the printed circuit board 60.
  • a flexible circuit film 61 is further disposed between the electrode lead 62 and the printed circuit board 60.
  • the flexible circuit film 61 uses a flexible circuit board as a carrier for packaging the chip, and the chip and the flexible Board bonding. During the packaging process, the flexible circuit film 61 can be bent, so that the printed circuit board 60 can be located on the side of the first substrate away from the second substrate, and then the first substrate and the second substrate are fixed by the package frame.
  • FIG. 1A, FIG. 1B, and FIG. 2 only exemplarily show the case where the conductive paste is dropped, and the shape of the conductive paste does not reflect its true proportion.
  • the number of peripheral regions included in the first substrate is also different according to the packaging manner or the driving manner of the liquid crystal display panel.
  • the display panel shown in FIG. 1A adopts the GOA mode, and one cutting line of the first substrate 100 exceeds the cutting line of the second substrate 200 corresponding to the cutting line, that is, the first substrate 100 includes a peripheral region 120.
  • the first substrate 100 may also include a plurality of peripheral regions.
  • the display panel shown in FIG. 1B adopts a COF mode, and the first substrate 100 is driven by a double gate, and thus the first substrate 100 includes two peripheral regions 130 and 140 in addition to the peripheral region 120.
  • the conductive paste 80 may be located in at least one or a combination of the three peripheral regions.
  • the conductive paste 80 may be disposed on a side of the first substrate 100 on which the printed circuit board 60 is disposed along the plane in which it is located, that is, the side where the peripheral region 120 is as shown in FIGS. 1A and 1B.
  • the conductive paste 80 is disposed on the side where the printed circuit board 60 is located, and the length of the wire 91 can be reduced, thereby reducing the electric resistance of the wire 91, compared to the other side disposed on the first substrate. For example, in FIG.
  • the conductive paste 80 is disposed in the peripheral region 120, and the wires pass only through the peripheral region 120, compared with the case where the conductive paste is disposed in the peripheral region 130 or 140 to pass through the peripheral region 130 or 140 and the peripheral region 120. This can effectively shorten the length of the wire.
  • the conductive paste 80 is disposed on a side of the first substrate on which the printed circuit board 60 is disposed, so that the first substrate provided with the conductive paste can adopt GOA (as shown in FIG. 1A ), COF.
  • GOA as shown in FIG. 1A
  • COF a variety of modes, such as shown in FIG. 1B, have better versatility.
  • the display panel provided in this embodiment may further include a sealant 40, as shown in FIG. 3A, FIG. 3B and FIG. 4 (FIG. 3A is a top view of FIG. 1A in the case of including a frame sealant, and FIG. 3B is a view. 1B is a top plan view in the case of a frame sealant, and FIG. 4 is a cross-sectional view taken along line II-II' of FIG. 3A).
  • the sealant 40 may be disposed on the outer side of the display region 110 of the first substrate 100 and enclose a circle, for example, on a side of the conductive portion 30 facing the display region 110.
  • the sealant 40 can be used for sealing the liquid crystal cell to prevent liquid crystal overflow and moisture intrusion, maintaining the thickness of the periphery of the liquid crystal cell, and adhering the first substrate and the second substrate, so the thickness of the sealant 40 is the first substrate 100 and the second substrate.
  • the thickness of the gap between 200 is achieved.
  • the width of the conductive portion 30 can be designed to be less than 50 ⁇ m, so that the width of the sealant 40 is less affected, and the peeling of the display panel can be well avoided.
  • a conductive portion is disposed in a peripheral region of the first substrate, the conductive portion is electrically connected to the black matrix of the second substrate, and the conductive portion is further electrically connected to the ground portion, so that the black matrix layer can be accumulated.
  • the static electricity is exported to prevent static electricity from affecting the display effect of the display panel or even damaging the display panel.
  • One embodiment of the present disclosure also provides a display panel that differs from the display panel provided in the above embodiment in the method of disposing the conductive portion 30.
  • the gate electrode 71 of the thin film transistor, the gate insulating layer 77, and the active layer may be sequentially disposed on the substrate of the first substrate.
  • 72 and the source/drain electrodes 73, 74, the passivation layer 78, the pixel electrode 75, and the pixel electrode 75 are electrically connected to the drain 74 of the thin film transistor through a via hole in the passivation layer 78.
  • the first conductive layer 310 may be disposed in the same layer as the electrodes in the display region of the first substrate.
  • the first conductive layer 310 of the conductive portion 30 can be formed while forming the electrode in the display region of the first substrate by a gray tone mask process, thereby eliminating the patterning process required for separately forming the first conductive layer 310, thereby Reduce the process flow.
  • a thin film transistor is disposed in the display region of the first substrate, and the thin film transistor includes a gate 71, an active layer 72, a source 73, and a drain 74. Since the gate 71 and the source/drain electrodes 73, 74 are made of metal, such as Metals such as aluminum, copper, and molybdenum have a small electrical resistance.
  • the first conductive layer 310 of the conductive portion 30 may be disposed in the same layer as the gate electrode 71; for example, as shown in FIG. 7, the first conductive layer 310 may be connected to the source/drain 73.
  • 74 are arranged in the same layer; for example, as shown in FIG.
  • two first conductive layers are disposed, which are respectively disposed in the same layer as the gate 71 and the source/drain electrodes 73, 74, that is, the first substrate display area
  • the conductive layer in the middle is a film layer provided by a gate or a source/drain.
  • the thin film transistor can be divided into a top gate type (ie, the gate 71 is located on a side of the active layer 72 away from the substrate) and a bottom gate type (ie, the gate 71 is active).
  • the structure of the thin film transistor is not limited.
  • the first conductive layer 310 of the conductive portion 30 can still be disposed in the same layer as the gate or the source/drain.
  • the following embodiments are mainly described by taking the bottom gate type as an example.
  • the gate signal line in the first substrate is connected to the gate, and the data signal line is connected to the source/drain. Therefore, the first conductive layer 310, the gate 71, and the gate signal line can be formed in the same patterning process. Alternatively, the first conductive layer 310, the source/drain electrodes 73, 74, and the data signal lines may be formed in the same patterning process.
  • the conductive portion 30 may further include an insulating layer 330 and a second conductive layer 320 covering the first conductive layer 310, and the second conductive layer
  • the layer 320 is electrically connected to the first conductive layer 310 through at least one via 33 in the insulating layer 330, and the second conductive layer 320 is electrically connected to the black matrix 41.
  • the number of the via holes 33 can be set as needed, and the second conductive layer and the first conductive layer can be electrically connected. This embodiment of the present disclosure is not limited.
  • the insulating layer 330 may be formed using a material of the gate insulating layer 77 and the passivation layer 78 in the first substrate display region.
  • the gate insulating layer is formed in the peripheral region of the first substrate in the process of forming the gate insulating layer 77.
  • the material simultaneously covers the first conductive layer 310; in the process of forming the active layer 72 on the gate insulating layer 77, the active layer material on the first conductive layer 310 on which the gate insulating layer material is formed is etched away; During formation of the source/drain electrodes 73, 74 on the active layer 72, the source/drain metal layer formed on the first conductive layer 310 is etched away; a passivation layer 78 is formed on the source/drain and passivation In the process of layer via, the passivation layer material is simultaneously covered with the first conductive layer 310 formed with the gate insulating layer material and the via holes 33 are formed, thereby forming the insulating layer 330 of the conductive portion 30 and the insulating layer 330.
  • the via hole 33 penetrates the gate insulating layer material and the passivation layer material to expose a partial region of the first conductive layer 310, so that the second conductive layer 320 formed thereon can be electrically connected to the first conductive layer 310. connection.
  • the insulating layer 330 is not limited to being formed using the material of the gate insulating layer 77 and the passivation layer 78 in the display region of the first substrate.
  • the insulating layer 330 may also be formed using only the material of the passivation layer 78 in the first substrate display region.
  • the second conductive layer 320 of the conductive portion 30 may be disposed in the same layer as the pixel electrode 75 in the first substrate display region.
  • the pixel electrode 75 and the second conductive portion 320 in the peripheral region of the first substrate can be simultaneously formed by one patterning process.
  • the common electrode 76 may be further disposed in the first substrate. Therefore, in this case, the second conductive layer 320 may also be disposed in the same layer as the common electrode 76.
  • the pixel electrode 75 is located between the common electrode 76 and the base substrate.
  • the process of forming the pixel electrode 75 on the passivation layer 78 it may be formed in the peripheral region of the first substrate.
  • the pixel electrode layer is etched away.
  • a portion of the insulating layer 79 corresponding to the via hole 33 in the insulating layer 330 is subjected to a via process to expose a portion of the first conductive layer 310.
  • the common electrode 76 and the second conductive layer 320 in the peripheral region of the first substrate may be simultaneously formed by using one patterning process, thereby making the second conductive layer 320 and the first conductive layer 310 achieves electrical connection.
  • the pixel electrode 75 and the common electrode 76 are transparent electrodes, and are usually made of a transparent metal oxide such as ITO (Indium Tin Oxide) or the like.
  • the film layers of the conductive portions are simultaneously formed in the peripheral regions of the first substrate, and each layer is formed by using a gray mask process.
  • the thickness of the conductive portion disposed in the peripheral region of the first substrate is greater than the thickness disposed in the display region of the first substrate, so that the conductive portion can be processed more easily in the process to form a desired thickness, thereby realizing black The electrical connection of the matrix.
  • the embodiment of the present disclosure does not limit the positional relationship of the pixel electrode 75 and the common electrode 76 in the array substrate.
  • the pixel electrode 75 may be located on the side of the common electrode 76 facing the substrate substrate 10.
  • the pixel electrode 75 may also be located on a side of the common electrode 76 remote from the substrate substrate 10.
  • the first conductive layer of the conductive portion may also be formed simultaneously with the gate or the source/drain of the thin film transistor included in the first substrate (ie, disposed in the same layer), and the insulating layer covering the first conductive layer is also It can be formed using a gate insulating layer and a passivation layer of a thin film transistor.
  • the first conductive layer and the insulating layer covering the first conductive layer may also be formed using other conductive structures or insulating layers on the first substrate in the OLED display panel.
  • the second conductive layer can be formed using a transparent conductive layer on the first substrate in the OLED display panel.
  • the conductive portion includes an insulating layer and a second conductive layer in addition to the first conductive layer, and the film layer structure of the conductive portion may be used once with the corresponding film layer in the first substrate display region.
  • the composition process is set in the same layer.
  • a gray mask process may also be adopted, so that the thickness of the film layer formed in the peripheral region of the first substrate is greater than the thickness of the corresponding film layer in the display region of the first substrate, so that the processing of the conductive portion is more easily performed, so that A certain thickness is achieved to achieve electrical connection with the black matrix to derive static electricity accumulated on the black matrix layer.
  • An embodiment of the present disclosure further provides a display panel, which is different from the above embodiment in that the conductive portion is disposed around the peripheral region of the first substrate and encloses a circle, and the black matrix disposed in the peripheral region of the second substrate is also surrounded. In a circle, and the conductive portion is in contact with the black matrix.
  • the black matrix is also disposed in the display region of the second substrate, as shown in FIG. 42, and the thickness of the black matrix 41 disposed in the peripheral region of the second substrate is greater than that displayed on the second substrate.
  • the black matrix 42 disposed in the display region 210 of the second substrate 200 can be used to block the scattered light of the liquid crystal layer, prevent color mixing between sub-pixels, and prevent ambient light from being irradiated onto the TFT channel.
  • the black matrix 41 disposed in the peripheral region of the second substrate and the black matrix 42 disposed in the display region of the second substrate may be formed by one patterning by a gray mask process, and may be set by the specific mask pattern.
  • the thickness of the black matrix 41 in the peripheral region of the two substrates is greater than the thickness of the black matrix 42 in the display region of the second substrate.
  • the second substrate further includes a flat layer 22 disposed in the second substrate display region, the flat layer 22 covering the black matrix 42 in the second substrate display region, and disposed in the peripheral region of the second substrate
  • the thickness of the black matrix 41 is equal to the sum of the thickness of the black matrix 42 and the thickness of the flat layer 22 disposed in the second substrate display region.
  • the embodiments of the present disclosure include but are not limited thereto.
  • the thickness of the black matrix 41 disposed in the peripheral region of the second substrate may also be greater than the sum of the thickness of the black matrix 42 and the thickness of the flat layer 22 disposed in the second substrate display region. Accordingly, the thickness of the conductive portion 30 is ensured to be in contact with the black matrix 41.
  • the conductive portion and the black matrix are electrically connected and the conductive portion is also electrically connected to the ground portion, so that the static electricity accumulated by the black matrix layer can be led out, thereby preventing static electricity from affecting the display effect of the display panel or even damaging the display panel.
  • the conductive portion is disposed around the peripheral region of the first substrate and encloses a circle
  • the portion of the black matrix disposed in the peripheral region of the second substrate also encloses a circle
  • the conductive portion is in contact with the black matrix, which is equivalent to using conductive
  • the portion and the black matrix enclose the entire panel, and the static electricity that is about to enter the gap between the first substrate and the second substrate can be guided away, thereby achieving the effect of electrostatic shielding.
  • An embodiment of the present disclosure further provides a display device comprising the display panel of any of the above embodiments.
  • the display device is a liquid crystal display device, which may further include a backlight for providing a light source to the display panel, and a polarizer on both sides of the display panel.
  • the display device can also be an OLED display device.
  • the display device provided by the embodiment of the present disclosure may further include a touch electrode structure, such as a Full In-Cell (FIC) capacitive touch screen, and the touch electrode structure is formed in, for example, a liquid crystal cell or an OLED.
  • the display device provided by the embodiment of the present disclosure can improve the electrostatic discharge effect, so that the static electricity can be prevented from affecting the display effect and the touch effect.
  • FIC Full In-Cell
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a touch panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., having any display function.
  • a liquid crystal panel an electronic paper
  • an OLED panel an organic light-emitting diode
  • a touch panel a mobile phone
  • a tablet computer a television
  • a display a notebook computer
  • a digital photo frame a navigator, etc.
  • the display device provided by the embodiment of the present disclosure may further include a metal frame.
  • the ground portion may also be a metal frame.
  • FIG. 9 is a schematic structural diagram of a surface contact of a conductive adhesive with a metal bezel according to an embodiment of the present disclosure.
  • the first substrate 100 and the second substrate 200 are post-casing through the bracket 500 and the metal frame 50 .
  • the conductive adhesive 80 can be brought into contact with the surface of the metal frame 50 to achieve electrical connection between the conductive adhesive 80 and the metal frame 50, because the conductive adhesive is connected to the conductive portion.
  • the conductive portion is electrically connected to the black matrix, so that the static electricity on the black matrix can be led out to the metal frame 50.
  • FIG. 9 only exemplarily shows the case after the conductive paste is dropped, and the shape of the conductive paste does not reflect its true proportion.
  • the technical effects of the display device provided by the embodiments of the present disclosure are consistent with the technical effects of the display panel provided by the above embodiments, that is, the static electricity accumulated by the black matrix layer can be derived, thereby preventing static electricity from affecting the display effect of the display panel or even damaging the display panel.
  • the static electricity that is about to enter the gap between the first substrate and the second substrate can be guided away, thereby achieving the effect of electrostatic shielding.
  • Embodiments of the present disclosure also provide a method of fabricating a display panel.
  • the method may include: providing a first substrate; providing a second substrate and causing the second substrate to be disposed opposite the first substrate.
  • the first substrate includes a display region and a peripheral region, and a conductive portion is disposed in the peripheral region of the first substrate, the conductive portion is electrically connected to the ground portion;
  • the second substrate includes a display region and a peripheral region, and the black matrix is disposed at least on the second substrate Among the peripheral regions, the black matrix is electrically connected to the conductive portion.
  • the method can include the following steps:
  • Step 110 providing a first substrate, forming a conductive portion in a peripheral region of the first substrate, and electrically connecting the conductive portion to the ground portion;
  • Step 120 providing a second substrate, and forming a black matrix in a peripheral region of the second substrate;
  • step 130 the first substrate and the second substrate are paired to make the conductive portion and the black matrix contact, thereby achieving electrical connection between the conductive portion and the black matrix.
  • the first substrate may be an array substrate, and other conventional process steps in the array fabrication process may be included in step 110, for example, further including forming a film structure of the TFTs in the display region of the array substrate.
  • the second substrate may be a color film substrate
  • the step 120 may further include other conventional process steps in the color film manufacturing process, for example, including a color filter layer, a flat layer, and the like for forming a color filter substrate.
  • step 130 other conventional process steps in the manufacturing process of the liquid crystal cell may be included, for example, process steps such as liquid crystal dropping, border glue coating, and the like.
  • each film layer do not reflect the true ratio, and the purpose thereof is intended to schematically explain the basic structure of each film layer of the display panel in the embodiment of the present disclosure and shape.

Abstract

一种显示面板及其制造方法、显示装置。该显示面板包括相对设置的第一基板(100)和第二基板(200)，所述第一基板(100)包括显示区域(110)和周边区域(120)，在所述第一基板(100)的周边区域(120)中设置有导电部(30)，所述导电部(30)与接地部电连接。所述第二基板(200)包括显示区域(210)和周边区域(220)，其中黑矩阵(41)至少设置在所述第二基板(200)的周边区域(220)之中，所述黑矩阵(41)与所述导电部(30)电连接。

Description

显示面板及其制造方法、显示装置
本申请要求于2017年6月27日递交的中国专利申请第201720762032.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的至少一个实施例涉及一种显示面板及其制造方法、显示装置。
背景技术
触摸屏又称为触摸面板，已经在各种电子产品中广泛应用并被消费者广泛接受。内嵌式电容触摸屏将触控电极结构集成在显示屏中，具有结构简单、轻、薄、成本低的优点，越来越成为触摸屏的主流技术，越来越广泛应用于各种便携智能终端(诸如手机)中。内嵌式电容触摸屏可以分为On-Cell触摸屏和In-Cell触摸屏，其中In-Cell触摸屏又可分为复合内嵌式(Hybrid In-Cell，HIC)电容触摸屏和完全内嵌式(Full In-Cell，FIC)电容触摸屏。
发明内容
本公开至少一实施例提供一种显示面板及其制造方法、显示装置。本公开至少一实施例提供一种显示面板，包括相对设置的第一基板和第二基板，其中，所述第一基板包括显示区域和周边区域，在所述第一基板的周边区域中设置有导电部，所述导电部与接地部电连接。所述第二基板包括显示区域和周边区域，其中黑矩阵至少设置在所述第二基板的周边区域之中，所述黑矩阵与所述导电部电连接。
例如，在本公开一实施例提供的显示面板中，所述导电部包括至少一个第一导电层，且所述第一导电层分别与所述第一基板显示区域中的导电层同层设置。
例如，在本公开一实施例提供的显示面板中，所述第一基板周边区域 中所述第一导电层的厚度大于所述第一基板显示区域中与所述第一导电层同层设置的所述导电层的厚度，且所述第一导电层与所述黑矩阵电连接。
例如，在本公开一实施例提供的显示面板中，所述第一基板显示区域中的所述导电层包括遮光层，且所述第一导电层与所述遮光层同层设置。
例如，在本公开一实施例提供的显示面板中，所述第一基板的显示区域中设置有薄膜晶体管，所述薄膜晶体管包括栅极和源/漏极，所述第一导电层与所述栅极或者所述源/漏极所属的金属层同层设置。
例如，在本公开一实施例提供的显示面板中，所述导电部还包括绝缘层和第二导电层，其中所述绝缘层覆盖所述第一导电层，所述第二导电层通过所述绝缘层中的至少一个过孔与所述第一导电层电连接，所述第二导电层与所述黑矩阵电连接。
例如，在本公开一实施例提供的显示面板中，所述第一基板还包括像素电极，所述第二导电层与所述像素电极同层设置。或者，所述第一基板还包括公共电极，所述第二导电层与所述公共电极同层设置。
例如，在本公开一实施例提供的显示面板中，所述黑矩阵还设置在所述第二基板的显示区域中，且设置在所述第二基板周边区域中的黑矩阵的厚度大于设置在所述第二基板显示区域中的黑矩阵的厚度。
例如，在本公开一实施例提供的显示面板中，所述导电部设置在所述第一基板周边区域的四周并围成一圈，所述黑矩阵设置在所述第二基板周边区域的部分围成一圈，且所述导电部与所述黑矩阵接触。
例如，在本公开一实施例提供的显示面板中，所述第二基板还包括设置在所述第二基板显示区域中的平坦层，所述平坦层覆盖所述第二基板显示区域中的黑矩阵，且设置在所述第二基板周边区域中的黑矩阵的厚度等于设置在所述第二基板显示区域中的黑矩阵的厚度和所述平坦层的厚度之和。
例如，本公开一实施例提供的显示面板还包括封框胶，所述封框胶设置在所述导电部朝向所述第一基板显示区域的一侧。
例如，本公开一实施例提供的显示面板还包括导电胶，所述导电部通过所述导电胶与所述接地部电连接。
例如，本公开一实施例提供的显示面板为完全内嵌式电容触摸屏。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例所 述的显示面板。
例如，本公开一实施例提供的显示装置还包括金属边框，其中，所述接地部为所述金属边框。
例如，本公开一实施例还提供一种显示面板的制造方法，包括提供第一基板；提供第二基板且使得所述第二基板与所述第一基板相对设置。其中，所述第一基板包括显示区域和周边区域，在所述第一基板的周边区域中设置有导电部，所述导电部与接地部电连接；所述第二基板包括显示区域和周边区域，其中黑矩阵至少设置在所述第二基板的周边区域之中，所述黑矩阵与所述导电部电连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开实施例提供的一种采用GOA模式的显示面板的俯视示意图；
图1B为本公开实施例提供的一种采用COF模式的显示面板的俯视示意图；
图2为沿图1A中I-I'线的剖视图；
图3A为对应于图1A在包括封框胶情形下的俯视示意图；
图3B为对应于图1B在包括封框胶情形下的俯视示意图；
图4为沿图3A中II-II'线的剖视图；
图5为黑矩阵和导电部的厚度设置方式之一示意图；
图6为本公开实施例提供的显示面板中一种第一基板的剖视示意图；
图7为本公开实施例提供的显示面板中另一种第一基板的剖视示意图；
图8为本公开实施例提供的显示面板中再一种第一基板的剖视示意图；以及
图9为本公开实施例提供的一种导电胶与金属边框的表面接触的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
FIC采用单层触控走线设计，采用的是自电容原理。对于FIC触摸屏，其触控功能的实现是借助手指与面板内部起触控功能的金属层形成电容的方式来实现的。基于此，其彩膜基板表面不能再镀覆任何金属层，以免影响甚至完全屏蔽触控功能。所以，目前FIC产品的彩膜基板表面没有释放静电的途径，其抗ESD(Electro-Static Discharge，静电释放)能力弱，静电不易导出。但是，ESD可能造成器件性能变差，甚至击穿器件而导致器件永久性损坏。
另外，由于彩膜基板侧的黑矩阵材料的电阻率较低，阻值为兆欧级，静电一般集中在黑矩阵上，可能导致面板显示异常。同时，在彩膜基板和阵列基板的缝隙里也很容易导入静电，从而击穿阵列基板侧的电路，导致面板显示异常。
本公开至少一实施例提供一种显示面板。该显示面板包括相对设置的第一基板和第二基板，所述第一基板包括显示区域和周边区域，在所述第一基板的周边区域中设置有导电部，所述导电部与接地部电连接。所述第 二基板包括显示区域和周边区域，其中黑矩阵至少设置在所述第二基板的周边区域之中，所述黑矩阵与所述导电部电连接。本公开至少一实施例还提供了上述显示面板的制造方法以及包括上述显示面板的显示装置。
本公开的实施例提供的显示面板可以将黑矩阵层积累的静电导出，从而可以避免静电影响显示面板的显示效果甚至损坏显示面板(例如完全内嵌式电容触摸屏)。
需要说明的是，在本公开的实施例中，第一基板的显示区域和周边区域为第一基板朝向第二基板的一侧上的区域，第二基板的显示区域和周边区域为第二基板朝向第一基板的一侧上的区域。
另外，在本公开的实施例中，导电胶是一种固化或干燥后具有一定导电性能的胶黏剂，通常其成分可以包括基体树脂、导电粒子、分散添加剂和助剂等，导电胶通过基体树脂的粘接作用把导电粒子结合在一起，形成导电通路，实现被粘材料的电连接。
此外，本公开的实施例不限定接地部与第一基板或第二基板的位置和连接关系，只要是显示面板中可以使与黑矩阵电连接的导电部上的静电导出以使静电得到释放的部件都可以作为本公开实施例中的接地部。需要说明的是，接地部不限定为与大地连接，例如，显示装置的金属边框，静电导出至金属边框上即得到了释放，当然，当显示装置接入三相市电时，金属边框连接到大地，静电也可以通过大地导走。
本公开的实施例可以适用于液晶显示面板、OLED(Organic Light Emitting Diode)显示面板等多种显示面板，以下实施例主要以液晶显示面板为例进行说明。
液晶显示面板的封装方式可包括COG(chip on glass，用导体使芯片与玻璃基板相互连接)、COB(chip on board，用导线将裸露的芯片直接连接到印刷电路板上)、COF(chip on film，芯片安装在薄膜上)等方式，液晶显示装置的栅极驱动方式可采用GOA(gate driver on array，阵列基板行驱动)等方式。本公开的实施例不限于这些驱动芯片或驱动电路的设置方式。
下面结合附图对本公开的实施例及其示例进行详细说明。
图1A为本公开的实施例提供的一种采用GOA模式的显示面板的俯视示意图，图1B为本公开的实施例提供的一种采用COF模式的显示面板的 俯视示意图。
本公开至少一个实施例提供一种显示面板，如图1A和图2所示(其中图2是沿图1A中I-I'线的剖视图)，该显示面板包括相对设置的第一基板100和第二基板200。
例如，第一基板100可以为阵列基板，第一基板100朝向第二基板200的一侧包括显示区域110和周边区域120。在第一基板100的周边区域120中设置有导电部30和接地部(例如，印刷电路板60)，导电部30与接地部电连接。需要说明的是，图2中仅示例性的示出了第一基板100上具有的膜层结构，例如，第一基板100还可以包括TFT(Thin Film Transistor，薄膜晶体管)等其他膜层，图中未具体示出。
例如，第二基板200为对置基板，例如可以为彩膜基板，第二基板200朝向第一基板100的一侧包括显示区域210和周边区域220。第二基板200的显示区域210在第一基板100上的正投影和第一基板100的显示区域110重合。黑矩阵至少设置在第二基板200的周边区域220中，如图2中41所示，黑矩阵41与导电部30电连接，例如可以通过直接接触实现电连接，设置在第二基板周边区域220中的黑矩阵41可以起到遮挡环境光的作用。需要说明的是，黑矩阵还可设置在第二基板200的显示区域210中，如图2中标号42所示位置，可以用于遮挡液晶层的杂乱散射光，防止亚像素之间混色和防止环境光照射到TFT沟道。需要说明的是，在图1A和1B中未示出设置在第二基板200的显示区域210中的黑矩阵42，另外黑矩阵的材料可采用有机材料，例如，黑色的丙烯树脂类(主要通过掺入炭黑)。
例如，如图1A和图2所示，第二基板200的显示区域210中还可以设置有彩色滤光层21、平坦层22等膜层，彩色滤光层21通常包括多个红色子像素R、多个绿色子像素G和多个蓝色子像素B。需要说明的是，图1A、图1B和图2中仅示出了第二基板的部分子像素。
如图2所示，导电部30和设置在第二基板周边区域220中的黑矩阵41可以通过直接接触实现电连接，例如，可以在对盒工艺中直接压合使导电部30和黑矩阵41紧密贴合以实现电连接。
在本公开的至少一个实施例中，导电部30包括至少一个第一导电层，该第一导电层与第一基板100的显示区域110中的导电层同层设置，且第一导电层的厚度大于第一基板100的显示区域110中与第一导电层同层设 置的导电层的厚度。第一导电层与第二基板周边区域中的黑矩阵41电连接，例如，可以通过直接接触实现电连接。
在本公开的实施例的一个示例中，如图2所示，在第一基板100的显示区域的玻璃基板上设置有遮光层115，例如，遮光层115可以直接设置在第一基板100的显示区域110的玻璃基板上，可以用于遮挡沟道区以及防止背光源对沟道区产生影响。遮光层115采用金属材料得到，例如，金属钼，本实施例包括但不限于此。
在第一基板显示区域110中形成遮光层115时，可以采用一次构图工艺同时在第一基板周边区域120中形成第一导电层。例如，可以采用灰色调掩膜工艺一次形成，使上述设置在第一基板周边区域120中的第一导电层的厚度大于设置在第一基板显示区域110中的遮光层115的厚度，这里的遮光层115可以作为第一导电层在第一基板100的显示区域110中对应的导电层。
需要说明的是，图1A和图1B是俯视图，由于导电部30在黑矩阵41的下方，所以无法示出，在图1A和图1B中用虚线框表示导电部30可设置的区域。本实施例中的导电部至少设置在第一基板的周边区域的一边所在的区域即可，例如，导电部可以只在第一基板的周边区域的一边区域设置，又例如，导电部可以在周边区域的两个或更多边区域设置，即只要在第一基板的周边区域中设置有导电部实现和黑矩阵的电连接即可。
例如，在本公开的实施例的一个示例中，如图1A、1B所示，第一基板100的数据信号输入侧设置有印刷电路板60，第一基板100上设置的信号线的末端通过电极引脚62以及柔性电路薄膜61连接到该印刷电路板60。需要说明的是，图1A和图1B中未示出信号线与电极引脚的连接关系。由于黑矩阵上的静电可以通过印刷电路板60得到释放，因此接地部可以为印刷电路板60。
如图1A、图1B和图2所示，导电部30可以通过导电胶80以及导线91和印刷电路板60实现电连接。通过在导电部30和导线91之间滴入导电胶80实现导电部30和导线91的电连接。在本公开实施例中，导电胶80可以通过自动化点胶设备滴入，由于表面张力作用，导电胶80形成椭圆形并浸润到导电部30和导线91，从而实现导电部30和导线91的电连接。导线91连接到电极引脚62从而最终实现导电部30和印刷电路板60 的电连接。由于黑矩阵上的静电可以通过与导电部30电连接的印刷电路板60得到释放，因此接地部可以为印刷电路板60。
另外，如图1A和图1B所示，在电极引脚62与印刷电路板60之间还设置有柔性电路薄膜61，该柔性电路薄膜61运用柔性电路板作封装芯片的载体，将芯片与柔性电路板接合。在封装过程中，可以将柔性电路薄膜61进行弯折，可以使印刷电路板60位于第一基板的远离第二基板的一侧，之后采用封装边框将第一基板和第二基板固定。
需要说明的是，图1A、图1B、图2仅示例性地示出了导电胶滴入后的情形，导电胶的形状并不反映其真实比例。
在本公开的实施例中，根据液晶显示面板的封装方式或驱动方式的不同，第一基板包括的周边区域的数量也不相同。例如，图1A所示的显示面板采用GOA模式，第一基板100的一条切割线超出该切割线对应的第二基板200的切割线，即第一基板100包括一个周边区域120。当然，第一基板100也可以包括多个周边区域。例如，图1B所示的显示面板采用COF模式，其第一基板100采用双边栅极驱动，因此第一基板100除了包括周边区域120外，还包括两个周边区域130和140。导电胶80可以位于这三个周边区域中的至少一个或几个的组合中。
在至少一个实施例中，可以将导电胶80设置于第一基板100沿其所在平面方向设置有印刷电路板60的一侧，即如图1A和图1B中的周边区域120所在的一侧。导电胶80设置于印刷电路板60所在的一侧，相比设置于第一基板的其他侧，可以减小导线91的长度，从而减小导线91的电阻。例如，在图1B中，导电胶80设置于周边区域120中，导线只经过周边区域120，与导电胶设置在周边区域130或140中需经过周边区域130或140以及周边区域120的情形相比，这样可以有效地缩短导线的长度。此外，在本公开的实施例中，将导电胶80设置于第一基板设置有印刷电路板60的一侧，使得设置有导电胶的第一基板可以采用GOA(如图1A所示)、COF(如图1B所示)等多种模式，从而具有较好的通用性。
例如，本实施例提供的显示面板还可以包括封框胶40，如图3A、图3B和图4所示(其中图3A是图1A在包括封框胶情形下的俯视示意图，图3B是图1B在包括封框胶情形下的俯视示意图，图4是沿图3A中II-II'线的剖视图)。封框胶40可以设置在第一基板100的显示区域110的四周 外侧并围成一圈，例如位于导电部30朝向显示区域110的一侧。封框胶40可以用于密封液晶盒防止液晶溢出和水汽侵入，维持液晶盒周边盒厚，以及黏附第一基板和第二基板，所以封框胶40的厚度为第一基板100和第二基板200之间的间隙厚度以达到效果。另外，为了避免出现剥落问题，导电部30的宽度可以设计为小于50μm，这样对封框胶40的宽度影响较小，可以很好地避免显示面板剥落。
在本公开的实施例中，在第一基板的周边区域中设置有导电部，导电部与第二基板的黑矩阵电连接，并且导电部还与接地部电连接，从而可以将黑矩阵层积累的静电导出，避免静电影响显示面板的显示效果甚至损坏显示面板。
本公开的一个实施例还提供一种显示面板，该显示面板与上述实施例中所提供的显示面板的区别在于导电部30的设置方法。
在本公开的实施例的一个示例中，如图6、图7和图8所示，第一基板的衬底基板上可以依次设置有薄膜晶体管的栅极71、栅绝缘层77、有源层72以及源/漏极73、74，钝化层78、像素电极75，像素电极75通过钝化层78中的过孔与薄膜晶体管的漏极74电连接。
例如，如图6、图7和图8所示，第一导电层310可以与第一基板的显示区域中的电极同层设置。这样可以通过一次灰色调掩膜工艺在形成第一基板显示区域中的电极的同时形成导电部30的第一导电层310，以省去单独形成第一导电层310所需的构图工艺，从而可以减少工艺流程。
第一基板的显示区域中设置有薄膜晶体管，薄膜晶体管包括栅极71、有源层72、源极73和漏极74，由于栅极71和源/漏极73、74采用金属制成，如铝、铜、钼等金属，金属的电阻较小。例如，如图6和图8所示，导电部30的第一导电层310可以与栅极71同层设置；又例如，如图7所示，第一导电层310可以与源/漏极73、74同层设置；再例如，如图7所示，设置两层第一导电层，分别与栅极71和源/漏极73、74同层设置，也就是说，上述第一基板显示区域中的导电层为栅极或源/漏极所设置的膜层。
需要说明的是，根据栅极的位置，薄膜晶体管可以分为顶栅型(即栅极71位于有源层72的远离衬底基板的一侧)和底栅型(即栅极71位于有源层72的面向衬底基板的一侧，如图6、图7和图8所示)；根据源/漏极 73、74与有源层72的接触方式，薄膜晶体管可以分为顶接触型(即源/漏极73、74位于有源层72的远离衬底基板的一侧，如图6、图7和图8所示)和底接触型(即源/漏极73、74位于有源层72的面向衬底基板10的一侧)。在本公开的实施例中，对薄膜晶体管的结构不作限定，例如，薄膜晶体管为顶栅型时，导电部30的第一导电层310依然可以与栅极或源/漏极同层设置。以下各实施例主要以底栅型为例进行说明。
此外，第一基板中的栅极信号线与栅极连接，数据信号线与源/漏极连接，因此，第一导电层310、栅极71以及栅极信号线可以在同一构图工艺中形成，或者，第一导电层310、源/漏极73、74和数据信号线可以在同一构图工艺中形成。
在本公开的实施例的另一个示例中，如图6、图7和图8所示，导电部30还可以包括覆盖第一导电层310的绝缘层330和第二导电层320，第二导电层320通过绝缘层330中的至少一个过孔33与第一导电层310电连接，第二导电层320与黑矩阵41电连接。过孔33的数量可以根据需要进行设置，可以实现第二导电层和第一导电层电连接即可，对此本公开的实施例不作限定。
例如，如图6所示，绝缘层330可以利用第一基板显示区域中的栅绝缘层77和钝化层78的材料形成。如图6所示，在利用形成栅极71的栅金属层形成导电部30的第一导电层310后，在形成栅绝缘层77的过程中，在第一基板的周边区域中使栅绝缘层材料同时覆盖第一导电层310；在栅绝缘层77上形成有源层72的过程中，将其上形成有栅绝缘层材料的第一导电层310上的有源层材料刻蚀掉；在有源层72上形成源/漏极73、74的过程中，将形成在第一导电层310上的源/漏金属层刻蚀掉；在源/漏极上形成钝化层78以及钝化层过孔的过程中，使钝化层材料同时覆盖形成有栅绝缘层材料的第一导电层310并形成过孔33，由此形成了导电部30的绝缘层330和绝缘层330中的过孔33。此时，该过孔33贯穿栅绝缘层材料和钝化层材料以暴露出第一导电层310的部分区域，从而使在其上形成的第二导电层320可以与第一导电层310实现电连接。
需要注意的是，根据实际情况，绝缘层330并不限于利用第一基板显示区域中的栅绝缘层77和钝化层78的材料形成。
例如，如图7所示，当第一导电层310与源/漏极73、74同层设置时， 绝缘层330也可以仅利用第一基板显示区域中的钝化层78的材料形成。
本公开的实施例的一个示例中，如图6和图7所示，导电部30的第二导电层320可以与第一基板显示区域中的像素电极75同层设置。这样，在钝化层78上形成像素电极75的过程中，可以采用一次构图工艺同时形成像素电极75和第一基板周边区域中的第二导电部320。
此外，如图8所示，对于采用水平电场模式的显示面板，第一基板中还可以设置有公共电极76。因此，在这种情况下，第二导电层320也可以与公共电极76同层设置。
图8是以像素电极75位于公共电极76与衬底基板之间为例进行说明的，此时，在钝化层78上形成像素电极75的过程中，可以将形成在第一基板周边区域中的像素电极层刻蚀掉。在形成像素电极75和公共电极76之间的绝缘层79的过程中，对该绝缘层79对应绝缘层330中的过孔33的部分进行过孔工艺以暴露出第一导电层310的部分区域；在绝缘层79上方形成公共电极76的过程中，可以采用一次构图工艺同时形成公共电极76和第一基板周边区域中的第二导电层320，从而使第二导电层320与第一导电层310实现电连接。
在本公开的实施例中，像素电极75和公共电极76为透明电极，通常采用透明金属氧化物制作，例如ITO(氧化铟锡)等。
需要说明的是，上述在形成第一基板显示区域各膜层时，同时在第一基板的周边区域中形成导电部的各膜层结构，每形成一层，均可采用灰色调掩膜工艺，使同层设置在第一基板周边区域中的导电部的厚度大于设置在第一基板显示区域中的厚度，这样可以使导电部在工艺上更加容易加工以形成所需要的厚度，从而实现与黑矩阵的电连接。
另外，本公开的实施例不限定像素电极75和公共电极76在阵列基板中的位置关系。例如，如图8所示，像素电极75可以位于公共电极76的面向衬底基板10的一侧。又例如，像素电极75也可以位于公共电极76的远离衬底基板10的一侧。
此外，对于OLED显示面板，导电部的第一导电层也可以与第一基板包括的薄膜晶体管的栅极或源/漏极同时形成(即同层设置)，覆盖第一导电层的绝缘层也可以利用薄膜晶体管的栅绝缘层和钝化层形成。当然，根据实际情况，第一导电层和覆盖第一导电层的绝缘层也可以利用OLED显 示面板中第一基板上的其他导电结构或绝缘层形成。相应地，第二导电层可以利用OLED显示面板中第一基板上的透明导电层形成。
在本公开的一些实施例中，导电部除了包括第一导电层外还包括绝缘层和第二导电层，且导电部的膜层结构均可以与第一基板显示区域中对应的膜层采用一次构图工艺同层设置。形成时例如还可以采用灰色调掩膜工艺，使形成在第一基板周边区域中的膜层厚度大于第一基板显示区域中对应的膜层厚度，这样更易于导电部的工艺加工，使其具有一定的厚度，从而实现与黑矩阵的电连接，以导出黑矩阵层上积累的静电。
本公开的一个实施例还提供一种显示面板，与上述实施例的区别在于，导电部设置在第一基板周边区域的四周并围成一圈，设置在第二基板周边区域的黑矩阵也围成一圈，且所述导电部与所述黑矩阵接触。例如，如图4所示，黑矩阵还设置在第二基板的显示区域中，如图中42所示，且设置在第二基板周边区域中的黑矩阵41的厚度大于设置在第二基板显示区域中的黑矩阵42的厚度。设置在第二基板200的显示区域210中的黑矩阵42，可用于遮挡液晶层的杂乱散射光，防止亚像素之间混色和防止环境光照射到TFT沟道。
例如，上述设置在第二基板周边区域中的黑矩阵41和设置在第二基板显示区域中的黑矩阵42可以通过灰色调掩膜工艺一次构图形成，通过特定的掩膜图案可以使设置在第二基板周边区域中的黑矩阵41的厚度大于第二基板显示区域中的黑矩阵42的厚度。
例如，如图4所示，第二基板还包括设置在第二基板显示区域中的平坦层22，平坦层22覆盖第二基板显示区域中的黑矩阵42，且设置在第二基板周边区域中的黑矩阵41的厚度等于设置在第二基板显示区域中的黑矩阵42的厚度和平坦层22的厚度之和。
需要说明的是，上述关于黑矩阵41和导电部30的厚度设置方式，本公开的实施例包括但不限于此。例如，如图5所示，设置在第二基板周边区域中的黑矩阵41的厚度还可以大于设置在第二基板显示区域中的黑矩阵42的厚度和平坦层22的厚度之和。相应的，导电部30的厚度保证使其可以与黑矩阵41接触即可。
和上述实施例相同，导电部和黑矩阵电连接且导电部还和接地部电连接，这样可以把黑矩阵层积累的静电导出，从而避免静电影响显示面板的 显示效果甚至损坏显示面板。同时，由于导电部设置在第一基板周边区域的四周并围成一圈，黑矩阵设置在第二基板周边区域的部分也围成一圈，且导电部和黑矩阵接触，这样相当于用导电部和黑矩阵将面板整个包裹在里面，可以将即将进入第一基板和第二基板之间缝隙的静电导走，从而达到静电屏蔽的效果。
需要说明的是，在不冲突的情况下，上述实施例中描述的特征可以相互组合以得到新的实施例。
本公开的一个实施例还提供一种显示装置，包括上述任一实施例所述的显示面板。例如，该显示装置为液晶显示装置，其还可以包括用于给显示面板提供光源的背光源，以及位于显示面板两侧的偏光片。该显示装置也可以为OLED显示装置。本公开的实施例提供的显示装置还可以包括触控电极结构，例如可以为完全内嵌式(Full In-Cell，FIC)电容触摸屏，触控电极结构形成在例如液晶盒(cell)内或OLED封装内，由此本公开的实施例提供的显示装置可以改善静电释放效果，从而可以避免静电影响显示效果以及触控效果。
例如，本公开的实施例提供的显示装置可以为：液晶面板、电子纸、OLED面板、触控面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置还可以包括金属边框，当显示面板采用金属边框进行封装时，接地部也可以为金属边框。图9为本公开的实施例提供的一种导电胶与金属边框的表面接触的结构示意图，如图9所示，第一基板100和第二基板200对盒后通过支架500和金属边框50进行固定，通过控制导电胶滴入第一基板100中的量，可以使导电胶80与金属边框50的表面接触以实现导电胶80与金属边框50之间的电连接，因为导电胶连接导电部，导电部与黑矩阵电连接，从而可以实现将黑矩阵上的静电导出至金属边框50上。
需要说明的是，图9仅示例性地示出了导电胶滴入后的情形，导电胶的形状并不反映其真实比例。
本公开的实施例提供的显示装置的技术效果和上述实施例提供的显示面板的技术效果一致，即可以把黑矩阵层积累的静电导出，从而避免静电影响显示面板的显示效果甚至损坏显示面板。同时可以将即将进入第一 基板和第二基板之间缝隙的静电导走，从而达到静电屏蔽的效果。
本公开的实施例还提供一种显示面板的制造方法。例如，该方法可以包括：提供第一基板；提供第二基板且使得第二基板与第一基板相对设置。第一基板包括显示区域和周边区域，在第一基板的周边区域中设置有导电部，导电部与接地部电连接；第二基板包括显示区域和周边区域，黑矩阵至少设置在第二基板的周边区域之中，黑矩阵与导电部电连接。
例如，在一个示例中，该方法可以包括以下步骤：
步骤110，提供第一基板，在第一基板的周边区域中形成有导电部，且使导电部与接地部电连接；
步骤120，提供第二基板，在第二基板的周边区域中形成有黑矩阵；
步骤130，将第一基板和第二基板进行对盒使导电部和黑矩阵接触，进而实现导电部和黑矩阵的电连接。
例如，第一基板可为阵列基板，步骤110中还可以包括阵列制造工程中的其他常规工艺步骤，例如，还包括形成阵列基板显示区域中的TFT的各膜层结构。
例如，第二基板可为彩膜基板，步骤120中还可以包括彩膜制造工程中的其他常规工艺步骤，例如，还包括形成彩膜基板的彩膜滤光层、平坦层等其他结构。
在步骤130前，还可以包括液晶盒制造工程中的其他常规工艺步骤，例如，还包括液晶滴注、边框胶涂布等工艺步骤。
本实施例中关于导电部、黑矩阵以及接地部的具体描述可参考前述实施例中的相应描述，这里不再赘述。
需要说明的是，在本公开的附图中，各个膜层的尺寸和形状并不反映真实的比例，其目的旨在示意性说明本公开的实施例中显示面板的各个膜层的基本结构和形状。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种显示面板，包括：
    相对设置的第一基板和第二基板，其中，
    所述第一基板包括显示区域和周边区域，在所述第一基板的周边区域中设置有导电部，所述导电部与接地部电连接；
    所述第二基板包括显示区域和周边区域，其中黑矩阵至少设置在所述第二基板的周边区域之中，所述黑矩阵与所述导电部电连接。
  2. 根据权利要求1所述的显示面板，其中，所述导电部包括至少一个第一导电层，且所述第一导电层分别与所述第一基板显示区域中的导电层同层设置。
  3. 根据权利要求2所述的显示面板，其中，所述第一基板周边区域中所述第一导电层的厚度大于所述第一基板显示区域中与所述第一导电层同层设置的所述导电层的厚度，且所述第一导电层与所述黑矩阵电连接。
  4. 根据权利要求3所述的显示面板，其中，所述第一基板显示区域中的所述导电层包括遮光层，且所述第一导电层与所述遮光层同层设置。
  5. 根据权利要求3所述的显示面板，其中，所述第一基板的显示区域中设置有薄膜晶体管，所述薄膜晶体管包括栅极和源/漏极，所述第一导电层与所述栅极或者所述源/漏极所属的金属层同层设置。
  6. 根据权利要求5所述的显示面板，其中，所述导电部还包括绝缘层和第二导电层，其中，所述绝缘层覆盖所述第一导电层，所述第二导电层通过所述绝缘层中的至少一个过孔与所述第一导电层电连接，所述第二导电层与所述黑矩阵电连接。
  7. 根据权利要求6所述的显示面板，其中，所述第一基板还包括像素电极，所述第二导电层与所述像素电极同层设置；或者
    所述第一基板还包括公共电极，所述第二导电层与所述公共电极同层设置。
  8. 根据权利要求1-7任一所述的显示面板，其中，所述黑矩阵还设置在所述第二基板的显示区域中，且设置在所述第二基板周边区域中的黑矩阵的厚度大于设置在所述第二基板显示区域中的黑矩阵的厚度。
  9. 根据权利要求8所述的显示面板，其中，所述导电部设置在所述 第一基板周边区域的四周并围成一圈，所述黑矩阵设置在所述第二基板周边区域的部分围成一圈，且所述导电部与所述黑矩阵接触。
  10. 根据权利要求9所述的显示面板，其中，所述第二基板还包括设置在所述第二基板显示区域中的平坦层，所述平坦层覆盖所述第二基板显示区域中的黑矩阵，且
    设置在所述第二基板周边区域中的黑矩阵的厚度等于设置在所述第二基板显示区域中的黑矩阵的厚度和所述平坦层的厚度之和。
  11. 根据权利要求1-10任一所述的显示面板，还包括封框胶，所述封框胶设置在所述导电部朝向所述第一基板显示区域的一侧。
  12. 根据权利要求1-11任一所述的显示面板，还包括导电胶，其中，所述导电部通过所述导电胶与所述接地部电连接。
  13. 根据权利要求1-12任一所述的显示面板，其中，所述显示面板为完全内嵌式电容触摸屏。
  14. 一种显示装置，包括权利要求1-13任一所述的显示面板。
  15. 根据权利要求14所述的显示装置，还包括金属边框，其中，所述接地部为所述金属边框。
  16. 一种显示面板的制造方法，包括：
    提供第一基板；
    提供第二基板且使得所述第二基板与所述第一基板相对设置；
    其中，所述第一基板包括显示区域和周边区域，在所述第一基板的周边区域中设置有导电部，所述导电部与接地部电连接；
    所述第二基板包括显示区域和周边区域，其中黑矩阵至少设置在所述第二基板的周边区域之中，所述黑矩阵与所述导电部电连接。
PCT/CN2018/072560 2017-06-27 2018-01-15 显示面板及其制造方法、显示装置 WO2019000912A1 (zh)

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