WO2020019468A1 - Tft阵列基板及其制造方法与柔性液晶显示面板 - Google Patents

Tft阵列基板及其制造方法与柔性液晶显示面板 Download PDF

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Publication number
WO2020019468A1
WO2020019468A1 PCT/CN2018/107154 CN2018107154W WO2020019468A1 WO 2020019468 A1 WO2020019468 A1 WO 2020019468A1 CN 2018107154 W CN2018107154 W CN 2018107154W WO 2020019468 A1 WO2020019468 A1 WO 2020019468A1
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metal layer
tft array
array substrate
bonding
portions
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PCT/CN2018/107154
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English (en)
French (fr)
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尹炳坤
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武汉华星光电技术有限公司
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Priority to US16/313,048 priority Critical patent/US20200035712A1/en
Publication of WO2020019468A1 publication Critical patent/WO2020019468A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of display technology, and in particular, to a TFT array substrate, a manufacturing method thereof, and a flexible liquid crystal display panel.
  • liquid crystal display devices Liquid Crystal Display, LCD
  • cathode ray tube Cathode Ray Tube, CRT
  • the liquid crystal display device has many advantages such as a thin body, power saving, and no radiation, and has been widely used.
  • a liquid crystal display panel includes a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) and a sealant sandwiched between the color film substrate and the thin film transistor array substrate.
  • Frame (Sealant) composition The working principle of a liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many small vertical and horizontal wires in the middle of the two glass substrates. The liquid crystal molecules are changed in direction by power on or off, and the light of the backlight module is changed. Refracted to produce a picture.
  • a first metal layer including a gate line and a TFT device is fabricated on a substrate.
  • a chip (IC) outside the TFT array substrate it is generally A bonding pad located in the first metal layer is set in a bonding region on the edge of the TFT array substrate, and the pins of the chip are connected to the bonding end, so that the chip is bonded to the first metal layer.
  • Flexible liquid crystal display panels have the characteristics of ultra-thin, light weight, flexible, high design freedom, etc., and have a broad market space in wearable, mobile phone communications, television, commercial advertising and military applications.
  • the substrate of a TFT array substrate used in a flexible liquid crystal display panel is usually made of a flexible material such as polyethylene terephthalate (PET) or polyimide (PI), and has a large thermal expansion coefficient. It is easy to generate thermal expansion, and when the bonding end of the first metal layer is fabricated on the substrate, when the substrate undergoes thermal expansion, the bonding end will also generate corresponding thermal expansion, so that a bond between the bonding end and the pin of the chip will be generated The deflection affects the bonding effect between the first metal layer and the chip. In severe cases, it will cause poor chip bonding and affect the normal display of the display panel.
  • PET polyethylene terephthalate
  • PI polyimide
  • the purpose of the present invention is to provide a TFT array substrate, which can eliminate the problem of the bond and offset between the TFT array substrate and the chip, and improve the chip bond yield of the flexible liquid crystal display panel.
  • Another object of the present invention is to provide a method for manufacturing a TFT array substrate, which can eliminate the problem of the bonding offset between the TFT array substrate and the chip, and improve the chip bonding yield of the flexible liquid crystal display panel.
  • Yet another object of the present invention is to provide a flexible display panel, which can eliminate the problem of the bonding offset between the TFT array substrate and the chip, and improve the chip bonding yield of the flexible liquid crystal display panel.
  • the present invention first provides a TFT array substrate, which includes a flexible substrate, a first metal layer provided on the flexible substrate, an insulating layer covering the first metal layer, and a second metal provided on the insulating layer.
  • a TFT array substrate which includes a flexible substrate, a first metal layer provided on the flexible substrate, an insulating layer covering the first metal layer, and a second metal provided on the insulating layer.
  • the first metal layer includes a plurality of spaced connecting portions; the second metal layer includes a plurality of spaced bonding terminals; each bonding terminal corresponds to a connecting portion; Multiple vias above the connecting portion; multiple bonding terminals are in contact with the corresponding connecting portion via the vias above the corresponding connecting portion, respectively.
  • the material of the flexible substrate is PET or PI.
  • Each bonding terminal includes one end and a trace.
  • the projection of the end in the vertical direction is located on the side of the corresponding connection portion away from the center of the flexible substrate, and one end of the wiring is connected to the end. , The other end is in contact with the corresponding connecting portion through a via hole above the corresponding connecting portion.
  • the shapes of the plurality of connecting portions are all rectangular; the shapes of the plurality of end portions are all rectangular.
  • a plurality of connecting portions are arranged in a straight line, and a plurality of end portions are arranged in a straight line.
  • the arrangement direction of the plurality of connecting portions is parallel to the arrangement direction of the plurality of end portions.
  • the insulating layer is provided with two vias corresponding to each of the connecting portions, and a plurality of bonding terminals are respectively in contact with the corresponding connecting portions through the two vias above the corresponding connecting portions.
  • the TFT array substrate further includes a buffer layer provided on the flexible substrate;
  • the first metal layer is disposed on the buffer layer.
  • the invention also provides a method for manufacturing a TFT array substrate, including the following steps:
  • Step S1 providing a flexible substrate
  • Step S2 forming a buffer layer on the flexible substrate
  • Step S3 depositing and patterning a metal material on the buffer layer to form a first metal layer; the first metal layer includes a plurality of spaced connection portions;
  • Step S4 forming an insulating layer covering the first metal layer, and patterning the insulating layer to form a plurality of vias respectively located above the plurality of connecting portions;
  • Step S5 depositing and patterning a metal material on the insulating layer to form a second metal layer; the second metal layer includes a plurality of spaced bonding terminals; each bonding terminal corresponds to a connection portion; The fixed terminals are in contact with the corresponding connection portions through vias above the corresponding connection portions.
  • the present invention also provides a flexible liquid crystal display panel including the above-mentioned TFT array substrate.
  • the TFT array substrate of the present invention includes a flexible substrate, a first metal layer provided above the flexible substrate, an insulating layer covering the first metal layer, and a second metal layer provided on the insulating layer.
  • a metal layer includes a plurality of spaced-apart connection portions
  • a second metal layer includes a plurality of spaced-apart bond terminals.
  • Each bond terminal corresponds to a connection portion. Holes, multiple bonding terminals are in contact with the corresponding connection portions through vias above the corresponding connection portions, and the bonding terminals are connected to the chip pins so that the TFT array substrate and the chip are bonded, and the flexible substrate is caused by thermal expansion.
  • the expansion of the first metal layer will not cause the chip and the TFT array substrate to bond and deviate, thereby improving the chip bond yield of the flexible liquid crystal display panel.
  • the manufacturing method of the TFT array substrate of the present invention can eliminate the problem of the bonding offset between the TFT array substrate and the chip, and improve the chip bonding yield of the flexible liquid crystal display panel.
  • the flexible display panel of the present invention can eliminate the problem of the bonding offset between the TFT array substrate and the chip, and improve the chip bonding yield of the flexible liquid crystal display panel.
  • FIG. 1 is a schematic cross-sectional view of a TFT array substrate according to the present invention.
  • FIG. 2 is a schematic top view of a TFT array substrate according to the present invention.
  • FIG. 3 is a schematic diagram of relative positions of a first metal layer and a second metal layer of a TFT array substrate according to the present invention
  • FIG. 4 is a flowchart of a method for manufacturing a TFT array substrate according to the present invention.
  • FIG. 5 is a schematic diagram of steps S1 and S2 of the method for manufacturing a TFT array substrate according to the present invention.
  • FIG. 6 and 7 are schematic views of step S3 of the method for manufacturing a TFT array substrate according to the present invention.
  • step S4 of the method for manufacturing a TFT array substrate according to the present invention are schematic diagrams of step S4 of the method for manufacturing a TFT array substrate according to the present invention.
  • the TFT array substrate of the present invention includes a flexible substrate 10, a first metal layer 20 provided above the flexible substrate 10, an insulating layer 30 covering the first metal layer 20, and an insulating layer 30. ⁇ ⁇ ⁇ ⁇ ⁇ 40 ⁇ On the second metal layer 40.
  • the first metal layer 20 includes a plurality of spaced-apart connection portions 21.
  • the second metal layer 40 includes a plurality of spaced bonding terminals 41. Each bonding terminal 41 corresponds to a connecting portion 21.
  • the insulating layer 30 is provided with a plurality of via holes 31 respectively located above the plurality of connecting portions 21. The plurality of bonding terminals 41 are in contact with the corresponding connection portions 21 through the via holes 31 above the corresponding connection portions 21, respectively.
  • the material of the flexible substrate 10 may be a flexible material commonly used to make a substrate in the prior art, for example, it may be PET or PI.
  • the flexible substrate 10 includes a display area and a bonding area located outside the display area, and the connecting portion 21 and the bonding terminal 41 are both disposed corresponding to the bonding area.
  • the first metal layer 20 further includes a plurality of gate lines 22 respectively connected to the plurality of connection portions 21, and the plurality of gate lines 22 are disposed corresponding to the display area.
  • each bonding terminal 41 includes an end portion 411 and a wiring 412.
  • the projection of the end portion 411 in the vertical direction is located at the corresponding connection portion.
  • 21 is a side far from the center of the flexible substrate 10.
  • One end of the trace 412 is connected to the end portion 411, and the other end is in contact with the corresponding connection portion 21 through the via hole 31 above the corresponding connection portion 21.
  • the shapes of the plurality of connecting portions 21 are all rectangular.
  • Each of the plurality of end portions 411 has a rectangular shape.
  • the plurality of connecting portions 21 and the plurality of end portions 411 may also adopt other shapes.
  • the plurality of connecting portions 21 are arranged along a straight line, and the plurality of end portions 411 are arranged along a straight line. Further, the arrangement direction of the plurality of connecting portions 21 is parallel to the arrangement direction of the plurality of end portions 411.
  • the insulating layer 30 is provided with two vias 31 corresponding to each of the connecting portions 21, and the plurality of bonding terminals 41 pass through the two vias 31 and the corresponding connecting portions 21 respectively above the corresponding connecting portions 21. Contact, thereby enhancing the connection effect of each bonding terminal 41 and the corresponding connection portion 21.
  • the TFT array substrate further includes a buffer layer 50 disposed on the flexible substrate 10.
  • the first metal layer 20 is disposed on the buffer layer 50.
  • the TFT array substrate further includes an active layer and a source-drain electrode layer disposed above the first metal layer 20 and insulated from the first metal layer 20, and disposed above the source-drain electrode layer and connected to the source-drain electrode.
  • the electrode layer is an insulating transparent conductive electrode layer.
  • the second metal layer 40 may be disposed on the insulating structure layer between the transparent conductive electrode layer and the source-drain electrode layer.
  • the insulating layer 30 includes the first metal layer 20 and the active layer and the source-drain electrode layer.
  • the insulating structure layer between the layers and the insulating structure layer between the source and drain electrode layers and the transparent conductive electrode layer are laminated.
  • the TFT array substrate of the present invention is provided with a plurality of vias 31 respectively located above the plurality of connecting portions 21 of the first metal layer 20 through the insulating layer 30 on the first metal layer 20, and then the insulating layer 30 A second metal layer 40 is formed thereon, so that the plurality of bonding terminals 41 of the second metal layer 40 respectively contact the plurality of connection portions 21 through the holes 31, so that the plurality of bonding terminals 41 are electrically connected to the first metal layer 40. Therefore, the plurality of bonding terminals 41 are used to bond the TFT array substrate and the pins of the chip so as to bond the chip and the first metal layer 20 to each other.
  • the present invention also provides a method for manufacturing a TFT array substrate, including the following steps:
  • Step S1 referring to FIG. 5, a flexible substrate 10 is provided.
  • the flexible substrate 10 provided in step S1 is formed on a rigid substrate 60.
  • the material of the flexible substrate 10 may be a flexible material commonly used to make a substrate in the prior art, for example, it may be PET or PI.
  • the material of the rigid substrate 60 may be glass.
  • the flexible substrate 10 includes a display area and a bonding area located outside the display area.
  • Step S2 Referring to FIG. 5, a buffer layer 50 is formed on the flexible substrate 10.
  • Step S3 depositing and patterning a metal material on the buffer layer 50 to form a first metal layer 20.
  • the first metal layer 20 includes a plurality of spaced-apart connection portions 21.
  • the connecting portion 21 is provided corresponding to the bonding area.
  • the shapes of the plurality of connecting portions 21 are all rectangular.
  • the plurality of connecting portions 21 may also adopt other shapes.
  • the plurality of connecting portions 21 are arranged along a straight line.
  • step S4 referring to FIGS. 8 and 9, an insulating layer 30 covering the first metal layer 20 is formed, and the insulating layer 30 is patterned to form a plurality of via holes 31 respectively located above the plurality of connecting portions 21.
  • the insulating layer 30 is provided with two vias 31 corresponding to each of the connecting portions 21, so as to enhance the connection effect between the bonding terminal 41 and the corresponding connecting portion 21 made later.
  • the process of forming the insulating layer 30 in step S4 is specifically forming an active layer and a source-drain electrode layer that are insulated from the first metal layer 20 above the first metal layer 20, and forming a contact with the source-drain electrode layer above
  • the source electrode and the drain electrode layer are insulated with a transparent conductive electrode layer.
  • Step S5. a metal material is deposited on the insulating layer 30 and patterned to form a second metal layer 40.
  • the second metal layer 40 includes a plurality of spaced bonding terminals 41. Each bonding terminal 41 corresponds to a connecting portion 21.
  • the plurality of bonding terminals 41 are in contact with the corresponding connection portions 21 through the via holes 31 above the corresponding connection portions 21, respectively.
  • the bonding terminal 41 is provided corresponding to the bonding region.
  • each bonding terminal 41 includes an end portion 411 and a wiring 412.
  • the projection of the end portion 411 in the vertical direction is located at the corresponding connection portion.
  • 21 is a side far from the center of the flexible substrate 10.
  • One end of the trace 412 is connected to the end portion 411, and the other end is in contact with the corresponding connection portion 21 through the via hole 31 above the corresponding connection portion 21.
  • the shapes of the plurality of end portions 411 are all rectangular.
  • the plurality of connecting portions 21 and the plurality of end portions 411 may also adopt other shapes.
  • the plurality of end portions 411 are aligned along a straight line. Further, the arrangement direction of the plurality of connecting portions 21 is parallel to the arrangement direction of the plurality of end portions 411.
  • step S5 a step of separating the rigid substrate 60 from the flexible substrate 10 is further provided.
  • a plurality of vias 31 respectively located above the plurality of connection portions 21 of the first metal layer 20 are provided on the insulating layer 30 on the first metal layer 20, and then A second metal layer 40 is formed on the insulating layer 30, so that the plurality of bonding terminals 41 of the second metal layer 40 respectively contact the plurality of connecting portions 21 through the holes 31, so that the plurality of bonding terminals 41 and the first metal layer 40
  • the electrical connection enables the pins of the TFT array substrate and the chip to be bonded by using the plurality of bonding terminals 41 to bond the chip to the first metal layer 20 even when the flexible metal substrate 10 is thermally expanded to cause the first metal layer 20 to expand.
  • the expansion will not cause a bond misalignment between the pin of the chip and the bond terminal 41, that is, a bond misalignment does not occur between the chip and the TFT array substrate, thereby improving the chip bond of the flexible liquid crystal display panel. Set yield.
  • the present invention also provides a flexible liquid crystal display panel.
  • the flexible liquid crystal display panel includes the above-mentioned TFT array substrate and a chip bound to the TFT array substrate. The description of the structure of the TFT array substrate is not repeated here.
  • the chip has multiple pins, and the multiple pins are respectively bonded to a plurality of bonding terminals 41 of the TFT array substrate, so that the TFT array substrate and the chip are bonded.
  • the TFT array substrate of the flexible liquid crystal display panel of the present invention is provided with a plurality of via holes 31 located above the plurality of connection portions 21 of the first metal layer 20 through the insulating layer 30 on the first metal layer 20, Then, a second metal layer 40 is formed on the insulating layer 30, so that the plurality of bonding terminals 41 of the second metal layer 40 respectively contact the plurality of connection portions 21 through the holes 31, so that the plurality of bonding terminals 41 and the first metal
  • the layer 40 is electrically connected, so that the pins of the TFT array substrate and the chip are bonded by the plurality of bonding terminals 41 so that the chip and the first metal layer 20 are timed, even if the flexible substrate 10 is thermally expanded by the first metal.
  • the expansion of the layer 20 does not cause a bond misalignment between the pin of the chip and the bonding terminal 41, that is, a bond misalignment does not occur between the chip and the TFT array substrate, thereby improving the flexibility of the liquid crystal display panel. Chip bonding yield.
  • the TFT array substrate of the present invention includes a flexible substrate, a first metal layer provided above the flexible substrate, an insulating layer covering the first metal layer, and a second metal layer provided on the insulating layer.
  • the metal layer includes a plurality of spaced connection portions.
  • the second metal layer includes a plurality of spaced bond terminals. Each bond terminal corresponds to a connection portion.
  • the insulating layer is provided with a plurality of via holes respectively above the plurality of connection portions. A plurality of bonding terminals are in contact with the corresponding connection portions through vias above the corresponding connection portions. After connecting the bonding terminals to the chip pins, the TFT array substrate and the chip are bonded, which is caused by thermal expansion of the flexible substrate.
  • the expansion of the first metal layer will not cause the chip and the TFT array substrate to be bonded and displaced, thereby improving the chip bonding yield of the flexible liquid crystal display panel.
  • the manufacturing method of the TFT array substrate of the present invention can eliminate the problem of the bonding offset between the TFT array substrate and the chip, and improve the chip bonding yield of the flexible liquid crystal display panel.
  • the flexible display panel of the present invention can eliminate the problem of the bonding offset between the TFT array substrate and the chip, and improve the chip bonding yield of the flexible liquid crystal display panel.

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Abstract

本发明提供一种TFT阵列基板及其制造方法与柔性液晶显示面板。本发明的TFT阵列基板包括柔性衬底、设于柔性衬底上方的第一金属层、覆盖第一金属层的绝缘层以及设于绝缘层上的第二金属层，第一金属层包括多个间隔的连接部，第二金属层包括多个间隔的邦定端子，每一邦定端子与一连接部对应，绝缘层设有分别位于多个连接部上方的多个过孔，多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触，将邦定端子与芯片的引脚连接使TFT阵列基板与芯片邦定后，柔性衬底受热膨胀引起的第一金属层膨胀并不会导致芯片与TFT阵列基板发生邦定偏位，从而提升柔性液晶显示面板的芯片邦定良率。

Description

TFT阵列基板及其制造方法与柔性液晶显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制造方法与柔性液晶显示面板。
背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
现有的TFT阵列基板在衬底上制作包括栅极线以及TFT器件的第一金属层，为了实现将第一金属层与TFT阵列基板外的芯片(IC)进行邦定(bonding)，一般会在TFT阵列基板边缘的邦定区中设置位于第一金属层中的邦定端(bonding pad)，利用芯片的引脚与邦定端连接，从而实现芯片与第一金属层的邦定。
柔性液晶显示面板具有超薄、质量轻、可绕曲、设计自由度高等特点，在可穿戴、手机通讯、电视、商业广告及军事应用中有着广阔的市场空间。应用于柔性液晶显示面板的TFT阵列基板的衬底通常采用聚对苯二甲酸乙二醇酯(PET)或聚酰亚胺(PI)等柔性材料制作，热膨胀系数较大，在高温环境下极容易产生热膨胀，而第一金属层的邦定端制作在该衬底上时，当衬底发生热膨胀，邦定端也会相应地产生热膨胀，使得邦定端与芯片的引脚之间产生邦定偏位，影响第一金属层与芯片的邦定效果，严重时会造成芯片邦定不良，影响显示面板的正常显示。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。
本发明的另一目的在于提供一种TFT阵列基板的制造方法，能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。
本发明的又一目的在于提供一种柔性显示面板，能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。
为实现上述目的，本发明首先提供一种TFT阵列基板，包括柔性衬底、设于柔性衬底上方的第一金属层、覆盖第一金属层的绝缘层以及设于绝缘层上的第二金属层；
所述第一金属层包括多个间隔的连接部；所述第二金属层包括多个间隔的邦定端子；每一邦定端子与一连接部对应；所述绝缘层设有分别位于多个连接部上方的多个过孔；多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触。
所述柔性衬底的材料为PET或PI。
每一邦定端子均包括一端部及一走线，每一邦定端子中，端部在竖直方向的投影位于对应的连接部远离柔性衬底中心的一侧，走线的一端连接端部，另一端经对应的连接部上方的过孔与对应的连接部接触。
多个连接部的形状均为矩形；多个端部的形状均为矩形。
多个连接部沿直线排列，多个端部沿直线排列。
多个连接部的排列方向与多个端部的排列方向平行。
所述绝缘层于每一连接部上方对应设有两个过孔，多个邦定端子分别经对应的连接部上方的两个过孔与对应的连接部接触。
所述TFT阵列基板还包括设于柔性衬底上的缓冲层；
所述第一金属层设于所述缓冲层上。
本发明还提供一种TFT阵列基板的制造方法，包括如下步骤：
步骤S1、提供柔性衬底；
步骤S2、在柔性衬底上形成缓冲层；
步骤S3、在缓冲层上沉积金属材料并进行图案化，形成第一金属层；所述第一金属层包括多个间隔的连接部；
步骤S4、形成覆盖第一金属层的绝缘层，对绝缘层进行图案化，形成分别位于多个连接部上方的多个过孔；
步骤S5、在绝缘层上沉积金属材料并进行图案化，形成第二金属层；所述第二金属层包括多个间隔的邦定端子；每一邦定端子与一连接部对应； 多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触。
本发明还提供一种柔性液晶显示面板，包括上述TFT阵列基板。
本发明的有益效果：本发明的TFT阵列基板包括柔性衬底、设于柔性衬底上方的第一金属层、覆盖第一金属层的绝缘层以及设于绝缘层上的第二金属层，第一金属层包括多个间隔的连接部，第二金属层包括多个间隔的邦定端子，每一邦定端子与一连接部对应，绝缘层设有分别位于多个连接部上方的多个过孔，多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触，将邦定端子与芯片的引脚连接使TFT阵列基板与芯片邦定后，柔性衬底受热膨胀引起的第一金属层膨胀并不会导致芯片与TFT阵列基板发生邦定偏位，从而提升柔性液晶显示面板的芯片邦定良率。本发明的TFT阵列基板的制造方法能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。本发明的柔性显示面板能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的TFT阵列基板的剖视示意图；
图2为本发明的TFT阵列基板的俯视示意图；
图3为本发明的TFT阵列基板的第一金属层及第二金属层的相对位置示意图；
图4为本发明的TFT阵列基板的制造方法的流程图；
图5为本发明的TFT阵列基板的制造方法的步骤S1及步骤S2的示意图；
图6及图7为本发明的TFT阵列基板的制造方法的步骤S3的示意图；
图8及图9为本发明的TFT阵列基板的制造方法的步骤S4的示意图。
具体实施方式
为更进一步
阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图3，本发明的TFT阵列基板包括柔性衬底10、设于柔性衬底10上方的第一金属层20、覆盖第一金属层20的绝缘层30以及设于绝缘层30上的第二金属层40。
所述第一金属层20包括多个间隔的连接部21。所述第二金属层40包括多个间隔的邦定端子41。每一邦定端子41与一连接部21对应。所述绝缘层30设有分别位于多个连接部21上方的多个过孔31。多个邦定端子41分别经对应的连接部21上方的过孔31与对应的连接部21接触。
具体地，所述柔性衬底10的材料可以为现有技术中常用于制作衬底的柔性材料，例如可以为PET或PI。
具体地，所述柔性衬底10包括显示区及位于显示区外侧的邦定区，所述连接部21及邦定端子41均对应邦定区设置。
具体地，请参阅图3，所述第一金属层20还包括分别与多个连接部21连接的多个栅极线22，多个栅极线22均对应显示区设置。
具体地，请参阅图2及图3，每一邦定端子41均包括一端部411及一走线412，每一邦定端子41中，端部411在竖直方向的投影位于对应的连接部21远离柔性衬底10中心的一侧，走线412的一端连接端部411，另一端经对应的连接部21上方的过孔31与对应的连接部21接触。
具体地，在图2及图3所示的实施例中，多个连接部21的形状均为矩形。多个端部411的形状均为矩形。当然，根据实际的产品需求，多个连接部21及多个端部411也可采用其他形状。
具体地，在图2及图3所示的实施例中，多个连接部21沿直线排列，多个端部411沿直线排列。进一步地，多个连接部21的排列方向与多个端部411的排列方向平行。
优选地，所述绝缘层30于每一连接部21上方对应设有两个过孔31，多个邦定端子41分别经对应的连接部21上方的两个过孔31与对应的连接部21接触，从而增强每一邦定端子41与对应的连接部21的连接效果。
具体地，请参阅图1，所述TFT阵列基板还包括设于柔性衬底10上的缓冲层50。所述第一金属层20设于所述缓冲层50上。
具体地，所述TFT阵列基板还包括设置在第一金属层20上方且与第一金属层20绝缘的有源层及源漏极电极层、设于源漏极电极层上方且与源漏极电极层绝缘的透明导电电极层。所述第二金属层40可设置在透明导电电极层与源漏极电极层之间的绝缘结构层之上，所述绝缘层30由第一金属层20与有源层及源漏极电极层之间的绝缘结构层以及源漏极电极层与透明导电电极层之间的绝缘结构层层叠而成。
需要说明的是，本发明的TFT阵列基板通过在第一金属层20上的绝缘层30设置分别位于第一金属层20的多个连接部21上方的多个过孔31，而后在绝缘层30上形成第二金属层40，使得第二金属层40的多个邦定端子41分别经过孔31对应与多个连接部21接触，从而多个邦定端子41与第一金属层40电性连接，使得利用该多个邦定端子41将TFT阵列基板与芯片的引脚邦定从而将芯片与第一金属层20邦定时，即使柔性衬底10受热膨胀引起的第一金属层20膨胀，也并不会导致芯片的引脚与邦定端子41之间发生邦定偏位，也即芯片与TFT阵列基板之间不会发生邦定偏位，从而提升柔性液晶显示面板的芯片邦定良率。
请参阅图4，基于同一发明构思，本发明还提供一种TFT阵列基板的制造方法，包括如下步骤：
步骤S1、请参阅图5，提供柔性衬底10。
具体地，请参阅图5，所述步骤S1提供的柔性衬底10形成在刚性衬底60上。
具体地，所述柔性衬底10的材料可以为现有技术中常用于制作衬底的柔性材料，例如可以为PET或PI。
具体地，所述刚性衬底60的材料可以为玻璃。
具体地，所述柔性衬底10包括显示区及位于显示区外侧的邦定区。
步骤S2、请参阅图5，在柔性衬底10上形成缓冲层50。
步骤S3、请参阅图6及图7，在缓冲层50上沉积金属材料并进行图案化，形成第一金属层20。所述第一金属层20包括多个间隔的连接部21。
具体地，所述连接部21对应邦定区设置。
具体地，在图7所示的实施例中，多个连接部21的形状均为矩形。当然，根据实际的产品需求，多个连接部21也可采用其他形状。
具体地，在图7所示的实施例中，多个连接部21沿直线排列。
步骤S4、请参阅图8及图9，形成覆盖第一金属层20的绝缘层30，对绝缘层30进行图案化，形成分别位于多个连接部21上方的多个过孔31。
优选地，所述绝缘层30于每一连接部21上方对应设有两个过孔31，从而增强后续制作的邦定端子41与对应的连接部21的连接效果。
具体地，所述步骤S4形成绝缘层30的过程具体为在第一金属层20上方形成与第一金属层20绝缘的有源层及源漏极电极层，在源漏极电极层上方形成与源漏极电极层绝缘的透明导电电极层，由第一金属层20与有源层及源漏极电极层之间的绝缘结构层以及源漏极电极层与透明导电电极层之间的绝缘结构层层叠形成所述绝缘层30。
步骤S5、请参阅图1至图3，在绝缘层30上沉积金属材料并进行图案化，形成第二金属层40。所述第二金属层40包括多个间隔的邦定端子41。每一邦定端子41与一连接部21对应。多个邦定端子41分别经对应的连接部21上方的过孔31与对应的连接部21接触。
具体地，所述邦定端子41对应邦定区设置。
具体地，请参阅图2及图3，每一邦定端子41均包括一端部411及一走线412，每一邦定端子41中，端部411在竖直方向的投影位于对应的连接部21远离柔性衬底10中心的一侧，走线412的一端连接端部411，另一端经对应的连接部21上方的过孔31与对应的连接部21接触。
具体地，在图2及图3所示的实施例中，多个端部411的形状均为矩形。当然，根据实际的产品需求，多个连接部21及多个端部411也可采用其他形状。
具体地，在图2及图3所示的实施例中，多个端部411沿直线排列。进一步地，多个连接部21的排列方向与多个端部411的排列方向平行。
具体地，所述步骤S5之后还设置将刚性衬底60与柔性衬底10分离的步骤。
需要说明的是，本发明的TFT阵列基板的制造方法通过在第一金属层20上的绝缘层30设置分别位于第一金属层20的多个连接部21上方的多个过孔31，而后在绝缘层30上形成第二金属层40，使得第二金属层40的多个邦定端子41分别经过孔31对应与多个连接部21接触，从而多个邦定端子41与第一金属层40电性连接，使得利用该多个邦定端子41将TFT阵列基板与芯片的引脚邦定从而将芯片与第一金属层20邦定时，即使柔性衬底10受热膨胀引起的第一金属层20膨胀，也并不会导致芯片的引脚与邦定端子41之间发生邦定偏位，也即芯片与TFT阵列基板之间不会发生邦定偏位，从而提升柔性液晶显示面板的芯片邦定良率。
基于同一发明构思，本发明还提供一种柔性液晶显示面板。该柔性液晶显示面板包括上述的TFT阵列基板及与所述TFT阵列基板邦定的芯片。在此不再对TFT阵列基板的结构进行重复性描述。所述芯片具有多个引脚，所述多个引脚分别与TFT阵列基板的多个邦定端子41邦定，从而使TFT阵列基板与芯片邦定。
需要说明的是，本发明的柔性液晶显示面板的TFT阵列基板通过在第一金属层20上的绝缘层30设置分别位于第一金属层20的多个连接部21上方的多个过孔31，而后在绝缘层30上形成第二金属层40，使得第二金属层40的多个邦定端子41分别经过孔31对应与多个连接部21接触，从 而多个邦定端子41与第一金属层40电性连接，使得利用该多个邦定端子41将TFT阵列基板与芯片的引脚邦定从而将芯片与第一金属层20邦定时，即使柔性衬底10受热膨胀引起的第一金属层20膨胀，也并不会导致芯片的引脚与邦定端子41之间发生邦定偏位，也即芯片与TFT阵列基板之间不会发生邦定偏位，从而提升柔性液晶显示面板的芯片邦定良率。
综上所述，本发明的TFT阵列基板包括柔性衬底、设于柔性衬底上方的第一金属层、覆盖第一金属层的绝缘层以及设于绝缘层上的第二金属层，第一金属层包括多个间隔的连接部，第二金属层包括多个间隔的邦定端子，每一邦定端子与一连接部对应，绝缘层设有分别位于多个连接部上方的多个过孔，多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触，将邦定端子与芯片的引脚连接使TFT阵列基板与芯片邦定后，柔性衬底受热膨胀引起的第一金属层膨胀并不会导致芯片与TFT阵列基板发生邦定偏位，从而提升柔性液晶显示面板的芯片邦定良率。本发明的TFT阵列基板的制造方法能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。本发明的柔性显示面板能够消除TFT阵列基板与芯片的邦定偏位问题，提升柔性液晶显示面板的芯片邦定良率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板，包括柔性衬底、设于柔性衬底上方的第一金属层、覆盖第一金属层的绝缘层以及设于绝缘层上的第二金属层；
    所述第一金属层包括多个间隔的连接部；所述第二金属层包括多个间隔的邦定端子；每一邦定端子与一连接部对应；所述绝缘层设有分别位于多个连接部上方的多个过孔；多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触。
  2. 如权利要求1所述的TFT阵列基板，其中，所述柔性衬底的材料为PET或PI。
  3. 如权利要求1所述的TFT阵列基板，其中，每一邦定端子均包括一端部及一走线，每一邦定端子中，端部在竖直方向的投影位于对应的连接部远离柔性衬底中心的一侧，走线的一端连接端部，另一端经对应的连接部上方的过孔与对应的连接部接触。
  4. 如权利要求3所述的TFT阵列基板，其中，多个连接部的形状均为矩形；多个端部的形状均为矩形。
  5. 如权利要求3所述的TFT阵列基板，其中，多个连接部沿直线排列，多个端部沿直线排列。
  6. 如权利要求4所述的TFT阵列基板，其中，多个连接部的排列方向与多个端部的排列方向平行。
  7. 如权利要求1所述的TFT阵列基板，其中，所述绝缘层于每一连接部上方对应设有两个过孔，多个邦定端子分别经对应的连接部上方的两个过孔与对应的连接部接触。
  8. 如权利要求1所述的TFT阵列基板，还包括设于柔性衬底上的缓冲层；
    所述第一金属层设于所述缓冲层上。
  9. 一种TFT阵列基板的制造方法，包括如下步骤：
    步骤S1、提供柔性衬底；
    步骤S2、在柔性衬底上形成缓冲层；
    步骤S3、在缓冲层上沉积金属材料并进行图案化，形成第一金属层；所述第一金属层包括多个间隔的连接部；
    步骤S4、形成覆盖第一金属层的绝缘层，对绝缘层进行图案化，形成分别位于多个连接部上方的多个过孔；
    步骤S5、在绝缘层上沉积金属材料并进行图案化，形成第二金属层；所述第二金属层包括多个间隔的邦定端子；每一邦定端子与一连接部对应；多个邦定端子分别经对应的连接部上方的过孔与对应的连接部接触。
  10. 一种柔性液晶显示面板，包括如权利要求1所述的TFT阵列基板。
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