WO2017036110A1 - 阵列基板、其制作方法及显示装置 - Google Patents

阵列基板、其制作方法及显示装置 Download PDF

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Publication number
WO2017036110A1
WO2017036110A1 PCT/CN2016/075326 CN2016075326W WO2017036110A1 WO 2017036110 A1 WO2017036110 A1 WO 2017036110A1 CN 2016075326 W CN2016075326 W CN 2016075326W WO 2017036110 A1 WO2017036110 A1 WO 2017036110A1
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WIPO (PCT)
Prior art keywords
driving circuit
metal trace
array substrate
region
display
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Application number
PCT/CN2016/075326
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English (en)
French (fr)
Inventor
何晓龙
武延兵
王红
刘圣烈
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/324,296 priority Critical patent/US10002887B2/en
Publication of WO2017036110A1 publication Critical patent/WO2017036110A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • the present invention relates to the field of display technologies, and more particularly to an array substrate, a method for fabricating the same, and a display device.
  • Flat panel displays are classified into an emissive flat panel display such as an organic light emitting display and a plasma display, and a non-emissive flat panel display that does not emit light like a liquid crystal display.
  • a conventional flat panel display usually consists of a display panel for displaying an image, a backlight module, a printed circuit board (PCB), and the like.
  • the circuit on the PCB board includes a Timer Control Register (TCON) and a System on Chip (SOC).
  • TCON Timer Control Register
  • SOC System on Chip
  • the thinness of the display panel is a research hotspot, and the backlight module can be fully bonded to the display panel to reduce the thickness; and the PCB circuit board generally needs to be bonded to the back surface (ie, the back surface) of the display panel by tape. Or other locations, occupying a certain amount of modular space.
  • panel manufacturers need to purchase PCB boards to assemble modules, further reducing the profit of the products.
  • an embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device, which can save the printed circuit board portion, achieve display and circuit drive integration, save production time and cost, and reduce the thickness of the panel.
  • the module is light and thin.
  • an embodiment of the present invention provides an array substrate having a display area and a driving circuit area adjacent to the display area;
  • the display area and the driving circuit area have the same base substrate
  • the driving circuit region includes a timing control circuit and/or a system circuit; the timing control circuit is configured to implement timing control on the array substrate; and the system circuit is configured to implement driving control on the array substrate.
  • the array substrate includes a thin film transistor, a passivation layer, and a resin disposed on the display substrate and sequentially disposed on the substrate Layer and common electrode lines;
  • the array substrate further includes a first metal trace, a first insulating layer and a second metal trace, which are disposed on the substrate substrate in the driving circuit region, and are electrically connected to the second metal trace a timing control chip in the connected timing control circuit and/or a system chip in the system circuit;
  • the first metal trace, the second metal trace and the timing control chip constitute the timing control circuit; and/or, the first metal trace, the second metal trace and the system chip constitute the system circuit;
  • the first metal trace and the second metal trace are used to transmit signals provided by the timing control chip and/or the system chip to a display area.
  • the first metal trace located in the driving circuit region is a two-layer structure
  • a gate electrode in the thin film transistor of the display region is in the same layer material as a first layer structure of the first metal trace in the driving circuit region;
  • the source drain of the thin film transistor located in the display region is of the same material as the second layer of the first metal trace located in the drive circuit region.
  • the first insulating layer located in the driving circuit region is a two-layer structure
  • the passivation layer located in the display area is the same material as the first layer structure of the first insulating layer located in the driving circuit region;
  • the resin layer located in the display region and the second layer structure of the first insulating layer located in the driving circuit region are of the same material.
  • the second metal trace located in the driving circuit region is a two-layer structure
  • a second layer structure of the second metal trace located in the driver circuit region is over the first layer structure of the second metal trace.
  • the array substrate further includes a second insulation having a via hole located in the driving circuit region and disposed above the second metal trace
  • the timing control chip or the system chip is electrically connected to the second metal trace through a via of the second insulating layer.
  • the embodiment of the present invention further provides a method for fabricating the above array substrate provided by the embodiment of the present invention, including:
  • the driving circuit area includes a timing control circuit and/or a system circuit; the timing control circuit is configured to implement timing control on the array substrate; The circuit is used to implement drive control of the array substrate.
  • the display area and the driving circuit area on the substrate substrate specifically include:
  • a thin film transistor disposed in the display region and a first metal located in a driving circuit region are formed on the substrate substrate.
  • the graphics of the line specifically include:
  • a pattern of a source layer drain including a thin film transistor in the display region and a second layer structure of the first metal trace in the driver circuit region is formed on the base substrate by the same patterning process.
  • a passivation layer, a resin layer, and the driving circuit disposed on the display region are formed on the base substrate.
  • the pattern of the first insulating layer of the region specifically includes:
  • a pattern including a resin layer located in the display region and a second layer structure of the first insulating layer located in the driving circuit region is formed on the base substrate by the same patterning process.
  • a common electrode line including the display region and a portion located in the driving circuit region are formed on the base substrate.
  • the graphics of the two metal traces specifically include:
  • a pattern of a second layer structure of the second metal traces of the driver circuit region is formed on the first layer structure of the second metal traces of the driver circuit region by a patterning process.
  • the method further includes:
  • the embodiment of the invention further provides a display device, which comprises the above array substrate provided by the embodiment of the invention.
  • the array substrate has a display area and a driving circuit area adjacent to the display area; wherein the display area and the driving circuit area have the same substrate; the driving circuit The area includes timing control circuitry and/or system circuitry; the timing control circuitry is used to implement the alignment Timing control of the column substrate; the system circuit is used to implement drive control of the array substrate. Since the display region and the driving circuit region in the array substrate provided by the embodiment of the present invention are formed on the same substrate, the printed circuit board portion can be omitted, the display and circuit driving integration can be realized, the production time and cost can be saved, and the panel can be reduced.
  • the thickness of the module can be used for transparent display and ultra-thin display.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a method for fabricating an array substrate according to an embodiment of the present invention after each step is performed.
  • each film layer in the drawings do not reflect the true proportion of the array substrate, and the purpose is only to illustrate the contents of the present invention.
  • An embodiment of the present invention provides an array substrate. As shown in FIG. 1 , the array substrate has a display area A and a driving circuit area B adjacent to the display area A.
  • the display area A and the driving circuit area B have the same base substrate 1; the driving circuit area B includes a timing control circuit and/or a system circuit; wherein the timing control circuit is used to implement timing control on the array substrate, and the system circuit is used to implement the pair Drive control of the array substrate.
  • the circuit on the existing printed circuit board PCB includes the timing control circuit TCON and the system circuit SOC.
  • the display region and the driving circuit region are formed on the same substrate.
  • the driving circuit region on the substrate substrate includes a timing control circuit and/or a system circuit, it can be considered that the driving circuit region replaces the PCB portion of the prior art, thereby eliminating the PCB portion and achieving display and circuit driving. Integration, saving production time and cost, reducing the thickness of the panel, making the module light and thin, can be used for transparent display, ultra-thin display.
  • the array substrate may include a thin film transistor and a passivation layer which are disposed on the display substrate A and sequentially disposed on the substrate 1 . 4.
  • the resin layer 5 and the common electrode line 6; the array substrate may further include a first metal trace 7, a first insulating layer 8, and a second metal trace 9 which are disposed on the substrate substrate 1 in the driving circuit region B and are sequentially disposed on the substrate substrate 1.
  • each film layer located in the display area A and each film layer located in the drive circuit area B are made in the same On the base substrate 1, the degree of integration is high, and the module can be made thinner and lighter.
  • the first metal trace 7 and the second metal trace 9 are specifically used for connecting a timing control chip or a system chip necessary for driving the circuit region, forming a timing control circuit or a system circuit, and providing a signal provided by the timing control chip or the system chip. Transfer to the display area, wherein the surface of the second metal trace 9 can serve as a pad area for forming a metal hole for soldering component leads.
  • the first metal trace 7 located in the driving circuit region B may be disposed in a two-layer structure; wherein the film located in the display region A
  • the gate electrode 2 in the transistor and the first layer structure 71 of the first metal trace 7 in the driving circuit region B may be of the same layer material; and the source and drain electrodes 3 in the thin film transistor of the display region A and the driving circuit region
  • the second layer structure 72 of the first metal trace 7 of B can be of the same material.
  • the design of the double metal trace can reduce the resistance of the metal trace of the drive circuit region by increasing the thickness of the metal film (relative to the display).
  • the resistance of the driver circuit region is lower, the process precision and integration are improved, and on the other hand, the first layer structure can be protected by the second layer structure of the first metal trace to prevent the second layer structure from being engraved.
  • the first layer structure is damaged during the etching process; and, in the preparation of the array substrate, no additional preparation process is required, and only the same patterning process is required to form the gate electrode and the first metal.
  • a second pattern layer structure lines of the first pattern layer structure, and only the drain and source can be formed by the same patterning process a first metal wiring, it is possible to save manufacturing costs, improve value-added products.
  • the first insulating layer 8 located in the driving circuit region B may be disposed in a two-layer structure; wherein, the passivation in the display region A is The layer 4 and the first layer structure 81 of the first insulating layer 8 located in the driving circuit region B may be of the same layer; the resin layer 5 located in the display region A and the second layer of the first insulating layer 8 located in the driving circuit region B
  • the structure 82 can be of the same material in the same layer.
  • the double-layer insulating layer can be designed to prevent signal interference by increasing the film thickness of the insulating layer; and, in the preparation of the array substrate, no additional preparation process is required, and only the same patterning process is required.
  • the pattern of the first layer structure of the passivation layer and the first insulating layer can be formed, and the pattern of the second layer structure of the resin layer and the first insulating layer can be formed only by the same patterning process, thereby saving the manufacturing cost and improving Product added value.
  • the second metal trace 9 located in the driving circuit region B may be disposed in a two-layer structure; wherein, the public in the display area A
  • the electrode layer 6 and the first layer structure 91 of the second metal trace 9 located in the driving circuit region B may be of the same material, and the second layer structure 92 of the second metal trace 9 located in the driving circuit region B is located at the second metal.
  • the first layer structure 91 of the line 9 can be separately fabricated.
  • the design of the double metal trace can reduce the resistance of the metal trace of the driving circuit region by increasing the thickness of the metal film (relative to the display area).
  • the resistance of the driver circuit region is lower, the process precision and integration are improved, and on the other hand, the first layer structure can be protected by the second layer structure of the second metal trace to prevent the second layer structure from being etched.
  • the first layer structure is damaged during the process; and only the pattern of the first layer structure of the common electrode line and the second metal trace can be formed by the same patterning process, and the process can be simplified. Preparation costs and enhance value-added products.
  • the array substrate may further include a second via hole disposed in the driving circuit region B and disposed above the second metal trace 9 .
  • the insulating layer 10, the via of the second insulating layer can be used as a pad patterning region for soldering subsequent chips, that is, the timing control chip or the system chip can pass through the via of the second insulating layer 10 and the second metal trace 9 electrical connections.
  • a gate insulating layer, an active layer, a common electrode, a pixel electrode and the like are generally formed on the substrate, and the specific structures may be implemented in various manners. The way is not limited here.
  • an embodiment of the present invention further provides a method for fabricating the above array substrate provided by an embodiment of the present invention.
  • the method for fabricating the array substrate includes:
  • the driving circuit area includes a timing control circuit and/or a system circuit; the timing control circuit is configured to implement timing control on the array substrate; the system circuit Used to implement drive control of the array substrate.
  • the display region and the driving circuit region are simultaneously fabricated on the same substrate, the printed circuit board portion can be omitted, the display and circuit driving integration can be achieved, and the production time can be saved. And the cost, reduce the thickness of the panel, to make the module thin and light, can be used for transparent display, ultra-thin display.
  • the step of forming the display region and the driving circuit region on the substrate substrate may specifically include:
  • the first metal trace and the second metal trace are used to transmit signals provided by the system chip in the timing control chip or the system circuit in the timing control circuit to the display area.
  • a thin film transistor including a display region and a first metal trace located in a driving circuit region are formed on the substrate.
  • the steps of the graphics may be as follows:
  • the gate is located under the active layer, and the formed thin film transistor is a bottom gate type structure.
  • the order of the above steps S101 and S102 may be reversed. I will not repeat them here.
  • a passivation layer, a resin layer, and a region located in the driving circuit region including the display region are formed on the substrate.
  • the step of patterning an insulating layer may specifically be as follows:
  • a common electrode line including a display region and a second metal located at a driving circuit region are formed on the base substrate.
  • the steps of the line graphic specifically include:
  • the method may further include:
  • Step 1 forming, by using the same patterning process, a pattern including a gate layer located in the display region and a first layer structure of the first metal trace located in the driving circuit region on the base substrate, as shown in FIG. 3a;
  • a thin film of a metal material is deposited on the same substrate 1 (such as a glass substrate), and a pattern of the gate 2 is formed in the display region A by one patterning process, and a first metal is formed in the driving circuit region B. a pattern of the first layer structure 71 of the line 7;
  • Step 2 sequentially forming a pattern of a gate insulating layer and an active layer on a gate of the display region by a patterning process, as shown in FIG. 3b;
  • an insulating layer film is deposited on the substrate 1 after the completion of the step 1.
  • the pattern of the gate insulating layer 11 is formed in the display region A by a patterning process, and the insulating layer film located in the driving circuit region B is completely Etching off; then depositing an active layer film on the base substrate 1, forming a pattern of the active layer 12 in the display area A by one patterning process, completely etching the active layer film located in the driving circuit area B ;
  • Step 3 forming a pattern including a source drain of the display region and a second layer structure of the first metal trace located in the driving circuit region on the base substrate by the same patterning process, as shown in FIG. 3c;
  • a thin film of a metal material is deposited on the base substrate 1 of the second step, and a pattern of the source and drain electrodes 3 is formed in the display region A by one patterning process, and a first metal trace is formed in the driving circuit region B.
  • Step 4 forming a pattern of a first layer structure including a passivation layer located in the display region and a first insulating layer located in the driving circuit region on the base substrate by the same patterning process, as shown in FIG. 3d;
  • a passivation layer film is deposited on the substrate of the third step, and a pattern of the passivation layer 4 is formed in the display region A by one patterning process, while the first insulating layer 8 is formed in the driving circuit region B. a pattern of the first layer structure 81;
  • Step 5 forming a pattern of a second layer structure including a resin layer located in the display region and a first insulating layer located in the driving circuit region on the base substrate by the same patterning process, as shown in FIG. 3e;
  • a film of a resin material is deposited on the substrate of the fourth step, and a pattern of the resin layer 5 is formed in the display region A by one patterning process, and the first insulating layer 8 is formed in the driving circuit region B.
  • Step 6 forming a pattern of the common electrode layer on the resin layer located in the display area by a patterning process, as shown in FIG. 3f;
  • a transparent conductive layer film is deposited on the substrate 1 after the step 5 is completed, and the pattern of the common electrode layer 13 is formed in the display region A by one patterning process, and the transparent conductive layer located in the driving circuit region B is formed.
  • the film is completely etched away;
  • Step 7 forming a pattern of a first layer structure including a common electrode line located in the display area and a second metal trace located in the driving circuit area on the base substrate by the same patterning process, as shown in FIG. 3g;
  • a thin film of a metal material is deposited on the substrate of the sixth step, and a pattern of the common electrode line 6 is formed in the display region A by one patterning process, and a first metal trace 9 is formed in the driving circuit region B. a pattern of the first layer structure 91;
  • Step 8 forming a second passivation layer, a pixel electrode layer, and a second layer structure of the second metal trace in the driving circuit region on the substrate substrate by a patterning process, as shown in FIG. 3h. Show
  • a passivation layer film is deposited on the substrate of the seventh step, and a pattern of the second passivation layer 14 is formed in the display region A by a patterning process, and the passivation layer is located in the driving circuit region B.
  • the film is completely etched away; then a thin film of a metal material is deposited on the base substrate 1, and a second metal trace is formed on the first layer structure 91 of the second metal trace 9 located in the drive circuit region B by one patterning process.
  • the pattern of the second layer structure 92 of 9 completely etches away the thin film of the metal material located in the display area A; finally, a transparent conductive layer film is deposited on the substrate, and the pixel electrode layer 15 is formed in the display area A by one patterning process. a pattern in which the transparent conductive layer film located in the drive circuit region B is completely etched away;
  • Step 9 forming a pattern of a second insulating layer having via holes on a second metal trace on the driving circuit region by a patterning process, and the timing control chip or the system chip passes through the via of the second insulating layer and the second metal
  • the wiring is electrically connected, as shown in Figure 3i;
  • a thin film of insulating material is deposited on the base substrate on which the step 8 is completed, and a via having a via hole is formed on the second layer structure 91 of the second metal trace 9 located in the driving circuit region B by one patterning process.
  • the pattern of the second insulating layer 10 completely etches away the insulating material film located in the display area A; the timing control chip or the system chip is electrically connected to the second metal trace through the via of the second insulating layer.
  • the above array substrate provided by the embodiment of the present invention is produced through the above steps 1 to 9 provided by the above specific examples.
  • an embodiment of the present invention further provides a display device, which is provided by the embodiment of the present invention.
  • the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.
  • For the implementation of the display device refer to the embodiment of the above array substrate, and the repeated description is omitted.
  • the array substrate has a display area and a driving circuit area adjacent to the display area; wherein the display area and the driving circuit area have the same substrate; the driving circuit The area includes a timing control circuit and/or a system circuit; a timing control circuit is used to implement timing control on the array substrate; and a system circuit is used to implement driving control of the array substrate. Since the display region and the driving circuit region in the above array substrate provided by the embodiment of the present invention are formed on the same substrate, and the driving circuit region on the substrate substrate includes the timing control circuit and/or the system circuit, the driving can be considered as driving.
  • the circuit area replaces the PCB part of the prior art, thereby eliminating the printed circuit board part, achieving display and circuit drive integration, saving production time and cost, reducing the thickness of the panel, and making the module thin and light, which can be used for Transparent display, ultra-thin display.

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Abstract

一种阵列基板、其制作方法及显示装置，阵列基板具有显示区域（A）和与显示区域相邻的驱动电路区域（B）；其中，显示区域（A）和驱动电路区域（B）具有同一衬底基板（1）；驱动电路区域包括时序控制电路和/或系统电路；时序控制电路用于实现对阵列基板的时序控制；系统电路用于实现对阵列基板的驱动控制。由于上述阵列基板中的显示区域（A）和驱动电路区域（B）形成在同一衬底基板（1）上，又由于在衬底基板（1）上的驱动电路区域（B）包括时序控制电路和/或系统电路，可以认为驱动电路区域（B）代替了现有技术的PCB部分，进而省去PCB部分，达到显示、电路驱动一体化，节省制作时间和费用，降低面板的厚度，做到模组的轻薄化，可以用于透明显示、超薄显示。

Description

阵列基板、其制作方法及显示装置
本申请要求于2015年9月1日递交中国专利局的、申请号为201510552742.X的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本发明涉及显示技术领域，尤指一种阵列基板、其制作方法及显示装置。
背景技术
平板显示器分为诸如有机发光显示器和等离子体显示器的发射型平板显示器以及像液晶显示器一样不发光的非发射型平板显示器。
现有的平板显示器通常是由用于显示图像的显示面板、背光模组、印刷电路板(Printed circuit board，简称PCB)等组成。PCB电路板上的电路包括时序控制电路(Timer Control Register，简称TCON)和系统电路(System on Chip，简称SOC)。目前，显示面板的轻薄化是研究热点，背光模组已经可以做到与显示面板全贴合，以降低厚度；而PCB电路板一般需要通过胶带粘接在显示面板的背表面(即后表面)或其他位置上，占用了一定的模组空间。此外，面板厂商需要购买PCB电路板来进行模组的组装，进一步降低了产品的利润。
发明内容
有鉴于此，本发明实施例提供一种阵列基板、其制作方法及显示装置，可以省去印刷电路板部分，达到显示、电路驱动一体化，节省制作时间和费用，降低面板的厚度，做到模组的轻薄化。
因此，本发明实施例提供了一种阵列基板，所述阵列基板具有显示区域和与显示区域相邻的驱动电路区域；其中，
所述显示区域和所述驱动电路区域具有同一衬底基板；
所述驱动电路区域包括时序控制电路和/或系统电路；所述时序控制电路用于实现对所述阵列基板的时序控制；所述系统电路用于实现对所述阵列基板的驱动控制。
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，所述阵列基板包括位于所述显示区域且依次设置在所述衬底基板上的薄膜晶体管、钝化层、树脂层和公共电极线；
所述阵列基板还包括位于所述驱动电路区域且依次设置在所述衬底基板上的第一金属走线、第一绝缘层和第二金属走线，以及与所述第二金属走线电连接的所述时序控制电路中的时序控制芯片和/或所述系统电路中的系统芯片；
所述第一金属走线、第二金属走线与时序控制芯片构成所述时序控制电路；和/或，所述第一金属走线、第二金属走线与系统芯片构成所述系统电路；
所述第一金属走线和第二金属走线用于将所述时序控制芯片和/或系统芯片提供的信号传输到显示区域。
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，位于所述驱动电路区域的第一金属走线为双层结构；其中，
位于所述显示区域的薄膜晶体管中的栅极与位于所述驱动电路区域的第一金属走线的第一层结构同层同材质；
位于所述显示区域的薄膜晶体管中的源漏极与位于所述驱动电路区域的第一金属走线的第二层结构同材质。
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，位于所述驱动电路区域的第一绝缘层为双层结构；其中，
位于所述显示区域的钝化层与位于所述驱动电路区域的第一绝缘层的第一层结构同层同材质；
位于所述显示区域的树脂层与位于所述驱动电路区域的第一绝缘层的第二层结构同层同材质。
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，位于所述驱动电路区域的第二金属走线为双层结构；其中，
位于所述显示区域的公共电极线与位于所述驱动电路区域的第二金属走线的第一层结构同材质；
位于所述驱动电路区域的第二金属走线的第二层结构位于所述第二金属走线的第一层结构之上。
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，所述阵列基板还包括位于所述驱动电路区域且设置在第二金属走线上方的具有过孔的第二绝缘层；所述时序控制芯片或系统芯片通过所述第二绝缘层的过孔与所述第二金属走线电连接。
本发明实施例还提供了一种本发明实施例提供的上述阵列基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上制作显示区域和驱动电路区域；所述驱动电路区域包括时序控制电路和/或系统电路；所述时序控制电路用于实现对所述阵列基板的时序控制；所述系统电路用于实现对所述阵列基板的驱动控制。
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板的制作方法中，在所述衬底基板上制作显示区域和驱动电路区域具体包括：
在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管、钝化层、树脂层和公共电极线以及位于所述驱动电路区域的第一金属走线、第一绝缘层和第二金属走线的图形；所述第一金属走线和第二金属走线用于将所述时序控制电路中的时序控制芯片和/或所述系统电路中的系统芯片提供的信号传输到显示区域。
在一种可能的实现方式中，本发明实施例提供的上述阵列基板的制作方法中，在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管和位于驱动电路区域的第一金属走线的图形具体包括：
通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管中的栅极和位于所述驱动电路区域的第一金属走线的第一层结构的图形；
通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管中的源漏极和位于所述驱动电路区域的第一金属走线的第二层结构的图形。
在一种可能的实现方式中，本发明实施例提供的上述阵列基板的制作方法中，在所述衬底基板上形成包括位于所述显示区域的钝化层、树脂层和位于所述驱动电路区域的第一绝缘层的图形具体包括：
通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的钝化层和位于所述驱动电路区域的第一绝缘层的第一层结构的图形；
通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的树脂层和位于所述驱动电路区域的第一绝缘层的第二层结构的图形。
在一种可能的实现方式中，本发明实施例提供的上述阵列基板的制作方法中，在所述衬底基板上形成包括位于所述显示区域的公共电极线和位于所述驱动电路区域的第二金属走线的图形具体包括：
通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的公共电极线和位于所述驱动电路区域的第二金属走线的第一层结构的图形；
通过构图工艺在位于所述驱动电路区域的第二金属走线的第一层结构上形成位于所述驱动电路区域的第二金属走线的第二层结构的图形。
在一种可能的实现方式中，本发明实施例提供的上述阵列基板的制作方法中，在所述衬底基板上形成位于所述驱动电路区域的第二金属走线的图形之后，还包括：
通过构图工艺在位于所述驱动电路区域的第二金属走线上形成具有过孔的第二绝缘层的图形；所述时序控制芯片或系统芯片通过所述第二绝缘层的过孔与所述第二金属走线电连接。
本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述阵列基板。
本发明实施例的有益效果包括：
本发明实施例提供的一种阵列基板、其制作方法及显示装置，阵列基板具有显示区域和与显示区域相邻的驱动电路区域；其中，显示区域和驱动电路区域具有同一衬底基板；驱动电路区域包括时序控制电路和/或系统电路；时序控制电路用于实现对阵 列基板的时序控制；系统电路用于实现对阵列基板的驱动控制。由于本发明实施例提供的上述阵列基板中的显示区域和驱动电路区域形成在同一衬底基板上，可以省去印刷电路板部分，达到显示、电路驱动一体化，节省制作时间和费用，降低面板的厚度，做到模组的轻薄化，可以用于透明显示、超薄显示。
附图说明
图1为本发明实施例提供的阵列基板的结构示意图；
图2为本发明实施例提供的阵列基板的制作方法流程图；
图3a至图3i分别为本发明实施例提供的阵列基板的制作方法在各步骤执行后的结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的阵列基板、其制作方法及显示装置的具体实施方式进行详细地说明。
其中，附图中各膜层的厚度和形状不反映阵列基板的真实比例，目的只是示意说明本发明内容。
本发明实施例提供了一种阵列基板，如图1所示，阵列基板具有显示区域A和与显示区域A相邻的驱动电路区域B；其中，
显示区域A和驱动电路区域B具有同一衬底基板1；驱动电路区域B包括时序控制电路和/或系统电路；其中，时序控制电路用于实现对阵列基板的时序控制，系统电路用于实现对阵列基板的驱动控制。
需要说明的是，现有的印刷电路板PCB上的电路包括时序控制电路TCON和系统电路SOC，而在本发明实施例提供的上述阵列基板中，由于显示区域和驱动电路区域形成在同一衬底基板上，又由于在衬底基板上的驱动电路区域包括时序控制电路和/或系统电路，可以认为驱动电路区域代替了现有技术的PCB部分，进而可以省去PCB部分，达到显示、电路驱动一体化，节省制作时间和费用，降低面板的厚度，做到模组的轻薄化，可以用于透明显示、超薄显示。
具体地，在具体实施时，在本发明实施例提供的上述阵列基板中，如图1所示，阵列基板可以包括位于显示区域A且依次设置在衬底基板1上的薄膜晶体管、钝化层4、树脂层5和公共电极线6；阵列基板还可以包括位于驱动电路区域B且依次设置在衬底基板1上的第一金属走线7、第一绝缘层8和第二金属走线9，以及与第二金属走线9电连接的时序控制芯片或系统芯片；第一金属走线、第二金属走线与时序控制芯片可以构成时序控制电路；或，第一金属走线、第二金属走线与系统芯片可以构成系统电路。这样将位于显示区域A的各膜层和位于驱动电路区域B的各膜层制作在同一 衬底基板1上，集成度高，可以达到模组的轻薄化。这里的第一金属走线7和第二金属走线9具体用于连接驱动电路区域所必需的时序控制芯片或系统芯片，形成时序控制电路或系统电路，将时序控制芯片或系统芯片提供的信号传输到显示区域，其中第二金属走线9的表面可以作为焊盘区，用于形成焊接元器件引脚的金属孔。
在具体实施时，在本发明实施例提供的上述阵列基板中，如图1所示，位于驱动电路区域B的第一金属走线7可以设置为双层结构；其中，位于显示区域A的薄膜晶体管中的栅极2与位于驱动电路区域B的第一金属走线7的第一层结构71可以同层同材质；以及位于显示区域A的薄膜晶体管中的源漏极3与位于驱动电路区域B的第一金属走线7的第二层结构72可以同材质，这种双层金属走线的设计一方面可以通过增加金属膜厚来降低驱动电路区域的金属走线的电阻(相对于显示区域来说，驱动电路区域的电阻要求更低)，提高工艺精度和集成度，另一方面可以利用第一金属走线的第二层结构对第一层结构进行保护，防止第二层结构刻蚀过程中对第一层结构造成破坏；并且，在制备阵列基板时不需要增加额外的制备工序，只需要通过同一构图工艺即可形成栅极和第一金属走线的第一层结构的图形，以及只需要通过同一构图工艺即可形成源漏极和第一金属走线的第二层结构的图形，能够节省制备成本，提升产品附加值。
在具体实施时，在本发明实施例提供的上述阵列基板中，如图1所示，位于驱动电路区域B的第一绝缘层8可以设置为双层结构；其中，位于显示区域A的钝化层4与位于驱动电路区域B的第一绝缘层8的第一层结构81可以同层同材质；位于显示区域A的树脂层5与位于驱动电路区域B的第一绝缘层8的第二层结构82可以同层同材质，这种双层绝缘层的设计可以通过增加绝缘层的膜厚来防止信号干扰；并且，在制备阵列基板时不需要增加额外的制备工序，只需要通过同一构图工艺即可形成钝化层和第一绝缘层的第一层结构的图形，以及只需要通过同一构图工艺即可形成树脂层和第一绝缘层的第二层结构的图形，能够节省制备成本，提升产品附加值。
在具体实施时，在本发明实施例提供的上述阵列基板中，如图1所示，位于驱动电路区域B的第二金属走线9可以设置为双层结构；其中，位于显示区域A的公共电极线6与位于驱动电路区域B的第二金属走线9的第一层结构91可以同材质，而位于驱动电路区域B的第二金属走线9的第二层结构92位于第二金属走线9的第一层结构91之上，可以单独制作而成，这种双层金属走线的设计一方面可以通过增加金属膜厚来降低驱动电路区域的金属走线的电阻(相对于显示区域来说，驱动电路区域的电阻要求更低)，提高工艺精度和集成度，另一方面可以利用第二金属走线的第二层结构对第一层结构进行保护，防止第二层结构刻蚀过程中对第一层结构造成破坏；并且，只需要通过同一构图工艺即可形成公共电极线和第二金属走线的第一层结构的图形，并且，能够简化工艺，节省制备成本，提升产品附加值。
在具体实施时，在本发明实施例提供的上述阵列基板中，如图1所示，阵列基板还可以包括位于驱动电路区域B且设置在第二金属走线9上方的具有过孔的第二绝缘层10，该第二绝缘层的过孔可以作为焊盘图案化区，用于后续芯片的焊接，即时序控制芯片或系统芯片可以通过第二绝缘层10的过孔与第二金属走线9电连接。
在具体实施时，在本发明实施例提供的阵列基板中，在衬底基板上还一般形成有栅极绝缘层、有源层、公共电极、像素电极等结构，这些具体结构可以有多种实现方式，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种本发明实施例提供的上述阵列基板的制作方法。
在具体实施时，本发明实施例提供的阵列基板的制作方法包括：
提供一衬底基板；
在上述衬底基板上制作显示区域和驱动电路区域；所述驱动电路区域包括时序控制电路和/或系统电路；所述时序控制电路用于实现对所述阵列基板的时序控制；所述系统电路用于实现对所述阵列基板的驱动控制。
在本发明实施例提供的上述阵列基板的制作方法中，由于显示区域和驱动电路区域同时制作在同一衬底基板上，可以省去印刷电路板部分，达到显示、电路驱动一体化，节省制作时间和费用，降低面板的厚度，做到模组的轻薄化，可以用于透明显示、超薄显示。
在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，上述在衬底基板上制作显示区域和驱动电路区域的步骤具体可以包括：
在上述衬底基板上形成包括位于显示区域的薄膜晶体管、钝化层、树脂层和公共电极线的图形，以及位于驱动电路区域的第一金属走线、第一绝缘层和第二金属走线的图形；第一金属走线和第二金属走线用于将时序控制电路中的时序控制芯片或系统电路中的系统芯片提供的信号传输到显示区域。
在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，如图2所示，在衬底基板上形成包括位于显示区域的薄膜晶体管和位于驱动电路区域的第一金属走线的图形的步骤具体可以采用如下方式：
S101、通过同一构图工艺在衬底基板上形成包括位于显示区域的薄膜晶体管中的栅极和位于驱动电路区域的第一金属走线的第一层结构的图形；
S102、通过同一构图工艺在衬底基板上形成包括位于显示区域的薄膜晶体管中的源漏极和位于驱动电路区域的第一金属走线的第二层结构的图形。
需要说明的是，图1示出了栅极位于有源层的下方，形成的薄膜晶体管为底栅型结构，当薄膜晶体管为顶栅型结构时，上述步骤S101和步骤S102的顺序可以颠倒，在此不再赘述。
在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，如图2所示，在衬底基板上形成包括位于显示区域的钝化层、树脂层和位于驱动电路区域的第一绝缘层的图形的步骤具体可以采用如下方式：
S103、通过同一构图工艺在衬底基板上形成包括位于显示区域的钝化层和位于驱动电路区域的第一绝缘层的第一层结构的图形；
S104、通过同一构图工艺在衬底基板上形成包括位于显示区域的树脂层和位于驱动电路区域的第一绝缘层的第二层结构的图形。
在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，如图2所示，在衬底基板上形成包括位于显示区域的公共电极线和位于驱动电路区域的第二金属走线的图形的步骤具体包括：
S105、通过同一构图工艺在衬底基板上形成包括位于显示区域的公共电极线和位于驱动电路区域的第二金属走线的第一层结构的图形；
S106、通过构图工艺在位于驱动电路区域的第二金属走线的第一层结构上形成位于驱动电路区域的第二金属走线的第二层结构的图形。
在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，执行步骤S106之后，还可以包括：
S107、通过构图工艺在位于驱动电路区域的第二金属走线上形成具有过孔的第二绝缘层的图形；时序控制芯片或系统芯片通过第二绝缘层的过孔与第二金属走线电连接。
下面以一个具体的示例详细说明本发明实施例提供的阵列基板的制作方法，具体步骤如下：
步骤一、通过同一构图工艺在衬底基板上形成包括位于显示区域的栅极和位于驱动电路区域的第一金属走线的第一层结构的图形，如图3a所示；
在具体实施时，在同一衬底基板1(如玻璃基板)上沉积一层金属材料薄膜，通过一次构图工艺在显示区域A形成栅极2的图形，同时在驱动电路区域B形成第一金属走线7的第一层结构71的图形；
步骤二、通过构图工艺在位于显示区域的栅极上依次形成栅极绝缘层和有源层的图形，如图3b所示；
在具体实施时，在完成步骤一后的衬底基板1上沉积一层绝缘层薄膜，通过构图工艺在显示区域A形成栅极绝缘层11的图形，将位于驱动电路区域B的绝缘层薄膜完全刻蚀掉；然后在衬底基板1上沉积一层有源层薄膜，通过一次构图工艺在显示区域A形成有源层12的图形，将位于驱动电路区域B的有源层薄膜完全刻蚀掉；
步骤三、通过同一构图工艺在衬底基板上形成包括位于显示区域的源漏极和位于驱动电路区域的第一金属走线的第二层结构的图形，如图3c所示；
在具体实施时，在完成步骤二的衬底基板1上沉积一层金属材料薄膜，通过一次构图工艺在显示区域A形成源漏极3的图形，同时在驱动电路区域B形成第一金属走线7的第二层结构72的图形；
步骤四、通过同一构图工艺在衬底基板上形成包括位于显示区域的钝化层和位于驱动电路区域的第一绝缘层的第一层结构的图形，如图3d所示；
在具体实施时，在完成步骤三的衬底基板上沉积一层钝化层薄膜，通过一次构图工艺在显示区域A形成钝化层4的图形，同时在驱动电路区域B形成第一绝缘层8的第一层结构81的图形；
步骤五、通过同一构图工艺在衬底基板上形成包括位于显示区域的树脂层和位于驱动电路区域的第一绝缘层的第二层结构的图形，如图3e所示；
在具体实施时，在完成步骤四的衬底基板上沉积一层树脂材料薄膜，通过一次构图工艺在显示区域A形成树脂层5的图形，同时在驱动电路区域B形成第一绝缘层8的第二层结构82的图形；
步骤六、通过构图工艺在位于显示区域的树脂层上形成公共电极层的图形，如图3f所示；
在具体实施时，在完成步骤五后的衬底基板1上沉积一层透明导电层薄膜，通过一次构图工艺在显示区域A形成公共电极层13的图形，将位于驱动电路区域B的透明导电层薄膜完全刻蚀掉；
步骤七、通过同一构图工艺在衬底基板上形成包括位于显示区域的公共电极线和位于驱动电路区域的第二金属走线的第一层结构的图形，如图3g所示；
在具体实施时，在完成步骤六的衬底基板上沉积一层金属材料薄膜，通过一次构图工艺在显示区域A形成公共电极线6的图形，同时在驱动电路区域B形成第一金属走线9的第一层结构91的图形；
步骤八、通过构图工艺分别在衬底基板上形成位于显示区域的第二钝化层、像素电极层，以及位于驱动电路区域的第二金属走线的第二层结构的图形，如图3h所示；
在具体实施时，在完成步骤七的衬底基板上沉积一层钝化层薄膜，通过一次构图工艺在显示区域A形成第二钝化层14的图形，将位于驱动电路区域B的钝化层薄膜完全刻蚀掉；然后在衬底基板1上沉积一层金属材料薄膜，通过一次构图工艺在位于驱动电路区域B的第二金属走线9的第一层结构91上形成第二金属走线9的第二层结构92的图形，将位于显示区域A的金属材料薄膜完全刻蚀掉；最后衬底基板上沉积一层透明导电层薄膜，通过一次构图工艺在显示区域A形成像素电极层15的图形，将位于驱动电路区域B的透明导电层薄膜完全刻蚀掉；
步骤九、通过构图工艺在位于驱动电路区域的第二金属走线上形成具有过孔的第二绝缘层的图形，时序控制芯片或系统芯片通过第二绝缘层的过孔与所述第二金属走线电连接，如图3i所示；
在具体实施时，在完成步骤八的衬底基板上沉积一层绝缘材料薄膜，通过一次构图工艺在位于驱动电路区域B的第二金属走线9的第二层结构91上形成具有过孔的第二绝缘层10的图形，将位于显示区域A的绝缘材料薄膜完全刻蚀掉；时序控制芯片或系统芯片通过第二绝缘层的过孔与第二金属走线电连接。
至此，经过上述具体实例提供的上述步骤一至步骤九制作出了本发明实施例提供的上述阵列基板。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述阵列基板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
本发明实施例提供的一种阵列基板、其制作方法及显示装置，阵列基板具有显示区域和与显示区域相邻的驱动电路区域；其中，显示区域和驱动电路区域具有同一衬底基板；驱动电路区域包括时序控制电路和/或系统电路；时序控制电路，用于实现对阵列基板的时序控制；系统电路，用于实现对阵列基板的驱动控制。由于本发明实施例提供的上述阵列基板中的显示区域和驱动电路区域形成在同一衬底基板上，又由于在衬底基板上的驱动电路区域包括时序控制电路和/或系统电路，可以认为驱动电路区域代替了现有技术的PCB部分，进而可以省去印刷电路板部分，达到显示、电路驱动一体化，节省制作时间和费用，降低面板的厚度，做到模组的轻薄化，可以用于透明显示、超薄显示。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (13)

  1. 一种阵列基板，其特征在于，所述阵列基板具有显示区域和与所述显示区域相邻的驱动电路区域；其中，
    所述显示区域和所述驱动电路区域具有同一衬底基板；
    所述驱动电路区域包括时序控制电路和/或系统电路；其中，所述时序控制电路用于实现对所述阵列基板的时序控制，所述系统电路用于实现对所述阵列基板的驱动控制。
  2. 如权利要求1所述的阵列基板，其特征在于，所述阵列基板包括位于所述显示区域且依次设置在所述衬底基板上的薄膜晶体管、钝化层、树脂层和公共电极线；
    所述阵列基板还包括位于所述驱动电路区域且依次设置在所述衬底基板上的第一金属走线、第一绝缘层和第二金属走线，以及与所述第二金属走线电连接的时序控制芯片和/或系统芯片；
    所述第一金属走线、第二金属走线与时序控制芯片构成所述时序控制电路；和/或，所述第一金属走线、第二金属走线与系统芯片构成所述系统电路；
    所述第一金属走线和第二金属走线用于将所述时序控制芯片和/或系统芯片提供的信号传输到显示区域。
  3. 如权利要求2所述的阵列基板，其特征在于，位于所述驱动电路区域的第一金属走线为双层结构；其中，
    位于所述显示区域的薄膜晶体管中的栅极与位于所述驱动电路区域的第一金属走线的第一层结构同层同材质；
    位于所述显示区域的薄膜晶体管中的源漏极与位于所述驱动电路区域的第一金属走线的第二层结构同材质。
  4. 如权利要求2或3所述的阵列基板，其特征在于，位于所述驱动电路区域的第一绝缘层为双层结构；其中，
    位于所述显示区域的钝化层与位于所述驱动电路区域的第一绝缘层的第一层结构同层同材质；
    位于所述显示区域的树脂层与位于所述驱动电路区域的第一绝缘层的第二层结构同层同材质。
  5. 如权利要求2-4中任一项所述的阵列基板，其特征在于，位于所述驱动电路区域的第二金属走线为双层结构；其中，
    位于所述显示区域的公共电极线与位于所述驱动电路区域的第二金属走线的第一层结构同材质；
    位于所述驱动电路区域的第二金属走线的第二层结构位于所述第二金属走线的第一层结构之上。
  6. 如权利要求2-5中任一项所述的阵列基板，其特征在于，所述阵列基板还包括位于所述驱动电路区域且设置在第二金属走线上方的具有过孔的第二绝缘层；所述时序控制芯片和/或系统芯片通过所述第二绝缘层的过孔与所述第二金属走线电连接。
  7. 一种阵列基板的制作方法，其特征在于，包括：
    提供一衬底基板；
    在所述衬底基板上制作显示区域和驱动电路区域；其中，所述驱动电路区域包括时序控制电路和/或系统电路；所述时序控制电路用于实现对所述阵列基板的时序控制，所述系统电路用于实现对所述阵列基板的驱动控制。
  8. 如权利要求7所述的方法，其特征在于，在所述衬底基板上制作显示区域和驱动电路区域的步骤包括：
    在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管、钝化层、树脂层和公共电极线以及位于所述驱动电路区域的第一金属走线、第一绝缘层和第二金属走线的图形；所述第一金属走线和第二金属走线用于将所述时序控制电路中的时序控制芯片和/或所述系统电路中的系统芯片提供的信号传输到显示区域。
  9. 如权利要求8所述的方法，其特征在于，在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管和位于驱动电路区域的第一金属走线的图形的步骤包括：
    通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管中的栅极和位于所述驱动电路区域的第一金属走线的第一层结构的图形；
    通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的薄膜晶体管中的源漏极和位于所述驱动电路区域的第一金属走线的第二层结构的图形。
  10. 如权利要求8或9所述的方法，其特征在于，在所述衬底基板上形成包括位于所述显示区域的钝化层、树脂层和位于所述驱动电路区域的第一绝缘层的图形的步骤包括：
    通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的钝化层和位于所述驱动电路区域的第一绝缘层的第一层结构的图形；
    通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的树脂层和位于所述驱动电路区域的第一绝缘层的第二层结构的图形。
  11. 如权利要求8-10中任一项所述的方法，其特征在于，在所述衬底基板上形成包括位于所述显示区域的公共电极线和位于所述驱动电路区域的第二金属走线的图形的步骤包括：
    通过同一构图工艺在所述衬底基板上形成包括位于所述显示区域的公共电极线和位于所述驱动电路区域的第二金属走线的第一层结构的图形；
    通过构图工艺在位于所述驱动电路区域的第二金属走线的第一层结构上形成位于所述驱动电路区域的第二金属走线的第二层结构的图形。
  12. 如权利要求8或11所述的方法，其特征在于，在所述衬底基板上形成位于所述驱动电路区域的第二金属走线的图形之后，还包括：
    通过构图工艺在位于所述驱动电路区域的第二金属走线上形成具有过孔的第二绝缘层的图形；所述时序控制芯片和/或系统芯片通过所述第二绝缘层的过孔与所述第二金属走线电连接。
  13. 一种显示装置，其特征在于，包括如权利要求1-6所述的阵列基板。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105096753A (zh) 2015-09-01 2015-11-25 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN105788466A (zh) * 2016-05-13 2016-07-20 京东方科技集团股份有限公司 一种显示面板、其制作方法及显示装置
CN108663863B (zh) * 2018-06-25 2021-01-26 Tcl华星光电技术有限公司 阵列基板
CN109064987A (zh) * 2018-08-31 2018-12-21 深圳市华星光电技术有限公司 液晶显示面板及具有该液晶显示面板的液晶显示装置
CN109087922B (zh) * 2018-09-19 2020-09-29 合肥鑫晟光电科技有限公司 阵列基板及其制作方法、显示面板
KR102504834B1 (ko) * 2019-03-11 2023-02-28 삼성전자 주식회사 집적회로 칩 및 그 제조 방법과 집적회로 칩을 포함하는 집적회로 패키지 및 디스플레이 장치
CN111999950B (zh) * 2020-08-03 2023-07-28 京东方科技集团股份有限公司 阵列基板、阵列基板的制备方法及液晶面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1794068A (zh) * 2004-12-24 2006-06-28 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
CN201886231U (zh) * 2010-12-06 2011-06-29 北京京东方光电科技有限公司 集成驱动的tft阵列基板和液晶面板
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN103064223A (zh) * 2013-01-07 2013-04-24 京东方科技集团股份有限公司 一种阵列基板和一种显示面板
CN103810981A (zh) * 2014-01-26 2014-05-21 京东方科技集团股份有限公司 阵列基板和显示面板
CN105096753A (zh) * 2015-09-01 2015-11-25 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08220562A (ja) * 1994-12-14 1996-08-30 Toshiba Corp 表示装置用アレイ基板およびその製造方法
CN103293727B (zh) * 2012-06-29 2016-02-17 上海中航光电子有限公司 液晶显示装置的阵列基板
CN102998865B (zh) * 2012-11-16 2015-02-11 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103676379B (zh) * 2013-12-24 2016-03-30 合肥京东方光电科技有限公司 阵列基板及显示装置
CN104538408B (zh) * 2015-01-14 2018-05-18 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN104749806B (zh) * 2015-04-13 2016-03-02 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1794068A (zh) * 2004-12-24 2006-06-28 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
CN201886231U (zh) * 2010-12-06 2011-06-29 北京京东方光电科技有限公司 集成驱动的tft阵列基板和液晶面板
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN103064223A (zh) * 2013-01-07 2013-04-24 京东方科技集团股份有限公司 一种阵列基板和一种显示面板
CN103810981A (zh) * 2014-01-26 2014-05-21 京东方科技集团股份有限公司 阵列基板和显示面板
CN105096753A (zh) * 2015-09-01 2015-11-25 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

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