WO2022052218A1

WO2022052218A1 - Array substrate and preparation method therefor, and display panel

Info

Publication number: WO2022052218A1
Application number: PCT/CN2020/122191
Authority: WO
Inventors: 刘俊领
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2020-09-08
Filing date: 2020-10-20
Publication date: 2022-03-17
Also published as: CN111900176A; US20220308376A1

Abstract

Provided are an array substrate and a preparation method therefor, and a display panel. The array substrate is divided into a display area and a bending area. The array substrate comprises a glass substrate and a flexible base, wherein the glass substrate is arranged corresponding to the display area; and the flexible base is arranged corresponding to the bending area. A plurality of binding wires in the bending area are respectively connected to a plurality of signal wires in the display area. The flexible base is bent towards a back face of the array substrate for COF binding, such that the problem of a relatively low yield caused by the use of a nano-silver colloid is avoided.

Description

Array substrate and preparation method thereof, and display panel

technical field

The present application relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display panel.

Background technique

With the development of display technology, borderless displays have become the mainstream of high-end products in the display market. The two major advantages of borderless displays are that they are beautiful in appearance and more fashionable. Second, the display with borderless technology can well realize display splicing, realizing double screen, triple screen and even multi-screen. In addition, the borderless display can bring users a wider visual experience, eliminating the sense of restraint of the original thick bezel display.

There are two existing implementations of borderless or narrow borders, one of which is the side bonding method: that is, the lines originally bound by the peripheral (bonding) traces are shortened or shrunk into the plane, and printed on the side of the array substrate. Nano-silver (Ag) glue is connected to the circuit, and then the chip-on-chip (Chip) On Film, COF) is bound to the side of the array substrate, so as to achieve a narrow border or no border effect. The other is the backside bonding method, which shortens or shrinks the lines originally bound by the peripheral lines into the plane, and uses the backside technology to design the corresponding peripheral lines on the backside. Then, the side-printed nano-silver glue is also used to connect the lines correspondingly, so that the binding traces on the front and the peripheral circuits on the back are correspondingly connected, and finally COF binding is performed on the back to achieve the effect of narrow or no border. However, both of the above two bonding methods need to print nano-silver paste on the side of the array substrate, and the printing accuracy is limited. During the process, silver ions often cause short circuits in the substrate due to diffusion and penetration of silver ions or abnormal alignment of the nano-silver paste. As a result, the product yield rate is low, and the cost remains high, resulting in the inability to widely adopt and popularize the borderless technology.

Therefore, the problem of low yield caused by the use of nano-silver glue in the existing array substrate bonding process needs to be solved.

technical problem

The present application provides an array substrate, a preparation method thereof, and a display panel, so as to alleviate the technical problem of low yield caused by using nano-silver glue in the existing array substrate bonding process.

technical solutions

In order to solve the above-mentioned problems, the technical solutions provided by this application are as follows:

An embodiment of the present application provides an array substrate. The array substrate is divided into a display area and a bending area. The bending area is located on one side of the display area. The array substrate includes a glass substrate and a flexible substrate. The glass substrate Corresponding to the display area, the flexible substrate corresponds to the bending area, and the flexible substrate extends from the bending area to the upper surface of one side of the glass substrate covering the display area. The display area further includes: a buffer layer, a thin film transistor, a plurality of signal lines and pixel electrodes. The buffer layer is disposed on the glass substrate and is in contact with the flexible substrate. The thin film transistor is disposed above the buffer layer and the flexible substrate. The plurality of signal lines are arranged in the same layer as the gate electrode of the thin film transistor. The pixel electrode is disposed on the thin film transistor and connected to the thin film transistor. The bending area further includes a plurality of binding wires, the plurality of binding wires are arranged on the flexible substrate, and the plurality of binding wires are respectively connected to the plurality of binding wires in the display area. Multiple signal lines are connected. Wherein, the flexible substrate in the bending area is suitable for bending along the side edge of the glass substrate to the side of the glass substrate away from the thin film transistor.

In the array substrate provided in the embodiment of the present application, the material of the flexible substrate includes polyimide.

In the array substrate provided in the embodiment of the present application, the thickness of the flexible substrate is 3 micrometers to 100 micrometers.

In the array substrate provided in the embodiments of the present application, the buffer layer and the flexible substrate have the same film thickness.

In the array substrate provided by the embodiment of the present application, the structure of the thin film transistor includes a back channel etch type, an etch stop type and a top gate structure type.

In the array substrate provided in the embodiment of the present application, the thin film transistor further includes an active layer and a source and drain electrode, the active layer is disposed under the gate electrode, and the source and drain electrode are disposed under the gate electrode on both sides.

In the array substrate provided in the embodiment of the present application, the material of the active layer includes one of amorphous silicon, low temperature polysilicon or metal oxide semiconductor.

In the array substrate provided in the embodiment of the present application, the material of the pixel electrode includes indium tin oxide.

An embodiment of the present application further provides a display panel, which includes the array substrate of the foregoing embodiment and a chip-on-film disposed under the array substrate, and the chip-on film is bound to the plurality of bonding wires.

In the display panel provided by the embodiment of the present application, the display panel is a liquid crystal display panel, and the liquid crystal display panel further includes a color filter substrate disposed opposite to the array substrate, and a color filter substrate located between the array substrate and the color filter Multiple liquid crystal molecules between substrates.

In the display panel provided by the embodiment of the present application, the display panel is an OLED display panel, and the OLED display panel further includes a light-emitting functional layer disposed on the array substrate, and an encapsulation disposed on the light-emitting functional layer Floor.

Embodiments of the present application further provide a method for fabricating an array substrate, which includes the following steps: Step S10, providing a glass substrate, the glass substrate is divided into a display area and a bending area, and a buffer layer is prepared on one side of the glass substrate and preparing a flexible substrate on the other side of the glass substrate, wherein the buffer layer and part of the flexible substrate are arranged corresponding to the display area, and another part of the flexible substrate is arranged corresponding to the bending area. Step S20, preparing a thin film transistor and a pixel electrode on the buffer layer and the flexible substrate in the display area, preparing a plurality of signal lines in the display area while preparing the thin film transistor, and preparing a plurality of signal lines in the bending area. A plurality of bonding wires are prepared on the flexible substrate in the folding area, and the plurality of signal wires are respectively connected with the plurality of bonding wires. Step S30 , removing the glass substrate corresponding to the bending area, bending the exposed flexible substrate to the side of the glass substrate away from the thin film transistor, and fixing it.

In the method for fabricating the array substrate provided in the embodiment of the present application, the material of the flexible substrate includes polyimide.

In the method for fabricating the array substrate provided in the embodiment of the present application, the thickness of the flexible substrate is 3 micrometers to 100 micrometers.

In the method for fabricating the array substrate provided in the embodiment of the present application, the buffer layer and the flexible substrate have the same film thickness.

In the method for fabricating the array substrate provided by the embodiment of the present application, the structure of the thin film transistor includes a back channel etching type, an etching barrier type and a top gate structure type.

In the method for fabricating the array substrate provided in the embodiment of the present application, the thin film transistor further includes an active layer and a source and drain electrodes, the active layer is disposed below the gate electrode, and the source and drain electrodes are disposed on the both sides of the gate.

In the method for fabricating the array substrate provided in the embodiment of the present application, the material of the active layer includes one of amorphous silicon, low temperature polysilicon or metal oxide semiconductor.

In the method for fabricating the array substrate provided in the embodiment of the present application, in step S30, the method for removing the glass substrate corresponding to the bending region includes at least one of substrate thinning technology, cutting, and laser burning.

In the method for fabricating the array substrate provided by the embodiment of the present application, in step S30, the fixing material for fixing the exposed flexible substrate includes at least one of double-sided tape or glue.

beneficial effect

In the array substrate and the preparation method thereof and the display panel provided by the present application, a flexible substrate is prepared on the glass substrate side of the array substrate, and then the thin film transistors are prepared on the glass substrate and the bonding wires are prepared on the flexible substrate. After the array process of the array substrate is completed, the glass substrate corresponding to the bending area is removed, and the flexible substrate prepared with the binding traces is bent to the back of the glass substrate for COF binding to achieve a borderless design. The use of nano-silver glue in the bonding process is avoided. The problem of low yield caused by the use of nano-silver glue in the bonding process of the existing array substrates to achieve narrow borders or no borders is solved.

Description of drawings

In order to more clearly illustrate the embodiments or technical solutions in the prior art, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for invention. In some embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic side view of the film layer structure before the bending region of the array substrate provided by the embodiment of the present application.

FIG. 2 is a schematic diagram of a film layer structure of a thin film transistor according to an embodiment of the present application.

FIG. 3 is a schematic top view of a partial structure of an array substrate provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of a film layer structure after the bending region of the array substrate provided by the embodiment of the present application is bent.

FIG. 5 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application.

FIG. 6 to FIG. 7 are schematic diagrams of structures of film layers prepared in each step in the method for fabricating an array substrate provided in an embodiment of the present application.

FIG. 8 is a schematic diagram of a first structure of a display panel according to an embodiment of the present application.

FIG. 9 is a schematic diagram of a second structure of a display panel according to an embodiment of the present application.

Embodiments of the present invention

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present application may be practiced. Directional terms mentioned in this application, such as [upper], [lower], [front], [rear], [left], [right], [inner], [outer], [side], etc., are only for reference Additional schema orientation. Therefore, the directional terms used are used to describe and understand the present application, rather than to limit the present application. In the figures, structurally similar elements are denoted by the same reference numerals. In the drawings, the size and thickness of some components are exaggerated for understanding and convenience of description.

Referring to FIGS. 1 and 2 , in an embodiment, an array substrate 100 is provided. As shown in FIG. 1 , the array substrate 100 is divided into a display area AA and a bending area BA, and the bending area BA is located at one side of the display area AA. The array substrate 100 includes a glass substrate 10 and a flexible substrate 60. The glass substrate 10 corresponds to the display area AA, the flexible substrate 60 corresponds to the bending area BA, and the flexible substrate 60 extends from the The bending area BA extends to the upper surface of the side 11 of the glass substrate 10 covering the display area AA. The display area AA further includes: a buffer layer 20 , a thin film transistor 40 , a plurality of signal lines 30 , and a pixel electrode 50 . The buffer layer 20 is disposed on the glass substrate 10 and is in contact with the flexible substrate 60 . The thin film transistor 40 is disposed above the buffer layer 20 and the flexible substrate 60 . The plurality of signal lines 30 are disposed in the same layer as the gate electrode 42 of the thin film transistor 40 . The pixel electrode 50 is disposed on the thin film transistor 40 and connected to the thin film transistor 40 . The bending area BA also includes a plurality of bonding wires 70 disposed on the flexible substrate 60 (FIG. 1 is a schematic diagram of the film layer structure of the array substrate, and the bonding wires 70 and the signal wires 30 are shown. 3 is a schematic top view of a partial structure of the array substrate, showing that a plurality of binding wires 70 and a plurality of signal wires 30 are electrically connected). The plurality of binding wires 70 are respectively connected to the plurality of signal wires 30 in the display area AA. The flexible substrate 60 in the bending area BA is suitable for bending along the side edge 11 of the glass substrate 10 to the side of the glass substrate 10 away from the thin film transistor 40 , as shown in FIG. 4 shown.

Specifically, the structure of the thin film transistor includes a back channel etch (BCE) type, an etch stop layer (ESL) and a top gate (Top gate) structure type, etc.

Specifically, the thin film transistor 40 shown in FIG. 1 and FIG. 2 is described by taking the top gate structure as an example. Specifically, as shown in FIG. 2 , the thin film transistor 40 includes an active layer 41 , a gate electrode 42 , and a source and drain electrode 43 . The gate 42 is disposed above the active layer 41 . The source and drain electrodes 43 are disposed on both sides of the gate electrode 42 , and the source and drain electrodes 43 include a source electrode 431 and a drain electrode 432 . The active layer 41 includes a doped region 411 and a channel region 412 , and the source electrode 431 and the drain electrode 432 are respectively connected to the doped region 411 of the active layer 41 .

Specifically, the active layer 41 can be made of amorphous silicon (Amorphous Silicon, a-Si), low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or metal oxide semiconductors, such as Indium Gallium Zinc Oxide (IGZO), etc.

Specifically, please refer to FIG. 1 and FIG. 2 , a plurality of signal lines 30 are also prepared in the display area AA, and the plurality of signal lines 30 are arranged in the same layer as the gate electrode 42 of the thin film transistor 40 . And the signal line 30 is connected to the binding wire 70 of the bending area BA. The film layer between the bonding wire 70 and the flexible substrate 60 may include the insulating layer 80 in the normal manufacturing process of the thin film transistor, such as a gate insulating layer and the like. Of course, the connection method between the signal line and the binding line of the present application is not limited to that shown in FIG. 1 , the binding line may be formed at the same time as the signal line, and the binding line is an extension of the signal line. Alternatively, the signal lines can also be connected to the bonding traces by arranging vias in the gate insulating layer. Or when the thin film transistor adopts the bottom gate, the signal line is directly disposed on the surface of the buffer layer 20 and the flexible substrate 60, and is directly connected to the binding line.

Further, a schematic top view of a partial structure in which the plurality of signal lines 30 and the plurality of binding wires 70 are connected is shown in FIG. 3 . For the convenience of description, FIG. 3 only shows the signal line 30 , the bonding wire 70 , the glass substrate 10 and the flexible substrate 60 . A plurality of signal lines 30 are disposed above the glass substrate 10, and fan out to the bending area BA at the junction of the display area AA and the bending area BA, which are respectively connected with the multiple signal lines 30 on the flexible substrate 60 in the bending area BA. A bond trace 70 is connected.

Specifically, the plurality of signal lines include signal lines such as gate lines and data lines. The signal lines shown in FIG. 1 and FIG. 2 are gate lines.

Further, the array substrate 100 further includes a pixel electrode 50 located above the thin film transistor 40 . The pixel electrode 50 may be connected to the source electrode 431 or the drain electrode 432 through a via hole. 1 and 2 show that the pixel electrode 50 is connected to the drain electrode 432 . Of course, the array substrate also includes multiple insulating layers between each film layer of the thin film transistor and the pixel electrodes, but the insulating layer is the prior art and is not the focus of this application, so it is not particularly marked in the figure or drawing, which will not be repeated here.

Specifically, the material of the pixel electrode includes a transparent conductive electrode material such as indium tin oxide (Indium Tin Oxide, ITO).

Specifically, the buffer layer 20 of the display area AA is disposed on the glass substrate 10 and is the same layer as the flexible substrate 60 , and the upper surfaces of the two are at the same level, that is, the film layers of the two are at the same level. Same thickness. In this way, the height difference between the plurality of binding wires 70 and the plurality of signal wires 30 can be well balanced, and a breakage can be avoided. Of course, according to actual process requirements, the film thicknesses of the buffer layer and the flexible substrate can also be different.

Further, the material of the flexible substrate 60 in the bending area BA includes a bendable flexible material such as polyimide (PI).

Further, the thickness of the flexible substrate 60 can be set in the range of 3 microns to 100 microns according to actual process requirements.

Further, the flexible substrate 60 can be bent to the back of the glass substrate 10 and fixed on the back of the glass substrate by other fixing methods such as double-sided tape or glue, so as to facilitate COF binding.

In this embodiment, the substrate of the array substrate is a combination of a glass substrate and a flexible substrate, and the bonding wires are prepared on the flexible substrate. The flexible substrate prepared with the bonding traces can be bent to the back of the glass substrate and bound by COF to achieve a borderless design. Avoid the problem of low yield caused by the use of nano-silver glue.

In one embodiment, a method for fabricating an array substrate is provided, as shown in FIG. 5 , which includes the following steps:

Step S10, providing a glass substrate, the glass substrate is divided into a display area and a bending area, a buffer layer is prepared on one side of the glass substrate, and a flexible substrate is prepared on the other side of the glass substrate, wherein the The buffer layer and part of the flexible substrate are disposed corresponding to the display area, and another part of the flexible substrate is disposed corresponding to the bending area.

Specifically, according to actual process requirements, a deposition process such as chemical vapor deposition (CVD) is used to deposit an inorganic film layer on one side of the glass substrate 10 as the buffer layer 20 , and on the other side of the glass substrate 10 , an inorganic film layer is deposited. A flexible film layer is deposited on one side as a flexible substrate 60, the flexible substrate 60 extends from the bending area BA to the display area AA, and is in contact with the buffer layer 20, as shown in FIG. 6 .

Further, the material of the flexible substrate 60 includes bendable flexible materials such as polyimide.

Further, the thickness of the flexible substrate 60 can be set according to actual process requirements, and the thickness ranges from 3 micrometers to 100 micrometers.

Specifically, the buffer layer 20 of the display area AA is disposed on the glass substrate 10 and is the same layer as the flexible substrate 60 , which can well balance the multiple binding wires and the multiple binding wires. The height difference of each signal line is avoided to avoid breakage.

Step S20, preparing a thin film transistor and a pixel electrode on the buffer layer and the flexible substrate in the display area, preparing a plurality of signal lines in the display area while preparing the thin film transistor, and preparing a plurality of signal lines in the bending area. A plurality of bonding wires are prepared on the flexible substrate in the folding area, and the plurality of signal wires are respectively connected with the plurality of bonding wires.

Specifically, as shown in FIG. 7 , a buffer layer 20 and a part of the flexible substrate 60 are prepared on the glass substrate 10 in the display area AA. Thin film transistors 40 and pixel electrodes 50 are fabricated on the buffer layer 20 and part of the flexible substrate 60 .

Specifically, as shown in FIG. 2 , the thin film transistor 40 includes an active layer 41 , a gate electrode 42 , and a source and drain electrode 43 . The gate 42 is disposed above the active layer 41 . The source and drain electrodes 43 are disposed on both sides of the gate electrode 42 , and the source and drain electrodes 43 include a source electrode 431 and a drain electrode 432 . The active layer 41 includes a doped region 411 and a channel region 412 , and the source electrode 431 and the drain electrode 432 are respectively connected to the doped region 411 of the active layer 41 .

Further, while preparing the thin film transistor 40 on the buffer layer 20 and part of the flexible substrate 60, a plurality of signal lines 30 are prepared in the display area AA, and the flexible substrate in the bending area BA A plurality of binding wires 70 are prepared on the bottom 60 , an insulating layer 80 is also arranged between the plurality of binding wires 70 and the flexible substrate 60 , and the plurality of signal wires 30 are respectively connected with the plurality of binding wires 70 , as shown in Figure 7.

Further, the pixel electrode 50 is connected to the source electrode or the drain electrode through a via hole. Of course, the array substrate further includes a plurality of insulating layers between each film layer of the thin film transistor and the pixel electrode, which will not be repeated here.

Step S30 , removing the glass substrate corresponding to the bending area, bending the exposed flexible substrate to the side of the glass substrate away from the thin film transistor, and fixing it.

Specifically, the glass substrate 10 corresponding to the bending area BA is removed by adopting at least one of the substrate thinning technology, cutting, laser burning and other processes to form the structure shown in FIG. 1 .

Further, as shown in FIG. 4 , after removing the glass substrate corresponding to the bending area, the flexible substrate 60 prepared with a plurality of binding wires 70 is bent to the back of the glass substrate 10 . (that is, the side away from the thin film transistor 40).

Further, the flexible substrate bent to the back of the glass substrate is fixed on the glass substrate using double-sided tape or glue or other fixing methods.

In one embodiment, a display panel is provided, which includes the array substrate in the foregoing embodiment and a chip-on-film disposed under the array substrate, the chip-on film is bound to the plurality of bonding wires Certainly.

Specifically, the display panel is a liquid crystal display panel. As shown in FIG. 8 , the liquid crystal display panel 1000 includes an array substrate 100 , a color filter substrate 300 disposed opposite to the array substrate 100 , and a color filter substrate 300 located between the array substrate 100 and the array substrate 100 . A plurality of liquid crystal molecules 200 between the color filter substrates 300 . The liquid crystal display panel 1000 further includes a chip on film 400 , and the chip on film 400 is bound to a plurality of bonding wires 70 on the flexible substrate 60 .

Specifically, the display panel is an OLED display panel. As shown in FIG. 9 , the OLED display panel 1001 includes an array substrate 100 , a light-emitting functional layer 500 disposed on the array substrate 100 , and a light-emitting functional layer disposed on the light-emitting functional layer. Encapsulation layer 600 on 500 . The OLED display panel 1001 further includes a chip on film 400 , and the chip on film 400 is bound to a plurality of bonding wires 70 on the flexible substrate 60 .

It should be noted that the present application adopts the method of combining the glass substrate and the flexible substrate to prepare the binding wires on the flexible substrate. Then, the flexible substrate prepared with the bonding traces is bent to the back of the glass substrate, and the chip-on-film COF bonding is performed to realize the frameless design method, which is not limited to the array substrate provided in the embodiments of the present application. The borderless design method is also applicable to GOA (Gate Driver on Array, row driver of array substrate) substrates or COA (Color-filter on Array, color filter on array) substrates, etc., which will not be repeated here.

According to the above embodiment, it can be known that:

The present application provides an array substrate, a preparation method thereof, and a display panel. A flexible substrate is prepared on one side of a glass substrate of the array substrate, and then a thin film transistor is prepared on the glass substrate and binding wires are prepared on the flexible substrate. After the array process of the array substrate is completed, the glass substrate under the flexible substrate is removed, and the flexible substrate is bent to the back of the glass substrate for COF binding to achieve a borderless design. The use of nano-silver glue in the bonding process is avoided. The problem of low yield caused by the use of nano-silver glue in the bonding process of the existing array substrates to achieve narrow-sided models or no borders is solved.

To sum up, although the present application has disclosed the above-mentioned preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art, without departing from the spirit and scope of this application, can Therefore, the scope of protection of the present application is subject to the scope defined by the claims.

Claims

An array substrate is divided into a display area and a bending area, the bending area is located on one side of the display area, the array substrate includes a glass substrate and a flexible substrate, the glass substrate corresponds to the display area, The flexible substrate corresponds to the bending area, and the flexible substrate extends from the bending area to the upper surface of one side of the glass substrate covering the display area; wherein the display area is further include:

a buffer layer, disposed on the glass substrate and in contact with the flexible substrate;

a thin film transistor, disposed above the buffer layer and the flexible substrate;

a plurality of signal lines arranged in the same layer as the gate electrode of the thin film transistor; and

a pixel electrode, disposed on the thin film transistor and connected to the thin film transistor;

The bending area further includes a plurality of binding wires, the plurality of binding wires are arranged on the flexible substrate, and the plurality of binding wires are respectively connected to the plurality of binding wires in the display area. Multiple signal line connections;

Wherein, the flexible substrate in the bending region is suitable for bending along the side edge of the glass substrate to the side of the glass substrate away from the thin film transistor.
The array substrate of claim 1, wherein a material of the flexible substrate comprises polyimide.
The array substrate of claim 1, wherein the flexible substrate has a thickness of 3 micrometers to 100 micrometers.
The array substrate of claim 1, wherein the buffer layer and the flexible substrate have the same film thickness.
The array substrate according to claim 1, wherein the thin film transistor has a structure including a back channel etch type, an etch stop type and a top gate structure type.
The array substrate according to claim 5, wherein the thin film transistor further comprises an active layer and a source and drain electrode, the active layer is arranged below the gate, and the source and drain are arranged on the gate both sides of the pole.
The array substrate according to claim 6, wherein the material of the active layer comprises one of amorphous silicon, low temperature polysilicon or metal oxide semiconductor.
The array substrate according to claim 1, wherein the material of the pixel electrode comprises indium tin oxide.
A display panel, comprising the array substrate according to claim 1 and a chip-on film disposed under the array substrate, the chip-on film being bound to the plurality of bonding wires.
The display panel according to claim 9, wherein the display panel is a liquid crystal display panel, and the liquid crystal display panel further comprises a color filter substrate disposed opposite to the array substrate, and a color filter substrate located between the array substrate and the color filter substrate. A plurality of liquid crystal molecules between the film substrates.
The display panel according to claim 9, wherein the display panel is an OLED display panel, the OLED display panel further comprises a light-emitting functional layer disposed on the array substrate, and a light-emitting functional layer disposed on the light-emitting functional layer encapsulation layer.
A method for preparing an array substrate, comprising the following steps:

Step S10, providing a glass substrate, the glass substrate is divided into a display area and a bending area, a buffer layer is prepared on one side of the glass substrate, and a flexible substrate is prepared on the other side of the glass substrate, wherein the The buffer layer and part of the flexible substrate are arranged corresponding to the display area, and another part of the flexible substrate is arranged corresponding to the bending area;

Step S20, preparing a thin film transistor and a pixel electrode on the buffer layer and the flexible substrate in the display area, preparing a plurality of signal lines in the display area while preparing the thin film transistor, and preparing a plurality of signal lines in the bending area. A plurality of bonding wires are prepared on the flexible substrate in the folding area, and the plurality of signal wires are respectively connected with the plurality of bonding wires; and

Step S30 , removing the glass substrate corresponding to the bending area, bending the exposed flexible substrate to the side of the glass substrate away from the thin film transistor, and fixing it.
The method for fabricating an array substrate according to claim 12, wherein the material of the flexible substrate comprises polyimide.
The method for fabricating an array substrate according to claim 12, wherein the flexible substrate has a thickness of 3 micrometers to 100 micrometers.
The method for fabricating an array substrate according to claim 12, wherein the buffer layer and the flexible substrate have the same film thickness.
The method for fabricating an array substrate according to claim 12, wherein the structure of the thin film transistor includes a back channel etch type, an etch stop type and a top gate structure type.
The method for fabricating an array substrate according to claim 16, wherein the thin film transistor further comprises an active layer and a source and drain electrode, the active layer is disposed below the gate electrode, and the source and drain electrode are disposed on the both sides of the gate.
The method for fabricating an array substrate according to claim 17, wherein the material of the active layer comprises one of amorphous silicon, low temperature polysilicon or metal oxide semiconductor.
The method for fabricating an array substrate according to claim 12, wherein, in step S30, the method for removing the glass substrate corresponding to the bending region includes at least one of substrate thinning technology, cutting, and laser burning.
The method for fabricating an array substrate according to claim 12, wherein, in step S30, a fixing material for fixing the exposed flexible substrate comprises at least one of double-sided tape or glue.