WO2021226868A1 - 驱动基板及其制作方法、显示装置 - Google Patents

驱动基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021226868A1
WO2021226868A1 PCT/CN2020/090001 CN2020090001W WO2021226868A1 WO 2021226868 A1 WO2021226868 A1 WO 2021226868A1 CN 2020090001 W CN2020090001 W CN 2020090001W WO 2021226868 A1 WO2021226868 A1 WO 2021226868A1
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Prior art keywords
layer
metal layer
pattern
source
driving
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PCT/CN2020/090001
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English (en)
French (fr)
Inventor
曹占锋
刘英伟
王珂
刘冬妮
玄明花
袁广才
陈蕾
董学
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020227013914A priority Critical patent/KR20230008016A/ko
Priority to PCT/CN2020/090001 priority patent/WO2021226868A1/zh
Priority to CN202080000728.8A priority patent/CN114026631B/zh
Priority to EP20894918.0A priority patent/EP4006890A4/en
Priority to JP2021572618A priority patent/JP2023533880A/ja
Priority to US17/265,806 priority patent/US11495718B2/en
Publication of WO2021226868A1 publication Critical patent/WO2021226868A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the present disclosure relates to the field of display technology, in particular to a drive substrate, a manufacturing method thereof, and a display device.
  • Micro-LED Micro Light Emitting Diode
  • display technology is to reduce the size of the existing LED (Light Emitting Diode) to less than 100um, and then transfer it to the drive substrate through mass transfer technology to form a variety of different sizes of Micro- LED display.
  • Micro-LED has many advantages such as self-luminous high brightness, high contrast, super high resolution and color saturation, long life, fast response speed, energy saving, and wide adaptation to the environment. It has good application prospects in various fields.
  • the embodiments of the present disclosure provide a drive substrate, a manufacturing method thereof, and a display device, which can reduce the number of patterning processes for manufacturing the drive substrate.
  • a drive substrate including:
  • the first driving function layer is disposed on the first surface of the base substrate, the first driving function layer includes a plurality of driving thin film transistors and a plurality of signal wirings, at least one of the signal wirings adopts a single-layer structure and The thickness is greater than the threshold;
  • a pad layer is disposed on a side of the first driving function layer away from the base substrate, the pad layer includes a plurality of first pads and a plurality of second pads, the The first pad is connected to the corresponding first electrode of the driving thin film transistor, and the second pad is connected to the common electrode line in the signal wiring.
  • the driving substrate further includes:
  • the second driving function layer is disposed on the second surface of the base substrate, the second surface is opposite to the first surface, and the second driving function layer includes a lead pad and is connected to the lead pad The binding pins;
  • the side surface of the base substrate is provided with a plurality of grooves, each of the grooves extends in a direction perpendicular to the base substrate and penetrates the first surface and the second surface of the base substrate;
  • the plurality of signal traces include a power supply voltage signal line and the common electrode line, and the thickness of the power supply voltage signal line and the common electrode line are both greater than the threshold value.
  • the power supply voltage signal line and the common electrode line are provided in the same layer and the same material.
  • the driving substrate further includes: a signal transmission line connected to the signal wiring, and the signal transmission line and the signal wiring form a grid structure.
  • the first driving function layer sequentially includes:
  • the first source and drain metal layer
  • a second source-drain metal layer, the pattern of the second source-drain metal layer includes the signal wiring
  • the third flat layer is the third flat layer.
  • the second source/drain metal layer includes a stacked copper layer and a metal layer, and the metal layer is located on a side of the copper layer close to the base substrate, and the metal layer and the first The adhesion of the two flat layers is greater than the adhesion of the copper layer and the second flat layer.
  • the thickness of the copper layer is 2-30um.
  • the driving substrate further includes a first passivation layer located between the copper layer and the first flat layer, and the first passivation layer is made of an inorganic insulating material.
  • the driving substrate further includes a second passivation layer located between the copper layer and the second flat layer, and the second passivation layer is made of an inorganic insulating material.
  • a display device which includes the above-mentioned driving substrate and an electronic component fixed on the pad layer, the first pole of the electronic component is bonded and connected to the first pad, so The second pole of the electronic component is bonded and connected to the second pad.
  • a method for manufacturing a driving substrate including:
  • a first driving function layer is formed on the first surface of the base substrate.
  • the first driving function layer includes a plurality of driving thin film transistors and a plurality of signal traces. At least one of the signal traces adopts a single-layer structure and has a thickness Greater than the threshold
  • a pad layer is formed on the side of the first driving function layer away from the base substrate.
  • the pad layer includes a plurality of first pads and a plurality of second pads.
  • the first electrode of the driving thin film transistor is connected, and the second pad is connected to the common electrode line in the signal wiring.
  • the driving substrate includes a pattern of a first source-drain metal layer and a pattern of a second source-drain metal layer, and the pattern of the second source-drain metal layer includes the signal traces to form the signal traces.
  • the line includes:
  • a conductive layer is grown on the seed layer by an electroplating method, and the seed layer and the conductive layer constitute a second source and drain metal layer;
  • the second source-drain metal layer is patterned to form the signal wiring.
  • the driving substrate includes a pattern of a first source-drain metal layer and a pattern of a second source-drain metal layer, and the pattern of the second source-drain metal layer includes the signal traces to form the signal traces.
  • the line includes:
  • a pattern of a conductive layer is grown on the pattern of the seed layer by electroless plating, and the pattern of the conductive layer and the pattern of the seed layer form the signal wiring.
  • forming the seed layer includes:
  • a laminated copper layer and a metal layer are formed, the metal layer is located on the side of the copper layer close to the base substrate, and the adhesion between the metal layer and the insulating layer is greater than that of the copper layer and the insulating layer Of adhesion.
  • FIG. 1 is a schematic diagram of the structure of a related art drive substrate
  • FIG. 2 is a schematic diagram of the structure of a driving substrate according to an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the wiring of the driving substrate in the display area according to the embodiment of the disclosure.
  • Fig. 4 is a partial enlarged schematic diagram of Fig. 3;
  • Figure 5 is a schematic cross-sectional view of Figure 4 in the AA' direction;
  • Fig. 6 is a schematic cross-sectional view of Fig. 4 in the BB' direction;
  • Fig. 7 is a schematic cross-sectional view of Fig. 4 in the CC' direction;
  • Fig. 8 is a schematic cross-sectional view of Fig. 4 in the DD' direction;
  • FIG. 9 is a schematic diagram of the driving substrate in the pad area of the embodiment of the disclosure.
  • Fig. 10 is a schematic cross-sectional view of Fig. 9 in the EE' direction.
  • the current load of the drive substrate of the Micro-LED display is large, which can reach tens of milliamps.
  • the line width and resistance of the signal trace are required to be high. If the resistance of the signal trace is too large, it will cause electricity on the signal trace. The signal loss is large, which in turn causes the power consumption of the drive substrate to be high.
  • FIG. 1 is a schematic diagram of the structure of a driving substrate in the related art.
  • the driving substrate includes a base substrate 10, a first driving function layer located on the first surface of the base substrate 10, and a second driving function layer located on the second surface of the base substrate 10.
  • the first surface and the second The surfaces are two opposite surfaces.
  • the first driving function layer includes: the active layer 11, the active layer 11 can be polysilicon, and the thickness is roughly in the range of 400-500 angstroms; the first gate insulating layer 12, the first gate insulating layer 12 Inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride can be used, and the thickness is roughly in the range of 400-800 angstroms; the first gate metal layer 13 and the first gate metal layer 13 can be Mo with a thickness Approximately take a value in the range of 2500-3600 angstroms; the second gate insulating layer 14, the second gate insulating layer 14 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., with a thickness of approximately 1000-2000 The value is within the range of angstroms; the second gate metal layer 15, the second gate metal layer 15 can be Mo, and the thickness is roughly in the range of 2500-3600 angstroms; the interlayer insulation layer
  • the thickness is roughly in the range of 2000-3000 angstroms;
  • the third source and drain metal layer 22, the third source and drain metal layer 22 can be copper, and the thickness is roughly in the range of 5500-6500 angstroms
  • the second passivation layer 23, the second passivation layer 23 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness is roughly in the range of 2000-3000 angstroms;
  • the third flat layer 24 and the third flat layer 24 can be made of organic resin, and the thickness is approximately in the range of 18000-22000 angstroms.
  • the first driving function layer may also include a buffer layer (not shown) between the active layer 11 and the base substrate 10.
  • the buffer layer may be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. Specifically, a laminated structure of silicon nitride/silicon oxide can be used, and the thickness can be 500 angstroms/3000 angstroms respectively.
  • the first source-drain metal layer 17 is used to make data lines.
  • the first source-drain metal layer 17 further includes a first sub-pattern 171 and a second sub-pattern 172.
  • the first sub-pattern 171 is used to transmit a VDD (power supply voltage) signal;
  • the two sub-patterns 172 are used to transmit driving voltage signals;
  • the second source-drain metal layer 19 includes a third sub-pattern 191 and a fourth sub-pattern 192, the third sub-pattern 191 is used to transmit the VDD signal;
  • the fourth sub-pattern 192 is used to transmit VSS (low voltage) signal;
  • the third source-drain metal layer 22 includes a fifth sub-pattern 221, a sixth sub-pattern 222, and a seventh sub-pattern 223, the fifth sub-pattern 221 is used to transmit the VDD signal;
  • the sixth sub-pattern 222 is used To transmit the VSS signal, the seventh sub-pattern 223 is used to transmit the
  • the third flat layer 24 includes via holes exposing the sixth sub-pattern 222 and the seventh sub-pattern 223.
  • the sixth sub-pattern 222 and the seventh sub-pattern 223 can be used as pads, and the N pad252 of the LED 25 can be connected to the sixth sub-pattern 222. Bound and connect together, the P pad 251 of the LED 25 can be bound and connected with the seventh sub-graphic 223.
  • the second driving function layer includes: fan-out wiring structure 26, fan-out wiring structure 26 can adopt Al/Mo laminated structure, the thickness can be 6000 angstroms/600 angstroms respectively; passivation layer 27, passivation layer 27 can adopt nitrogen Inorganic insulating materials such as silicon oxide, silicon oxide, silicon oxynitride, etc., whose thickness is roughly in the range of 5000-7000 angstroms; the binding pins 282 used to bind to the flexible circuit board and the fan-out wiring structure 26
  • the lead pad 281 connected to the bonding pin 282 can be made of a transparent conductive material such as ITO, and the thickness is approximately in the range of 400-600 angstroms.
  • the multiple lead pads 281 are connected in parallel with the first conductive sub-pattern 312 and the second conductive sub-pattern 344 to form a conductive structure
  • the orthographic projection of the plurality of lead pads 281 on the plane where the substrate is located basically coincides with the conductive structure. Therefore, the arrangement pitch of two adjacent lead pads 281 among the plurality of lead pads 281 is larger than that of multiple bindings.
  • the arrangement spacing of the two adjacent bonding pins 282 among the pins 282 should be large.
  • first source-drain metal layer 17 further includes an eighth sub-pattern 173
  • second source-drain metal layer 19 further includes a ninth sub-pattern 193
  • the third source-drain metal layer 22 further includes a tenth sub-pattern 224.
  • the pattern 173, the ninth sub-pattern 193, and the tenth sub-pattern 224 form a conductive structure, which is used to connect to the lead pad 281 along the groove on the side surface of the base substrate 10 to transmit the signal output by the flexible circuit board to the VDD trace and VSS routing.
  • the drive substrate shown in Figure 1 it can be seen that in order to reduce IR Drop, two layers of metal (the third sub-pattern 191 and the fifth sub-pattern 221) are connected in parallel to form VDD traces, and three layers of source and drain are provided on the drive substrate.
  • the structure of the metal layer and the driving substrate is relatively complicated, which leads to a large number of patterning processes for manufacturing the driving substrate, which affects the production cycle of the driving substrate, and causes the production cost of the driving substrate to be relatively high.
  • the embodiments of the present disclosure provide a drive substrate, a manufacturing method thereof, and a display device, which can reduce the number of patterning processes for manufacturing the drive substrate.
  • An embodiment of the present disclosure provides a driving substrate, including:
  • the first driving function layer is disposed on the first surface of the base substrate, the first driving function layer includes a plurality of driving thin film transistors and a plurality of signal wirings, at least one of the signal wirings adopts a single-layer structure and The thickness is greater than the threshold;
  • a pad layer is disposed on a side of the first driving function layer away from the base substrate, the pad layer includes a plurality of first pads and a plurality of second pads, the The first pad is connected to the corresponding first electrode of the driving thin film transistor, and the second pad is connected to the common electrode line in the signal wiring.
  • the thickness of the signal trace itself is relatively large, which can effectively reduce the IR drop, so there is no need to form signal traces in parallel, which can reduce the number of metal layers included in the drive substrate, thereby reducing the cost of manufacturing the drive substrate.
  • the number of patterning processes reduces the production cost of the drive substrate.
  • the above-mentioned threshold may be 2 ⁇ m.
  • the signal traces of the driving substrate include power supply voltage signal lines VDD traces and common electrode lines VSS traces.
  • the VDD traces are used to transmit the first fixed-level signal
  • the VSS traces are used to transmit the second fixed-level signal.
  • the larger resistance of the trace and the VSS trace will result in higher power consumption of the drive substrate (larger IR Drop), in which the amplitude of the first fixed-level signal and the second fixed-level signal are different.
  • the second source-drain metal layer 19 may adopt a stacked structure of titanium/aluminum/titanium, and the thickness may be 500 angstroms/6500 angstroms/500 angstroms, respectively, and the third source-drain metal layer 22 may be Using copper with a thickness of 6000 angstroms, the second source-drain metal layer 19 and the third source-drain metal layer 22 are used in parallel to form signal traces (such as VDD traces and VSS traces), and the resistivity of the signal traces is 0.0035 ohms. About meters...
  • a single layer of conductive material with a thickness greater than 2um, such as copper, is directly used to make the signal trace, which can reduce the resistivity of the signal trace to about 0.001 ohm ⁇ meter, which can greatly reduce the resistivity of the signal trace. Not only can the IR Drop of the signal routing be reduced, but also the process flow can be saved.
  • the power supply voltage signal line and the common electrode line can be arranged in the same layer and the same material, so that the power supply voltage signal line and the common electrode line can be formed by one patterning process, which can reduce the number of patterning processes for manufacturing the drive substrate .
  • the driving substrate includes: a base substrate 10, a first driving function layer located on the first surface of the base substrate 10, and a first driving function layer located on the base substrate 10.
  • the second driving function layer on two surfaces, the first surface and the second surface are two opposite surfaces.
  • the first driving function layer includes: the active layer 11, the active layer 11 may be P-Si, and the thickness is roughly in the range of 400-500 angstroms, specifically 470 angstroms; the first gate insulating layer 12.
  • the first gate insulating layer 12 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness is roughly in the range of 400-800 angstroms. Specifically, silicon oxide/silicon nitride can be used.
  • the first gate metal layer 13 the pattern of the first gate metal layer 3 includes gate lines and the gates of thin film transistors, etc., the first gate metal layer 13 can be made of Mo, the thickness The value is roughly in the range of 2500-3600 angstroms, specifically 3100 angstroms;
  • the second gate insulating layer 14 and the second gate insulating layer 14 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the thickness is approximately in the range of 1000-2000 angstroms, and can be specifically 1400 angstroms;
  • the second gate metal layer 15 has a pattern of the second gate metal layer 15 including the electrode plate of the storage capacitor;
  • the second gate metal layer 15 can Using Mo, the thickness is roughly in the range of 2500-3600 angstroms, specifically 3100 angstroms;
  • the first flat layer 30, the first flat layer 30 can be made of organic resin, and the thickness is roughly in the range of 18000-22000 angstroms Values between;
  • the first source-drain metal layer 31, the pattern of the first source-drain metal layer 31 includes a connecting line 311 and the first electrode 312 of the driving thin film transistor, wherein the connecting line 311 is used to transmit the VDD signal, the first electrode It can be a source electrode or a drain electrode.
  • the first source-drain metal layer 31 can also be used to make a data line.
  • the first source-drain metal layer 31 can adopt a stacked structure of titanium/aluminum/titanium, and the thickness can be 500 angstroms/5000 respectively. Angstroms/500 Angstroms; the second flat layer 32, the second flat layer 32 can be made of organic resin, and the thickness is approximately in the range of 18000-22000 Angstroms; the second source-drain metal layer 34, the second source-drain metal layer The thickness of the second source-drain metal layer 34 is greater than the threshold value.
  • the pattern of the second source-drain metal layer 34 includes signal traces and second pads 343.
  • the signal traces include VDD traces 341 and VSS traces 342.
  • the VSS traces 342 also serve as the first For bonding pads, the second bonding pad 343 is connected to the first pole 312 of the driving thin film transistor; the third flat layer 36, the third flat layer 36 can be made of organic resin, and the thickness is roughly in the range of 18000-22000 angstroms .
  • the first driving function layer may also include a buffer layer (not shown) between the active layer 11 and the base substrate 10.
  • the buffer layer may be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. Specifically, a silicon nitride/silicon oxide laminated structure can be used, and the thickness can be 500 angstroms/3000 angstroms respectively.
  • the buffer layer can prevent impurities on the base substrate 10 from entering the active layer 11, thereby affecting the performance of the thin film transistor.
  • the third flat layer 36 includes via holes exposing part of the surface of the VSS trace 342 and the second pad 343.
  • the N pad 252 of the LED 25 can be bonded and connected with the VSS trace 342, and the P pad 251 of the LED 25 can be connected to the first The two pads 343 are bonded and connected together.
  • the signal routing is not limited to using copper, and other metals, such as silver, aluminum, etc., can also be used.
  • the thickness of the copper layer can be adjusted according to the size of the current load. The greater the current load, the greater the thickness of the copper layer. The thickness of the copper layer may be 2-30 um, and in some embodiments, it may be 2 um specifically.
  • the copper layer can be completed by sputtering, electroplating, chemical plating, etc.
  • the driving substrate further includes a first passivation layer 33 on the second flat layer 32. 32 for protection.
  • the first passivation layer 33 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the first passivation layer 33 is approximately in the range of 500-3000 angstroms.
  • the copper layer is formed by a low-temperature deposition method, since the low-temperature deposition method will not cause damage to the second flat layer 32, the provision of the first passivation layer 33 can be omitted at this time.
  • the driving substrate further includes a second passivation layer 35 on the second source and drain metal layer 34.
  • the second passivation layer 35 can protect the copper and prevent the surface of the copper from being oxidized when the third flat layer 36 is cured at a high temperature.
  • the second passivation layer 35 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the second passivation layer 35 is approximately in the range of 500-3000 angstroms.
  • the N pad 252 of the LED 25 needs to be bound and connected to the first pad 342, and the P pad 251 of the LED 25 needs to be bound and connected to the second pad 343. Therefore, it can be connected to the first pad.
  • 342 and the second pad 343 are not provided with the second passivation layer 35; alternatively, the second passivation layer 35 is also provided on the first pad 342 and the second pad 343, but before bonding the LED 25, The second passivation layer 35 on the first pad 342 and the second pad 343 is removed.
  • the second source and drain metal layer 34 also includes a metal layer on the side of the copper layer close to the base substrate.
  • the adhesion between the metal layer and the second flat layer 32 The force is greater than the adhesion force of the copper layer and the second flat layer 32 to prevent the copper layer from falling off the base substrate.
  • the metal layer may use at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and may also use metal oxides such as IGZO, IZO, GZO, and ITO.
  • the thickness of the metal layer is approximately in the range of 200-500 angstroms.
  • the second driving function layer includes: fan-out wiring structure 26, fan-out wiring structure 26 can adopt Al/Mo laminated structure, the thickness can be 6000 angstroms/600 angstroms respectively; passivation layer 27, passivation layer 27 can adopt nitrogen Inorganic insulating materials such as silicon oxide, silicon oxide, silicon oxynitride, etc., whose thickness is roughly in the range of 5000-7000 angstroms; the binding pins 282 used to bind to the flexible circuit board and the fan-out wiring structure 26
  • the lead pad 281 connected to the bonding pin 282 can be made of a transparent conductive material such as ITO, and the thickness is approximately in the range of 400-600 angstroms.
  • the first driving function layer, the first source-drain metal layer 31 further includes a first conductive sub-pattern 312, and the second source-drain metal layer 34 further includes a second conductive sub-pattern 344, the first conductive sub-pattern 312 and the second conductive sub-pattern.
  • the electronic patterns 344 are connected in parallel to form a conductive structure, which is connected to the signal traces in the display area; the conductive structure can be connected to the lead pad 281 through the conductive connection part on the side of the substrate (the area shown by the elliptical dashed frame), thereby realizing the lead pad 281 Connection with signal traces to transfer the signal output from the flexible circuit board to the signal traces.
  • a groove corresponding to the conductive connection portion can be provided on the side of the substrate, such as the area shown by the elliptical dashed frame, so that at least a part of the conductive connection portion is located in the groove, which can reduce the conductive connection. Risk of injury to the part.
  • one of the source and drain metal layers used to form the signal wiring in the three-layer source and drain metal layers basically covers the entire display area of the substrate.
  • the thickness of the insulating layer between the two source and drain metal layers is relatively small, and the probability of a defective short circuit between the two source and drain metal layers is high, which will lead to subsequent processes, such as the third flat layer 36 made by chemical vapor deposition.
  • static charges will accumulate on the large-area metal layer, causing arc discharge, damaging the machine, and affecting the yield of the drive substrate.
  • the first source-drain metal layer 31 is used to make a signal transmission line, and the signal transmission line is connected to the signal wiring made of the second source-drain metal layer 34 to form a grid structure.
  • the signal traces made by the source-drain metal layer 34 include VSS traces and VDD traces. A part of the signal transmission lines are connected with the VSS traces to form a grid structure to transmit VSS signals. Among them, the signal transmission lines for transmitting the VSS signals are connected to the corresponding VSS traces.
  • the line is connected at the intersection through the via hole penetrating the second flat layer 32; the other part of the signal transmission line is connected with the VDD trace to form a grid structure to transmit the VDD signal, where the signal transmission line for transmitting the VDD signal is connected to the corresponding VDD trace.
  • the intersections are connected by vias penetrating through the second flat layer 32. Since this embodiment adopts a single-layer source and drain metal layer to make signal traces, the occurrence rate of short-circuit defects can be reduced to less than 1%, and the yield rate of the driving substrate is ensured.
  • the number of source-drain metal layers included in the driving substrate is small, even if the width of the signal traces made by the second source-drain metal pattern 34 increases, the occupied area will increase, and no short circuit will be caused. The incidence of defects has increased significantly.
  • FIG. 4 is a partial enlarged schematic view of Fig. 3
  • Fig. 5 is a schematic cross-sectional view of Fig. 4 in the AA' direction
  • Fig. 6 is a schematic cross-sectional view of Fig. 4 in the BB’ direction
  • Fig. 7 is a cross-sectional view of Fig. 4 in the CC’ direction
  • FIG. 8 is a schematic cross-sectional view of FIG. 4 in the DD' direction.
  • the line width of the signal transmission line formed by the first source-drain metal layer 31 is a
  • the line width of the signal line formed by the second source-drain metal layer 34 is b
  • the spacing between is c, where the value of a/b is 1-1.2, which can be 1.1 specifically; the value of b/c is 1.8-2.2, which can be specifically 2.
  • the above parameters are used to determine the line width of the signal transmission line ,
  • the line width and spacing of the signal traces are designed to reduce the transmission loss of the VSS signal and the VDD signal, and also reduce the incidence of short-circuit defects.
  • FIG. 9 is a schematic diagram of the driving substrate in the pad area of the embodiment of the disclosure
  • FIG. 10 is a schematic cross-sectional view of FIG. 9 in the EE' direction.
  • the pad area includes a first pad area H1 and a second pad area H2.
  • a pad area H1 is provided with a first pad
  • a second pad area H2 is provided with a second pad. As shown in FIG.
  • d is the horizontal distance between the edge of the first source-drain metal layer 31 and the edge of the second source-drain metal layer 34
  • e is the edge of the second source-drain metal layer 34 and the second
  • f is the distance between the edge of the second flat layer 32 and the edge of the first passivation layer 33 in the horizontal direction
  • g is the distance between the edge of the first passivation layer 33 and the third passivation layer 33.
  • the distance of the edge of the flat layer 36 in the horizontal direction, and h is the distance between the edge of the third flat layer 36 and the edge of the second passivation layer 35 in the horizontal direction.
  • the value of e/d is 1.4-1.6, specifically 1.5; the value of f/e is 1.4-1.6, specifically 1.5; the value of f/g is 1.4-1.6, specifically 1.5; The value of h/g is 1.4-1.8, specifically 1.67.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned driving substrate and an electronic component fixed on the pad layer, and a first pole of the electronic component is bonded and connected to the first pad layer , The second pole of the electronic component is bonded and connected to the second pad.
  • the electronic component is an LED.
  • the N pad 252 of the LED 25 can be bound and connected to the first pad 342, and the P pad 251 of the LED 25 can be bound and connected to the second pad 343.
  • the display device may be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, and a flexible circuit board Bind with binding pin 282.
  • the embodiment of the present disclosure also provides a manufacturing method of a driving substrate, including:
  • a first driving function layer is formed on the first surface of the base substrate.
  • the first driving function layer includes a plurality of driving thin film transistors and a plurality of signal traces. At least one of the signal traces adopts a single-layer structure and has a thickness Greater than the threshold
  • a pad layer is formed on the side of the first driving function layer away from the base substrate.
  • the pad layer includes a plurality of first pads and a plurality of second pads.
  • the first electrode of the driving thin film transistor is connected, and the second pad is connected to the common electrode line in the signal wiring.
  • the thickness of the signal trace itself is relatively large, which can effectively reduce the IR drop, so there is no need to form signal traces in parallel, which can reduce the number of metal layers included in the drive substrate, thereby reducing the cost of manufacturing the drive substrate.
  • the number of patterning processes reduces the production cost of the drive substrate.
  • the manufacturing method of the drive substrate of this embodiment is used to manufacture the drive substrate in the above-mentioned embodiment.
  • the signal routing is not limited to using copper, and other metals, such as silver, aluminum, etc., can also be used.
  • the thickness of the copper layer can be adjusted according to the size of the current load. The greater the current load, the greater the thickness of the copper layer. The thickness of the copper layer may be 2-30 um, and in some embodiments, it may be 2 um specifically.
  • the copper layer can be completed by sputtering, electroplating, chemical plating, etc.
  • the manufacturing method of the drive substrate specifically includes the following steps:
  • Step 1 Provide a base substrate 10, and form a buffer layer and an active layer 11 on the base substrate 10;
  • the base substrate 10 may be a glass substrate, a quartz substrate or a flexible substrate.
  • a plasma-enhanced chemical vapor deposition (PECVD) method can be used to form a buffer layer on the base substrate 10.
  • the buffer layer can be oxide, nitride, or oxygen-nitrogen compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • the buffer layer may adopt a laminated structure of silicon nitride/silicon oxide, and the thickness may be 500 angstroms/3000 angstroms, respectively.
  • a layer of semiconductor material is formed on the buffer layer, and the semiconductor material is patterned to form the active layer 11.
  • the active layer 11 may be P-Si, and the thickness may be 400-500 angstroms, specifically 470 angstroms.
  • Step 2 Form the first gate insulating layer 12;
  • PECVD can be used to deposit the first gate insulating layer 12 with a thickness of 400-800 angstroms.
  • the first gate insulating layer 12 can be selected from oxides, nitrides or oxynitride compounds, and the corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • Step 3 Form a pattern of the first gate metal layer 13;
  • the first gate metal layer 13 may be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn. , Ti, Ta, W and other metals and alloys of these metals, specifically Mo can be used.
  • a layer of photoresist is coated on the first gate metal layer 13, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist
  • the reserved area corresponds to the area where the pattern of the first gate metal layer 13 is located, and the unreserved photoresist area corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist
  • the thickness of the photoresist in the reserved area remains unchanged; the first gate metal layer 13 in the unreserved area of the photoresist is completely etched by an etching process, and the remaining photoresist is stripped to form a pattern of the first gate metal layer 13.
  • the pattern of the first gate metal layer 3 includes gate lines and gates of thin film transistors.
  • Step 4 Form a second gate insulating layer 14;
  • PECVD can be used to deposit the second gate insulating layer 14 with a thickness of 1000-2000 angstroms.
  • the second gate insulating layer 14 can be selected from oxides, nitrides or oxynitride compounds, and the corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • Step 5 Form a pattern of the second gate metal layer 15;
  • the second gate metal layer 15 may be Cu, Al, Ag, Mo, Cr, Nd, Ni. , Mn, Ti, Ta, W and other metals and alloys of these metals, specifically Mo can be used.
  • a layer of photoresist is coated on the second gate metal layer 15, and a mask is used to expose the photoresist so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, where the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the second gate metal layer 15 is formed, and the unreserved area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the second gate metal layer 15 is formed by completely etching away the unreserved area of the photoresist by the etching process, and the remaining photoresist is stripped to form the second gate metal layer 15
  • the pattern forming the second gate metal layer 15 includes the plate of the storage capacitor and the like.
  • Step 6 Form a first flat layer 30
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the first flat layer 30.
  • Step 7 Form a pattern of the first source-drain metal layer 31;
  • magnetron sputtering, thermal evaporation or other film forming methods can be used to deposit a source and drain metal layer with a thickness of about 5000-6000 angstroms.
  • the source and drain metal layers can be Cu, Al, Ag, Mo, Cr, Nd. , Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the source and drain metal layer can be a single-layer structure or a multi-layer structure. Multi-layer structures such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc., can be specifically stacked with Ti/Al/Ti, and the thickness can be They are 500 angstroms/5000 angstroms/500 angstroms respectively.
  • a layer of photoresist is coated on the first source and drain metal layer 31, and the photoresist is exposed by a mask, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the first source/drain metal layer 31 is located, and the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the first source/drain metal layer 31 in the unreserved area of the photoresist is completely etched by the etching process, and the remaining photoresist is stripped to form the first source/drain metal layer 31.
  • the pattern of the first source-drain metal layer 31 includes a connecting line 311 and the first electrode 312 of the driving thin film transistor.
  • the connecting line 311 is used to transmit the VDD signal.
  • the first electrode can be a source or a drain.
  • the pattern of a source-drain metal layer 31 also includes data lines.
  • Step 8 Form a second flat layer 32;
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the second flat layer 32.
  • a second source-drain metal layer 34 is formed on the second flat layer 32 by sputtering.
  • the second source-drain metal layer 34 adopts a metal layer/copper laminated structure.
  • the adhesion between the metal layer and the second flat layer 32 The adhesion force is greater than the adhesion force between the copper and the second flat layer 32, which can increase the adhesion between the copper and the second flat layer 32, so that the copper is not easy to fall off.
  • the metal layer may be Mo.
  • the thickness of Mo may be 300 angstroms, and the thickness of copper may be about 2um.
  • a layer of photoresist is coated on the second source and drain metal layer 34, and the photoresist is exposed by a mask, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, where the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the second source and drain metal layer 34 is located, and the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the second source/drain metal layer 34 in the unreserved area of the photoresist is completely etched by an etching process, and the remaining photoresist is stripped to form a second source/drain metal layer 34.
  • the second source and drain metal layer 34 includes signal traces and second pads 343.
  • the signal traces include VDD traces 341 and VSS traces 342.
  • the VSS traces 342 also serve as the first pads.
  • the second pad 343 is connected to the first electrode 312 of the driving thin film transistor.
  • Step 10 forming a third flat layer 36.
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated, and cured at a high temperature to form the third flat layer 36.
  • the third flat layer 36 may be patterned to form a via hole exposing the VSS trace 342 and the second pad 343.
  • the base substrate 10 can be turned over, and a second driving function layer can be fabricated on the other side surface of the base substrate 10 to complete the fabrication of the driving substrate.
  • the first passivation layer 33 may be an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the first passivation layer 33 may be 500-3000 angstroms.
  • the step of forming the first passivation layer 33 can be omitted at this time.
  • a second passivation layer 35 is formed on the pattern of the second source and drain metal layer 34.
  • the second passivation layer 35 can protect the copper and prevent the surface of the copper from being oxidized when the third flat layer 36 is cured at a high temperature.
  • the second passivation layer 35 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the second passivation layer 35 can be 500-3000 angstroms.
  • the manufacturing method of the drive substrate specifically includes the following steps:
  • Step 1 Provide a base substrate 10, and form a buffer layer and an active layer 11 on the base substrate 10;
  • the base substrate 10 may be a glass substrate, a quartz substrate or a flexible substrate.
  • a plasma-enhanced chemical vapor deposition (PECVD) method can be used to form a buffer layer on the base substrate 10.
  • the buffer layer can be oxide, nitride, or oxygen-nitrogen compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • the buffer layer may adopt a laminated structure of silicon nitride/silicon oxide, and the thickness may be 500 angstroms/3000 angstroms, respectively.
  • a layer of semiconductor material is formed on the buffer layer, and the semiconductor material is patterned to form the active layer 11.
  • the active layer 11 may be P-Si, and the thickness may be 400-500 angstroms, specifically 470 angstroms.
  • Step 2 Form the first gate insulating layer 12;
  • PECVD can be used to deposit the first gate insulating layer 12 with a thickness of 400-800 angstroms.
  • the first gate insulating layer 12 can be selected from oxides, nitrides or oxynitride compounds, and the corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • Step 3 Form a pattern of the first gate metal layer 13;
  • the first gate metal layer 13 may be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn. , Ti, Ta, W and other metals and alloys of these metals, specifically Mo can be used.
  • a layer of photoresist is coated on the first gate metal layer 13, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist
  • the reserved area corresponds to the area where the pattern of the first gate metal layer 13 is located, and the unreserved photoresist area corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist
  • the thickness of the photoresist in the reserved area remains unchanged; the first gate metal layer 13 in the unreserved area of the photoresist is completely etched by an etching process, and the remaining photoresist is stripped to form a pattern of the first gate metal layer 13.
  • the pattern of the first gate metal layer 3 includes gate lines and gates of thin film transistors.
  • Step 4 Form a second gate insulating layer 14;
  • PECVD can be used to deposit the second gate insulating layer 14 with a thickness of 1000-2000 angstroms.
  • the second gate insulating layer 14 can be selected from oxides, nitrides or oxynitride compounds, and the corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • Step 5 Form a pattern of the second gate metal layer 15;
  • the second gate metal layer 15 may be Cu, Al, Ag, Mo, Cr, Nd, Ni. , Mn, Ti, Ta, W and other metals and alloys of these metals, specifically Mo can be used.
  • a layer of photoresist is coated on the second gate metal layer 15, and a mask is used to expose the photoresist so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, where the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the second gate metal layer 15 is formed, and the unreserved area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the second gate metal layer 15 is formed by completely etching away the unreserved area of the photoresist by the etching process, and the remaining photoresist is stripped to form the second gate metal layer 15
  • the pattern forming the second gate metal layer 15 includes the plate of the storage capacitor and the like.
  • Step 6 Form a first flat layer 30
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the first flat layer 30.
  • Step 7 Form a pattern of the first source-drain metal layer 31;
  • magnetron sputtering, thermal evaporation or other film forming methods can be used to deposit a source and drain metal layer with a thickness of about 5000-6000 angstroms.
  • the source and drain metal layers can be copper, Al, Ag, Mo, Cr, Nd. , Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the source/drain metal layer can be a single-layer structure or a multi-layer structure.
  • Multi-layer structures such as copper ⁇ Mo, Ti ⁇ copper ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc., can be specifically a laminated structure of titanium/aluminum/titanium, and the thickness can be They are 500 angstroms/5000 angstroms/500 angstroms respectively.
  • a layer of photoresist is coated on the first source and drain metal layer 31, and the photoresist is exposed by a mask, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the first source/drain metal layer 31 is located, and the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the first source/drain metal layer 31 in the unreserved area of the photoresist is completely etched by the etching process, and the remaining photoresist is stripped to form the first source/drain metal layer 31.
  • the pattern of the first source-drain metal layer 31 includes a connecting line 311 and the first electrode 312 of the driving thin film transistor.
  • the connecting line 311 is used to transmit the VDD signal.
  • the first electrode can be a source or a drain.
  • the pattern of a source-drain metal layer 31 also includes data lines.
  • Step 8 Form a second flat layer 32;
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the second flat layer 32.
  • Step 9 Form a pattern of the second source and drain metal layer 34;
  • a seed layer is formed on the second flat layer 32 by sputtering.
  • the seed layer adopts a metal layer/copper laminated structure.
  • the adhesion between the metal layer and the second flat layer 32 is greater than that between copper and the second flat layer 32
  • the adhesion between the copper and the second flat layer 32 can increase the adhesion between the copper and the second flat layer 32, so that the copper is not easy to fall off.
  • the metal layer can be Mo.
  • the thickness of the seed layer is less than the threshold.
  • the thickness of Mo in the seed layer may be 300 angstroms, and the thickness of copper in the seed layer may be 3000 angstroms.
  • a layer of metallic copper is grown on the seed layer by electroplating, and the thickness of the grown copper can reach more than 2 um.
  • the grown copper and the seed layer form the second source and drain metal layer 34.
  • a layer of photoresist is coated on the second source and drain metal layer 34, and the photoresist is exposed by a mask, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, where the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the second source and drain metal layer 34 is located, and the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the second source/drain metal layer 34 in the unreserved area of the photoresist is completely etched by an etching process, and the remaining photoresist is stripped to form a second source/drain metal layer 34.
  • the second source and drain metal layer 34 includes signal traces and second pads 343.
  • the signal traces include VDD traces 341 and VSS traces 342.
  • the VSS traces 342 also serve as the first pads.
  • the second pad 343 is connected to the first electrode 312 of the driving thin film transistor.
  • Step 10 forming a third flat layer 36.
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the third flat layer 36.
  • the third flat layer 36 may be patterned to form a via hole exposing the VSS trace 342 and the second pad 343.
  • the base substrate 10 can be turned over, and a second driving function layer can be fabricated on the other side surface of the base substrate 10 to complete the fabrication of the driving substrate.
  • the first passivation layer 33 may be an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the first passivation layer 33 may be 500-3000 angstroms.
  • the step of forming the first passivation layer 33 can be omitted at this time.
  • a second passivation layer 35 is formed on the pattern of the second source and drain metal layer 34.
  • the second passivation layer 35 can protect the copper and prevent the surface of the copper from being oxidized when the third flat layer 36 is cured at a high temperature.
  • the second passivation layer 35 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the second passivation layer 35 can be 500-3000 angstroms.
  • the manufacturing method of the drive substrate specifically includes the following steps:
  • Step 1 Provide a base substrate 10, and form a buffer layer and an active layer 11 on the base substrate 10;
  • the base substrate 10 may be a glass substrate, a quartz substrate or a flexible substrate.
  • a plasma-enhanced chemical vapor deposition (PECVD) method can be used to form a buffer layer on the base substrate 10.
  • the buffer layer can be oxide, nitride, or oxygen-nitrogen compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • the buffer layer may adopt a laminated structure of silicon nitride/silicon oxide, and the thickness may be 500 angstroms/3000 angstroms, respectively.
  • a layer of semiconductor material is formed on the buffer layer, and the semiconductor material is patterned to form the active layer 11.
  • the active layer 11 may be P-Si, and the thickness may be 400-500 angstroms, specifically 470 angstroms.
  • Step 2 Form the first gate insulating layer 12;
  • PECVD can be used to deposit the first gate insulating layer 12 with a thickness of 400-800 angstroms.
  • the first gate insulating layer 12 can be selected from oxides, nitrides or oxynitride compounds, and the corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • the first gate metal layer 13 may be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn. , Ti, Ta, W and other metals and alloys of these metals, specifically Mo can be used.
  • a layer of photoresist is coated on the first gate metal layer 13, and a mask is used to expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist
  • the reserved area corresponds to the area where the pattern of the first gate metal layer 13 is located, and the unreserved photoresist area corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist
  • the thickness of the photoresist in the reserved area remains unchanged; the first gate metal layer 13 in the unreserved area of the photoresist is completely etched by an etching process, and the remaining photoresist is stripped to form a pattern of the first gate metal layer 13.
  • the pattern of the first gate metal layer 3 includes gate lines and gates of thin film transistors.
  • Step 4 Form a second gate insulating layer 14;
  • PECVD can be used to deposit the second gate insulating layer 14 with a thickness of 1000-2000 angstroms.
  • the second gate insulating layer 14 can be selected from oxides, nitrides or oxynitride compounds, and the corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • Step 5 Form a pattern of the second gate metal layer 15;
  • the second gate metal layer 15 may be Cu, Al, Ag, Mo, Cr, Nd, Ni. , Mn, Ti, Ta, W and other metals and alloys of these metals, specifically Mo can be used.
  • a layer of photoresist is coated on the second gate metal layer 15, and a mask is used to expose the photoresist so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, where the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the second gate metal layer 15 is formed, and the unreserved area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the second gate metal layer 15 is formed by completely etching away the unreserved area of the photoresist by the etching process, and the remaining photoresist is stripped to form the second gate metal layer 15
  • the pattern forming the second gate metal layer 15 includes the plate of the storage capacitor and the like.
  • Step 6 Form a first flat layer 30
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the first flat layer 30.
  • Step 7 Form a pattern of the first source-drain metal layer 31;
  • magnetron sputtering, thermal evaporation or other film forming methods can be used to deposit a source and drain metal layer with a thickness of about 5000-6000 angstroms.
  • the source and drain metal layers can be Cu, Al, Ag, Mo, Cr, Nd. , Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the source and drain metal layer can be a single-layer structure or a multi-layer structure. Multi-layer structures such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc., can be specifically stacked with Ti/Al/Ti, and the thickness can be They are 500 angstroms/5000 angstroms/500 angstroms respectively.
  • a layer of photoresist is coated on the first source and drain metal layer 31, and the photoresist is exposed by a mask, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photolithography
  • the remaining area of the photoresist corresponds to the area where the pattern of the first source/drain metal layer 31 is located, and the unreserved area of photoresist corresponds to the area other than the above-mentioned pattern; after the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the resist reserved area remains unchanged; the first source/drain metal layer 31 in the unreserved area of the photoresist is completely etched by the etching process, and the remaining photoresist is stripped to form the first source/drain metal layer 31.
  • the pattern of the first source-drain metal layer 31 includes a connecting line 311 and the first electrode 312 of the driving thin film transistor.
  • the connecting line 311 is used to transmit the VDD signal.
  • the first electrode can be a source or a drain.
  • the pattern of a source-drain metal layer 31 also includes data lines.
  • Step 8 Form a second flat layer 32;
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the second flat layer 32.
  • Step 9 Form a pattern of the second source and drain metal layer 34;
  • a seed layer is formed on the second flat layer 32 by sputtering.
  • the seed layer adopts a metal layer/copper laminated structure.
  • the adhesion between the metal layer and the second flat layer 32 is greater than that between copper and the second flat layer 32
  • the adhesion between the copper and the second flat layer 32 can increase the adhesion between the copper and the second flat layer 32, so that the copper is not easy to fall off.
  • the metal layer can be Mo.
  • the thickness of the seed layer is less than the threshold.
  • the thickness of Mo in the seed layer may be 300 angstroms, and the thickness of copper in the seed layer may be 3000 angstroms.
  • the photoresist unreserved area corresponds to the area outside the above pattern; the development process is performed, the photoresist in the photoresist unreserved area is completely removed, and the photoresist remaining area is The thickness of the photoresist remains unchanged; the seed layer in the unreserved area of the photoresist is completely etched by an etching process to form a pattern of the seed layer.
  • a layer of metallic copper is grown on the pattern of the seed layer by electroless plating, and the thickness of the grown copper can reach 2-3 um.
  • the pattern of the grown copper and the seed layer forms the pattern of the second source and drain metal layer 34.
  • the pattern of the second source and drain metal layer 34 includes signal traces and second pads 343.
  • the signal traces include VDD traces 341 and VSS traces 342.
  • the VSS traces 342 are also used as first pads, and the second The pad 343 is connected to the first electrode 312 of the driving thin film transistor.
  • a layer of organic resin with a thickness of 18000-22000 angstroms can be coated and cured at a high temperature to form the third flat layer 36.
  • the third flat layer 36 may be patterned to form a via hole exposing the VSS trace 342 and the second pad 343.
  • the base substrate 10 can be turned over, and a second driving function layer can be fabricated on the other side surface of the base substrate 10 to complete the fabrication of the driving substrate.
  • the first passivation layer 33 may be an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the first passivation layer 33 may be 500-3000 angstroms.
  • the step of forming the first passivation layer 33 can be omitted at this time.
  • a second passivation layer 35 is formed on the pattern of the second source and drain metal layer 34.
  • the second passivation layer 35 can protect the copper and prevent the surface of the copper from being oxidized when the third flat layer 36 is cured at a high temperature.
  • the second passivation layer 35 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the second passivation layer 35 can be 500-3000 angstroms.
  • sequence number of each step cannot be used to limit the sequence of each step.
  • sequence of each step is changed without creative work. It is also within the protection scope of the present disclosure.

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Abstract

一种驱动基板及其制作方法、显示装置，属于显示技术领域。驱动基板包括：衬底基板(10)；第一驱动功能层，设置于所述衬底基板(10)的第一表面，所述第一驱动功能层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；焊盘层，所述焊盘层设置于所述第一驱动功能层远离所述衬底基板的一侧，所述焊盘层包括多个第一焊盘(343)和多个第二焊盘(342)，所述第一焊盘(343)与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘(342)与所述信号走线中的公共电极线连接。通过上述技术方案，能够减少制作驱动基板的构图工艺的次数。

Description

驱动基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别是指一种驱动基板及其制作方法、显示装置。
背景技术
Micro-LED(微发光二极管)显示技术是将现有LED(发光二极管)的尺寸微缩至100um以下，再通过巨量转移技术，将其转移到驱动基板上，从而形成各种不同尺寸的Micro-LED显示器。Micro-LED具有自发光高亮度、高对比度、超高分辨率与色彩饱和度、长寿命、响应速度快、节能、适应环境宽泛等诸多优点，在各领域都有良好的应用前景。
发明内容
本公开实施例提供一种驱动基板及其制作方法、显示装置，能够减少制作驱动基板的构图工艺的次数。
本公开的实施例提供技术方案如下：
一方面，提供一种驱动基板，包括：
衬底基板；
第一驱动功能层，设置于所述衬底基板的第一表面，所述第一驱动功能层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；
焊盘层，所述焊盘层设置于所述第一驱动功能层远离所述衬底基板的一侧，所述焊盘层包括多个第一焊盘和多个第二焊盘，所述第一焊盘与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘与所述信号走线中的公共电极线连接。
一些实施例中，所述驱动基板还包括：
第二驱动功能层，设置于所述衬底基板的第二表面，所述第二表面与所述第一表面相对，所述第二驱动功能层包括引线衬垫和与所述引线衬垫连接 的绑定引脚；
所述衬底基板的侧表面设置有多个凹槽，每个所述凹槽均沿垂直于所述衬底基板的方向延伸，且贯穿所述衬底基板的第一表面和第二表面；
与所述凹槽一一对应的导电连接部，所述导电连接部的至少一部分位于对应的所述凹槽内，且所述导电连接部用于分别连接相对应的所述信号走线和所述引线衬垫。
一些实施例中，所述多条信号走线包括电源电压信号线和所述公共电极线，所述电源电压信号线和所述公共电极线的厚度均大于所述阈值。
一些实施例中，所述电源电压信号线和所述公共电极线同层同材料设置。
一些实施例中，驱动基板还包括：与所述信号走线连接的信号传输线，所述信号传输线与所述信号走线组成网格状结构。
一些实施例中，沿远离所述第一表面的方向，所述第一驱动功能层依次包括：
有源层；
第一栅绝缘层；
第一栅金属层；
第二栅绝缘层；
第二栅金属层；
第一平坦层；
第一源漏金属层；
第二平坦层；
第二源漏金属层，所述第二源漏金属层的图形包括所述信号走线；
第三平坦层。
一些实施例中，所述第二源漏金属层包括层叠设置的铜层和金属层，所述金属层位于所述铜层靠近所述衬底基板的一侧，所述金属层与所述第二平坦层的粘附力大于所述铜层与所述第二平坦层的粘附力。
一些实施例中，所述铜层的厚度为2-30um。
一些实施例中，所述驱动基板还包括位于所述铜层和所述第一平坦层之间的第一钝化层，所述第一钝化层采用无机绝缘材料。
一些实施例中，所述驱动基板还包括位于所述铜层和所述第二平坦层之间的第二钝化层，所述第二钝化层采用无机绝缘材料。
另一方面，提供一种显示装置，包括如上所述的驱动基板和固定在所述焊盘层上的电子元件，所述电子元件的第一极与所述第一焊盘绑定连接，所述电子元件的第二极与所述第二焊盘绑定连接。
另一方面，提供一种驱动基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板的第一表面形成第一驱动功能层，所述第一驱动功能层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；
在所述第一驱动功能层远离所述衬底基板的一侧形成焊盘层，所述焊盘层包括多个第一焊盘和多个第二焊盘，所述第一焊盘与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘与所述信号走线中的公共电极线连接。
一些实施例中，所述驱动基板包括第一源漏金属层的图形和第二源漏金属层的图形，所述第二源漏金属层的图形包括所述信号走线，形成所述信号走线包括：
形成厚度小于阈值的种子层；
在所述种子层上以电镀方法生长出导电层，所述种子层和所述导电层组成第二源漏金属层；
对所述第二源漏金属层进行构图，形成所述信号走线。
一些实施例中，所述驱动基板包括第一源漏金属层的图形和第二源漏金属层的图形，所述第二源漏金属层的图形包括所述信号走线，形成所述信号走线包括：
形成厚度小于阈值的种子层；
对所述种子层进行构图形成种子层的图形，所述种子层的图形位于待形成的信号走线所在区域；
在所述种子层的图形上以化学镀方式生长出导电层的图形，所述导电层的图形和所述种子层的图形组成所述信号走线。
一些实施例中，形成所述种子层包括：
形成层叠设置的铜层和金属层，所述金属层位于所述铜层靠近所述衬底基板的一侧，所述金属层与绝缘层的粘附力大于所述铜层与所述绝缘层的粘附力。
附图说明
图1为相关技术驱动基板的结构示意图；
图2为本公开实施例驱动基板的结构示意图；
图3为本公开实施例驱动基板在显示区域的走线示意图；
图4为图3的局部放大示意图；
图5为图4在AA’方向上的截面示意图；
图6为图4在BB’方向上的截面示意图；
图7为图4在CC’方向上的截面示意图；
图8为图4在DD’方向上的截面示意图；
图9为本公开实施例驱动基板在焊盘区域的示意图；
图10为图9在EE’方向上的截面示意图。
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
Micro-LED显示器的驱动基板的电流负载大，可以达到几十毫安，对信号走线的线宽以及阻值要求高，如果信号走线阻值过大则会导致在信号走线上的电信号损耗较大，进而使驱动基板的功耗较高。
图1为相关技术中驱动基板的结构示意图。如图1所示，驱动基板包括衬底基板10、位于衬底基板10第一表面的第一驱动功能层和位于衬底基板10第二表面的第二驱动功能层，第一表面和第二表面为相对的两个表面。其中，第一驱动功能层包括：有源层11，有源层11可以采用多晶硅，厚度大致在400-500埃的范围内之间取值；第一栅绝缘层12，第一栅绝缘层12可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在400-800埃的范围内之间取值；第一栅金属层13，第一栅金属层13可以采用Mo，厚度大致 在2500-3600埃的范围内之间取值；第二栅绝缘层14，第二栅绝缘层14可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在1000-2000埃的范围内之间取值；第二栅金属层15，第二栅金属层15可以采用Mo，厚度大致在2500-3600埃的范围内之间取值；层间绝缘层16，层间绝缘层16可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在2000-3000埃的范围内之间取值；第一源漏金属层17，第一源漏金属层17可以采用钛/铝/钛的叠层结构，厚度可以分别为500埃/5000埃/500埃；第一平坦层18，第一平坦层18可以采用有机树脂，厚度大致在18000-22000埃的范围内之间取值；第二源漏金属层19，第二源漏金属层19可以采用钛/铝/钛的叠层结构，厚度可以分别为500埃/6500埃/500埃；第二平坦层20，第二平坦层20可以采用有机树脂，厚度大致在18000-22000埃的范围内之间取值；第一钝化层21，第一钝化层21可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在2000-3000埃的范围内之间取值；第三源漏金属层22，第三源漏金属层22可以采用铜，厚度大致在5500-6500埃的范围内之间取值；第二钝化层23，第二钝化层23可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在2000-3000埃的范围内之间取值；第三平坦层24，第三平坦层24可以采用有机树脂，厚度大致在18000-22000埃的范围内之间取值。进一步的，第一驱动功能层还可以包括位于有源层11和衬底基板10之间的缓冲层(未图示)，缓冲层可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，具体可以采用氮化硅/氧化硅的叠层结构，厚度可以分别为500埃/3000埃。
第一源漏金属层17用以制作数据线，第一源漏金属层17还包括第一子图形171和第二子图形172，第一子图形171用以传递VDD(电源电压)信号；第二子图形172用以传递驱动电压信号；第二源漏金属层19包括第三子图形191和第四子图形192，第三子图形191用以传递VDD信号；第四子图形192用以传递VSS(低电压)信号；第三源漏金属层22包括第五子图形221、第六子图形222和第七子图形223，第五子图形221用以传递VDD信号；第六子图形222用以传递VSS信号，第七子图形223用以传递驱动电压信号。第三平坦层24包括暴露出第六子图形222和第七子图形223的过孔， 第六子图形222和第七子图形223可以作为焊盘，LED25的N pad252可以与第六子图形222绑定连接在一起，LED25的P pad251可以与第七子图形223绑定连接在一起。
第二驱动功能层包括：扇出走线结构26，扇出走线结构26可以采用Al/Mo的叠层结构，厚度可以分别为6000埃/600埃；钝化层27，钝化层27可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在5000-7000埃的范围内之间取值；用以与柔性电路板绑定的绑定引脚282以及通过扇出走线结构26与绑定引脚282连接的引线衬垫281，可以采用透明导电材料比如ITO，厚度大致在400-600埃的范围内之间取值。
可以理解的是，由于多个绑定引脚282之后会与柔性电路板的端子进行绑定，而多个引线衬垫281与第一导电子图形312和第二导电子图形344并联组成导电结构一一对应，且多个引线衬垫281在基底所在平面的正投影与导电结构基本重合，因此多个引线衬垫281中的相邻两个引线衬垫281的排布间距比多个绑定引脚282中的相邻两个绑定引脚282的排布间距要大。
另外，第一源漏金属层17还包括第八子图形173，第二源漏金属层19还包括第九子图形193，第三源漏金属层22还包括第十子图形224，第八子图形173、第九子图形193和第十子图形224组成导电结构，用以沿衬底基板10侧表面的凹槽与引线衬垫281连接，将柔性电路板输出的信号传递至VDD走线和VSS走线。
图1所示的驱动基板中，可以看出，为了降低IR Drop，通过两层金属(第三子图形191和第五子图形221)并联组成VDD走线，在驱动基板上设置有三层源漏金属层，驱动基板的结构比较复杂，导致制作驱动基板的构图工艺的次数较多，影响了驱动基板的生产节拍，导致驱动基板的生产成本较大。
本公开实施例提供一种驱动基板及其制作方法、显示装置，能够减少制作驱动基板的构图工艺的次数。
本公开的实施例提供一种驱动基板，包括：
衬底基板；
第一驱动功能层，设置于所述衬底基板的第一表面，所述第一驱动功能 层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；
焊盘层，所述焊盘层设置于所述第一驱动功能层远离所述衬底基板的一侧，所述焊盘层包括多个第一焊盘和多个第二焊盘，所述第一焊盘与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘与所述信号走线中的公共电极线连接。
本实施例中，信号走线本身的厚度比较大，能够有效降低IR Drop，这样不需要通过并联的方式形成信号走线，能够减少驱动基板包括的金属层的层数，从而减少制作驱动基板的构图工艺的次数，降低驱动基板的生产成本。
具体地，上述阈值可以为2μm。
驱动基板的信号走线包括电源电压信号线VDD走线和公共电极线VSS走线，VDD走线用以传输第一固定电平信号，VSS走线用以传输第二固定电平信号，若VDD走线和VSS走线的阻值较大则会导致驱动基板的功耗较高(IR Drop较大)，其中第一固定电平信号和第二固定电平信号的幅值不同。
如图1所示的相关技术中，第二源漏金属层19可以采用钛/铝/钛的叠层结构，厚度可以分别为500埃/6500埃/500埃，第三源漏金属层22可以采用厚度为6000埃的铜，采用第二源漏金属层19和第三源漏金属层22并联组成信号走线(如VDD走线和VSS走线)，信号走线的电阻率为0.0035欧姆·米左右.。本实施例中，直接采用单层的厚度大于2um的导电材料如铜来制作信号走线，可以使得信号走线的电阻率降低到0.001欧姆·米左右，能够大大降低信号走线的电阻率，不但可以降低信号走线的IR Drop，而且可以节约工艺流程，。
一些实施例中，所述电源电压信号线和所述公共电极线可以同层同材料设置，这样可以通过一次构图工艺形成电源电压信号线和公共电极线，能够降低制作驱动基板的构图工艺的次数。
如图2所示，一具体实施例中，以电子元件为LED为例，驱动基板包括：衬底基板10、位于衬底基板10第一表面的第一驱动功能层和位于衬底基板10第二表面的第二驱动功能层，第一表面和第二表面为相对的两个表面。
其中，第一驱动功能层包括：有源层11，有源层11可以采用P-Si，厚度大致在400-500埃的范围内之间取值，具体可以为470埃；第一栅绝缘层12，第一栅绝缘层12可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在400-800埃的范围内之间取值，具体可以采用氧化硅/氮化硅的叠层结构，厚度分别为800埃和400埃；第一栅金属层13，第一栅金属层3的图形包括栅线和薄膜晶体管的栅极等，第一栅金属层13可以采用Mo，厚度大致在2500-3600埃的范围内之间取值，具体可以为3100埃；第二栅绝缘层14，第二栅绝缘层14可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在1000-2000埃的范围内之间取值，具体可以为1400埃；第二栅金属层15，第二栅金属层15的图形包括存储电容的极板；第二栅金属层15可以采用Mo，厚度大致在2500-3600埃的范围内之间取值，具体可以为3100埃；第一平坦层30，第一平坦层30可以采用有机树脂，厚度大致在18000-22000埃的范围内之间取值；第一源漏金属层31，第一源漏金属层31的图形包括连接线311和驱动薄膜晶体管的第一极312，其中，连接线311用以传递VDD信号，第一极可以为源极或漏极，第一源漏金属层31还可以用以制作数据线，第一源漏金属层31可以采用钛/铝/钛的叠层结构，厚度可以分别为500埃/5000埃/500埃；第二平坦层32，第二平坦层32可以采用有机树脂，厚度大致在18000-22000埃的范围内之间取值；第二源漏金属层34，第二源漏金属层34的厚度大于阈值，第二源漏金属层34的图形包括信号走线和第二焊盘343，信号走线包括VDD走线341、VSS走线342，其中，VSS走线342还作为第一焊盘使用，第二焊盘343与驱动薄膜晶体管的第一极312连接；第三平坦层36，第三平坦层36可以采用有机树脂，厚度大致在18000-22000埃的范围内之间取值。
进一步的，第一驱动功能层还可以包括位于有源层11和衬底基板10之间的缓冲层(未图示)，缓冲层可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，具体可以采用氮化硅/氧化硅的叠层结构，厚度可以分别为500埃/3000埃，缓冲层可以避免衬底基板10上的杂质进入有源层11中，进而影响薄膜晶体管的性能。
其中。第三平坦层36包括暴露出VSS走线342和第二焊盘343部分表面的过孔，LED 25的N pad 252可以与VSS走线342绑定连接在一起，LED25的P pad 251可以与第二焊盘343绑定连接在一起。
由于驱动基板的电流负载大，可以达到几十毫安，对信号走线的电阻性能要求高，需要采用电阻较小的金属，否则走线发热量大会导致温度过高；而铜的导电性能优越，因此，采用铜来作为信号走线的主体。当然，信号走线并不局限于采用铜，还可以采用其他金属，比如银、铝等。可以根据电流负载的大小调节铜层的厚度，电流负载越大，则铜层的厚度越大。铜层的厚度可以为2～30um，在一些实施例中，具体可以为2um。铜层可以通过溅射、电镀、化学镀等方式完成。
在第二平坦层32上通过溅射方式形成铜层时，溅射时的等离子体可能会对第二平坦层32造成损伤，使得第二平坦层32出现碎屑脱落的现象，脱落的碎屑会污染溅射腔室，为了避免这一情况，如图2所示，驱动基板还包括位于第二平坦层32上的第一钝化层33，第一钝化层33可以对第二平坦层32进行保护。第一钝化层33可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第一钝化层33的厚度大致在500-3000埃的范围内之间取值。
若通过低温沉积的方式形成铜层，由于低温沉积方式不会对第二平坦层32造成损伤，因此此时可以省去第一钝化层33的设置。
另外，在信号走线采用铜时，在信号走线上形成第三平坦层36时，第三平坦层36高温固化时会导致铜的表面氧化，为了避免这一情况，如图2所示，驱动基板还包括位于第二源漏金属层34上的第二钝化层35，第二钝化层35可以对铜进行保护，避免第三平坦层36高温固化时铜的表面氧化。第二钝化层35可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第二钝化层35的厚度大致在500-3000埃的范围内之间取值。由于后续工艺中LED 25的N pad 252需要与第一焊盘342绑定连接在一起，LED 25的P pad 251需要与第二焊盘343绑定连接在一起，因此，可以在第一焊盘342和第二焊盘343上不设置第二钝化层35；或者，在第一焊盘342和第二焊盘343上也设置第二钝化层35，但在绑定LED 25之前，将第一焊盘342和第二焊盘343上的第 二钝化层35去除。
在一些实施例中，第二源漏金属层34除包括铜层之外，还包括位于铜层靠近衬底基板一侧的金属层，所述金属层与所述第二平坦层32的粘附力大于所述铜层与第二平坦层32的粘附力，防止铜层从衬底基板上脱落。具体地，金属层可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi，还可以采用IGZO、IZO、GZO、ITO等金属氧化物。金属层的厚度大致在200-500埃的范围内之间取值。
第二驱动功能层包括：扇出走线结构26，扇出走线结构26可以采用Al/Mo的叠层结构，厚度可以分别为6000埃/600埃；钝化层27，钝化层27可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，厚度大致在5000-7000埃的范围内之间取值；用以与柔性电路板绑定的绑定引脚282以及通过扇出走线结构26与绑定引脚282连接的引线衬垫281可以采用透明导电材料比如ITO，厚度大致在400-600埃的范围内之间取值。
另外，第一驱动功能层，第一源漏金属层31还包括第一导电子图形312，第二源漏金属层34还包括第二导电子图形344，第一导电子图形312和第二导电子图形344并联组成导电结构，与显示区域的信号走线连接；导电结构可以通过基板侧面(如椭圆形虚线框所示区域)的导电连接部与引线衬垫281连接，从而实现引线衬垫281与信号走线的连接，以将柔性电路板输出的信号传递至信号走线。如果导电连接部裸露在基板外部，容易受到损伤。为了避免导电连接部受到损伤，可以在基板侧面设置与导电连接部所在位于对应的凹槽，如椭圆形虚线框所示区域，使得导电连接部的至少一部分位于凹槽内，这样能够降低导电连接部受到损伤的风险。
相关技术中，为了降低信号走线的降低信号走线的IR Drop，三层源漏金属层中用以形成信号走线的其中一层源漏金属层，基本上覆盖了基板的整个显示区域，且两层源漏金属层之间的绝缘层的厚度较小，两层源漏金属层之间发生短路不良的概率较高，会导致后续制程，如通过化学气相沉积法制作第三平坦层36层时，静电荷会聚集在大面积金属层上，导致电弧放电，损坏机台，并影响了驱动基板的良率。
如图3所示，本实施例中，利用第一源漏金属层31制作信号传输线，信号传输线与第二源漏金属层34制作的信号走线连接，组成网格状结构，其中，第二源漏金属层34制作的信号走线包括VSS走线和VDD走线，一部分信号传输线与VSS走线连接组成网格状结构以传递VSS信号，其中，传递VSS信号的信号传输线与对应的VSS走线在交叉处通过贯穿第二平坦层32的过孔连接；另一部分信号传输线与VDD走线连接组成网格状结构以传递VDD信号，其中，传递VDD信号的信号传输线与对应的VDD走线在交叉处通过贯穿第二平坦层32的过孔连接。由于本实施例采用单层源漏金属层制作信号走线，可以将短路不良发生率降低至1％以下，保证了驱动基板的良率。另外，本实施例中，由于驱动基板包括的源漏金属层的层数较少，即使第二源漏金属图形34制作的信号走线的宽度增大，占据的面积增多，也不会导致短路不良发生率大幅增多。
图4为图3的局部放大示意图，图5为图4在AA’方向上的截面示意图，图6为图4在BB’方向上的截面示意图，图7为图4在CC’方向上的截面示意图，图8为图4在DD’方向上的截面示意图。
如图5所示，第一源漏金属层31构成的信号传输线的线宽为a，如图7所示，第二源漏金属层34构成的信号走线的线宽为b，信号走线之间的间距为c，其中，a/b的取值为1-1.2，具体可以为1.1；b/c的取值为1.8-2.2，具体可以为2，采用上述参数对信号传输线的线宽、信号走线的线宽和间距进行设计，可以降低VSS信号和VDD信号的传输损耗，又可以降低短路不良发生率。
图9为本公开实施例驱动基板在焊盘区域的示意图，图10为图9在EE’方向上的截面示意图，焊盘区域包括第一焊盘区域H1和第二焊盘区域H2，在第一焊盘区域H1设置有第一焊盘，在第二焊盘区域H2设置有第二焊盘。如图10所示，其中，d为第一源漏金属层31的边缘与第二源漏金属层34的边缘在水平方向上的距离，e为第二源漏金属层34的边缘与第二平坦层32的边缘在水平方向上的距离，f为第二平坦层32的边缘与第一钝化层33的边缘在水平方向上的距离，g为第一钝化层33的边缘与第三平坦层36的边缘 在水平方向上的距离，h为第三平坦层36的边缘与第二钝化层35的边缘在水平方向上的距离。其中，e/d的取值为1.4-1.6，具体可以为1.5；f/e的取值为1.4-1.6，具体可以为1.5；f/g的取值为1.4-1.6，具体可以为1.5；h/g的取值为1.4-1.8，具体可以为1.67。采用上述参数对第一源漏金属层31与第二源漏金属层34搭接处的结构进行设计，可以保证第一源漏金属层31与第二源漏金属层34的连接良率。
本公开实施例还提供了一种显示装置，包括如上所述的驱动基板和固定在所述焊盘层上的电子元件，所述电子元件的第一极与所述第一焊盘绑定连接，所述电子元件的第二极与所述第二焊盘绑定连接。
具体地，所述电子元件为LED，如图2所示，LED25的N pad252可以与第一焊盘342绑定连接在一起，LED25的P pad251可以与第二焊盘343绑定连接在一起。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板，柔性电路板与绑定引脚282绑定。
本公开实施例还提供了一种驱动基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板的第一表面形成第一驱动功能层，所述第一驱动功能层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；
在所述第一驱动功能层远离所述衬底基板的一侧形成焊盘层，所述焊盘层包括多个第一焊盘和多个第二焊盘，所述第一焊盘与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘与所述信号走线中的公共电极线连接。
本实施例中，信号走线本身的厚度比较大，能够有效降低IR Drop，这样不需要通过并联的方式形成信号走线，能够减少驱动基板包括的金属层的层数，从而减少制作驱动基板的构图工艺的次数，降低驱动基板的生产成本。
本实施例的驱动基板的制作方法用于制作上述实施例中的驱动基板。
由于驱动基板的电流负载大，可以达到几十毫安，对信号走线的电阻性 能要求高，需要采用电阻较小的金属，否则走线发热量大会导致温度过高；而铜的导电性能优越，因此，采用铜来作为信号走线的主体。当然，信号走线并不局限于采用铜，还可以采用其他金属，比如银、铝等。可以根据电流负载的大小调节铜层的厚度，电流负载越大，则铜层的厚度越大。铜层的厚度可以为2～30um，在一些实施例中，具体可以为2um。铜层可以通过溅射、电镀、化学镀等方式完成。
一实施例中，以采用铜制作信号走线，采用溅射方式形成厚度较大的铜层，电子元件为LED为例，驱动基板的制作方法具体包括以下步骤：
步骤1、提供一衬底基板10，在衬底基板10上形成缓冲层、有源层11；
其中，衬底基板10可为玻璃基板、石英基板或柔性基板。
可以采用等离子体增强化学气相沉积(PECVD)方法在衬底基板10上形成缓冲层，缓冲层可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。缓冲层具体可以采用氮化硅/氧化硅的叠层结构，厚度可以分别为500埃/3000埃。
在缓冲层上形成一层半导体材料，对半导体材料进行构图形成有源层11，有源层11可以采用P-Si，厚度可以为400-500埃，具体可以为470埃。
步骤2、形成第一栅绝缘层12；
具体地，可以采用PECVD沉积厚度为400-800埃的第一栅绝缘层12，第一栅绝缘层12可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。
步骤3、形成第一栅金属层13的图形；
具体地，可以采用溅射或热蒸发的方法沉积厚度为2500-3600埃的第一栅金属层13，第一栅金属层13可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具体可以采用Mo。在第一栅金属层13上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一栅金属层13的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶 厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一栅金属层13，剥离剩余的光刻胶，形成第一栅金属层13的图形，第一栅金属层3的图形包括栅线和薄膜晶体管的栅极等。
步骤4、形成第二栅绝缘层14；
具体地，可以采用PECVD沉积厚度为1000-2000埃的第二栅绝缘层14，第二栅绝缘层14可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。
步骤5、形成第二栅金属层15的图形；
具体地，可以采用溅射或热蒸发的方法沉积厚度为2500-3600埃的形成第二栅金属层15，形成第二栅金属层15可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具体可以采用Mo。在形成第二栅金属层15上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于形成第二栅金属层15的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的形成第二栅金属层15，剥离剩余的光刻胶，形成第二栅金属层15的图形，形成第二栅金属层15的图形包括存储电容的极板等。
步骤6、形成第一平坦层30；
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第一平坦层30。
步骤7、形成第一源漏金属层31的图形；
具体地，可以采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为5000～6000埃的源漏金属层，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等，具体可以采用Ti/Al/Ti的叠层结构，厚度可以分别为500埃/5000埃/500埃。在第一源漏金属层31上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形 成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一源漏金属层31的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一源漏金属层31，剥离剩余的光刻胶，形成第一源漏金属层31的图形，第一源漏金属层31的图形包括连接线311和驱动薄膜晶体管的第一极312，其中，连接线311用以传递VDD信号，第一极可以为源极或漏极，第一源漏金属层31的图形还包括数据线。
步骤8、形成第二平坦层32；
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第二平坦层32。
步骤9、形成第二源漏金属层34的图形；
在第二平坦层32上采用溅射的方式形成第二源漏金属层34，第二源漏金属层34采用金属层/铜的叠层结构，金属层与第二平坦层32之间的粘附力大于铜与第二平坦层32之间的粘附力，可以增加铜与第二平坦层32之间的粘附力，使得铜不易脱落，具体地，金属层可以采用Mo。第二源漏金属层34中，Mo的厚度可以为300埃，铜的厚度可为2um左右。
在第二源漏金属层34上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第二源漏金属层34的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第二源漏金属层34，剥离剩余的光刻胶，形成第二源漏金属层34的图形，第二源漏金属层34的图形包括信号走线和第二焊盘343，信号走线包括VDD走线341、VSS走线342，其中，VSS走线342还作为第一焊盘使用，第二焊盘343与驱动薄膜晶体管的第一极312连接。
步骤10、形成第三平坦层36。
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后 形成第三平坦层36。
之后可以对第三平坦层36进行构图，形成暴露出VSS走线342和第二焊盘343的过孔。
在经过上述步骤1-10制作第一驱动功能层之后，可以将衬底基板10翻转，在衬底基板10的另一侧表面制作第二驱动功能层，即可完成驱动基板的制作。
另外，在第二平坦层32上通过溅射方式形成铜层时，溅射时的等离子体可能会对第二平坦层32造成损伤，使得第二平坦层32出现碎屑脱落的现象，脱落的碎屑会污染溅射腔室，为了避免这一情况，在形成第二平坦层后32，还形成位于第二平坦层32上的第一钝化层33，第一钝化层33可以对第二平坦层32进行保护。第一钝化层33可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第一钝化层33的厚度可以为500-3000埃。
若通过低温沉积的方式形成铜层，由于低温沉积方式不会对第二平坦层32造成损伤，因此此时可以省去形成第一钝化层33的步骤。
另外，在铜层上形成第三平坦层36时，第三平坦层36高温固化时会导致铜的表面氧化，为了避免这一情况，在形成第二源漏金属层34的图形后，在第二源漏金属层34的图形上形成第二钝化层35，第二钝化层35可以对铜进行保护，避免第三平坦层36高温固化时铜的表面氧化。第二钝化层35可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第二钝化层35的厚度可以为500-3000埃。
另一实施例中，以采用铜制作信号走线，采用电镀方式形成厚度较大的铜层，电子元件为LED为例，驱动基板的制作方法具体包括以下步骤：
步骤1、提供一衬底基板10，在衬底基板10上形成缓冲层、有源层11；
其中，衬底基板10可为玻璃基板、石英基板或柔性基板。
可以采用等离子体增强化学气相沉积(PECVD)方法在衬底基板10上形成缓冲层，缓冲层可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。缓冲层具体可以采用氮化硅/氧化硅的叠层结构，厚度可以分别为500埃/3000埃。
在缓冲层上形成一层半导体材料，对半导体材料进行构图形成有源层11，有源层11可以采用P-Si，厚度可以为400-500埃，具体可以为470埃。
步骤2、形成第一栅绝缘层12；
具体地，可以采用PECVD沉积厚度为400-800埃的第一栅绝缘层12，第一栅绝缘层12可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。
步骤3、形成第一栅金属层13的图形；
具体地，可以采用溅射或热蒸发的方法沉积厚度为2500-3600埃的第一栅金属层13，第一栅金属层13可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具体可以采用Mo。在第一栅金属层13上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一栅金属层13的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一栅金属层13，剥离剩余的光刻胶，形成第一栅金属层13的图形，第一栅金属层3的图形包括栅线和薄膜晶体管的栅极等。
步骤4、形成第二栅绝缘层14；
具体地，可以采用PECVD沉积厚度为1000-2000埃的第二栅绝缘层14，第二栅绝缘层14可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。
步骤5、形成第二栅金属层15的图形；
具体地，可以采用溅射或热蒸发的方法沉积厚度为2500-3600埃的形成第二栅金属层15，形成第二栅金属层15可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具体可以采用Mo。在形成第二栅金属层15上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于形成第二栅金属层15的图形所在区域，光刻胶未保留区域对应于上述图形 以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的形成第二栅金属层15，剥离剩余的光刻胶，形成第二栅金属层15的图形，形成第二栅金属层15的图形包括存储电容的极板等。
步骤6、形成第一平坦层30；
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第一平坦层30。
步骤7、形成第一源漏金属层31的图形；
具体地，可以采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为5000～6000埃的源漏金属层，源漏金属层可以是铜，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如铜\Mo，Ti\铜\Ti，Mo\Al\Mo等，具体可以采用钛/铝/钛的叠层结构，厚度可以分别为500埃/5000埃/500埃。在第一源漏金属层31上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一源漏金属层31的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一源漏金属层31，剥离剩余的光刻胶，形成第一源漏金属层31的图形，第一源漏金属层31的图形包括连接线311和驱动薄膜晶体管的第一极312，其中，连接线311用以传递VDD信号，第一极可以为源极或漏极，第一源漏金属层31的图形还包括数据线。
步骤8、形成第二平坦层32；
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第二平坦层32。
步骤9、形成第二源漏金属层34的图形；
在第二平坦层32上采用溅射的方式形成种子层，种子层采用金属层/铜的叠层结构，金属层与第二平坦层32之间的粘附力大于铜与第二平坦层32 之间的粘附力，可以增加铜与第二平坦层32之间的粘附力，使得铜不易脱落，具体地，金属层可以采用Mo。种子层的厚度小于阈值，具体地，种子层中Mo的厚度可以为300埃，种子层中铜的厚度可以为3000埃。
在种子层上以电镀方式生长出一层金属铜，生长出的铜的厚度可以达到2um以上，生长出的铜与种子层组成第二源漏金属层34。
在第二源漏金属层34上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第二源漏金属层34的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第二源漏金属层34，剥离剩余的光刻胶，形成第二源漏金属层34的图形，第二源漏金属层34的图形包括信号走线和第二焊盘343，信号走线包括VDD走线341、VSS走线342，其中，VSS走线342还作为第一焊盘使用，第二焊盘343与驱动薄膜晶体管的第一极312连接。
步骤10、形成第三平坦层36。
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第三平坦层36。
之后可以对第三平坦层36进行构图，形成暴露出VSS走线342和第二焊盘343的过孔。
在经过上述步骤1-10制作第一驱动功能层之后，可以将衬底基板10翻转，在衬底基板10的另一侧表面制作第二驱动功能层，即可完成驱动基板的制作。
另外，在第二平坦层32上通过溅射方式形成铜层时，溅射时的等离子体可能会对第二平坦层32造成损伤，使得第二平坦层32出现碎屑脱落的现象，脱落的碎屑会污染溅射腔室，为了避免这一情况，在形成第二平坦层后32，还形成位于第二平坦层32上的第一钝化层33，第一钝化层33可以对第二平坦层32进行保护。第一钝化层33可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第一钝化层33的厚度可以为500-3000埃。
若通过低温沉积的方式形成铜层，由于低温沉积方式不会对第二平坦层32造成损伤，因此此时可以省去形成第一钝化层33的步骤。
另外，在铜层上形成第三平坦层36时，第三平坦层36高温固化时会导致铜的表面氧化，为了避免这一情况，在形成第二源漏金属层34的图形后，在第二源漏金属层34的图形上形成第二钝化层35，第二钝化层35可以对铜进行保护，避免第三平坦层36高温固化时铜的表面氧化。第二钝化层35可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第二钝化层35的厚度可以为500-3000埃。
另一实施例中，以采用铜制作信号走线，采用化学镀方式形成厚度较大的铜层，电子元件为LED为例，驱动基板的制作方法具体包括以下步骤：
步骤1、提供一衬底基板10，在衬底基板10上形成缓冲层、有源层11；
其中，衬底基板10可为玻璃基板、石英基板或柔性基板。
可以采用等离子体增强化学气相沉积(PECVD)方法在衬底基板10上形成缓冲层，缓冲层可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。缓冲层具体可以采用氮化硅/氧化硅的叠层结构，厚度可以分别为500埃/3000埃。
在缓冲层上形成一层半导体材料，对半导体材料进行构图形成有源层11，有源层11可以采用P-Si，厚度可以为400-500埃，具体可以为470埃。
步骤2、形成第一栅绝缘层12；
具体地，可以采用PECVD沉积厚度为400-800埃的第一栅绝缘层12，第一栅绝缘层12可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。
步骤3、形成第一栅金属层13的图形；
具体地，可以采用溅射或热蒸发的方法沉积厚度为2500-3600埃的第一栅金属层13，第一栅金属层13可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具体可以采用Mo。在第一栅金属层13上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一栅金属层 13的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一栅金属层13，剥离剩余的光刻胶，形成第一栅金属层13的图形，第一栅金属层3的图形包括栅线和薄膜晶体管的栅极等。
步骤4、形成第二栅绝缘层14；
具体地，可以采用PECVD沉积厚度为1000-2000埃的第二栅绝缘层14，第二栅绝缘层14可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH 4、NH 3、N 2或SiH 2Cl 2、NH 3、N 2。
步骤5、形成第二栅金属层15的图形；
具体地，可以采用溅射或热蒸发的方法沉积厚度为2500-3600埃的形成第二栅金属层15，形成第二栅金属层15可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具体可以采用Mo。在形成第二栅金属层15上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于形成第二栅金属层15的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的形成第二栅金属层15，剥离剩余的光刻胶，形成第二栅金属层15的图形，形成第二栅金属层15的图形包括存储电容的极板等。
步骤6、形成第一平坦层30；
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第一平坦层30。
步骤7、形成第一源漏金属层31的图形；
具体地，可以采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为5000～6000埃的源漏金属层，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等，具体可以 采用Ti/Al/Ti的叠层结构，厚度可以分别为500埃/5000埃/500埃。在第一源漏金属层31上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一源漏金属层31的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一源漏金属层31，剥离剩余的光刻胶，形成第一源漏金属层31的图形，第一源漏金属层31的图形包括连接线311和驱动薄膜晶体管的第一极312，其中，连接线311用以传递VDD信号，第一极可以为源极或漏极，第一源漏金属层31的图形还包括数据线。
步骤8、形成第二平坦层32；
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第二平坦层32。
步骤9、形成第二源漏金属层34的图形；
在第二平坦层32上采用溅射的方式形成种子层，种子层采用金属层/铜的叠层结构，金属层与第二平坦层32之间的粘附力大于铜与第二平坦层32之间的粘附力，可以增加铜与第二平坦层32之间的粘附力，使得铜不易脱落，具体地，金属层可以采用Mo。种子层的厚度小于阈值，具体地，种子层中Mo的厚度可以为300埃，种子层中铜的厚度可以为3000埃。
在种子层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第二源漏金属层34的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的种子层，形成种子层的图形。
在种子层的图形上以化学镀方式生长出一层金属铜，生长出的铜的厚度可以达到2-3um，生长出的铜与种子层的图形组成第二源漏金属层34的图形。第二源漏金属层34的图形包括信号走线和第二焊盘343，信号走线包括VDD 走线341、VSS走线342，其中，VSS走线342还作为第一焊盘使用，第二焊盘343与驱动薄膜晶体管的第一极312连接。
步骤10、形成第三平坦层36。
具体地，可以涂覆一层厚度为18000-22000埃的有机树脂，高温固化后形成第三平坦层36。
之后可以对第三平坦层36进行构图，形成暴露出VSS走线342和第二焊盘343的过孔。
在经过上述步骤1-10制作第一驱动功能层之后，可以将衬底基板10翻转，在衬底基板10的另一侧表面制作第二驱动功能层，即可完成驱动基板的制作。
另外，在第二平坦层32上通过溅射方式形成铜层时，溅射时的等离子体可能会对第二平坦层32造成损伤，使得第二平坦层32出现碎屑脱落的现象，脱落的碎屑会污染溅射腔室，为了避免这一情况，在形成第二平坦层后32，还形成位于第二平坦层32上的第一钝化层33，第一钝化层33可以对第二平坦层32进行保护。第一钝化层33可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第一钝化层33的厚度可以为500-3000埃。
若通过低温沉积的方式形成铜层，由于低温沉积方式不会对第二平坦层32造成损伤，因此此时可以省去形成第一钝化层33的步骤。
另外，在铜层上形成第三平坦层36时，第三平坦层36高温固化时会导致铜的表面氧化，为了避免这一情况，在形成第二源漏金属层34的图形后，在第二源漏金属层34的图形上形成第二钝化层35，第二钝化层35可以对铜进行保护，避免第三平坦层36高温固化时铜的表面氧化。第二钝化层35可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第二钝化层35的厚度可以为500-3000埃。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种驱动基板，其特征在于，包括：
    衬底基板；
    第一驱动功能层，设置于所述衬底基板的第一表面，所述第一驱动功能层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；
    焊盘层，所述焊盘层设置于所述第一驱动功能层远离所述衬底基板的一侧，所述焊盘层包括多个第一焊盘和多个第二焊盘，所述第一焊盘与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘与所述信号走线中的公共电极线连接。
  2. 根据权利要求1所述的驱动基板，其特征在于，所述驱动基板还包括：
    第二驱动功能层，设置于所述衬底基板的第二表面，所述第二表面与所述第一表面相对，所述第二驱动功能层包括引线衬垫和与所述引线衬垫连接的绑定引脚；
    所述衬底基板的侧表面设置有多个凹槽，每个所述凹槽均沿垂直于所述衬底基板的方向延伸，且贯穿所述衬底基板的第一表面和第二表面；
    与所述凹槽一一对应的导电连接部，所述导电连接部的至少一部分位于对应的所述凹槽内，且所述导电连接部用于分别连接相对应的所述信号走线和所述引线衬垫。
  3. 根据权利要求1所述的驱动基板，其特征在于，所述多条信号走线包括电源电压信号线和所述公共电极线，所述电源电压信号线和所述公共电极线的厚度均大于所述阈值。
  4. 根据权利要求3所述的驱动基板，其特征在于，所述电源电压信号线和所述公共电极线同层同材料设置。
  5. 根据权利要求3所述的驱动基板，其特征在于，还包括：
    与所述信号走线连接的信号传输线，所述信号传输线与所述信号走线组成网格状结构。
  6. 根据权利要求1-5中任一项所述的驱动基板，其特征在于，沿远离所述第一表面的方向，所述第一驱动功能层依次包括：
    有源层；
    第一栅绝缘层；
    第一栅金属层；
    第二栅绝缘层；
    第二栅金属层；
    第一平坦层；
    第一源漏金属层；
    第二平坦层；
    第二源漏金属层，所述第二源漏金属层的图形包括所述信号走线；
    第三平坦层。
  7. 根据权利要求6所述的驱动基板，其特征在于，所述第二源漏金属层包括层叠设置的铜层和金属层，所述金属层位于所述铜层靠近所述衬底基板的一侧，所述金属层与所述第二平坦层的粘附力大于所述铜层与所述第二平坦层的粘附力。
  8. 根据权利要求7所述的驱动基板，其特征在于，所述铜层的厚度为2-30um。
  9. 根据权利要求7所述的驱动基板，其特征在于，所述驱动基板还包括位于所述铜层和所述第一平坦层之间的第一钝化层，所述第一钝化层采用无机绝缘材料。
  10. 根据权利要求7所述的驱动基板，其特征在于，所述驱动基板还包括位于所述铜层和所述第二平坦层之间的第二钝化层，所述第二钝化层采用无机绝缘材料。
  11. 一种显示装置，其特征在于，包括如权利要求1-10中任一项所述的驱动基板和固定在所述焊盘层上的电子元件，所述电子元件的第一极与所述第一焊盘绑定连接，所述电子元件的第二极与所述第二焊盘绑定连接。
  12. 一种驱动基板的制作方法，其特征在于，包括：
    提供一衬底基板；
    在所述衬底基板的第一表面形成第一驱动功能层，所述第一驱动功能层包括多个驱动薄膜晶体管和多条信号走线，至少一条所述信号走线采用单层结构且厚度大于阈值；
    在所述第一驱动功能层远离所述衬底基板的一侧形成焊盘层，所述焊盘层包括多个第一焊盘和多个第二焊盘，所述第一焊盘与对应的所述驱动薄膜晶体管的第一极连接，所述第二焊盘与所述信号走线中的公共电极线连接。
  13. 根据权利要求12所述的驱动基板的制作方法，其特征在于，所述驱动基板包括第一源漏金属层的图形和第二源漏金属层的图形，所述第二源漏金属层的图形包括所述信号走线，形成所述信号走线包括：
    形成厚度小于阈值的种子层；
    在所述种子层上以电镀方法生长出导电层，所述种子层和所述导电层组成第二源漏金属层；
    对所述第二源漏金属层进行构图，形成所述信号走线。
  14. 根据权利要求13所述的驱动基板的制作方法，其特征在于，所述驱动基板包括第一源漏金属层的图形和第二源漏金属层的图形，所述第二源漏金属层的图形包括所述信号走线，形成所述信号走线包括：
    形成厚度小于阈值的种子层；
    对所述种子层进行构图形成种子层的图形，所述种子层的图形位于待形成的信号走线所在区域；
    在所述种子层的图形上以化学镀方式生长出导电层的图形，所述导电层的图形和所述种子层的图形组成所述信号走线。
  15. 根据权利要求13或14所述的驱动基板的制作方法，其特征在于，形成所述种子层包括：
    形成层叠设置的铜层和金属层，所述金属层位于所述铜层靠近所述衬底基板的一侧，所述金属层与绝缘层的粘附力大于所述铜层与所述绝缘层的粘附力。
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