WO2021238682A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021238682A1
WO2021238682A1 PCT/CN2021/093904 CN2021093904W WO2021238682A1 WO 2021238682 A1 WO2021238682 A1 WO 2021238682A1 CN 2021093904 W CN2021093904 W CN 2021093904W WO 2021238682 A1 WO2021238682 A1 WO 2021238682A1
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Prior art keywords
layer
lead
base substrate
away
metal
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PCT/CN2021/093904
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English (en)
French (fr)
Inventor
梁志伟
曹占锋
王珂
刘英伟
姚舜禹
梁爽
狄沐昕
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/800,236 priority Critical patent/US20230060979A1/en
Publication of WO2021238682A1 publication Critical patent/WO2021238682A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
  • a seed lead can be formed on the base substrate first, and then a copper growth layer is formed on the seed lead by a copper electroplating process, so that a metal lead with a larger thickness can be prepared and the voltage drop on the metal lead can be reduced.
  • the purpose of the present disclosure is to provide an array substrate, a preparation method thereof, and a display device to increase the thickness of a part of the metal wiring layer of the array substrate.
  • a method for manufacturing an array substrate including:
  • forming a driving circuit layer on one side of the base substrate includes: forming at least one first lead layer on one side of the base substrate; and forming any layer of the first lead layer includes:
  • the removable pattern defining layer is provided with lead openings, and the lead openings expose part of the conductive seed layer;
  • forming a removable pattern defining layer on the surface of the conductive seed layer away from the base substrate includes:
  • a patterning operation is performed on the removable insulating material layer to form the removable pattern defining layer.
  • forming a removable insulating material layer on the surface of the conductive seed layer away from the base substrate includes:
  • Performing a patterning operation on the removable insulating material layer includes:
  • Exposing and developing the photoresist material layer to form the removable pattern defining layer Exposing and developing the photoresist material layer to form the removable pattern defining layer.
  • forming a photoresist material layer on the surface of the conductive seed layer away from the base substrate includes:
  • a degradable photoresist material is used to form a layer of photoresist material on the surface of the conductive seed layer away from the base substrate.
  • the degradable photoresist material is light that can be dissolved in the degradation liquid after curing. Resist material;
  • Removing the removable pattern defining layer includes:
  • the degradable liquid is used to dissolve the removable pattern defining layer.
  • forming a photoresist material layer on the surface of the conductive seed layer away from the base substrate includes:
  • Exposing and developing the photoresist material layer includes:
  • the photoresist material layer is exposed and developed to form a removable pattern defining layer with lead openings, so that the width of the end of the lead opening close to the base substrate is larger than that far away from the base substrate. The width of one end.
  • forming a removable pattern defining layer on the surface of the conductive seed layer away from the base substrate includes:
  • Using an electroplating process or an electroless plating process to form a metal plating layer on the surface of the conductive seed layer in the lead opening includes:
  • a metal plating layer on the surface of the conductive seed layer is formed in the lead opening, so that the thickness of the metal plating layer is a second size value, and the second size value is not greater than that of the first size value. 5 times.
  • forming at least one first lead layer on one side of the base substrate includes:
  • a second planarization layer is formed on the side of the first transition metal layer away from the base substrate, and the second planarization layer has a first connection via; the first connection via exposes a portion of the A first transition metal layer, and the orthographic projection of the first connection via on the first lead layer does not overlap with the first lead layer;
  • Another layer of the first lead layer is formed on the surface of the second planarization layer away from the base substrate, and the other layer of the first lead layer is connected to the first transfer layer through the first connection via hole. Connect the metal layer connection.
  • an array substrate including a base substrate, a driving circuit layer, and a functional device layer that are stacked in sequence;
  • the driving circuit layer includes at least one first lead layer, and any one of the first lead layers includes at least one first lead;
  • Any one of the first leads includes a seed lead set on one side of the base substrate, and a growth lead set on the surface of the seed lead away from the base substrate, and the growth lead is on the base substrate
  • the orthographic projection of the seed lead coincides with the orthographic projection of the seed lead on the base substrate.
  • the thickness of the first lead is not more than 5 times the width of the seed lead.
  • the width of the end of the first lead away from the base substrate is smaller than the width of the end of the first lead near the base substrate.
  • the driving circuit layer includes:
  • the first lead layer is arranged on one side of the base substrate
  • the first planarization layer is provided on the side of the first lead layer away from the base substrate;
  • the first transition metal layer is provided on a side of the first planarization layer away from the base substrate and connected to the first lead layer;
  • the second planarization layer is provided on a side of the first transfer metal layer away from the base substrate, and is provided with a first connection via; the first connection via exposes a portion of the first transfer A metal layer, and the orthographic projection of the first connection via on the first lead layer does not overlap with the first lead layer;
  • the other first lead layer is disposed on the surface of the second planarization layer away from the base substrate, and is connected to the first transition metal layer through the first connection via.
  • the driving circuit layer includes:
  • the driving transistor is arranged on one side of the base substrate, and the driving transistor includes a source and drain metal layer forming a source electrode and a drain electrode;
  • the third planarization layer is provided on a side of the driving transistor away from the base substrate, and is provided with a third connection via that exposes at least part of the source and drain metal layers;
  • the second transition metal layer is provided on a side of the third planarization layer away from the base substrate, and is connected to the source/drain metal layer through the third connection via;
  • the fourth planarization layer is provided on a side of the second transfer metal layer away from the base substrate, and has a fourth connection via; the fourth connection via exposes a portion of the second transfer metal Layer, and the orthographic projection of the fourth connection via on the base substrate and the orthographic projection of the third connection via on the base substrate do not overlap;
  • the first lead layer is disposed on the surface of the fourth planarization layer away from the base substrate, and is connected to the second transition metal layer through the fourth connection via.
  • the driving circuit layer includes:
  • the driving transistor is arranged on one side of the base substrate, and the driving transistor includes a source and drain metal layer forming a source electrode and a drain electrode;
  • the third planarization layer is provided on a side of the source/drain metal layer away from the base substrate, and is provided with a third connection via that exposes at least part of the source/drain metal layer; the third connection via The orthographic projection on the base substrate and the orthographic projection of the second connection via on the base substrate do not overlap;
  • the first lead layer is arranged on the surface of the third planarization layer away from the base substrate, and is connected to the source and drain metal layer through the third connection via.
  • the driving circuit layer includes a driving transistor, and the driving transistor includes:
  • the semiconductor layer is arranged on one side of the base substrate; the semiconductor layer includes a source contact area and a drain contact area;
  • the interlayer dielectric layer is arranged on the side of the semiconductor away from the base substrate;
  • the first lead layer is arranged on the side of the interlayer dielectric layer away from the base substrate to form a source electrode and a drain electrode; the source electrode is connected to the source contact area, and the drain The electrode is connected to the drain contact area.
  • a display device including the above-mentioned array substrate.
  • a conductive seed layer on the entire surface and a removable pattern defining layer covering the conductive seed layer can be formed first, so as to ensure that there is no missing conductive seed layer in the lead opening. situation. Then, an electroplating process or an electroless plating process is used to grow metal in the lead opening, and a precursor growth lead located in the lead opening is prepared to form a metal plating layer.
  • the removable pattern defining layer makes the precursor growth lead have a good side morphology; the conductive seed layer can provide a complete electroplating or electroless plating substrate, so that the surface of the precursor growth lead has more Good uniformity.
  • the removable pattern defining layer is removed and the conductive seed layer is patterned by etching to form seed leads covered by the precursor growth leads.
  • the precursor growth leads can also be partially etched during the etching process to form growth leads. The difference in etching speeds at different positions during the etching process can further improve the uniformity of the growth leads away from the surface of the base substrate.
  • the first lead layer includes a first lead, and the first lead includes a seed lead and a growth lead laminated on the surface of the seed lead. The surface of the first lead has better surface uniformity and can improve the performance of the array substrate.
  • the electroplating process of the entire conductive seed layer can make the electroplating process suitable for any metal wiring layer of the array substrate, and can increase the thickness of any metal wiring layer of the array substrate, and The thickness uniformity of the formed first lead layer is improved, which overcomes the application limitation of the electroplating process in the prior art.
  • FIG. 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic view of the process of forming any layer of the first lead layer according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a structure of a base substrate provided in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of forming a conductive seed layer on one side of a base substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of forming a removable pattern defining layer on the surface of the conductive seed layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of forming a metal plating layer on the surface of a conductive seed layer in a lead opening by an electroplating process according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the structure of removing the removable pattern defining layer according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of etching to form a first lead layer according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a passivation layer on the surface of the first lead layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a process of forming a first lead layer group according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of forming a first planarization layer on the side of the previous first lead layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of forming a first transition metal layer on a side of the first planarization layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of forming a second planarization layer on the side of the first transition metal layer away from the base substrate according to an embodiment of the present disclosure.
  • 15 is a schematic structural diagram of a first lead layer after a first lead layer is formed on the surface of the second planarization layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of forming a pixel definition layer on the side of the driving circuit layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of forming a functional device layer on the side of the driving circuit layer away from the base substrate according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a driving circuit layer having a first lead layer laminated in multiple layers according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic flowchart of forming a first lead layer electrically connected to a driving transistor according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic flowchart of forming a first lead layer electrically connected to a driving transistor according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic flowchart of forming a first lead layer electrically connected to a driving transistor according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 26 is a schematic top view of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 27 is a schematic top view of the structure of an array substrate according to an embodiment of the present disclosure.
  • a structure When a structure is “on” another structure, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is “directly” arranged on other structures, or that a certain structure is “indirectly” arranged on other structures through another structure. On other structures.
  • the width of the lead refers to the dimension of the lead perpendicular to its extending direction on a plane parallel to the base substrate.
  • the thickness of a film layer or lead refers to the size of the film layer or lead in the direction perpendicular to the base substrate.
  • a seed lead can be formed on the base substrate first, and then a copper growth layer is formed on the seed lead by a copper electroplating process to form a thick electroplated metal lead.
  • a barrier structure can also be arranged between the seed leads, and then the copper electroplating process is performed to constrain the width of the copper growth layer.
  • the present disclosure provides a method for preparing an array substrate.
  • the array substrate includes a base substrate 100, a driving circuit layer 200 and a functional device layer 300 stacked in sequence.
  • the preparation method of the array substrate includes:
  • Step S110 as shown in FIG. 4, a base substrate 100 is provided;
  • Step S120 forming a driving circuit layer 200 on one side of the base substrate 100;
  • Step S130 forming a functional device layer 300 on the side of the driving circuit layer 200 away from the base substrate 100;
  • forming the driving circuit layer 200 on one side of the base substrate 100 includes: forming at least one first lead layer 201 on one side of the base substrate 100; as shown in FIG. 3, forming any first lead layer 201 include:
  • Step S210 as shown in FIG. 5, a conductive seed layer 410 is formed on one side of the base substrate 100;
  • Step S220 as shown in FIG. 6, a removable pattern defining layer 420 is formed on the surface of the conductive seed layer 410 away from the base substrate 100.
  • the removable pattern defining layer 420 is provided with a lead opening 421, and the lead opening 421 exposes a portion Conductive seed layer 410;
  • Step S230 as shown in FIG. 7, a metal plating layer 430 on the surface of the conductive seed layer 410 is formed in the lead opening 421 by an electroplating process or an electroless plating process;
  • Step S240 remove the removable pattern defining layer 420;
  • step S250 as shown in FIG. 9, the portion of the conductive seed layer 410 that is not covered by the metal plating layer 430 is removed to form the first lead layer 201.
  • the entire conductive seed layer 410 and the removable pattern defining layer 420 covering the conductive seed layer 410 can be formed first. Since the conductive seed layer 410 has not been patterned, it can be It is ensured that the conductive seed layer 410 will not be missing in the lead opening 421, and the problem that a part of the lead opening 421 may be missing the electroplating substrate or the electroless plating substrate may be overcome. Then, an electroplating process or an electroless plating process is used to grow metal in the lead opening 421, and a precursor growth lead 431 located in the lead opening 421 is prepared to form a metal plating layer 430.
  • the removable pattern defining layer 420 can define the side surface of the precursor growth lead 431, so that the precursor growth lead 431 has a good side profile; the conductive seed layer 410 in the lead opening 421 can provide The complete plating base or electroless plating base makes the surface of the precursor growth lead 431 far away from the base substrate 100 have better uniformity. Then, the removable pattern defining layer 420 is removed and the conductive seed layer 410 is patterned by etching to form the seed leads 411 covered by the precursor growth leads 431. The precursor growth lead 431 can also be partially etched during the etching process to form the growth lead 432.
  • the first lead layer 201 includes a first lead 2011.
  • the first lead 2011 includes a seed lead 411 and a growth lead 432 laminated on the surface of the seed lead 411.
  • the surface of the first lead 2011 has better surface uniformity and can improve the array substrate. performance.
  • the preparation method of the array substrate provided by the present disclosure overcomes the limitation of the film position of the electroplated metal leads in the prior art, and the first lead layer 201 can be prepared at the required position according to the performance requirements of the array substrate, and then It is ensured that the functional device 310 of the functional device layer 300 obtains sufficient driving current.
  • the base substrate 100 of the array substrate may be provided.
  • the base substrate 100 may be a base substrate 100 made of inorganic material, or may be a base substrate 100 made of organic material.
  • the material of the base substrate 100 may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate 100 may be polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (Polyvinylphenol, PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate 100 may also be a flexible base substrate 100.
  • the material of the base substrate 100 may be polyimide (PI).
  • the base substrate 100 may also be a composite of multiple layers of materials.
  • the base substrate 100 may include a bottom film, a pressure-sensitive adhesive layer, The first polyimide layer and the second polyimide layer.
  • a driving circuit layer 200 may be formed on one side of the base substrate 100, and the driving circuit layer 200 is used to drive each functional device 310 in the functional device layer 300.
  • the driving circuit layer 200 includes a driving circuit composed of at least one metal wiring layer, and any metal wiring layer includes at least one metal lead. Among them, at least one metal wiring layer is the first lead layer 201 of the present disclosure.
  • the metal wiring layers in the driving circuit layer 200 may all be the first lead layer 201 or part of the first lead layer 201.
  • part of the metal wiring layer may be the first lead layer 201
  • another part of the metal wiring layer may be the second lead layer 202.
  • the second lead layer 202 may be prepared by forming a metal film layer by a deposition process and patterning the metal film layer; in other words, the second lead layer 202 may not use an electroplating process or an electroless plating process, and each of the second lead layers included therein The second lead can have a lower thickness.
  • the material of the second lead layer 202 may be the same as or different from the conductive seed layer 410.
  • one or more of the following metal wiring layers in the driving circuit layer 200 may be the second lead layer 202: a gate lead layer, a source and drain lead layer, a metal transfer layer, a light shielding layer, an electrode layer, or a bonding layer.
  • any one of the above-mentioned film layers can also be prepared into the first lead layer 201 by means of an electroplating process or an electroless plating process.
  • the first lead layer 201 can be prepared according to the preparation method shown in step S210 to step S250, so that any one of the first leads 2011 It may include a seed lead 411 and a growth lead 432 stacked on the seed lead 411 away from the surface of the base substrate 100.
  • the driving circuit layer 200 may include passive driving circuits.
  • the driving circuit layer 200 includes a driving circuit composed of at least one metal wiring layer, and any metal wiring layer includes at least one metal lead.
  • the present disclosure provides an array substrate with a passive driving circuit to explain and illustrate the structure and principle of the array substrate of the present disclosure.
  • FIG. 26 only shows the first metal wiring layer 710, the second metal wiring layer 720 and the functional device layer of the array substrate.
  • the array substrate includes a base substrate 100, a driving circuit layer 200, and a functional device layer 300 that are sequentially stacked.
  • the driving circuit layer 200 includes a first metal wiring layer 710, an insulating layer, and a second metal wiring layer 720 laminated on the base substrate 100;
  • the first metal wiring layer 710 includes a plurality of first metal leads 711;
  • the insulating layer is provided There are connection vias that expose part of the first metal lead 711 layer;
  • the second metal lead 721 layer includes a plurality of second metal leads 721, the second metal leads 721 can be used as the electrode layer of the driving circuit for binding to the functional device 310 Certainly.
  • part of the second metal lead 721 is electrically connected to the first metal lead 711 through a connection via.
  • the functional device layer 300 includes functional devices 310 distributed in an array, and the functional devices 310 may be LEDs 311. One end of the LED 311 is connected to a second metal lead 721 through solder paste, and the other end is connected to another second metal lead 721 through solder paste.
  • the first metal wiring layer 710 may adopt the structure of the first lead layer 201 of the embodiment of the present disclosure to ensure that sufficient current can be transmitted to the second metal wiring layer 720, and to avoid the obvious Pressure drop.
  • the second metal wiring layer 720 may adopt the structure of the first lead layer 201 of the present disclosure, or may adopt the structure of the second lead layer 202 of the present disclosure, which is not limited.
  • the array substrate may include a plurality of light-emitting areas, and any light-emitting area may be provided with four second metal leads 721 that are adjacent to each other end to end.
  • a set of two second metal leads 721 are arranged opposite to each other.
  • Two different first metal leads 711 are respectively connected through connection vias, and the other two second metal leads 721 are not electrically connected to the first metal leads 711.
  • An LED 311 is provided adjacent to the two second metal leads 721, and two ends of the LED 311 are respectively connected to two second metal leads 721. In this way, when the common voltage and the driving voltage are respectively applied to the two first metal wires 711, the four LEDs 311 can be driven to emit light.
  • the exemplary array substrate can be used as a backlight source of an LCD display device, and can also be used as a passively driven display panel, which is not particularly limited in the present disclosure.
  • the LED 311 may be an LED lamp bead, or may be a Micro LED or a Mini LED.
  • the driving circuit layer 200 may include active driving circuits.
  • the driving circuit layer 200 of the array substrate may also be provided with electronic components such as driving transistors.
  • the device layer 300 is electrically connected, and any metal wiring layer includes at least one metal lead. Among them, at least one metal wiring layer is the first lead layer 201 of the present disclosure.
  • the driving circuit layer 200 may also be provided with other electronic components, for example, it may also be provided with other required transistors besides the storage capacitor and the driving transistor.
  • the transistor may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS).
  • the transistor is a thin film transistor.
  • the thin film transistor may be a top-gate thin film transistor or a bottom-gate thin film transistor, which is not limited in the present disclosure.
  • the thin film transistor material can be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor or an oxide thin film transistor, which is not limited in the present disclosure.
  • the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor, which is not limited in the present disclosure.
  • each thin film transistor and storage capacitor may be formed of an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source and drain metal layer, and other film layers.
  • the thin film transistor may include a semiconductor layer located in the active layer, a gate insulating layer, a gate located in the gate layer, an interlayer dielectric layer, and a source and drain electrode layer located in the source and drain metal layer.
  • the source and drain electrode layers are composed of thin film transistors.
  • the source and drain are composed.
  • the semiconductor layer includes a channel area and a source contact area and a drain contact area on both sides of the channel area.
  • the source passes through the interlayer dielectric layer to connect with the source contact area
  • the drain passes through the interlayer dielectric layer to connect to the drain.
  • the electrode contact area is connected, and the gate and the channel area are separated by the gate insulating layer.
  • the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the driving circuit layer 200 may include an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor.
  • the driving circuit layer 200 may include a gate layer, a gate insulating layer, an active layer, an interlayer dielectric layer, and a source-drain metal layer that are sequentially stacked, and the thin film transistor thus formed is a bottom-gate thin film transistor.
  • the driving circuit layer 200 may also adopt a double gate structure, that is, the gate layer may include a first gate layer and a second gate layer, and the gate insulating layer may include a second gate layer for isolating the active layer and the first gate layer. A gate insulating layer, and a second gate insulating layer for isolating the first gate layer and the second gate layer.
  • the driving circuit layer 200 may include an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, and a second gate layer that are sequentially stacked on one side of the base substrate 100. , Interlayer dielectric layer, source and drain metal layer.
  • the present disclosure provides an array substrate with an active driving circuit to explain and illustrate the structure and principle of the array substrate of the present disclosure.
  • FIG. 27 shows only the driving transistor of the array substrate, the two metal wiring layers, and the LED as a functional device.
  • the driving circuit is a semi-active driving circuit, which includes a driving transistor 210, a scan wire 510, a data wire 520, a common voltage wire 530, and a bonding wire 540.
  • the scan wire 510 is used to control the driving transistor 210 to turn on.
  • the data lead 520 is connected to the source of the driving transistor 210
  • the binding lead is connected to the drain of the driving transistor 210
  • both ends of the LED as the functional device 310 are connected to the binding lead 540 and the common voltage lead 530, respectively.
  • the driving current can flow through the LED through the data wire 520, the driving transistor 210, the bonding wire, and the common voltage wire 530, so that the LED emits light.
  • the scan lead 510 may belong to the second lead layer 202, and each scan lead 510 does not need to be prepared by an electroplating process or an electroless plating process.
  • the data lead 520, the common voltage lead 530, and the bonding lead 540 belong to the same first lead layer 201.
  • An electroplating process or an electroless plating process can be used to increase the thickness of each lead and reduce the impedance of each lead to reduce the driving circuit on the data lead 520. And the voltage drop on the common voltage lead 530 and ensure the accuracy of the current flowing through the LED.
  • any first lead layer 201 can be prepared according to the preparation method shown in step S210 to step S250.
  • a metal material may be deposited on one side of the base substrate 100 to form a conductive seed layer 410.
  • a magnetron sputtering method may be used to deposit a metal material on one side of the base substrate 100 to prepare a conductive seed layer 410 as an electroplating base or an electroless plating base.
  • the conductive seed layer 410 prepared in step S210 can be used as an electroplating substrate.
  • the electroless plating process is used to prepare the metal plating layer 430 in step S230, the conductive seed layer 410 prepared in step S210 can be used as an electroless plating substrate.
  • an intermediate substrate can be obtained according to the process steps that have been performed.
  • the intermediate substrate may have a different structure, for example, it may be the base substrate 100 itself, or it may include the base substrate 100 and each of the formed films sequentially stacked on the base substrate 100.
  • a metal material may be deposited on the surface of the intermediate substrate on which the conductive seed layer 410 is to be formed.
  • the base substrate 100 is used as an intermediate substrate in this step, and the metal material is deposited on the base substrate. 100 surface.
  • the liner The base substrate 100 and the film structure as a whole serve as the intermediate substrate in this step, and the surface of the film structure away from the base substrate 100 is the surface on which the conductive seed layer 410 is to be formed.
  • the thickness of the conductive seed layer 410 may not be greater than 1 micrometer, so as to avoid excessively thick conductive seed layer 410 from generating excessive stress on the intermediate substrate and improve the stability and yield of the array substrate.
  • the thickness of the conductive seed layer 410 may not be greater than 0.5 ⁇ m, so as to shorten the etching time of the conductive seed layer 410 in step S250 and improve the side profile of the seed lead 411 formed after etching.
  • the conductive seed layer 410 may be a metal material, or an alloy formed of a variety of metal materials, and may also be a stack of multiple metal layers.
  • the present disclosure does not make special restrictions, so as to meet the requirements of the electroplating process or the electroless plating process. Requirements and performance requirements of the array substrate shall prevail.
  • the conductive seed layer 410 may include a protective metal layer and a target metal layer located on the protective metal layer away from the surface of the base substrate 100.
  • the target metal layer can be used as an electroplating base or an electroless plating base to form a metal plating layer 430 on the surface thereof away from the base substrate 100.
  • the material of the target metal layer may be copper.
  • the protective metal layer is used to protect the target metal layer from corrosion, or to protect the intermediate substrate from the metal material of the target metal layer from corrosion.
  • the material of the protective metal layer may be a simple metal or an alloy, such as molybdenum, titanium, molybdenum-titanium-nickel alloy, or the like.
  • the conductive seed layer 410 includes a protective metal layer and a target metal layer that are sequentially stacked on one side of the base substrate 100.
  • the material of the protective metal layer may be MTD alloy (molybdenum titanium nickel alloy) with a thickness of 250-350 angstroms; the material of the target metal layer is copper with a thickness of 2500-3500 angstroms.
  • the types and thicknesses of the metal materials deposited in step S210 may be the same or different, so that the structures and materials of the seed leads 411 of the different first lead layers 201 are the same or different.
  • a removable pattern defining layer 420 may be formed on the surface of the conductive seed layer 410 away from the base substrate 100, and the removable pattern defining layer 420 may be provided with a lead opening 421,
  • the lead opening 421 may include a part of the conductive seed layer 410.
  • the conductive seed layer 410 exposed by the lead opening 421 can be used as an electroless plating base to grow electroplated metal or electrolessly plated metal, and is formed by the removable pattern defining layer 420. Electroplating metal or electroless metal plating cannot grow on the covered conductive seed layer 410. Therefore, the orthographic projection of the lead opening 421 on the base substrate 100 can coincide with the orthographic projection of the metal plating layer 430 formed in step S230.
  • the removable pattern defining layer 420 may be prepared through step S221 and step S222:
  • Step S221 forming a removable insulating material layer on the surface of the conductive seed layer 410 away from the base substrate 100;
  • step S222 a patterning operation is performed on the removable insulating material layer to form a removable pattern defining layer 420.
  • the removable insulating material layer may be a photoresist material layer, that is, a photoresist material layer may be formed on the surface of the conductive seed layer 410 away from the base substrate 100.
  • the photoresist material layer can be patterned by exposure and development to form a removable pattern defining layer 420.
  • a degradable photoresist material may be used to form a layer of photoresist material on the surface of the conductive seed layer 410 away from the base substrate 100.
  • the degradable photoresist material is a photoresist material that can be dissolved in a degradation liquid after curing.
  • the degradable photoresist material has a decomposable crosslinking group or forms a decomposable crosslinking group when cured.
  • the cured degradable photoresist material can be treated with a degradation solution.
  • the decomposable in the cured degradable photoresist material The cross-linking group can react with the degradation liquid to break, so that the cured degradable photoresist material is decomposed into small molecular fragments that can be dissolved in the degradation liquid. In this way, the cured degradable photoresist material can be removed gently and completely.
  • a degradable photoresist material is used to prepare a photoresist material layer, and the material of the removable pattern defining layer 420 prepared in step S222 is a cured degradable photoresist material; in step S240, The degradable liquid can be used to dissolve the removable pattern defining layer 420 to realize the removal of the removable pattern defining layer 420, which not only ensures the complete removal of the removable pattern defining layer 420, but also avoids the removal of the removable pattern defining layer 420.
  • the metal plating layer 430 is damaged when the pattern defining layer 420 is formed.
  • a negative photoresist material may be used to form a layer of photoresist material on the surface of the conductive seed layer 410 away from the base substrate 100.
  • the photoresist material layer is exposed and developed to form a removable pattern defining layer 420 having a lead opening 421, so that the width of the end of the lead opening 421 close to the base substrate 100 is greater than that away from the substrate 100. The width of one end of the base substrate 100.
  • the width of the lead opening 421 can be reduced in the direction away from the base substrate 100 with the help of the material properties of the negative photoresist material, which not only facilitates the removal of the removable pattern defining layer 420, but also enables electroplating or
  • the width of the growth lead 432 formed by electroless plating decreases in the direction away from the base substrate 100, thereby increasing the strength of the growth lead 432 and reducing the risk of the growth lead 432 collapsing.
  • the width of the end of the first lead 2011 away from the base substrate 100 is smaller than the width of the end of the first lead 2011 close to the base substrate 100.
  • a passivation material may be deposited on the surface of the first lead 2011 away from the base substrate 100 and the side surface of the first lead 2011, such as depositing silicon oxide, silicon nitride, or oxynitride. Materials such as silicon are used to form the passivation layer 440 for protecting the first lead 2011. Since the width of the growth lead 432 formed by electroplating or electroless plating decreases in the direction away from the base substrate 100, the continuity of the passivation layer can be ensured.
  • removable insulating materials may also be used to prepare the removable pattern defining layer 420, and the removable pattern defining layer 420 may be removed in step S240 using a corresponding process 420, for example, using silicon oxide to prepare a removable pattern defining layer 420 and removing the removable pattern defining layer 420 through an etching process, or using a photosensitive resin to prepare a removable pattern defining layer 420 and using a dry lift-off process
  • the removable pattern defining layer 420 is removed, which is not described in further detail in this disclosure.
  • an electroplating process or an electroless plating process may be used to form a metal plating layer 430 on the surface of the conductive seed layer 410 in the lead opening 421.
  • electroplating or electroless plating is grown from the surface of the conductive seed layer 410 as the electroless plating base of the electroplating base.
  • the electroplating metal only grows in the lead opening 421, and
  • the precursor growth leads 431 located in the lead opening 421 are formed, and each of the precursor growth leads 431 forms a metal plating layer 430.
  • the metal plating layer 430 is formed by an electroplating process, the metal grown on the surface of the conductive seed layer 410 is electroplated metal, and the formed metal plating layer 430 can be used as the electroplated metal layer of the present disclosure.
  • the electroless plating process is used to form the metal plating layer 430, the metal grown on the surface of the conductive seed layer 410 is an electroless plating metal, and the formed metal plating layer 430 can be used as the electroless plating metal layer of the present disclosure.
  • the metal plating layer 430 on the surface of the conductive seed layer 410 is formed in the lead opening 421 by an electroplating process. Since the conductive seed layer 410 is a whole surface metal, it is convenient to load the electroplating current to the entire conductive seed layer 410 and make the conductive seed layer 410 have a small voltage drop, which can improve the uniformity of the electroplating rate at the position of each lead opening 421 Therefore, the uniformity of the surface of the precursor growth lead 431 away from the base substrate 100 is improved.
  • the preparation method of the present disclosure does not need to design additional connecting leads to ensure power supply to the patterned conductive seed layer 410, which not only simplifies the design process and preparation process of each first lead layer 201, but also enables the preparation of the first lead layer of the present disclosure.
  • the method of a lead layer 201 can be applied to any film layer position, and overcomes the defect that copper electroplating can only be performed on the first layer close to the substrate in the prior art.
  • the conductive seed layer needs to be patterned before electroplating, which requires the design of additional conductive leads to electrically connect the seed leads to each other to ensure that the seed leads can be loaded with current during the electroplating process. Since the conductive seed layer is patterned into seed leads, it is difficult to maintain uniformity of the electroplating current density on each seed lead, which is not conducive to the uniform growth of electroplated metal on different seed leads. In addition, the electroplated metal may grow on the side of the seed lead during the electroplating process, which will cause the metal plating layer to completely cover the seed lead and reduce the pattern restriction effect of the seed lead on the metal plating layer. More importantly, due to the need to design additional conductive leads to connect each seed lead, this method is only applicable to the metal wiring layer close to the base substrate, and cannot be applied to any metal wiring layer.
  • each precursor growth lead 431 that is, the thickness of the metal plating layer 430
  • the thickness of each precursor growth lead 431 can be controlled by controlling the parameters of the electroplating process or the parameters of the electroless plating process, such as electroplating current, electroplating time and other parameters.
  • the thickness of the metal plating layer 430 can be made not more than five times the width of the lead opening 421.
  • the minimum value of the width of the lead opening 421 is the first size value, that is, the minimum value of the width of the precursor growth lead 431 on the side close to the base substrate 100 is the first size value;
  • the thickness of the metal plating layer 430 is the second size value , That is, the thickness of the precursor growth lead 431 is the second size value;
  • the second size value is not greater than 5 times the first size value.
  • the aspect ratio of the prepared precursor growth lead 431 is not greater than 5, which can increase the bonding strength between the precursor growth lead 431 and the conductive seed layer 410, prevent the precursor growth lead 431 from collapsing, and improve the growth of the precursor. Stability of the lead 431.
  • the thickness of the first lead 2011 is not greater than 5 times the width of the seed lead 411.
  • the thickness of the metal plating layer 430 is 1.5-20 micrometers, for example, it can be 2 micrometers, 5 micrometers, 10 micrometers, 20 micrometers, and so on. Preferably, the thickness of the metal plating layer 430 is 5-10 microns.
  • the thickness of the metal plating layer 430 is greater than the thickness of the conductive seed layer 410 to ensure that the thickness of the first lead 2011 is greater than the thickness of the conductive seed layer 410 to achieve the purpose of increasing the thickness of the first lead 2011.
  • the material of the metal plating layer 430 may be copper through a copper electroplating process or an electroless copper plating process.
  • the resistance of the growth lead 432 can be reduced, thereby reducing the resistance of the first lead 2011.
  • the conductive seed layer 410 is far away from the surface of the base substrate 100 and includes at least one copper metal layer to ensure that the copper metal plating layer 430 can be smoothly grown on the surface of the conductive seed layer 410 during an electroplating process or an electroless copper plating process.
  • etching may be used to remove the portion of the conductive seed layer 410 that is not covered by the metal plating layer 430.
  • a suitable etching process can be selected according to the thickness and material of the conductive seed layer 410, including selecting a suitable etching solution, etching time, etc., so that the exposed part of the conductive seed layer 410 can be etched clean. .
  • the metal plating layer 430 does not need to be specially protected. In this way, the surface of each precursor growth lead 431 of the metal plating layer 430 is partially etched in the etching process, and the remaining part forms the growth lead 432 of the first lead 2011.
  • the metal plating layer 430 and the conductive seed layer 410 may be etched at a close speed, so that the thickness of the formed first lead 2011 is close to the thickness of the metal plating layer 430. For example, if the thickness of the metal plating layer 430 is 1.5-20 microns, the thickness of the formed first lead 2011 is 1.5-20 microns.
  • the surface of the precursor growth lead 431 away from the base substrate 100 has a slightly rough surface, and the protruding part of the surface is more easily etched by the etchant, thereby making the precursor growth lead 431 far away from the base substrate.
  • the flatness of the surface of 100 is continuously improved during the etching process.
  • the orthographic projection of the growth lead 432 on the base substrate 100 coincides with the orthographic projection of the seed lead 411 on the base substrate 100, which ensures The side surface of the first lead 2011 is flat, and the problem that the seed lead 411 protrudes from the growth lead 432 is avoided. Therefore, the flatness of the surface and the side surface of the first lead 2011 is higher, which can further improve the topography of the first lead 2011 and improve the performance of the array substrate.
  • the prepared array substrate includes a base substrate 100, a driving circuit layer 200, and a functional device layer 300 stacked in sequence;
  • the driving circuit layer 200 includes at least one first lead layer 201, any one of the first lead layers 201 includes at least one first lead 2011;
  • any one of the first leads 2011 includes a seed lead provided on one side of the base substrate 100 411, and the growth lead 432 disposed on the surface of the seed lead 411 away from the base substrate 100.
  • the orthographic projection of the growth lead 432 on the base substrate 100 coincides with the orthographic projection of the seed lead 411 on the base substrate 100.
  • the preparation method of the array substrate provided by the present disclosure may further include: forming an alignment mark layer 110 on one side of the base substrate 100, and the alignment mark layer 110 has Alignment pattern 111 for alignment. Then, a driving circuit layer 200 is formed on the side of the alignment mark layer 110 away from the base substrate 100. In this way, the pattern of the first lead layer 201 can be avoided as the alignment pattern 111, so as to avoid the problem that the first lead layer 201 is too thick and the edges are not clear.
  • the material of the alignment mark layer 110 may be metal, metal oxide, silicon or other materials.
  • the material of the alignment mark layer 110 may be molybdenum, titanium, copper, aluminum, tungsten, etc., or may be ITO. (Indium zinc oxide) and other metal oxides may also be materials such as amorphous silicon and polysilicon.
  • the material of the alignment mark layer 110 is molybdenum.
  • a buffer layer 120 may be further provided between the alignment mark layer 110 and the driving circuit layer 200, and the buffer layer 120 adopts an insulating material to isolate the alignment mark layer 110 and the driving circuit layer 200.
  • the alignment mark layer 110 may not be provided.
  • the prepared driving circuit layer 200 includes an active driving circuit
  • the active layer pattern of the active driving circuit can be used as the alignment pattern 111.
  • forming at least one first lead layer 201 on one side of the base substrate 100 may include:
  • Step S310 as shown in FIG. 12, a first lead layer 201 is formed on one side of the base substrate 100;
  • Step S320 as shown in FIG. 12, a first planarization layer 241 is formed on the side of the first lead layer 201 away from the base substrate 100, and the first planarization layer 241 exposes at least a part of the first lead layer 201;
  • Step S330 as shown in FIG. 13, a first transfer metal layer 261 is formed on the side of the first planarization layer 241 away from the base substrate 100, and the first transfer metal layer 261 is connected to the first lead layer 201;
  • Step S340 as shown in FIG. 14, a second planarization layer 242 is formed on the side of the first transition metal layer 261 away from the base substrate 100, and the second planarization layer 242 has a first connection via 251;
  • the via 251 exposes a part of the first transition metal layer 261, and the orthographic projection of the first connection via 251 on the first lead layer 201 does not overlap the first lead layer 201;
  • step S350 as shown in FIG. 15, another first lead layer 201 is formed on the surface of the second planarization layer 242 away from the base substrate 100, and another first lead layer 201 is connected to the first lead layer 201 through the first connection via 251.
  • a transition metal layer 261 is connected.
  • the driving circuit layer 200 may include the previous first lead layer 201a, the first planarization layer 241, and the first transfer metal layer 261 that are sequentially stacked.
  • the second planarization layer 242 and the latter first lead layer 201b, the former first lead layer 201a and the latter first lead layer 201b form a first lead layer group connected by the first transition metal layer 261.
  • the previous first lead layer 201a is provided on one side of the base substrate 100; the first planarization layer 241 is provided on the side of the previous first lead layer 201a away from the base substrate 100, and exposes at least part of the previous first lead layer 201a.
  • a lead layer 201a; the first transition metal layer 261 is provided on the side of the first planarization layer 241 away from the base substrate 100 and is connected to the previous first lead layer 201a; the second planarization layer 242 is provided on the first
  • the transfer metal layer 261 is far away from the base substrate 100 and is provided with a first connection via 251; the first connection via 251 exposes a part of the first transfer metal layer 261, and the first connection via 251 is in the previous
  • the orthographic projection on the first lead layer 201a does not overlap with the previous first lead layer 201a; the latter first lead layer 201b is provided on the surface of the second planarization layer 242 away from the base substrate 100, and is connected through the first
  • the hole 251 is connected to the first transit metal layer 261.
  • step S310 the previous first lead layer 201a can be formed on one side of the base substrate 100 through steps S210 to S250.
  • a first passivation layer may be formed on the surface of the previous first lead layer 201a away from the base substrate 100, and the first passivation layer is used to protect the first lead 2011 will not be eroded.
  • the first passivation layer exposes at least part of the previous first lead layer 201a, so that the previous first lead layer 201a can be electrically connected to the first transition metal layer 261.
  • a first planarization layer 241 may be formed on the side of the previous first lead layer 201a away from the base substrate 100, and the first planarization layer 241 may be filled with each first lead 2011 The gap therebetween provides a planarized surface for the first transit metal layer 261.
  • the material of the first planarization layer 241 may be an inorganic material, such as silicon oxide, silicon nitride, etc., or an organic material, such as epoxy resin, polyimide, and other resin materials. In an embodiment of the present disclosure, the material of the first planarization layer 241 is a resin material.
  • a first transfer metal layer 261 may be formed on the side of the first planarization layer 241 away from the base substrate 100, and the first transfer metal layer 261 is used to connect to the previous first lead layer. 201a and the latter first lead layer 201b.
  • a transfer metal material layer may be formed by a deposition method such as magnetron sputtering, and then a patterning operation is performed on the transfer metal material layer to form the first transfer metal.
  • the first transition metal layer can be a layer of conductive material or a stack of multiple layers of conductive material.
  • the first transition metal layer 261 may include a first conductive material layer, a second conductive material layer, and a first conductive material layer that are sequentially stacked, that is, present a sandwich structure.
  • the first conductive material layer can be selected from corrosion-resistant metals or alloys, such as molybdenum or titanium; the second conductive material layer can be selected from metals or alloys with high conductivity, such as copper, aluminum, and silver.
  • the first transition metal layer 261 may include a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in sequence, wherein the thickness of the titanium metal layer may be 400 to 600 angstroms, and the thickness of the aluminum metal layer may be 3,500 angstroms. ⁇ 5500 Angstroms.
  • the material of the first transit metal layer 261 may be the same as the material of the conductive seed layer 410.
  • the first transition metal layer 261 includes an MTD alloy layer and a copper layer stacked in sequence, the thickness of the MTD alloy layer is 250-350 angstroms, and the thickness of the copper layer is 2500-3500 angstroms.
  • the first transfer metal layer 261 A second passivation layer is formed on the surface away from the base substrate 100, and the second passivation layer is used to protect the first transition metal layer 261 from being corroded.
  • the second passivation layer exposes at least a part of the first transfer metal layer 261, so that the latter first lead layer 201b can be electrically connected to the first transfer metal layer 261.
  • a second planarization layer 242 may be formed on the side of the first transfer metal layer 261 away from the base substrate 100.
  • the material and preparation method of the second planarization layer 242 may be the same as or different from those of the first planarization layer 241, which is not particularly limited in the present disclosure.
  • the second planarization layer 242 has a first connection via 251; the first connection via 251 exposes a part of the first transition metal layer 261, and the first connection via 251 is located directly on the previous first lead layer 201a.
  • the projection does not overlap with the previous first lead layer 201a.
  • the first transition metal layer 261 at least includes a first connection area and a second connection area that do not overlap each other, wherein the first connection area is electrically connected to the previous first lead layer 201a, and the second connection area is electrically connected to the latter
  • the first lead layer 201b is electrically connected.
  • This arrangement method can prevent the unevenness of the previous first lead layer 201a from being transmitted to the latter first lead layer 201b, and can make the latter first lead layer 201b have a good topography without being on the previous first lead layer.
  • the deterioration of the topography occurs under the influence of the layer 201a.
  • this can also avoid the continuous formation of multiple thicker metal layers at the same position, improve the stability of each first lead 2011 in the first lead layer 201, and improve the stress of the array substrate.
  • step S350 the next first lead layer 201b can be formed on one side of the base substrate 100 through steps S210 to S250.
  • a third passivation layer may also be formed on the surface of the latter first lead layer 201b away from the base substrate 100, and the third passivation layer is used to protect the latter first lead layer 201b from Eroded.
  • the third passivation layer exposes at least part of the latter first lead layer 201b, so that the latter first lead layer 201b can be electrically connected to other structures of the array substrate.
  • the formed array substrate may have multiple first lead layers 201, for example, three or four One or five first lead layers 201.
  • a first lead layer group may be formed between two adjacent first lead layers 201.
  • the first lead layer 201 in the first lead layer group close to the base substrate 100 may be the previous first lead layer 201a.
  • the first lead layer 201 far away from the base substrate 100 in a lead layer group can be the latter first lead layer 201b, and the former first lead layer 201a and the latter first lead layer 201b can be sandwiched between two
  • the first transition metal layer 261 between the first lead layers 201 is electrically connected.
  • each conductive lead layer can be divided into a plurality of first lead layers 201 stacked in sequence, and two adjacent first lead layers 201 are electrically connected through the first transition metal layer 261. In this way, the multiple first lead layers 201 that are electrically connected to each other can be equivalent in effect to the required thick conductive lead layer, thereby improving the process feasibility and yield of the array substrate preparation.
  • step S120 may include step S410 to step S450 to form the driving circuit layer 200, so that the driving circuit layer 200 has a driving transistor 210 and a driving transistor. 210 connected to the first lead layer 201.
  • a driving transistor 210 is formed on one side of the base substrate 100.
  • the driving transistor 210 includes a source and drain electrode layer composed of a source electrode and a drain electrode.
  • the source and drain electrode layer is located in the source and drain metal layer of the driving circuit layer.
  • the driving transistor 210 may be formed on one side of the base substrate 100 by the following method:
  • an active layer, a gate insulating layer and a gate layer are formed on one side of the base substrate 100 to form the semiconductor layer and the gate of the driving transistor 210, wherein the semiconductor layer of the driving transistor 210 is located in the active layer, It also includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; the gate of the driving transistor is located on the gate layer; the channel region and the gate of the semiconductor layer are isolated by the gate insulating layer.
  • Step S412 forming an interlayer dielectric layer 220, the active layer, gate insulating layer and gate layer are all located between the interlayer dielectric layer 220 and the base substrate 100; the interlayer dielectric layer 220 is provided with a second connection via 252 , The second connection via 252 exposes the source contact area and the drain contact area.
  • a source-drain metal layer 230 is formed on the side of the interlayer dielectric layer 220 away from the base substrate 100.
  • the source-drain metal layer 230 is formed with the source and drain of the driving transistor.
  • the source and drain constitute the source of the driving transistor. Drain metal layer; wherein the source is connected to the source contact area through the second connection via 252, and the drain is connected to the drain contact area through the second connection via 252.
  • the material and thickness of the source and drain metal layer 230 may be the same as or different from the first transit metal layer 261.
  • a passivation layer may be formed on the surface of the source/drain metal layer 230 away from the substrate 100. It can be understood that the passivation layer exposes at least part of the source and drain metal layer 230 so that the source and drain metal layer 230 can be electrically connected to other conductive structures of the driving circuit layer 200.
  • a third planarization layer 243 is formed on the side of the driving transistor 210 away from the base substrate 100, and the third planarization layer 243 is provided with a third connection via 253 exposing at least part of the source and drain electrode layers.
  • the material of the third planarization layer 243 may be the same as or different from the first planarization layer 241.
  • the orthographic projection of the third connection via 253 on the base substrate 100 does not overlap with the orthographic projection of the second connection via 252 on the base substrate 100.
  • the third connection via 253 can expose the flat surface of the source/drain metal layer 230, which helps to improve the connection strength between the exposed source/drain metal layer 230 and other conductive structures of the driving circuit.
  • a second transition metal layer 262 is formed on the side of the third planarization layer 243 away from the base substrate 100, and the second transition metal layer 262 is connected to the source/drain metal layer 230 through the third connection via 253.
  • the material and thickness of the second transit metal layer 262 may be the same as or different from the first transit metal layer 261.
  • a fourth planarization layer 244 is formed on the side of the second transition metal layer 262 away from the base substrate 100.
  • the fourth planarization layer 244 has a fourth connection via 254; the fourth connection via 254 exposes part of the second The second transition metal layer 262, and the orthographic projection of the fourth connection via 254 on the base substrate 100 and the orthographic projection of the third connection via 253 on the base substrate 100 do not overlap.
  • the second transition metal layer 262 includes at least a third connection area and a fourth connection area that do not overlap each other, wherein the third connection area is electrically connected to the source/drain metal layer 230, and the fourth connection area is connected to the first lead layer. 201 electrical connection.
  • This arrangement method can prevent the unevenness of the source and drain metal layer 230 from being conducted to the first lead layer 201, and can enable the first lead layer 201 to have a good topography without being affected by the source and drain metal layer 230. The deterioration.
  • the material of the fourth planarization layer 244 may be the same as or different from the first planarization layer 241.
  • a first lead layer 201 is formed on the surface of the fourth planarization layer 244 away from the base substrate 100, and the first lead layer 201 is connected to the second transition metal layer 262 through the fourth connection via 254.
  • the first lead layer 201 may be formed according to the method shown in step S210 to step S250.
  • the prepared driving circuit layer 200 may include a driving transistor 210, a third planarization layer 243, and a second transfer metal layer stacked in sequence. 262, a fourth planarization layer 244 and a first lead layer 201. in,
  • the driving transistor 210 is provided on one side of the base substrate 100, and the driving transistor 210 includes a source and drain electrode layer composed of a source electrode and a drain; the third planarization layer 243 is provided on the side of the driving transistor 210 away from the base substrate 100, And a third connection via 253 exposing at least part of the source and drain electrode layers is provided; the second transition metal layer 262 is provided on the side of the third planarization layer 243 away from the base substrate 100 and passes through the third connection via 253 Connected to the source and drain electrode layers; the fourth planarization layer 244 is provided on the side of the second transition metal layer 262 away from the base substrate 100, and has a fourth connection via 254; the fourth connection via 254 exposes part of the second The transition metal layer 262, and the orthographic projection of the fourth connection via 254 on the base substrate 100 and the orthographic projection of the third connection via 253 on the base substrate 100 do not overlap; the first lead layer 201 is provided on the The four planarization layer 244 is away from the surface
  • step S120 may include steps S510 to S530 to form the driving circuit layer 200, and the driving circuit layer 200 has a driving transistor 210 and a driver The first lead layer 201 to which the transistor 210 is connected.
  • a driving transistor 210 is formed on one side of the base substrate 100.
  • the driving transistor 210 includes a source and drain electrode layer composed of a source electrode and a drain electrode.
  • the source and drain electrode layer is located in the source and drain metal layer of the driving circuit layer.
  • a third planarization layer 243 is formed on the side of the driving transistor 210 away from the base substrate 100, and the third planarization layer 243 is provided with a third connection via 253 exposing at least part of the source and drain electrode layers.
  • the orthographic projection of the third connection via 253 on the base substrate 100 and the orthographic projection of the second connection via 252 on the base substrate 100 do not overlap.
  • step S410 to step S420 can be referred to to implement step S510 to step S520.
  • a first lead layer 201 is formed on the surface of the third planarization layer 243 away from the base substrate 100, and the first lead layer 201 is connected to the source and drain electrode layers through the third connection via 253.
  • the first lead layer 201 may be formed according to the method shown in step S210 to step S250.
  • the prepared driving circuit layer 200 may include a driving transistor 210, a third planarization layer 243, and a first lead layer 201 stacked in sequence. . in,
  • the driving transistor 210 is provided on one side of the base substrate, and the driving transistor 210 includes a source and drain electrode layer composed of a source electrode and a drain; the third planarization layer 243 is provided on the source and drain electrode layer away from the base substrate 100 A first lead layer 201 is provided on the surface of the third planarization layer 243 away from the base substrate 100 and is connected through the third The hole 253 is connected to the source and drain electrode layers.
  • the source and drain metal layers 230 can be multiplexed as the second transit metal layer 262, so it is not necessary to prepare the second transit metal layer 262 and the fourth planarization layer 244, and the process can be Two patterning processes are reduced and related materials are saved, and two film layers can be reduced on the formed array substrate.
  • the preparation method shown in this embodiment mode can reduce the preparation cost of the array substrate and improve the preparation efficiency, and can make the array substrate have a smaller thickness.
  • step S120 may include step S610 to step S630 to form the driving circuit layer 200, so that the driving circuit layer 200 has a driving transistor 210 and a driver The first lead layer 201 to which the transistor 210 is connected.
  • step S610 an active layer, a gate insulating layer and a gate layer are formed on one side of the base substrate 100 to form the semiconductor layer and the gate of the driving transistor 210, wherein the semiconductor layer of the driving transistor 210 is located in the active layer, And includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; the gate of the driving transistor 210 is located on the gate layer; the channel region and the gate of the semiconductor layer are separated by a gate insulating layer;
  • step S620 an interlayer dielectric layer 220 is formed.
  • the active layer, the gate insulating layer and the gate layer are all located between the interlayer dielectric layer 220 and the base substrate 100;
  • the interlayer dielectric layer 220 is provided with a second connection via 252 ,
  • the second connection via 252 exposes the source contact area and the drain contact area;
  • a first lead layer 201 is formed on the side of the interlayer dielectric layer 220 away from the base substrate 100.
  • the first lead layer 201 forms a source electrode and a drain electrode.
  • the source electrode is connected to the source electrode through the second connection via 252.
  • the contact area is connected, and the drain is connected to the drain contact area through the second connection via 252.
  • the prepared driving circuit layer 200 may include a driving transistor, and the driving transistor may include a semiconductor layer, an interlayer dielectric layer, and a first lead layer; a semiconductor The layer is provided on one side of the base substrate; the semiconductor layer includes a source contact region and a drain contact region; the interlayer dielectric layer is provided on the side of the semiconductor layer away from the base substrate; A lead layer is provided on the side of the interlayer dielectric layer away from the base substrate, and forms a source electrode and a drain electrode; the source electrode is connected to the source contact area, and the drain electrode is connected to the The drain contact area is connected.
  • the first lead layer 201 can be multiplexed as the source/drain metal layer 230, which can further reduce the patterning process and film materials in the preparation process of the array substrate, reduce the preparation cost of the array substrate, and further Reduce the thickness of the array substrate.
  • the functional device layer 300 may be formed on the side of the driving circuit layer 200 away from the base substrate 100.
  • the functional device layer 300 may include functional devices 310 distributed in an array, for example, a light-emitting device for emitting light, an ultrasonic emitting device for emitting ultrasonic waves, a heating device for generating heat, or other current-driven functional devices 310.
  • the driving circuit layer 200 may include an electrode layer, and each functional device 310 may be electrically connected to the electrode layer.
  • the electrode layer may be the first lead layer 201 or the second lead layer 202, which is not particularly limited in the present disclosure.
  • the connecting electrode layer may include a first electrode and a second electrode that are adjacently disposed, the first end of the functional device 310 may be electrically connected to the first electrode, and the second end of the functional device 310 may be electrically connected to the second electrode. In this way, the driving current can flow through the functional device 310 through the first electrode and the second electrode, so that the functional device 310 works.
  • a pixel defining layer 271 may be formed on the side of the driving circuit layer away from the base substrate, and then conductive glue 272 may be coated in the area defined by the pixel defining layer 271. , And the functional device 310 is electrically connected to the electrode layer through the conductive glue 272.
  • the functional device 310 may be an LED, a Mini LED, or a Micro LED, and the Mini LED or the Micro LED may be connected to the electrode layer through a solder paste.
  • preparation method of the array substrate of the present disclosure may further include:
  • a bonding layer is prepared on the side of the base substrate 100 away from the driving circuit layer 200.
  • the bonding layer has a plurality of bonding pads, and each bonding pad is electrically connected to the driving circuit layer 200 through fan-out leads.
  • the prepared array substrate may include a base substrate 100, a driving circuit layer 200, and a functional device layer 300 stacked in sequence, a binding layer located on the side of the base substrate 100 away from the driving circuit layer 200, and a bonding layer located on the base substrate 100. Fan-out leads on the side of 100.
  • the array substrate may have a smaller edge, which facilitates the formation of a larger substrate by splicing a plurality of different array substrates, and enables the larger substrate to have a smaller splicing seam.
  • the functional device 310 is a Micro LED
  • a plurality of different small-sized array substrates may be spliced to form a large-sized display screen, and the splicing size of the display screen may be very small, thereby achieving a good display effect.
  • the driving circuits of each array substrate such as the driving circuit board and the driving chip arranged on the driving circuit board, can be electrically connected through bonding pads to realize the driving of the array substrate.
  • the bonding layer may include a backside lead layer 610, an insulating layer 620, and a bonding pad layer that are sequentially laminated on the surface of the base substrate 100 away from the driving circuit layer 200. 630.
  • the backside lead layer 610 can be electrically connected to the fan-out lead (not shown in FIG. 25), and the insulating layer 620 exposes a part of the backside lead layer 610, so that the bonding pad layer 630 can be electrically connected to the backside lead layer 610 .
  • the backside lead layer 610 may also be provided with a backside alignment pattern, and the material of the backside alignment pattern may be the same as or different from the backside lead layer 610.
  • the materials of the backside alignment pattern and the bonding pad layer 630 are both ITO.
  • the embodiments of the present disclosure also provide an array substrate, as shown in FIG. 1 and FIG. 2, the array substrate includes a base substrate 100, a driving circuit layer 200, and a functional device layer 300 stacked in sequence;
  • the driving circuit layer 200 includes at least one first lead layer 201, any one of the first lead layers 201 includes at least one first lead 2011; any one of the first leads 2011 includes a seed lead provided on one side of the base substrate 100 411, and the growth lead 432 disposed on the surface of the seed lead 411 away from the base substrate 100.
  • the orthographic projection of the growth lead 432 on the base substrate 100 coincides with the orthographic projection of the seed lead 411 on the base substrate 100.
  • the array substrate provided in the present disclosure can be prepared by any one of the preparation methods described in the foregoing embodiment of the preparation method of the array substrate, and therefore has the same or similar technical effects, and this disclosure will not be repeated here.
  • the thickness of the first lead 2011 is not greater than 5 times the width of the seed lead 411.
  • the thickness of the first lead 2011 is 1.5 micrometers to 20 micrometers.
  • the width of the end of the first lead 2011 away from the base substrate 100 is smaller than the width of the end of the first lead 2011 close to the base substrate 100.
  • the driving circuit layer 200 includes:
  • a first lead layer 201a is provided on one side of the base substrate 100;
  • the first planarization layer 241 is disposed on a side of the first lead layer 201a away from the base substrate 100, and exposes at least part of the first lead layer 201a;
  • the first transition metal layer 261 is provided on a side of the first planarization layer 241 away from the base substrate 100 and connected to the first lead layer 201a;
  • the second planarization layer 242 is disposed on a side of the first transfer metal layer 261 away from the base substrate 100, and is provided with a first connection via 251; the first connection via 251 exposes a part of the first transfer metal layer 261 , And the orthographic projection of the first connection via 251 on the first lead layer 201a does not overlap with the first lead layer 201a;
  • the other first lead layer 201b is disposed on the surface of the second planarization layer 242 away from the base substrate 100, and is connected to the first transition metal layer 261 through the first connection via 251.
  • the driving circuit layer 200 includes at least one first lead layer group, and any first lead layer group includes:
  • the previous first lead layer 201a is provided on one side of the base substrate 100;
  • the first planarization layer 241 is disposed on a side of the previous first lead layer 201a away from the base substrate 100, and exposes at least part of the previous first lead layer 201a;
  • the first transition metal layer 261 is disposed on the side of the first planarization layer 241 away from the base substrate 100 and connected to the previous first lead layer 201a;
  • the second planarization layer 242 is disposed on a side of the first transfer metal layer 261 away from the base substrate 100, and is provided with a first connection via 251; the first connection via 251 exposes a part of the first transfer metal layer 261 , And the orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap with the previous first lead layer 201a;
  • the latter first lead layer 201b is disposed on the surface of the second planarization layer 242 away from the base substrate 100, and is connected to the first transition metal layer 261 through the first connection via 251.
  • the driving circuit layer 200 includes:
  • the driving transistor 210 is arranged on one side of the base substrate 100, and the driving transistor 210 includes a source and drain electrode layer composed of a source electrode and a drain electrode;
  • the third planarization layer 243 is provided on a side of the source and drain electrode layers away from the base substrate 100, and is provided with a third connection via 253 exposing at least part of the source and drain electrode layers;
  • the second transition metal layer 262 is disposed on a side of the third planarization layer 243 away from the base substrate 100, and is connected to the source and drain electrode layers through the third connection via 253;
  • the fourth planarization layer 244 is disposed on a side of the second transfer metal layer 262 away from the base substrate 100, and has a fourth connection via 254; the fourth connection via 254 exposes a part of the second transfer metal layer 262, And the orthographic projection of the fourth connection via 254 on the base substrate 100 and the orthographic projection of the third connection via 253 on the base substrate 100 do not overlap;
  • a first lead layer 201 is disposed on the surface of the fourth planarization layer 244 away from the base substrate 100 and is connected to the second transition metal layer 262 through the fourth connection via 254.
  • the driving circuit layer 200 includes:
  • the driving transistor 210 is arranged on one side of the base substrate 100, and the driving transistor 210 includes a source and drain electrode layer composed of a source electrode and a drain electrode;
  • the third planarization layer 243 is provided on a side of the source and drain electrode layers away from the base substrate 100, and is provided with a third connection via 253 exposing at least part of the source and drain electrode layers;
  • a first lead layer 201 is disposed on the surface of the third planarization layer 243 away from the base substrate 100, and is connected to the source and drain electrode layers through the third connection via 253.
  • the driving circuit layer 200 includes a driving transistor, and the driving transistor includes:
  • the semiconductor layer is provided on one side of the base substrate 100; the semiconductor layer includes a source contact area and a drain contact area;
  • the interlayer dielectric layer 220 is provided on the side of the semiconductor layer away from the base substrate 100;
  • the first lead layer 201 is arranged on the side of the interlayer dielectric layer 220 away from the base substrate and forms a source electrode and a drain electrode; the source electrode is connected to the source contact area, and the drain electrode is connected to the The drain contact area is connected.
  • the embodiments of the present disclosure also provide a display device, which includes any one of the array substrates described in the above-mentioned array substrate embodiment.
  • the display device can be a mobile phone screen, a computer screen, a television or other types of display devices. Since the display device has any one of the array substrates described in the above-mentioned array substrate embodiments, it has the same beneficial effects, which will not be repeated in this disclosure.
  • the display device among the functional devices on the array substrate, at least some of the functional devices are light-emitting devices.

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Abstract

一种阵列基板及其制备方法，属于显示技术领域。该阵列基板的制备方法包括依次形成层叠的衬底基板（100）、驱动电路层（200）和功能器件层（300）；其中，形成驱动电路层（200）包括：在所述衬底基板（100）的一侧形成导电种子（410）；在所述导电种子层（410）表面形成可移除的图案限定层（420），所述可移除的图案限定层（420）设置有引线开口（421），所述引线开口（421）暴露部分所述导电种子层（410）；采用电镀工艺或者化学镀工艺在所述引线开口（421）内形成位于所述导电种子层（410）表面的金属镀层（430）；移除所述可移除的图案限定层（420）；去除所述导电种子层（410）未被所述金属镀层（430）覆盖的部分，以形成第一引线层（201）。该制备方法使得电镀工艺和化学镀工艺适用于任意金属布线层，且提高了第一引线层（201）的形貌。

Description

阵列基板及其制备方法、显示装置
交叉引用
本公开要求于2020年5月27日提交的申请号为202010461246.4、名称为“阵列基板及其制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
对于中大尺寸的自发光型面板，例如在中大尺寸的Micro LED显示面板、中大尺寸的Mini LED背光源或显示面板中，金属引线距离长而导致金属引线上的压降严重，难以保证为各个电流驱动的发光器件提供足够的驱动电流。现有技术中，可以先在衬底基板上形成种子引线，然后采用电镀铜工艺在种子引线上生成铜生长层，如此制备出具有较大厚度的金属引线，降低金属引线上的压降。然而，该方法仅适用于在衬底基板上直接制备厚铜金属引线，在适用性上具有较大的局限性，且难以精确控制所制备的金属引线的形貌及其厚度均一性，不利于产品特性的均一性。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种阵列基板及其制备方法、显示装置，提高阵列基板的部分金属布线层的厚度。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板的一侧形成驱动电路层；
在所述驱动电路层远离所述衬底基板的一侧形成功能器件层；
其中，在所述衬底基板的一侧形成驱动电路层包括：在所述衬底基板的一侧形成至少一层第一引线层；形成任意一层所述第一引线层包括：
在所述衬底基板的一侧形成导电种子层；
在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层，所述可移除的图案限定层设置有引线开口，所述引线开口暴露部分所述导电种子层；
采用电镀工艺或者化学镀工艺，在所述引线开口内形成位于所述导电种子层表面的金属镀层；
移除所述可移除的图案限定层；
去除所述导电种子层未被所述金属镀层覆盖的部分。
在本公开的一种示例性实施例中，在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层包括：
在所述导电种子层远离所述衬底基板的表面形成一层可移除的绝缘材料层；
对所述可移除的绝缘材料层进行图案化操作，以形成所述可移除的图案限定层。
在本公开的一种示例性实施例中，在所述导电种子层远离所述衬底基板的表面形成一层可移除的绝缘材料层包括：
在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层；
对所述可移除的绝缘材料层进行图案化操作包括：
对所述光刻胶材料层进行曝光和显影，以形成所述可移除的图案限定层。
在本公开的一种示例性实施例中，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层包括：
使用可降解光刻胶材料，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层，所述可降解光刻胶材料为在固化后能够溶解于降解液的光刻胶材料；
移除所述可移除的图案限定层包括：
使用所述降解液溶解所述可移除的图案限定层。
在本公开的一种示例性实施例中，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层包括：
使用负性光刻胶材料，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层；
对所述光刻胶材料层进行曝光和显影包括：
对所述光刻胶材料层进行曝光和显影，以形成具有引线开口的可移除的图案限定层，使得所述引线开口靠近所述衬底基板的一端的宽度大于远离所述衬底基板的一端的宽度。
在本公开的一种示例性实施例中，在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层包括：
在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层，所述引线开口的宽度的最小值为第一尺寸值；
采用电镀工艺或者化学镀工艺，在所述引线开口内形成位于所述导电种子层表面的金属镀层包括：
采用电镀工艺，在所述引线开口内形成位于所述导电种子层表面的金属镀层，使得所述金属镀层的厚度为第二尺寸值，所述第二尺寸值不大于所述第一尺寸值的5倍。
在本公开的一种示例性实施例中，在所述衬底基板的一侧形成至少一层第一引线层包括：
在所述衬底基板的一侧形成一层所述第一引线层；
在所述第一引线层远离所述衬底基板的一侧形成第一平坦化层，所述第一平坦化层暴露至少部分所述第一引线层；
在所述第一平坦化层远离所述衬底基板的一侧形成第一转接金属层，所述第一转接金属层连接所述第一引线层；
在所述第一转接金属层远离所述衬底基板的一侧形成第二平坦化层，所述第二平坦化层具有第一连接过孔；所述第一连接过孔暴露部分所述第一转接金属层，且所述第一连接过孔在所述第一引线层上的正投影与所述第一引线层不交叠；
在所述第二平坦化层远离所述衬底基板的表面形成另一层所述第一引线层，另一层所述第一引线层通过所述第一连接过孔与所述第一转接金 属层连接。
根据本公开的第二个方面，提供一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层和功能器件层；
其中，所述驱动电路层包括至少一层第一引线层，任意一层所述第一引线层包括至少一个第一引线；
任意一个所述第一引线包括设于所述衬底基板一侧的种子引线，以及设于所述种子引线远离所述衬底基板表面的生长引线，所述生长引线在所述衬底基板上的正投影与所述种子引线在衬底基板上的正投影重合。
在本公开的一种示例性实施例中，所述第一引线的厚度，不大于所述种子引线的宽度的5倍。
在本公开的一种示例性实施例中，所述第一引线远离所述衬底基板一端的宽度，小于所述第一引线靠近所述衬底基板一端的宽度。
在本公开的一种示例性实施例中，所述驱动电路层包括：
一所述第一引线层，设于所述衬底基板的一侧；
第一平坦化层，设于所述第一引线层远离所述衬底基板的一侧；
第一转接金属层，设于所述第一平坦化层远离所述衬底基板的一侧，且与所述第一引线层连接；
第二平坦化层，设于所述第一转接金属层远离所述衬底基板的一侧，且设置有第一连接过孔；所述第一连接过孔暴露部分所述第一转接金属层，且所述第一连接过孔在所述第一引线层上的正投影与所述第一引线层不交叠；
另一所述第一引线层，设于所述第二平坦化层远离所述衬底基板的表面，且通过所述第一连接过孔与所述第一转接金属层连接。
在本公开的一种示例性实施例中，所述驱动电路层包括：
驱动晶体管，设于所述衬底基板的一侧，所述驱动晶体管包括形成有源极和漏极的源漏金属层；
第三平坦化层，设于所述驱动晶体管远离所述衬底基板的一侧，且设置有暴露至少部分所述源漏金属层的第三连接过孔；
第二转接金属层，设于所述第三平坦化层远离所述衬底基板的一侧，且通过所述第三连接过孔与源漏金属层连接；
第四平坦化层，设于所述第二转接金属层远离所述衬底基板的一侧，且具有第四连接过孔；所述第四连接过孔暴露部分所述第二转接金属层，且所述第四连接过孔在所述衬底基板上的正投影与所述第三连接过孔在所述衬底基板上的正投影不交叠；
一所述第一引线层，设于所述第四平坦化层远离所述衬底基板的表面，且通过所述第四连接过孔与所述第二转接金属层连接。
在本公开的一种示例性实施例中，所述驱动电路层包括：
驱动晶体管，设于所述衬底基板的一侧，所述驱动晶体管包括形成有源极和漏极的源漏金属层；
第三平坦化层，设于所述源漏金属层远离所述衬底基板的一侧，且设置有暴露至少部分所述源漏金属层的第三连接过孔；所述第三连接过孔在所述衬底基板上的正投影与所述第二连接过孔在所述衬底基板上的正投影不交叠；
一所述第一引线层，设于所述第三平坦化层远离所述衬底基板的表面，且通过所述第三连接过孔与所述源漏金属层连接。
在本公开的一种示例性实施例中，所述驱动电路层包括驱动晶体管，所述驱动晶体管包括：
半导体层，设于所述衬底基板的一侧；所述半导体层包括源极接触区和漏极接触区；
层间电介质层，设于所述半导体远离所述衬底基板的一侧；
一所述第一引线层，设于所述层间电介质层远离所述衬底基板的一侧，形成有源极和漏极；所述源极与所述源极接触区连接，所述漏极与所述漏极接触区连接。
根据本公开的第三个方面，提供一种显示装置，包括上述的阵列基板。
根据本公开提供的阵列基板及其制备方法、显示装置，可以先形成整面的导电种子层和覆盖导电种子层的可移除的图案限定层，保证引线开口内不会出现导电种子层缺失的情形。然后，采用电镀工艺或者化学镀工艺在引线开口内生长金属，制备出位于引线开口内的前体生长引线以形成金属镀层。在电镀或者化学镀的过程中，可移除的图案限定层使得前体生长引线具有良好的侧面形貌；导电种子层可以提供完整的电镀基底或者化学 镀基底，使得前体生长引线表面具有更好地均一性。然后，移除可移除的图案限定层并通过刻蚀对导电种子层进行图案化，形成被前体生长引线覆盖的种子引线。前体生长引线在刻蚀过程中也可以被部分刻蚀并形成生长引线，利用刻蚀过程中不同位置的刻蚀速度差异，可以使得生长引线远离衬底基板的表面的均一性进一步提高。如此，第一引线层包括有第一引线，第一引线包括种子引线以及层叠于种子引线表面的生长引线，该第一引线的表面均一性更好，能够提高阵列基板性能。
不仅如此，当采用电镀工艺形成金属镀层时，整面导电种子层进行电镀的工艺，可以使得该电镀工艺适用于阵列基板的任意金属布线层，能够提高阵列基板的任意金属布线层的厚度，并提高所形成的第一引线层的厚度均一性，克服了电镀工艺在现有技术中的应用局限。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开一种实施方式的阵列基板的结构示意图。
图2是本公开一种实施方式的阵列基板的结构示意图。
图3是本公开一种实施方式的形成任意一层第一引线层的流程示意图。
图4是本公开一种实施方式的提供衬底基板的结构示意图。
图5是本公开一种实施方式的在衬底基板的一侧形成导电种子层的结构示意图。
图6是本公开一种实施方式的在导电种子层远离衬底基板的表面形成可移除的图案限定层的结构示意图。
图7是本公开一种实施方式的采用电镀工艺在引线开口内形成位于导电种子层表面的金属镀层的结构示意图。
图8是本公开一种实施方式的移除可移除的图案限定层的结构示意图。
图9是本公开一种实施方式的刻蚀以形成第一引线层的结构示意图。
图10是本公开一种实施方式的在第一引线层远离衬底基板的表面形成钝化层的结构示意图。
图11是本公开一种实施方式的形成第一引线层组的流程示意图。
图12是本公开一种实施方式的在前一第一引线层远离衬底基板的一侧形成第一平坦化层的结构示意图。
图13是本公开一种实施方式的在第一平坦化层远离衬底基板的一侧形成第一转接金属层的结构示意图。
图14是本公开一种实施方式的在第一转接金属层远离衬底基板的一侧形成第二平坦化层的结构示意图。
图15是本公开一种实施方式的在第二平坦化层远离衬底基板的表面形成后一第一引线层的结构示意图。
图16是本公开一种实施方式的在驱动电路层远离衬底基板的一侧形成像素定义层的结构示意图。
图17是本公开一种实施方式的在驱动电路层远离衬底基板的一侧形成功能器件层的结构示意图。
图18是本公开一种实施方式的具有多层依次层叠的第一引线层的驱动电路层的结构示意图。
图19是本公开一种实施方式的形成与驱动晶体管电连接的第一引线层的流程示意图。
图20是本公开一种实施方式的阵列基板的结构示意图。
图21是本公开一种实施方式的形成与驱动晶体管电连接的第一引线层的流程示意图。
图22是本公开一种实施方式的阵列基板的结构示意图。
图23是本公开一种实施方式的形成与驱动晶体管电连接的第一引线层的流程示意图。
图24是本公开一种实施方式的阵列基板的结构示意图。
图25是本公开一种实施方式的阵列基板的结构示意图。
图26是本公开一种实施方式的阵列基板的俯视结构示意图。
图27是本公开一种实施方式的阵列基板的俯视结构示意图。
图中主要元件附图标记说明如下：
100、衬底基板；110、对位标记层；111、对位图案；120、缓冲层；200、驱动电路层；201、第一引线层；201a、前一第一引线层；201b、后一第一引线层；2011、第一引线；202、第二引线层；210、驱动晶体管； 220、层间电介质层；230、源漏金属层；241、第一平坦化层；242、第二平坦化层；243、第三平坦化层；244、第四平坦化层；251、第一连接过孔；252、第二连接过孔；253、第三连接过孔；254、第四连接过孔；261、第一转接金属层；262、第二转接金属层；271、像素定义层；272、导电胶；300、功能器件层；310、功能器件；311、LED；410、导电种子层；411、种子引线；420、可移除的图案限定层；421、引线开口；430、金属镀层；431、前体生长引线；432、生长引线；440、钝化层；510、扫描引线；520、数据引线；530、公共电压引线；540、绑定引线；610、背侧引线层；620、绝缘层；630、绑定焊盘层；710、第一金属布线层；720、第二金属布线层；711、第一金属引线；721、第二金属引线。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成 部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本公开中，引线的宽度，指的是在平行于衬底基板的平面上，引线在垂直于其延伸方向的尺寸。一个膜层或者引线的厚度，指的是该膜层或者引线，在垂直于衬底基板方向上的尺寸。
在相关技术中，可以先在衬底基板上形成种子引线，然后采用电镀铜工艺在种子引线上生成铜生长层，形成厚的电镀金属引线。然而，在基于种子引线进行电镀铜时，铜生长层将会在种子引线的表面向外生长，其形貌和宽度不易控制。在一些相关技术中，还可以在种子引线之间设置挡墙结构，然后再进行电镀铜工艺，以约束铜生长层的宽度。然而，由于制备挡墙结构时存在对准误差，难以使得挡墙精准的嵌于种子引线之间，这制约了铜生长层的表面均一性的提高。
本公开提供一种阵列基板的制备方法，如图1和图2所示，该阵列基板包括依次层叠设置的衬底基板100、驱动电路层200和功能器件层300。该阵列基板的制备方法包括：
步骤S110，如图4所示，提供一衬底基板100；
步骤S120，在衬底基板100的一侧形成驱动电路层200；
步骤S130，在驱动电路层200远离衬底基板100的一侧形成功能器件层300；
其中，在衬底基板100的一侧形成驱动电路层200包括：在衬底基板100的一侧形成至少一层第一引线层201；如图3所示，形成任意一层第一引线层201包括：
步骤S210，如图5所示，在衬底基板100的一侧形成导电种子层410；
步骤S220，如图6所示，在导电种子层410远离衬底基板100的表面形成可移除的图案限定层420，可移除的图案限定层420设置有引线开口421，引线开口421暴露部分导电种子层410；
步骤S230，如图7所示，采用电镀工艺或者化学镀工艺在引线开口421内形成位于导电种子层410表面的金属镀层430；
步骤S240，如图8所示，移除可移除的图案限定层420；
步骤S250，如图9所示，去除导电种子层410未被金属镀层430覆盖的部分，以形成第一引线层201。
根据本公开提供的阵列基板的制备方法，可以先形成整面的导电种子层410和覆盖导电种子层410的可移除的图案限定层420，由于导电种子层410未经图案化操作，因此可以保证引线开口421内不会出现导电种子层410缺失的情形，克服引线开口421内部分区域可能缺失电镀基底或者缺失化学镀基底的问题。然后，采用电镀工艺或者化学镀工艺在引线开口421内生长金属，制备出位于引线开口421内的前体生长引线431以形成金属镀层430。在电镀或者化学镀过程中，可移除的图案限定层420可以限定前体生长引线431的侧面，使得前体生长引线431具有良好的侧面形貌；引线开口421内的导电种子层410可以提供完整的电镀基底或者化学镀基底，使得前体生长引线431远离衬底基板100的表面具有更好地均一性。然后，移除可移除的图案限定层420并通过刻蚀对导电种子层410进行图案化，形成被前体生长引线431覆盖的种子引线411。前体生长引线431在刻蚀过程中也可以被部分刻蚀并形成生长引线432，利用刻蚀过程中不同位置的刻蚀速度差异，可以使得生长引线432远离衬底基板100的表面的均一性进一步提高。如此，第一引线层201包括有第一引线2011，第一引线2011包括种子引线411以及层叠于种子引线411表面的生长引线432，该第一引线2011的表面均一性更好，能够提高阵列基板性能。不仅如此，利用本公开提供的阵列基板的制备方法，克服了现有工艺中对电镀金属引线的膜层位置限制，可以根据阵列基板的性能要求在所需的位置制备第一引线层201，进而保证功能器件层300的功能器件310获得足够的驱动电流。
下面，结合附图对本公开提供的阵列基板的制备方法的步骤、原理和效果做进一步地解释和说明。
在步骤S110中，可以提供阵列基板的衬底基板100。衬底基板100可以为无机材料的衬底基板100，也可以为有机材料的衬底基板100。举例而言，在本公开的一种实施方式中，衬底基板100的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板100的 材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板100也可以为柔性衬底基板100，例如衬底基板100的材料可以为聚酰亚胺(polyimide，PI)。衬底基板100还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板100可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
在步骤S120中，可以在衬底基板100的一侧形成驱动电路层200，驱动电路层200用于驱动功能器件层300中的各个功能器件310。驱动电路层200中包括由至少一个金属布线层组成的驱动电路，任意一个金属布线层包括至少一个金属引线。其中，至少一层金属布线层为本公开的第一引线层201。
可以理解的是，如图1和图2所示，驱动电路层200中的各个金属布线层，可以全部为第一引线层201，也可以为部分第一引线层201。举例而言，如图2所示，驱动电路层200中，部分金属布线层可以为第一引线层201，另外部分金属布线层可以为第二引线层202。其中，第二引线层202可以通过沉积工艺形成金属膜层、对金属膜层进行图案化操作进行制备；换言之，第二引线层202可以不采用电镀工艺或者化学镀工艺，其所包含的各个第二引线可以具有较低的厚度。在一些实施方式中，第二引线层202的材料可以与导电种子层410相同，也可以不相同。作为示例，驱动电路层200中的如下金属布线层中一种或者多种可以为第二引线层202：栅极引线层、源漏引线层、金属转接层、遮光层、电极层或者绑定层等；当然的，如上任意一个膜层也可以借助电镀工艺或者化学镀工艺，制备成第一引线层201。当驱动电路层200中的某一层金属布线层为第一引线层201时，可以根据步骤S210～步骤S250所示的制备方法，制备出该第一引线层201，使得任意一个第一引线2011可以包括种子引线411以及层叠于种子引线411远离衬底基板100表面的生长引线432。
在本公开的一些实施方式中，驱动电路层200可以包括无源驱动电路，例如驱动电路层200中包括由至少一个金属布线层组成的驱动电路，任意一个金属布线层包括至少一个金属引线。
作为示例，本公开提供一种具有无源驱动电路的阵列基板，以解释和说明本公开的阵列基板的结构和原理。图26仅展示了该阵列基板的第一金属布线层710、第二金属布线层720和功能器件层。在该示例中，阵列基板包括依次层叠的衬底基板100、驱动电路层200和功能器件层300。其中，驱动电路层200包括层叠于衬底基板100的第一金属布线层710、绝缘层和第二金属布线层720；第一金属布线层710包括有多个第一金属引线711；绝缘层设置有暴露部分第一金属引线711层的连接过孔；第二金属引线721层包括有多个第二金属引线721，第二金属引线721可以作为驱动电路的电极层，用于与功能器件310绑定。其中，部分第二金属引线721通过连接过孔与第一金属引线711电连接。功能器件层300包括有阵列分布的功能器件310，该功能器件310可以为LED 311。其中，LED 311的一端通过锡膏连接一个第二金属引线721，另一端通过锡膏连接另一第二金属引线721。
在该示例中，第一金属布线层710可以采用本公开实施方式的第一引线层201结构，以保证能够向第二金属布线层720传输足够且的电流，并避免在驱动过程中产生明显的压降。第二金属布线层720可以采用本公开的第一引线层201结构，也可以采用本公开的第二引线层202结构，对此不做限定。
作为进一步地示例性介绍，该阵列基板可以包括多个发光区域，任意一个发光区域内可以设置四条依次首尾相邻的第二金属引线721，其中，一组相对设置的两个第二金属引线721分别通过连接过孔连接两个不同的第一金属引线711，另外两个第二金属引线721不与第一金属引线711电连接。两个第二金属引线721的相邻位置设置有一个LED 311，LED 311的两端分别连接两个第二金属引线721。如此，当向两条第一金属引线711分别加载公共电压和驱动电压时，可以驱动四个LED 311发光。
可以理解的是，该示例性地阵列基板，既可以作为LCD显示装置的背光源，也可以作为无源驱动的显示面板，本公开对此不做特殊的限定。 其中，LED 311可以为LED灯珠，也可以为Micro LED或者Mini LED。
在本公开的另一些实施方式中，驱动电路层200可以包括有源驱动电路，例如阵列基板的驱动电路层200还可以设置有驱动晶体管等电子元件，各个电子元件通过至少一个金属布线层与功能器件层300电连接，任意一个金属布线层包括至少一个金属引线。其中，至少一层金属布线层为本公开的第一引线层201。当然的，根据阵列基板的需求，驱动电路层200还可以设置有其他电子元件，例如还可以设置有存储电容和驱动晶体管以外的其他所需的晶体管。
可选地，晶体管可以为薄膜晶体管(TFT)，也可以为金属氧化物半导体场效应晶体管(MOS)。晶体管为薄膜晶体管为例，在膜层结构上，薄膜晶体管可以为顶栅型薄膜晶体管或者底栅型薄膜晶体管，本公开对此不做限制。在薄膜晶体管材料上，薄膜晶体管可以为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管或者氧化物薄膜晶体管，本公开对此不做限制。在薄膜晶体管的导通条件上，薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管，本公开对此也不做限制。驱动电路层200中，各个薄膜晶体管和存储电容可以由有源层、栅极绝缘层、栅极层、层间电介质层、源漏金属层等膜层形成。其中，薄膜晶体管可以包括位于有源层的半导体层、栅极绝缘层、位于栅极层的栅极、层间电介质层、位于源漏金属层的源漏电极层，源漏电极层由薄膜晶体管的源极和漏极组成。半导体层包括沟道区以及沟道区两侧的源极接触区和漏极接触区，源极穿过层间电介质层以与源极接触区连接，漏极穿过层间电介质层以与漏极接触区连接，栅极和沟道区被栅极绝缘层隔离。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。举例而言，驱动电路层200可以包括依次层叠设置的有源层、栅极绝缘层、栅极层、层间电介质层和源漏金属层，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。再举例而言，驱动电路层200可以包括依次层叠设置的栅极层、栅极绝缘层、有源层、层间电介质层和源漏金属层，如此所形成的薄膜晶体管为底栅型薄膜晶体管。驱动电路层200还可以采用双栅极结构，即栅极层可以包括第一栅极层和第二栅极层，栅极绝缘层可以包括用于隔离有源层和第一栅极层的第一栅极绝缘层，以及包括用于隔离第一栅极层和第二栅极层的第二栅极绝缘层。举例而言，驱动电路层 200可以包括依次层叠设置于衬底基板100一侧的有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层、源漏金属层。
作为示例，如图27所示，本公开提供一种具有有源驱动电路的阵列基板，以解释和说明本公开的阵列基板的结构和原理。图27仅示出了阵列基板的驱动晶体管、两层金属布线层和作为功能器件的LED。在该示例中，驱动电路为半有源驱动电路，其包括有驱动晶体管210、扫描引线510、数据引线520、公共电压引线530和绑定引线540，扫描引线510用于控制驱动晶体管210导通或者截止，数据引线520连接驱动晶体管210的源极，绑定引线连接驱动晶体管210的漏极，作为功能器件310的LED的两端分别连接绑定引线540和公共电压引线530。当扫描引线510上加载有效扫描信号使得驱动晶体管210导通时，驱动电流可以通过数据引线520、驱动晶体管210、绑定引线和公共电压引线530而流过LED，使得LED发光。在该示例中，扫描引线510可以属于第二引线层202，各个扫描引线510无需采用电镀工艺或者化学镀工艺制备。数据引线520、公共电压引线530和绑定引线540属于同一第一引线层201，可以采用电镀工艺或者化学镀工艺以增加各个引线的厚度，减少各个引线的阻抗，以减少驱动电路在数据引线520和公共电压引线530上的压降并保证流经LED的电流的准确性。
在制备驱动电路层200时，可以根据步骤S210～步骤S250所示的制备方法，制备出任意第一引线层201。
在步骤S210中，如图5所示，可以在衬底基板100的一侧沉积金属材料以形成导电种子层410。举例而言，可以采用磁控溅射的方法在衬底基板100的一侧沉积金属材料，以制备出作为电镀基底或者化学镀基底的导电种子层410。可以理解的是，在本公开中，如果步骤S230采用电镀工艺制备金属镀层430，则步骤S210中所制备的导电种子层410可以作为电镀基底。在本公开中，如果步骤S230采用化学镀工艺制备金属镀层430，则步骤S210中所制备的导电种子层410可以作为化学镀基底。
可以理解的是，在沉积金属材料前，根据已经执行的工艺步骤可以获得一中间基板。根据已经执行的工艺步骤的不同，该中间基板可以具有不 同的结构，例如可以为衬底基板100本身，或者可以包括衬底基板100以及依次层叠于衬底基板100之上的各个已经形成的膜层。在步骤S210中，可以在中间基板的待形成导电种子层410的表面沉积金属材料。举例而言，在本公开的一种实施方式中，若需要在衬底基板100的表面形成第一引线层201，则该衬底基板100作为该步骤的中间基板，金属材料沉积于衬底基板100的表面。再举例而言，在本公开的另一种实施方式中，若在待形成的第一引线层201与衬底基板100之间具有膜层结构，则在制备该第一引线2011时，该衬底基板100和膜层结构整体作为该步骤的中间基板，且该膜层结构远离衬底基板100的表面为待形成导电种子层410的表面。
可选地，导电种子层410的厚度可以不大于1微米，以避免过厚的导电种子层410对中间基板产生过大的应力，提高阵列基板的稳定性和良率。优选地，导电种子层410的厚度可以不大于0.5微米，以缩短在步骤S250中对导电种子层410的刻蚀时间，并提高刻蚀后所形成的种子引线411的侧面形貌。
导电种子层410可以为一种金属材料，也可以为多种金属材料形成的合金，还可以为层叠的多种金属层，本公开不做特殊的限制，以能够满足电镀工艺或者化学镀工艺的需求以及阵列基板的性能要求为准。
可选地，导电种子层410可以包括保护金属层以及位于保护金属层远离衬底基板100表面的目标金属层。目标金属层可以作为电镀基底或者化学镀基底以在其远离衬底基板100的表面形成金属镀层430。举例而言，当电镀工艺或者化学镀工艺为镀铜工艺时，目标金属层的材料可以为铜。
保护金属层用于保护目标金属层不受侵蚀，或者保护中间基板不受目标金属层的金属材料的侵蚀。保护金属层的材料可以为金属单质或者合金，例如可以为钼、钛、钼钛镍合金等。
在本公开的一种实施方式中，导电种子层410包括依次层叠于衬底基板100一侧的保护金属层和目标金属层。其中，保护金属层的材料可以为MTD合金(钼钛镍合金)，厚度为250～350埃；目标金属层的材料为铜，厚度为2500～3500埃。
可以理解的是，在制备不同第一引线层201时，步骤S210中所沉积的金属材料的种类、厚度等可以相同或者不同，使得不同第一引线层201 的种子引线411的结构和材料相同或者不同。
在步骤S220中，如图6所示，可以在导电种子层410远离衬底基板100的表面形成可移除的图案限定层420，该可移除的图案限定层420可以设置有引线开口421，该引线开口421可以包括部分导电种子层410。如此，在进行电镀工艺或者化学镀工艺时，该引线开口421所暴露的导电种子层410可以作为电镀基底化学镀基底而生长电镀金属或者化学镀金属，而被可移除的图案限定层420所覆盖的导电种子层410上不能生长电镀金属或者化学镀金属。因此，引线开口421在衬底基板100上的正投影，与步骤S230中所形成的金属镀层430的正投影可以重合。
可选地，可以通过步骤S221和步骤S222制备可移除的图案限定层420：
步骤S221，在导电种子层410远离衬底基板100的表面形成一层可移除的绝缘材料层；
步骤S222，对可移除的绝缘材料层进行图案化操作，以形成可移除的图案限定层420。
优选地，在步骤S221中，可移除的绝缘材料层可以为光刻胶材料层，即可以在导电种子层410远离衬底基板100的表面形成一层光刻胶材料层。如此，在步骤S222中，可以通过曝光和显影实现对光刻胶材料层的图案化，形成可移除的图案限定层420。
在本公开的一种实施方式中，在步骤S221中，可以使用可降解光刻胶材料，在导电种子层410远离衬底基板100的表面形成一层光刻胶材料层。其中，可降解光刻胶材料为在固化后能够溶解于降解液的光刻胶材料。
可选的，可降解光刻胶材料具有可分解的交联基团或者在固化时形成可分解的交联基团。在可降解光刻胶材料固化之后，当需要移除固化的可降解光刻胶材料时，可以使用降解液处理固化的可降解光刻胶材料，固化的可降解光刻胶材料中的可分解的交联基团能够与降解液反应而断裂，使得固化的可降解光刻胶材料被分解为能够溶解于降解液的小分子片段。如此，可以实现温和且彻底地去除固化的可降解光刻胶材料。
在步骤S221中使用可降解光刻胶材料制备光刻胶材料层，则在步骤S222中制备的可移除的图案限定层420的材料为固化的可降解光刻胶材 料；在步骤S240中，可以使用降解液溶解可移除的图案限定层420，实现移除可移除的图案限定层420，既保证彻底移除可移除的图案限定层420，又可以避免在移除可移除的图案限定层420时损伤金属镀层430。
在本公开的另一种实施方式中，在步骤S221中，可以使用负性光刻胶材料，在导电种子层410远离衬底基板100的表面形成一层光刻胶材料层。如此，在步骤S222中，对光刻胶材料层进行曝光和显影，以形成具有引线开口421的可移除的图案限定层420，使得引线开口421靠近衬底基板100的一端的宽度大于远离衬底基板100的一端的宽度。换言之，可以借助负性光刻胶材料的材料特性，使得引线开口421的宽度沿远离衬底基板100的方向减小，这不仅便于移除可移除的图案限定层420，而且可以使得电镀或者化学镀形成的生长引线432的宽度沿远离衬底基板100的方向减小，进而提高生长引线432的强度，减小生长引线432坍塌的风险。如此，在所制备的第一引线2011中，第一引线2011远离衬底基板100一端的宽度，小于第一引线2011靠近衬底基板100一端的宽度。在进一步地实施方式中，如图10所示，还可以在第一引线2011远离衬底基板100的表面和第一引线2011的侧面沉积钝化材料，例如沉积氧化硅、氮化硅、氮氧化硅等材料，以形成保护第一引线2011的钝化层440。由于电镀或者化学镀形成的生长引线432的宽度沿远离衬底基板100的方向减小，因此可以保证钝化层的连续性。
当然的，在本公开的其他实施方式中，还可以采用其他可移除的绝缘材料制备可移除的图案限定层420，并在步骤S240中采用相应的工艺去除该可移除的图案限定层420，例如采用氧化硅制备可移除的图案限定层420并通过刻蚀工艺去除该可移除的图案限定层420，或者采用光敏树脂制备可移除的图案限定层420并通过干法剥离工艺去除该可移除的图案限定层420，本公开对此不做进一步的详述。
在步骤S230中，如图7所示，可以采用电镀工艺或者化学镀工艺在引线开口421内形成位于导电种子层410表面的金属镀层430。在电镀或者化学镀过程中，从作为电镀基底化学镀基底的导电种子层410的表面开始生长电镀金属或者化学镀金属，在引线开口421的约束下，电镀金属仅生长于引线开口421内，并最终在电镀后形成位于引线开口421内的前体 生长引线431，各个前体生长引线431形成金属镀层430。可以理解的是，当采用电镀工艺形成金属镀层430时，导电种子层410表面的生长的金属为电镀金属，所形成的金属镀层430可以作为本公开的电镀金属层。当采用化学镀工艺形成金属镀层430时，导电种子层410表面的生长的金属为化学镀金属，所形成的金属镀层430可以作为本公开的化学镀金属层。
在本公开的一种实施方式中，采用电镀工艺在引线开口421内形成位于导电种子层410表面的金属镀层430。由于导电种子层410为整面金属，因此可以方便地向整个导电种子层410加载电镀电流且使得导电种子层410具有很小的压降，如此可以提高各个引线开口421位置处的电镀速率的均一性，进而提高前体生长引线431远离衬底基板100的表面的均一性。本公开的制备方法无需设计额外的连接引线以保证向图案化的导电种子层410进行供电，由此不仅可以简化各个第一引线层201的设计过程和制备过程，而且可以使得本公开的制备第一引线层201的方法可以适用于任意膜层位置，克服了现有技术中只能在靠近基板的第一层进行电镀铜的缺陷。
而在现有技术中，需要先对导电种子层进行图案化操作再进行电镀，这需要设计额外的导电引线将各个种子引线相互电连接，以保证能够在电镀过程中向各个种子引线加载电流。由于导电种子层被图案化为种子引线，因此各个种子引线上的电镀电流密度难以保持均一性，这不利于电镀金属在不同种子引线上均匀生长。另外，电镀过程中电镀金属可能会在种子引线的侧面生长，会使得金属镀层完全包覆种子引线，降低种子引线对金属镀层的图案限定效果。更重要的是，由于需要设计额外的导电引线以连接各个种子引线，使得该方法仅适用于靠近衬底基板的金属布线层，而不能应用于任意金属布线层。
可选地，可以通过控制电镀工艺的参数或者化学镀工艺的参数，例如电镀电流、电镀时间等参数，进而控制各个前体生长引线431的厚度，即控制金属镀层430的厚度。可选地，在步骤S230中，可以使得金属镀层430的厚度不大于引线开口421的宽度的五倍。换言之，引线开口421的宽度的最小值为第一尺寸值，即前体生长引线431靠近衬底基板100一侧的宽度的最小值为第一尺寸值；金属镀层430的厚度为第二尺寸值，即前 体生长引线431的厚度为第二尺寸值；第二尺寸值不大于第一尺寸值的5倍。如此，所制备的前体生长引线431的高宽比不大于5，可以提高前体生长引线431与导电种子层410之间的结合强度，并避免前体生长引线431发生坍塌，提高前体生长引线431的稳定性。如此，在步骤S250之后所形成的第一引线2011中，第一引线2011的厚度不大于种子引线411的宽度的5倍。
可选地，金属镀层430的厚度为1.5～20微米，例如可以为2微米、5微米、10微米、20微米等。优选地，金属镀层430的厚度为5～10微米。
可选地，金属镀层430的厚度大于导电种子层410的厚度，以保证第一引线2011的厚度大于导电种子层410的厚度，达成提高第一引线2011的厚度的目的。
可选地，可以通过电镀铜工艺或者化学镀铜工艺，使得金属镀层430的材料为铜。如此，可以降低生长引线432的电阻，进而降低第一引线2011的电阻。进一步地，导电种子层410远离衬底基板100的表面，至少包括一层铜金属层，以保证电镀工艺或者化学镀铜工艺中能够在导电种子层410的表面顺利生长铜金属镀层430。
在步骤S250中，如图9所示，可以通过刻蚀以去除导电种子层410未被金属镀层430覆盖的部分。可选地，可以根据导电种子层410的厚度和材料，选择适宜的刻蚀工艺，包括选择合适的刻蚀液、刻蚀时间等，以能够将导电种子层410暴露的部分刻蚀干净为准。
在对导电种子层410进行刻蚀时，可以无需对金属镀层430进行专门的保护。如此，金属镀层430的各个前体生长引线431的表面在刻蚀工艺中被部分刻蚀，剩余部分形成第一引线2011的生长引线432。在一些实施方式中，金属镀层430和导电种子层410可以以接近的速度被刻蚀，则使得所形成的第一引线2011的厚度接近于金属镀层430的厚度。举例而言，若金属镀层430的厚度为1.5～20微米，则所形成的第一引线2011的厚度为1.5～20微米。
在一些实施方式中，前体生长引线431远离衬底基板100的表面具有略微粗糙的表面，该表面的凸出部分更容易被刻蚀液刻蚀，进而使得前体生长引线431远离衬底基板100的表面的平整度在刻蚀过程中不断提高。 不仅如此，由于无需对金属镀层430进行保护，所形成的第一引线2011中，生长引线432在衬底基板100上的正投影与种子引线411在衬底基板100上的正投影重合，这保证了第一引线2011侧面的平整，避免了种子引线411凸出于生长引线432的问题。因此，第一引线2011的表面和侧面的平整度更高，能够进一步改善第一引线2011的形貌并提高阵列基板的性能。
如此，利用本公开提供的阵列基板的制备方法，如图1、图2和图9所示，所制备的阵列基板包括依次层叠设置的衬底基板100、驱动电路层200和功能器件层300；其中，驱动电路层200包括至少一层第一引线层201，任意一层第一引线层201包括至少一个第一引线2011；任意一个第一引线2011包括设于衬底基板100一侧的种子引线411，以及设于种子引线411远离衬底基板100表面的生长引线432，生长引线432在衬底基板100上的正投影与种子引线411在衬底基板100上的正投影重合。
在本公开的一种实施方式中，如图4所示，本公开提供的阵列基板的制备方法还可以包括：在衬底基板100的一侧形成对位标记层110，对位标记层110具有用于对位的对位图案111。然后在对位标记层110远离衬底基板100的一侧形成驱动电路层200。如此，可以避免采用第一引线层201的图案作为对位图案111，以规避第一引线层201太厚而边沿不太清晰的问题。
可选地，对位标记层110的材料可以为金属、金属氧化物、硅或者其他材料，例如对位标记层110的材料可以为钼、钛、铜、铝、钨等金属，或者可以为ITO(氧化铟锌)等金属氧化物，还可以为非晶硅、多晶硅等材料。在本公开的一种实施方式中，对位标记层110的材料为钼。
可选地，在对位标记层110和驱动电路层200之间还可以设置有缓冲层120，缓冲层120采用绝缘材料以隔离对位标记层110和驱动电路层200。
可以理解的是，当阵列基板的其他膜层的结构可以作为对准图案时，则可以无需设置对位标记层110。举例而言，若制备的驱动电路层200包含有有源驱动电路，则可以利用有源驱动电路的有源层图案作为对位图案111。
在一些实施方式中，如图17所示，在制备驱动电路层200时，还可 以制备出通过转接金属层相连的层叠的两层第一引线层201。如图11所示，在衬底基板100的一侧形成至少一层第一引线层201可以包括：
步骤S310，如图12所示，在衬底基板100的一侧形成一层第一引线层201；
步骤S320，如图12所示，在第一引线层201远离衬底基板100的一侧形成第一平坦化层241，第一平坦化层241暴露至少部分第一引线层201；
步骤S330，如图13所示，在第一平坦化层241远离衬底基板100的一侧形成第一转接金属层261，第一转接金属层261连接第一引线层201；
步骤S340，如图14所示，在第一转接金属层261远离衬底基板100的一侧形成第二平坦化层242，第二平坦化层242具有第一连接过孔251；第一连接过孔251暴露部分第一转接金属层261，且第一连接过孔251在第一引线层201上的正投影与第一引线层201不交叠；
步骤S350，如图15所示，在第二平坦化层242远离衬底基板100的表面形成另一层第一引线层201，另一层第一引线层201通过第一连接过孔251与第一转接金属层261连接。
如此，如图17所示，根据该制备方法所制备的阵列基板中，驱动电路层200可以包括依次层叠的前一第一引线层201a、第一平坦化层241、第一转接金属层261、第二平坦化层242和后一第一引线层201b，前一第一引线层201a和后一第一引线层201b形成一个通过第一转接金属层261连接的第一引线层组。其中，前一第一引线层201a设于衬底基板100的一侧；第一平坦化层241设于前一第一引线层201a远离衬底基板100的一侧，且暴露至少部分前一第一引线层201a；第一转接金属层261设于第一平坦化层241远离衬底基板100的一侧，且与前一第一引线层201a连接；第二平坦化层242设于第一转接金属层261远离衬底基板100的一侧，且设置有第一连接过孔251；第一连接过孔251暴露部分第一转接金属层261，且第一连接过孔251在前一第一引线层201a上的正投影与前一第一引线层201a不交叠；后一第一引线层201b设于第二平坦化层242远离衬底基板100的表面，且通过第一连接过孔251与第一转接金属层261连接。
在步骤S310中，可以通过步骤S210～步骤S250在衬底基板100的一侧形成前一第一引线层201a。
在本公开的一种实施方式中，在步骤S320之前，还可以在前一第一引线层201a远离衬底基板100的表面形成第一钝化层，第一钝化层用于保护第一引线2011不被侵蚀。其中，第一钝化层暴露至少部分前一第一引线层201a，以使得前一第一引线层201a能够与第一转接金属层261电连接。
在步骤S320中，如图12所示，可以在前一第一引线层201a远离衬底基板100的一侧形成第一平坦化层241，第一平坦化层241可以填充满各个第一引线2011之间的间隙以为第一转接金属层261提供平坦化表面。第一平坦化层241的材料可以为无机材料，例如可以为氧化硅、氮化硅等材料，也可以为有机材料，例如可以为环氧树脂、聚酰亚胺等树脂材料。在本公开的一种实施方式中，第一平坦化层241的材料为树脂材料。
步骤S330，如图13所示，可以在第一平坦化层241远离衬底基板100的一侧形成第一转接金属层261，第一转接金属层261用于连接前一第一引线层201a和后一第一引线层201b。
可选地，可以通过磁控溅射等沉积方法形成一转接金属材料层，然后对转接金属材料层进行图案化操作以形成第一转接金属。第一转接金属层可以为一层导电材料，也可以为多层导电材料的层叠。在本公开的一种实施方式中，第一转接金属层261可以包括依次层叠的第一导电材料层、第二导电材料层和第一导电材料层，即呈现三明治结构。其中，第一导电材料层可以选用耐腐蚀的金属或者合金，例如可以选用钼或者钛；第二导电材料层可以选用高导电率的金属或者合金，例如可以选用铜、铝、银等。举例而言，第一转接金属层261可以包括依次层叠的钛金属层、铝金属层和钛金属层，其中，钛金属层的厚度可以为400～600埃，铝金属层的厚度可以为3500～5500埃。在本公开的另一种实施方式中，第一转接金属层261的材料可以与导电种子层410的材料相同。举例而言，第一转接金属层261包括依次层叠的MTD合金层和铜层，MTD合金层的厚度为250～350埃，铜层的厚度为2500～3500埃。
在本公开的一种实施方式中，如果第一转接金属远离衬底基板100的表面为铜或者铝等易被侵蚀的金属材料，在步骤S340之前，还可以在第一转接金属层261远离衬底基板100的表面形成第二钝化层，第二钝化层 用于保护第一转接金属层261不被侵蚀。其中，第二钝化层暴露至少部分第一转接金属层261，以使得后一第一引线层201b能够与第一转接金属层261电连接。
在步骤S340中，如图14所示，可以在第一转接金属层261远离衬底基板100的一侧形成第二平坦化层242。可选的，第二平坦化层242的材料和制备方法可以与第一平坦化层241相同，也可以不相同，本公开对此不做特殊的限制。
其中，第二平坦化层242具有第一连接过孔251；第一连接过孔251暴露部分第一转接金属层261，且第一连接过孔251在前一第一引线层201a上的正投影与前一第一引线层201a不交叠。如此，第一转接金属层261至少包括互不交叠的第一连接区域和第二连接区域，其中，第一连接区域与前一第一引线层201a电连接，第二连接区域与后一第一引线层201b电连接。这种设置方法可以避免前一第一引线层201a的不平整传导至后一第一引线层201b，可以使得后一第一引线层201b能够具有良好的形貌而不会在前一第一引线层201a的影响下发生形貌的恶化。尤其是，这样还可以避免在同一位置连续形成多层较厚的金属层，提高第一引线层201中各个第一引线2011的稳定性并改善阵列基板的应力。
在步骤S350中，如图15所示，可以通过步骤S210～步骤S250在衬底基板100的一侧形成后一第一引线层201b。在本公开的一种实施方式中，还可以在后一第一引线层201b远离衬底基板100的表面形成第三钝化层，第三钝化层用于保护后一第一引线层201b不被侵蚀。其中，第三钝化层暴露至少部分后一第一引线层201b，以使得后一第一引线层201b能够与阵列基板的其他结构电连接。
可以理解的是，按照本公开提供的阵列基板的制备方法，在一些实施方式中，如图18所示，所形成的阵列基板可以具有多个第一引线层201，例如可以具有三个、四个或者五个第一引线层201。相邻两个第一引线层201之间可以形成一个第一引线层组，该第一引线层组中靠近衬底基板100的第一引线层201可以为前一第一引线层201a，该第一引线层组中远离衬底基板100的第一引线层201可以为后一第一引线层201b，前一第一引线层201a和后一第一引线层201b之间可以通过夹设于两个第一引线层201 之间的第一转接金属层261电连接。在本公开的一种实施方式中，当根据阵列基板的性能要求而需要使得一导电引线层具有很厚的厚度时，为了避免一次电镀或者化学镀形成太厚的生长引线432而导致生长引线432容易坍塌的问题，可以将各导电引线层分割成多个依次层叠的第一引线层201，且使得相邻两个第一引线层201之间通过第一转接金属层261电连接。如此，可以使得这多个相互电连接的第一引线层201在效果上等同于所需的很厚的导电引线层，进而提高阵列基板制备的工艺可行性和良率。
在本公开的一种实施方式中，如图19和图20所示，步骤S120可以包括步骤S410～步骤S450，以形成驱动电路层200，且使得驱动电路层200具有驱动晶体管210以及与驱动晶体管210连接的第一引线层201。
步骤S410，在衬底基板100的一侧形成驱动晶体管210，驱动晶体管210包括由源极和漏极组成的源漏电极层，源漏电极层位于驱动电路层的源漏金属层。
可选地，可以通过如下方法在衬底基板100的一侧形成驱动晶体管210：
步骤S411，在衬底基板100的一侧形成有源层、栅极绝缘层和栅极层，以形成驱动晶体管210的半导体层和栅极，其中，驱动晶体管210的半导体层位于有源层，且包括沟道区和位于沟道区两侧的源极接触区和漏极接触区；驱动晶体管的栅极位于栅极层；半导体层的沟道区和栅极通过栅极绝缘层隔离。
步骤S412，形成层间电介质层220，有源层、栅极绝缘层和栅极层均位于层间电介质层220与衬底基板100之间；层间电介质层220设置有第二连接过孔252，第二连接过孔252暴露源极接触区和漏极接触区。
步骤S413，在层间电介质层220远离衬底基板100的一侧形成源漏金属层230，源漏金属层230形成有驱动晶体管的源极和漏极，源极和漏极组成驱动晶体管的源漏金属层；其中，源极通过第二连接过孔252与源极接触区连接，漏极通过第二连接过孔252与漏极接触区连接。
可选地，源漏金属层230的材料和厚度，可以与第一转接金属层261相同或者不相同。
可选地，在形成源漏金属层230后，还可以在源漏金属层230远离衬 底基板100的表面形成一层钝化层。可以理解的是，钝化层暴露至少部分源漏金属层230，以使得源漏金属层230能够与驱动电路层200的其他导电结构电连接。
步骤S420，在驱动晶体管210远离衬底基板100的一侧形成第三平坦化层243，第三平坦化层243设置有暴露至少部分源漏电极层的第三连接过孔253。
可选地，第三平坦化层243的材料，可以与第一平坦化层241相同或者不相同。
可选地，第三连接过孔253在衬底基板100上的正投影，与第二连接过孔252在衬底基板100上的正投影不交叠。如此，可以使得第三连接过孔253暴露源漏金属层230的平坦表面，有助于提高暴露的源漏金属层230与驱动电路的其他导电结构的连接强度。
步骤S430，在第三平坦化层243远离衬底基板100的一侧形成第二转接金属层262，第二转接金属层262通过第三连接过孔253与源漏金属层230连接。
可选地，第二转接金属层262的材料和厚度，可以与第一转接金属层261相同或者不相同。
步骤S440，在第二转接金属层262远离衬底基板100的一侧形成第四平坦化层244，第四平坦化层244具有第四连接过孔254；第四连接过孔254暴露部分第二转接金属层262，且第四连接过孔254在衬底基板100上的正投影与第三连接过孔253在衬底基板100上的正投影不交叠。
如此，第二转接金属层262至少包括互不交叠的第三连接区域和第四连接区域，其中，第三连接区域与源漏金属层230电连接，第四连接区域与第一引线层201电连接。这种设置方法可以避免源漏金属层230的不平整传导至第一引线层201，可以使得第一引线层201能够具有良好的形貌而不会在源漏金属层230的影响下发生形貌的恶化。
可选地，第四平坦化层244的材料，可以与第一平坦化层241相同或者不相同。
步骤S450，在第四平坦化层244远离衬底基板100的表面形成一第一引线层201，第一引线层201通过第四连接过孔254与第二转接金属层 262连接。可以按照步骤S210～步骤S250所示的方法，形成第一引线层201。
如此，按照该实施方式所介绍的阵列基板的制备方法，如图20所示，所制备的驱动电路层200可以包括依次层叠的驱动晶体管210、第三平坦化层243、第二转接金属层262、第四平坦化层244和一第一引线层201。其中，
驱动晶体管210设于衬底基板100的一侧，驱动晶体管210包括由源极和漏极组成的源漏电极层；第三平坦化层243设于驱动晶体管210远离衬底基板100的一侧，且设置有暴露至少部分源漏电极层的第三连接过孔253；第二转接金属层262设于第三平坦化层243远离衬底基板100的一侧，且通过第三连接过孔253与源漏电极层连接；第四平坦化层244设于第二转接金属层262远离衬底基板100的一侧，且具有第四连接过孔254；第四连接过孔254暴露部分第二转接金属层262，且第四连接过孔254在衬底基板100上的正投影与第三连接过孔253在衬底基板100上的正投影不交叠；第一引线层201设于第四平坦化层244远离衬底基板100的表面，且通过第四连接过孔254与第二转接金属层262连接。
在本公开的另一种实施方式中，如图21和图22所示，步骤S120可以包括步骤S510～步骤S530，以形成驱动电路层200，且使得驱动电路层200具有驱动晶体管210以及与驱动晶体管210连接的第一引线层201。
步骤S510，在衬底基板100的一侧形成驱动晶体管210，驱动晶体管210包括由源极和漏极组成的源漏电极层，源漏电极层位于驱动电路层的源漏金属层。
步骤S520，在驱动晶体管210远离衬底基板100的一侧形成第三平坦化层243，第三平坦化层243设置有暴露至少部分源漏电极层的第三连接过孔253。
可选地，第三连接过孔253在衬底基板100上的正投影与第二连接过孔252在衬底基板100上的正投影不交叠。
可选地，可以参考步骤S410～步骤S420所示的制备方法，来实现步骤S510～步骤S520。
步骤S530，在第三平坦化层243远离衬底基板100的表面形成一第 一引线层201，第一引线层201通过第三连接过孔253与源漏电极层连接。可以按照步骤S210～步骤S250所示的方法，形成第一引线层201。
如此，按照该实施方式所介绍的阵列基板的制备方法，如图22所示，所制备的驱动电路层200可以包括依次层叠的驱动晶体管210、第三平坦化层243和一第一引线层201。其中，
驱动晶体管210设于所述衬底基板的一侧，所述驱动晶体管210包括由源极和漏极组成的源漏电极层；第三平坦化层243设于源漏电极层远离衬底基板100的一侧，且设置有暴露至少部分源漏电极层的第三连接过孔253；一第一引线层201设于第三平坦化层243远离衬底基板100的表面，且通过第三连接过孔253与源漏电极层连接。
根据该实施方式所制备的阵列基板，源漏金属层230可以复用为第二转接金属层262，如此可以不必制备第二转接金属层262和第四平坦化层244，在工艺上可以减少两次图案化工艺并节省相关的材料，在形成的阵列基板上可以减少两个膜层。如此，该实施方式所示的制备方法，可以减少阵列基板的制备成本并提高制备效率，并可以使得阵列基板具有更小的厚度。
在本公开的另一种实施方式中，如图23和图24所示，步骤S120可以包括步骤S610～步骤S630，以形成驱动电路层200，且使得驱动电路层200具有驱动晶体管210以及与驱动晶体管210连接的第一引线层201。
步骤S610，在衬底基板100的一侧形成有源层、栅极绝缘层和栅极层，以形成驱动晶体管210的半导体层和栅极，其中，驱动晶体管210的半导体层位于有源层，且包括沟道区和位于沟道区两侧的源极接触区和漏极接触区；驱动晶体管210的栅极位于栅极层；半导体层的沟道区和栅极通过栅极绝缘层隔离；
步骤S620，形成层间电介质层220，有源层、栅极绝缘层和栅极层均位于层间电介质层220与衬底基板100之间；层间电介质层220设置有第二连接过孔252，第二连接过孔252暴露源极接触区和漏极接触区；
步骤S630，在层间电介质层220远离衬底基板100的一侧形成一第一引线层201，第一引线层201形成有源极和漏极，源极通过第二连接过孔252与源极接触区连接，漏极通过第二连接过孔252与漏极接触区连接。
如此，按照该实施方式所介绍的阵列基板的制备方法，如图24所示，所制备的驱动电路层200可以包括驱动晶体管，驱动晶体管包括半导体层、层间电介质层和第一引线层；半导体层设于所述衬底基板的一侧；所述半导体层包括源极接触区和漏极接触区；层间电介质层设于所述半导体层远离所述衬底基板的一侧；所述第一引线层设于所述层间电介质层远离所述衬底基板的一侧，且形成有源极和漏极；所述源极与所述源极接触区连接，所述漏极与所述漏极接触区连接。
根据该实施方式所制备的阵列基板，第一引线层201可以复用为源漏金属层230，可以进一步减少阵列基板制备过程中的图案化过程和膜层材料，降低阵列基板的制备成本，进一步降低阵列基板的厚度。
在步骤S130中，可以在驱动电路层200远离衬底基板100的一侧形成功能器件层300。功能器件层300可以包含有阵列分布的功能器件310，例如包括用于发光的发光器件、用于发出超声波的超声波发射器件、用于产生热量的加热器件或者其他电流驱动的功能器件310。
可选地，驱动电路层200可以包括一电极层，各个功能器件310可以与该电极层电连接。该电极层可以为第一引线层201，也可以为第二引线层202，本公开对此不做特殊的限定。进一步地，连接电极层可以包括相邻设置的第一电极和第二电极，功能器件310的第一端可以与第一电极电连接，功能器件310的第二端可以与第二电极电连接。如此驱动电流可以通过第一电极和第二电极流经功能器件310，使得功能器件310工作。
在一些实施方式中，如图16和图17所示，可以先在驱动电路层远离衬底基板的一侧形成像素定义层271，然后在像素定义层271所限定的区域内涂覆导电胶272，并将功能器件310通过导电胶272与电极层电连接。
示例性地，功能器件310可以为LED、Mini LED或者Micro LED，Mini LED或者Micro LED可以通过锡膏连接于电极层。
可选地，本公开的阵列基板的制备方法还可以包括：
在衬底基板100的侧面制备扇出引线，扇出引线与驱动电路层200电连接；
在衬底基板100远离驱动电路层200的一侧制备绑定层，绑定层具有多个绑定焊盘，各个绑定焊盘通过扇出引线与驱动电路层200电连接。
如此，所制备的阵列基板可以包括依次层叠的衬底基板100、驱动电路层200和功能器件层300，以及位于衬底基板100远离驱动电路层200一侧的绑定层，和位于衬底基板100侧面的扇出引线。如此，该阵列基板可以具有更小的边缘，便于多个不同的阵列基板通过拼接形成一个更大的基板，且使得该更大的基板具有更小的拼接缝。
示例性，当功能器件310为Micro LED时，多个不同的小尺寸的阵列基板可以通过拼接形成大尺寸的显示屏幕，且可以是得显示屏幕的拼接尺寸非常小，进而达成良好的显示效果。各个阵列基板的驱动电路，例如驱动电路板和设置于驱动电路板上的驱动芯片，可以通过绑定焊盘电连接，以实现对阵列基板的驱动。
在本公开的一种实施方式中，如图25所示，绑定层可以包括依次层叠于衬底基板100远离驱动电路层200表面的背侧引线层610、绝缘层620和绑定焊盘层630，背侧引线层610可以与扇出引线(图25中未示出)电连接，绝缘层620暴露部分背侧引线层610，使得绑定焊盘层630可以与背侧引线层610电连接。
可选地，背侧引线层610还可以设置有背侧对位图案，背侧对位图案的材料可以与背侧引线层610相同，也可以不相同。示例性地，背侧对位图案和绑定焊盘层630的材料均为ITO。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
本公开实施方式还提供一种阵列基板，如图1和图2所示，该阵列基板包括依次层叠设置的衬底基板100、驱动电路层200和功能器件层300；
其中，驱动电路层200包括至少一层第一引线层201，任意一层第一引线层201包括至少一个第一引线2011；任意一个第一引线2011包括设于衬底基板100一侧的种子引线411，以及设于种子引线411远离衬底基板100表面的生长引线432，生长引线432在衬底基板100上的正投影与种子引线411在衬底基板100上的正投影重合。
本公开提供的阵列基板可以采用上述阵列基板的制备方法实施方式所描述的任意一种制备方法进行制备，因此具有相同或者类似的技术效果，本公开在此不再赘述。
在本公开的一种实施方式中，第一引线2011的厚度，不大于种子引线411的宽度的5倍。
在本公开的一种实施方式中，第一引线2011的厚度为1.5微米～20微米。
在本公开的一种实施方式中，第一引线2011远离衬底基板100一端的宽度，小于第一引线2011靠近衬底基板100一端的宽度。
在本公开的一种实施方式中，如图17和图18所示，驱动电路层200包括：
一第一引线层201a，设于衬底基板100的一侧；
第一平坦化层241，设于第一引线层201a远离衬底基板100的一侧，且暴露至少部分第一引线层201a；
第一转接金属层261，设于第一平坦化层241远离衬底基板100的一侧，且与第一引线层201a连接；
第二平坦化层242，设于第一转接金属层261远离衬底基板100的一侧，且设置有第一连接过孔251；第一连接过孔251暴露部分第一转接金属层261，且第一连接过孔251在第一引线层201a上的正投影与第一引线层201a不交叠；
另一第一引线层201b，设于第二平坦化层242远离衬底基板100的表面，且通过第一连接过孔251与第一转接金属层261连接。
换言之，驱动电路层200包括至少一个第一引线层组，任意一个第一引线层组包括：
前一第一引线层201a，设于衬底基板100的一侧；
第一平坦化层241，设于前一第一引线层201a远离衬底基板100的一侧，且暴露至少部分前一第一引线层201a；
第一转接金属层261，设于第一平坦化层241远离衬底基板100的一侧，且与前一第一引线层201a连接；
第二平坦化层242，设于第一转接金属层261远离衬底基板100的一 侧，且设置有第一连接过孔251；第一连接过孔251暴露部分第一转接金属层261，且第一连接过孔251在前一第一引线层201a上的正投影与前一第一引线层201a不交叠；
后一第一引线层201b，设于第二平坦化层242远离衬底基板100的表面，且通过第一连接过孔251与第一转接金属层261连接。
在本公开的一种实施方式中，如图20所示，驱动电路层200包括：
驱动晶体管210，设于衬底基板100的一侧，驱动晶体管210包括由源极和漏极组成的源漏电极层；
第三平坦化层243，设于源漏电极层远离衬底基板100的一侧，且设置有暴露至少部分源漏电极层的第三连接过孔253；
第二转接金属层262，设于第三平坦化层243远离衬底基板100的一侧，且通过第三连接过孔253与源漏电极层连接；
第四平坦化层244，设于第二转接金属层262远离衬底基板100的一侧，且具有第四连接过孔254；第四连接过孔254暴露部分第二转接金属层262，且第四连接过孔254在衬底基板100上的正投影与第三连接过孔253在衬底基板100上的正投影不交叠；
一第一引线层201，设于第四平坦化层244远离衬底基板100的表面，且通过第四连接过孔254与第二转接金属层262连接。
在本公开的一种实施方式中，如图22所示，驱动电路层200包括：
驱动晶体管210，设于衬底基板100的一侧形，驱动晶体管210包括由源极和漏极组成的源漏电极层；
第三平坦化层243，设于源漏电极层远离衬底基板100的一侧，且设置有暴露至少部分源漏电极层的第三连接过孔253；
一第一引线层201，设于第三平坦化层243远离衬底基板100的表面，且通过第三连接过孔253与源漏电极层连接。
在本公开的一种实施方式中，如图24所示，驱动电路层200包括驱动晶体管，驱动晶体管包括：
半导体层，设于所述衬底基板100的一侧；所述半导体层包括源极接触区和漏极接触区；
层间电介质层220，设于所述半导体层远离所述衬底基板100的一侧；
一所述第一引线层201，设于层间电介质层220远离所述衬底基板的一侧，且形成有源极和漏极；源极与所述源极接触区连接，漏极与所述漏极接触区连接。
本公开提供的阵列基板其他细节和可能变形，在上述阵列基板的制备方法实施方式中进行了详细的描述，本公开在此不再赘述。
本公开实施方式还提供一种显示装置，该显示装置包括上述阵列基板实施方式所描述的任意一种阵列基板。该显示装置可以为手机屏幕、电脑屏幕、电视机或者其他类型的显示装置。由于该显示装置具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
在本公开的一种实施方式中，在显示装置中，阵列基板上的功能器件中，至少部分功能器件为发光器件。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (15)

  1. 一种阵列基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板的一侧形成驱动电路层；
    在所述驱动电路层远离所述衬底基板的一侧形成功能器件层；
    其中，在所述衬底基板的一侧形成驱动电路层包括：在所述衬底基板的一侧形成至少一层第一引线层；形成任意一层所述第一引线层包括：
    在所述衬底基板的一侧形成导电种子层；
    在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层，所述可移除的图案限定层设置有引线开口，所述引线开口暴露部分所述导电种子层；
    采用电镀工艺或者化学镀工艺，在所述引线开口内形成位于所述导电种子层表面的金属镀层；
    移除所述可移除的图案限定层；
    去除所述导电种子层未被所述金属镀层覆盖的部分。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层包括：
    在所述导电种子层远离所述衬底基板的表面形成一层可移除的绝缘材料层；
    对所述可移除的绝缘材料层进行图案化操作，以形成所述可移除的图案限定层。
  3. 根据权利要求2所述的阵列基板的制备方法，其中，在所述导电种子层远离所述衬底基板的表面形成一层可移除的绝缘材料层包括：
    在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层；
    对所述可移除的绝缘材料层进行图案化操作包括：
    对所述光刻胶材料层进行曝光和显影，以形成所述可移除的图案限定层。
  4. 根据权利要求3所述的阵列基板的制备方法，其中，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层包括：
    使用可降解光刻胶材料，在所述导电种子层远离所述衬底基板的表面 形成一层光刻胶材料层，所述可降解光刻胶材料为在固化后能够溶解于降解液的光刻胶材料；
    移除所述可移除的图案限定层包括：
    使用所述降解液溶解所述可移除的图案限定层。
  5. 根据权利要求3所述的阵列基板的制备方法，其中，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层包括：
    使用负性光刻胶材料，在所述导电种子层远离所述衬底基板的表面形成一层光刻胶材料层；
    对所述光刻胶材料层进行曝光和显影包括：
    对所述光刻胶材料层进行曝光和显影，以形成具有引线开口的可移除的图案限定层，使得所述引线开口靠近所述衬底基板的一端的宽度大于远离所述衬底基板的一端的宽度。
  6. 根据权利要求1所述的阵列基板的制备方法，其中，在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层包括：
    在所述导电种子层远离所述衬底基板的表面形成可移除的图案限定层，所述引线开口的宽度的最小值为第一尺寸值；
    采用电镀工艺或者化学镀工艺，在所述引线开口内形成位于所述导电种子层表面的金属镀层包括：
    采用电镀工艺或者化学镀工艺，在所述引线开口内形成位于所述导电种子层表面的金属镀层，使得所述金属镀层的厚度为第二尺寸值，所述第二尺寸值不大于所述第一尺寸值的5倍。
  7. 根据权利要求1～6任一项所述的阵列基板的制备方法，其中，在所述衬底基板的一侧形成至少一层第一引线层包括：
    在所述衬底基板的一侧形成一层所述第一引线层；
    在所述第一引线层远离所述衬底基板的一侧形成第一平坦化层，所述第一平坦化层暴露至少部分所述第一引线层；
    在所述第一平坦化层远离所述衬底基板的一侧形成第一转接金属层，所述第一转接金属层连接所述第一引线层；
    在所述第一转接金属层远离所述衬底基板的一侧形成第二平坦化层，所述第二平坦化层具有第一连接过孔；所述第一连接过孔暴露部分所述第 一转接金属层，且所述第一连接过孔在所述第一引线层上的正投影与所述第一引线层不交叠；
    在所述第二平坦化层远离所述衬底基板的表面形成另一层所述第一引线层，另一层所述第一引线层通过所述第一连接过孔与所述第一转接金属层连接。
  8. 一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层和功能器件层；
    其中，所述驱动电路层包括至少一层第一引线层，任意一层所述第一引线层包括至少一个第一引线；
    任意一个所述第一引线包括设于所述衬底基板一侧的种子引线，以及设于所述种子引线远离所述衬底基板表面的生长引线，所述生长引线在所述衬底基板上的正投影与所述种子引线在衬底基板上的正投影重合。
  9. 根据权利要求8所述的阵列基板，其中，所述第一引线的厚度，不大于所述种子引线的宽度的5倍。
  10. 根据权利要求8所述的阵列基板，其中，所述第一引线远离所述衬底基板一端的宽度，小于所述第一引线靠近所述衬底基板一端的宽度。
  11. 根据权利要求8～10任一项所述的阵列基板，其中，所述驱动电路层包括：
    一所述第一引线层，设于所述衬底基板的一侧；
    第一平坦化层，设于所述第一引线层远离所述衬底基板的一侧；
    第一转接金属层，设于所述第一平坦化层远离所述衬底基板的一侧，且与所述第一引线层连接；
    第二平坦化层，设于所述第一转接金属层远离所述衬底基板的一侧，且设置有第一连接过孔；所述第一连接过孔暴露部分所述第一转接金属层，且所述第一连接过孔在所述第一引线层上的正投影与所述第一引线层不交叠；
    另一所述第一引线层，设于所述第二平坦化层远离所述衬底基板的表面，且通过所述第一连接过孔与所述第一转接金属层连接。
  12. 根据权利要求8～10任一项所述的阵列基板，其中，所述驱动电路层包括：
    驱动晶体管，设于所述衬底基板的一侧，所述驱动晶体管包括由源极和漏极组成的源漏电极层；
    第三平坦化层，设于所述驱动晶体管远离所述衬底基板的一侧，且设置有暴露至少部分所述源漏电极层的第三连接过孔；
    第二转接金属层，设于所述第三平坦化层远离所述衬底基板的一侧，且通过所述第三连接过孔与所述源漏电极层连接；
    第四平坦化层，设于所述第二转接金属层远离所述衬底基板的一侧，且具有第四连接过孔；所述第四连接过孔暴露部分所述第二转接金属层，且所述第四连接过孔在所述衬底基板上的正投影与所述第三连接过孔在所述衬底基板上的正投影不交叠；
    一所述第一引线层，设于所述第四平坦化层远离所述衬底基板的表面，且通过所述第四连接过孔与所述第二转接金属层连接。
  13. 根据权利要求8～10任一项所述的阵列基板，其中，所述驱动电路层包括：
    驱动晶体管，设于所述衬底基板的一侧，所述驱动晶体管包括由源极和漏极组成的源漏电极层；
    第三平坦化层，设于所述源漏电极层远离所述衬底基板的一侧，且设置有暴露至少部分所述源漏电极层的第三连接过孔；
    一所述第一引线层，设于所述第三平坦化层远离所述衬底基板的表面，且通过所述第三连接过孔与所述源漏电极层连接。
  14. 根据权利要求8～10任一项所述的阵列基板，其中，所述驱动电路层包括驱动晶体管，所述驱动晶体管包括：
    半导体层，设于所述衬底基板的一侧；所述半导体层包括源极接触区和漏极接触区；
    层间电介质层，设于所述半导体层远离所述衬底基板的一侧；
    一所述第一引线层，设于所述层间电介质层远离所述衬底基板的一侧，且形成有源极和漏极；所述源极与所述源极接触区连接，所述漏极与所述漏极接触区连接。
  15. 一种显示装置，包括权利要求8～14任一项所述的阵列基板。
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