WO2022001431A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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WO2022001431A1
WO2022001431A1 PCT/CN2021/094250 CN2021094250W WO2022001431A1 WO 2022001431 A1 WO2022001431 A1 WO 2022001431A1 CN 2021094250 W CN2021094250 W CN 2021094250W WO 2022001431 A1 WO2022001431 A1 WO 2022001431A1
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Prior art keywords
layer
gate
driving transistor
source
base substrate
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PCT/CN2021/094250
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English (en)
French (fr)
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董学
袁广才
宁策
梁志伟
关峰
强朝辉
刘英伟
王珂
曹占锋
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京东方科技集团股份有限公司
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Priority to US17/772,234 priority Critical patent/US20220375966A1/en
Publication of WO2022001431A1 publication Critical patent/WO2022001431A1/zh

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display panel.
  • the purpose of the present disclosure is to provide an array substrate, a preparation method thereof, and a display panel, which can improve the saturation current of the driving transistor.
  • an array substrate comprising a base substrate, a driving circuit layer and a functional device layer stacked in sequence: wherein the driving circuit layer is provided with a first driving circuit, the first driving The circuit includes at least a drive transistor;
  • the driving circuit layer includes a first gate layer, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer and a source layer sequentially stacked on the base substrate a drain metal layer; wherein the first gate layer includes a first gate of the drive transistor; the semiconductor layer includes an active layer of the drive transistor, and the active layer of the drive transistor has the drive the channel region of the transistor; the orthographic projection of the first gate of the driving transistor on the semiconductor layer at least partially coincides with the channel region of the same driving transistor; the second gate layer includes the first gate of the driving transistor Two gates; the orthographic projection of the second gate of the driving transistor on the semiconductor layer at least partially overlaps with the channel region of the same driving transistor; the source-drain metal layer includes the source of the driving transistor and drain;
  • the first gate and the second gate of the same driving transistor are electrically connected through the source-drain metal layer;
  • the functional device layer includes a functional device, and the functional device is electrically connected to the drain of the driving transistor .
  • the source-drain metal layer further includes a gate bridge lead of the driving transistor; in the same driving transistor, the first gate and the second gate are connected with the gate bridge leads.
  • the driving circuit layer includes a first via hole and a second via hole
  • the first via hole penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer, and exposes at least a partial region of the first gate of the driving transistor;
  • the a second via hole penetrates the interlayer dielectric layer and the second gate insulating layer, and exposes at least a partial region of the second gate of the driving transistor;
  • the gate bridge wire is connected to the first gate through the first via hole, and is connected to the second gate through the second via hole.
  • the first driving circuit further includes a storage capacitor; the first gate layer further includes a first electrode plate of the storage capacitor, and the second gate layer further includes A second electrode plate including the storage capacitor.
  • the first driving circuit further includes a switch transistor; the semiconductor layer further includes an active layer of the switch transistor, and the active layer of the switch transistor has the switch The channel region of the transistor; the width of the channel region of the driving transistor is greater than the width of the channel region of the switching transistor.
  • the material of the semiconductor layer includes low temperature polysilicon.
  • the thickness of the semiconductor layer is 30-60 nanometers.
  • the driving circuit layer further includes:
  • a planarization layer disposed on the side of the source-drain metal layer away from the base substrate;
  • the electrode layer includes a second electrode and a first electrode of the first drive circuit; the same In a driving circuit, the first electrode is connected to the drain of the driving transistor;
  • the functional device connects the second electrode and the first electrode.
  • the electrode layer includes:
  • a first seed metal layer disposed on the side of the source-drain metal layer away from the base substrate, and connected to the drain of the driving transistor; the thickness of the first seed metal layer is not greater than 1 micron;
  • a first electroplating metal layer disposed on the side of the first seed metal layer away from the base substrate; the thickness of the first electroplating metal layer is 1-20 microns;
  • the functional device is connected to the first electroplated metal layer.
  • the electrode layer further includes a power supply lead connected to the source of the driving transistor.
  • the source-drain metal layer includes:
  • a second seed metal layer disposed on the side of the interlayer dielectric layer away from the base substrate and connected to the active layer of the driving transistor; the thickness of the second seed metal layer is not greater than 1 micron;
  • the second electroplating metal layer is disposed on the side of the second seed metal layer away from the base substrate; the thickness of the second electroplating metal layer is 1-20 microns.
  • the source-drain metal layer further includes a second electrode and a power supply lead; the power supply lead is connected to the source of the driving transistor, and the functional device is connected to the second electrode and the power supply lead. the drain of the drive transistor.
  • a display panel including the above-mentioned array substrate.
  • a method for fabricating an array substrate comprising sequentially forming a driving circuit layer and a functional device layer on one side of a base substrate: wherein the driving circuit layer is provided with a first driving circuit,
  • the first drive circuit includes at least a drive transistor; forming the drive circuit layer includes:
  • a first gate layer is formed on one side of the base substrate, and the first gate layer includes a first gate of the driving transistor;
  • a semiconductor layer is formed on a side of the first gate layer away from the base substrate, the semiconductor layer includes an active layer of a driving transistor, and the active layer of the driving transistor has a channel region of the driving transistor ; the orthographic projection of the first gate of the driving transistor on the semiconductor layer at least partially coincides with the channel region of the same driving transistor;
  • a second gate layer is formed on a side of the second gate insulating layer away from the base substrate, and the second gate layer includes a second gate of the driving transistor; the second gate of the driving transistor The orthographic projection of the semiconductor layer at least partially overlaps with the channel region of the same driving transistor; the first gate of the same driving transistor can be electrically connected to the second gate;
  • a source-drain metal layer is formed on a side of the interlayer dielectric layer away from the base substrate, the source-drain metal layer is connected to the active layer of the driving transistor, and the source-drain metal layer includes the driving transistor source and drain.
  • forming an interlayer dielectric layer on a side of the second gate layer away from the base substrate includes:
  • Forming a source-drain metal layer on the side of the interlayer dielectric layer away from the base substrate includes:
  • a patterning operation is performed on the source-drain metal material layer to form source, drain and gate bridge wires of the driving transistor, wherein the gate bridge wires are connected to the first via hole through the first via hole.
  • a gate is connected, and the gate bridge lead is connected to the second gate through the second via hole.
  • the driving circuit layer includes a first gate layer, a first gate insulating layer, a semiconductor layer, and a second gate insulating layer sequentially stacked on one side of the base substrate layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer.
  • the channel region of the driving transistor is located between the first gate of the driving transistor and the second gate of the driving transistor, which can avoid or weaken the floating body effect of the driving transistor, and eliminate the reduction of the saturation current of the driving transistor caused by the floating body effect. Make the drive transistor have a larger saturation current. In this way, the first driving circuit can provide a larger driving current for the functional device, avoid the influence of insufficient driving current on the performance of the functional device, and improve the performance of the array substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 4 is a schematic top-view structural diagram of a first electrode, an active layer, and a second electrode of a driving transistor in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of forming a semiconductor layer in an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of forming a second gate layer in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of forming an interlayer dielectric layer in an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of forming a source-drain metal layer in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of forming a third passivation layer in an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a source-drain metal layer in an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of forming a planarization layer and a first passivation layer in an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of forming an electrode layer in an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of forming a second passivation layer in an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of an active layer of a driving transistor in an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of an active layer of a switching transistor in an embodiment of the present disclosure.
  • FIG. 16 is an equivalent circuit diagram of a first driving circuit in an embodiment of the present disclosure.
  • 17 is a schematic top view of a first gate layer, a semiconductor layer, a second gate layer, and a source-drain metal layer in an embodiment of the disclosure.
  • FIG. 18 is a schematic top view of the first gate layer in one embodiment of the disclosure.
  • 19 is a schematic top view of a semiconductor layer in one embodiment of the disclosure.
  • FIG. 20 is a schematic top view of the second gate layer in one embodiment of the disclosure.
  • FIG. 21 is a schematic top view of a source-drain metal layer in an embodiment of the disclosure.
  • FIG. 22 is a schematic structural diagram of an array substrate when cut along AA' in FIG. 17 according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic flowchart of a method for preparing a driving circuit layer in an embodiment of the present disclosure.
  • FIG. 24 is a graph comparing the output curves of a single-gate transistor and a dual-gate transistor.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • the present disclosure provides an array substrate.
  • the array substrate includes a base substrate 110 , a driving circuit layer 130 and a functional device layer 140 stacked in sequence: wherein the driving circuit layer 130 is provided with a first driving circuit 200 ,
  • the first driving circuit 200 includes at least a driving transistor 210 .
  • 2 and 3 further illustrate the structure of the array substrate.
  • the second gate 351 of the driving transistor is shown as two parts that are not connected, this is the cross-sectional state of the second gate 351 of the driving transistor at a specific cutting position; It is understood that the second gate 351 of the driving transistor is a continuous integral structure, and when some select other cutting positions, the cross-section of the second gate 351 of the driving transistor is an undivided integral structure.
  • the driving circuit layer 130 includes a first gate layer 310 , a first gate insulating layer 320 , a semiconductor layer 330 , and a second gate insulating layer sequentially stacked on one side of the base substrate 110 340, the second gate layer 350, the interlayer dielectric layer 360 and the source-drain metal layer 370; wherein, the first gate layer 310 includes the first gate 311 of the driving transistor; the semiconductor layer 330 includes the active layer 331 of the driving transistor . As shown in FIG. 4 and FIG.
  • the active layer 331 of the driving transistor has a channel region 3311 of the driving transistor; the orthographic projection of the first gate 311 of the driving transistor on the semiconductor layer 330 is the same as the channel region 3311 of the same driving transistor. at least partially overlap; the second gate layer 350 includes the second gate 351 of the drive transistor; the orthographic projection of the second gate 351 of the drive transistor on the semiconductor layer 330 at least partially overlaps with the channel region 3311 of the same drive transistor; source The drain metal layer 370 is connected to the active layer 331 of the driving transistor, and the source-drain metal layer 370 includes the source electrode 371 and the drain electrode 372 of the driving transistor;
  • the first gate 311 and the second gate 351 of the same driving transistor are electrically connected through a source-drain metal layer 370 ;
  • the functional device layer 140 includes a functional device 141 that is electrically connected to the drain 372 of the driving transistor.
  • the driving circuit layer 130 includes a first gate layer 310 , a first gate insulating layer 320 , a semiconductor layer 330 , and a second gate insulating layer 340 sequentially stacked on one side of the base substrate 110 . , a second gate layer 350 , an interlayer dielectric layer 360 and a source-drain metal layer 370 .
  • the channel region 3311 of the driving transistor is located between the first gate 311 of the driving transistor and the second gate 351 of the driving transistor, which can avoid or weaken the floating body effect of the driving transistor 210 and eliminate the floating body effect of the driving transistor 210.
  • the reduction of the saturation current enables the driving transistor 210 to have a larger saturation current.
  • the first driving circuit 200 can provide a larger driving current for the functional device 141, avoid the influence of insufficient driving current on the performance of the functional device 141, and improve the performance of the array substrate.
  • the first gate electrode 311 and the second gate electrode 351 are electrically connected through the source-drain metal layer 370 , and there is no need to perform a patterning operation on the second gate insulating layer 340 before preparing the second gate electrode layer 350 .
  • the patterning operation in the preparation process of the array substrate is reduced, the number of mask plates is reduced, and the preparation cost of the array substrate is further reduced.
  • the saturation current of the driving transistor 210 refers to the leakage current of the saturated transistor when the driving transistor 210 is fully turned on.
  • the base substrate 110 may be the base substrate 110 of an inorganic material or the base substrate 110 of an organic material.
  • the material of the base substrate 110 may be glass materials such as soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate 110 may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (Polyvinyl phenol, PVP), Polyethersulfone (PES), Polyimide, Polyamide, Polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate 110 may also be a flexible base substrate 110 , for example, the material of the base substrate 110 may be polyimide (PI).
  • the base substrate 110 may also be a composite of multiple layers of materials.
  • the base substrate 110 may include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • a buffer layer 120 may also be provided on one side of the base substrate 110 , and the driving circuit layer 130 is provided on the side of the buffer layer 120 away from the base substrate 110 .
  • the buffer layer 120 may include an inorganic insulating material, for example, may include silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • the buffer layer 120 includes a silicon nitride layer and a silicon oxide layer sequentially stacked on the base substrate 110 , wherein the silicon nitride layer has a thickness of 40-60 nanometers, and the oxide layer has a thickness of 40-60 nanometers.
  • the thickness of the silicon layer is 180-220 nm.
  • the driving circuit layer 130 may have a plurality of first driving circuits 200 , and any one of the first driving circuits 200 may have a driving transistor 210 .
  • the driving transistor 210 may include an active layer 331 , a first gate 311 , a second gate 351 , a source 371 (not shown in FIG. 4 ), and a drain 372 (not shown in FIG. 4 ) ), wherein the active layer 331 and the first gate electrode 311 are isolated by the first gate insulating layer 320 , and the active layer 331 and the second gate electrode 351 are isolated by the second gate insulating layer 340 .
  • the active layer 331 may include a channel region 3311 and a source contact region 3312 and a drain contact region 3313 on both sides of the channel region 3311, the source contact region 3312 is electrically connected to the source electrode 371, and the drain contact region 3313 is connected to the drain Pole 372 is electrically connected. Since the first gate 311 and the second gate 351 are electrically connected to each other, the first gate 311 and the second gate 351 can have the same voltage, which can effectively isolate the active layer 351 from the base substrate 110 and avoid Capacitance and charge accumulation are formed between the active layer 351 and the base substrate 110 , thereby reducing or eliminating the floating body effect of the driving transistor 210 .
  • the electric field generated by the first gate 311 and the second gate 351 can simultaneously act on the channel region 3311 of the driving transistor, This enables the channel region 3311 to output the driving current more effectively and accurately in response to the data voltage.
  • the first gate 311 and the second gate 351 are electrically connected to each other, and the formation of parasitic capacitance between the first gate 311 and the second gate 351 can also be avoided, and the influence of the parasitic capacitance on the first driving circuit 200 can be avoided.
  • Figure 24 shows the output curves for some single-gate transistors and for dual-gate transistors.
  • the single-gate transistor has only one gate, and the gate can be located on the side of the active layer away from the base substrate or on the side of the active layer close to the base substrate.
  • the double-gate transistor has gates on both sides of the active layer, and the channel region is sandwiched between the two gates.
  • the driving transistor of the present disclosure is a dual-gate transistor.
  • DG-25/5 and DG-500/25 are double-gate transistors; among them, the width of the channel region of DG-25/5 is 25 microns and the length is 5 microns; The channel region has a width of 500 microns and a length of 25 microns.
  • TG-25/5 and TG-500/25 are single-gate transistors; the width of the channel region of TG-25/5 is 25 microns and the length is 5 microns; the width of the channel region of TG-500/25 is 500 microns and the length is 25 microns. It can be seen from FIG. 24 that under the condition that the channel region has the same width (W) length (L) ratio, the saturation current of the double-gate transistor is larger than that of the single-gate transistor.
  • the drain 372 of the drive transistor is electrically connected to the functional device 141 .
  • the first driving circuit 200 can drive the functional device 141 connected thereto through the driving transistor 210 .
  • the functional devices 141 can be self-luminous devices driven by current such as Micro LEDs and Mini LEDs, and these functional devices 141 can form sub-pixels of the array substrate; then the first driving circuit 200 can be used as a driver Pixel driver circuits for these self-luminous devices.
  • the driving circuit layer 130 may further include other driving circuits, for example, may also include a second driving circuit for fingerprint recognition, a third driving circuit for touch control, etc. Whether the driving circuit layer 130 includes other driving circuits, and the number and types of other driving circuits, etc., are not particularly limited.
  • the material of the first gate layer 310 may be selected from conductive materials, for example, metals, conductive metal oxides, conductive polymers, conductive composite materials, or a combination thereof may be selected.
  • the metal may be selected from platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or combinations thereof.
  • the conductive metal oxide may be selected from indium oxide, tin oxide, indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, or combinations thereof.
  • the conductive polymer can be selected from polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene)/polystyrene sulfonic acid (PEDOT/PSS) or a combination thereof , Dopants such as acids (such as hydrochloric acid, sulfuric acid, sulfonic acid, etc.), Lewis acids (such as phosphorus fluoride, arsenic fluoride, ferric chloride, etc.), halogens, and alkali metals can also be added to the conductive polymer.
  • the conductive composite material may be selected from conductive composite materials dispersed with carbon black, graphite powder, metal microparticles, and the like.
  • the first gate layer 310 may be a layer of conductive materials, or may be a stack of multiple layers of conductive materials.
  • the first gate layer 310 may include a first conductive material layer, a second conductive material layer, and a first conductive material layer that are sequentially stacked, that is, a sandwich structure.
  • the first conductive material layer can be selected from corrosion-resistant metals or alloys, such as molybdenum or titanium; the second conductive material layer can be selected from metals or alloys with high conductivity, such as copper, aluminum, silver, etc.
  • the first gate layer 310 may include a layer of conductive material, for example, the material of the first gate layer 310 may be molybdenum.
  • the thickness of the first gate layer 310 may be 30-100 nm; alternatively, the thickness of the gate layer may be 50 nm.
  • a first gate material layer may be formed on one side of the base substrate 110 first, and then a patterning operation is performed on the first gate material layer to form the first gate layer 310 .
  • the first gate material layer may be formed by a method of magnetron sputtering.
  • the first gate layer 310 may also be directly formed by methods such as screen printing.
  • the first gate insulating layer 320 is disposed on the side of the first gate layer 310 away from the base substrate 110 , and may be an organic or inorganic insulating material.
  • the material of the first gate insulating layer 320 may be silicon oxide, silicon nitride, silicon oxynitride or other inorganic insulating materials.
  • the material of the first gate insulating layer 320 may be silicon oxide, and the thickness may be 60-150 nanometers.
  • the first gate insulating layer 320 may be formed by physical vapor deposition, chemical vapor deposition, spin coating, screen printing, or other methods, which are not limited in the present disclosure.
  • a layer of silicon dioxide may be deposited on the side of the first gate layer 310 away from the base substrate 110 by plasma enhanced chemical vapor deposition (PECVD), to form the first gate insulating layer 320 .
  • PECVD plasma enhanced chemical vapor deposition
  • the semiconductor layer 330 is disposed on the side of the first gate insulating layer 320 away from the base substrate 110 , and may include amorphous silicon semiconductor materials, low temperature polysilicon semiconductor materials, single crystal silicon semiconductor materials, metal oxide semiconductor materials, and organic semiconductor materials or other types of semiconductor materials.
  • the material of the semiconductor layer 330 may include low temperature polysilicon.
  • the thickness of the semiconductor layer 330 is 30-60 nanometers, so as to avoid that the thickness is too small to reduce the saturation current of the driving transistor 210 .
  • the orthographic projection of the channel region 3311 of the driving transistor on the first gate layer 310 is located in the first gate 311 of the driving transistor;
  • the orthographic projection of the channel region 3311 on the second gate layer 350 is located in the second gate 351 of the driving transistor.
  • the channel region 3311 of the driving transistor can be completely controlled by the first gate and the second gate, which can eliminate the floating body effect of the driving transistor 210 and ensure that the driving transistor 210 has a large saturation current.
  • a low temperature polysilicon material layer may be formed on the side of the first gate insulating layer 320 away from the base substrate 110 first, and then the low temperature polysilicon material layer may be patterned to form the semiconductor layer 330 .
  • a plasma-enhanced chemical vapor deposition method can be used to form an amorphous silicon layer on the side of the first gate insulating layer 320 away from the base substrate 110, and then the amorphous silicon layer can be scanned by an excimer laser. , so that the amorphous silicon layer is crystallized into an amorphous silicon layer.
  • the second gate insulating layer 340 is disposed on the side of the semiconductor layer 330 away from the base substrate 110 for isolating the semiconductor layer 330 and the second gate layer 350 .
  • the material and thickness of the second gate insulating layer 340 may be the same as or different from those of the first gate insulating layer 320 .
  • the material of the second gate insulating layer 340 is silicon oxide, and the thickness is 60-200 nanometers.
  • the second gate insulating layer 340 may be formed by a plasma-enhanced chemical vapor deposition method.
  • the second gate layer 350 is disposed on the side of the second gate insulating layer 340 away from the base substrate 110 .
  • the material and thickness of the second gate layer 350 may be the same as or different from those of the first gate layer 310 .
  • the thickness of the second gate layer 350 is greater than that of the first gate layer 310, so as to facilitate the preparation of gate leads required for the array substrate on the second gate layer 350 and reduce the square resistance of the gate leads.
  • the material of the second gate layer 350 is molybdenum, and the thickness is 300-400 nanometers.
  • the second gate material layer may be formed on the side of the second gate insulating layer 340 away from the base substrate 110 by a method of magnetron sputtering, and then the second gate material layer A patterning process is performed to form the second gate layer 350 .
  • the second gate layer 350 may further include gate leads for transmitting various gate signals to the first driving circuit 200 , for example, it may also include one or more of scan leads for transmitting scan signals, reset leads for transmitting reset signals, and initialization leads for transmitting initialization signals.
  • the interlayer dielectric layer 360 is disposed on the side of the second gate layer 350 away from the base substrate 110 for isolating the second gate layer 350 and the source-drain metal layer 370 .
  • the material of the interlayer dielectric layer 360 may be an inorganic insulating material.
  • the interlayer dielectric layer 360 may include one layer of insulating material, or may include multiple layers of stacked insulating material.
  • the interlayer dielectric layer 360 may include a silicon nitride layer and a silicon oxide layer sequentially stacked on a side of the second gate layer 350 away from the base substrate 110 , wherein the nitrogen
  • the thickness of the silicon oxide layer is 150-250 nanometers, and the thickness of the silicon oxide layer is 250-350 nanometers.
  • an interlayer dielectric material layer may be formed on the side of the second gate layer 350 away from the base substrate 110 first, and then the interlayer dielectric material layer is patterned to form the interlayer dielectric layer 360 .
  • the interlayer dielectric material layer may be formed by plasma enhanced chemical vapor deposition.
  • a first via hole 701 exposing at least a partial region of the first gate electrode 311 of the driving transistor may also be formed and an exposure The second via hole 702 in at least a partial area of the second gate 351 of the driving transistor.
  • the first via hole 701 and the second via hole 702 can be formed, wherein the first via hole 701 penetrates through the interlayer dielectric layer 360 and the first gate insulating layer 320 And the second gate insulating layer 340, the orthographic projection of the first via hole 701 on the first gate layer 310, is located on the first gate 311 of the driving transistor.
  • the second via hole 702 penetrates through the interlayer dielectric layer 360 and the second gate insulating layer 340, and the orthographic projection of the second via hole 702 on the second gate electrode layer 350 is located on the second gate electrode 351 of the driving transistor.
  • the source-drain metal layer 370 may further include the gate bridge lead 373 of the driving transistor 210 ; in the same drive transistor 210 , the gate bridge lead 373
  • the first gate 311 is connected through the first via hole 701
  • the second gate 351 is connected through the second via hole 702 , so that the first gate 311 and the second gate 351 are both electrically connected to the gate bridge lead 373 .
  • the first gate 311 and the second gate 351 of the driving transistor can be electrically connected through the gate bridge wire 373 .
  • the first gate insulating layer 320 and the second gate insulating layer 340 may not need to be patterned, but can be patterned together when the interlayer dielectric material layer is patterned change. In this way, the patterning operation during the preparation of the array substrate can be reduced, thereby reducing the preparation cost of the array substrate.
  • interlayer dielectric layer 360 may also include other via holes, for example, including via holes for connecting the source electrode 371 and drain electrode 372 of the driving transistor with the active layer 331 of the driving transistor, etc., which is not covered in this disclosure. Detailed description.
  • the source-drain metal layer 370 is disposed on the side of the interlayer dielectric layer 360 away from the base substrate 110 , and includes the source electrode 371 and the drain electrode 372 of the driving transistor.
  • the source-drain metal layer 370 can be directly connected to the functional device 141 or indirectly connected to the functional device 141 as a transition layer, which is not specifically limited in the present disclosure.
  • the source-drain metal layer 370 may be used as a via layer to indirectly connect with the functional device 141 .
  • the source-drain metal layer 370 may include a source electrode 371 of the driving transistor, a drain electrode 372 of the driving transistor, a data transfer electrode, a power transfer electrode, and the like.
  • the thickness of the source-drain metal layer 370 may not be greater than 1 micrometer, so as to facilitate the preparation by the method of magnetron sputtering.
  • a metal material can be deposited on the side of the interlayer dielectric layer 360 away from the base substrate 110 by magnetron sputtering to form a source-drain metal material layer; and then the source-drain metal material layer is patterned to A source-drain metal layer 370 is formed.
  • the source-drain metal layer 370 may be one layer of metal material, or may be a stack of multiple layers of metal materials.
  • the source-drain metal layer 370 may include a first conductive material layer, a second conductive material layer, and a first conductive material layer stacked in sequence, that is, a sandwich structure.
  • the first conductive material layer can be selected from corrosion-resistant metals or alloys, such as molybdenum or titanium;
  • the second conductive material layer can be selected from metals or alloys with high conductivity, such as copper, aluminum, silver, etc.
  • the source-drain metal layer 370 may include a titanium layer, an aluminum layer, and a titanium layer that are stacked in sequence.
  • the driving circuit layer 130 may further include a planarization layer 380 and an electrode layer 390 , wherein the planarization layer 380 is provided on the side of the source-drain metal layer 370 away from the base substrate 110 ; the electrode layer 390 is provided on a flat surface
  • the electrode layer 390 includes the second electrode 501 and the first electrode 391 of the first driving circuit 200; in the same first driving circuit 200, the first electrode 391 It is connected to the drain 372 of the driving transistor; the functional device 141 is connected to the second electrode 501 and the first electrode 391 .
  • the second electrode 501 may be a common electrode; the first electrode 391 may be an electrode for loading a driving signal, for example, a pixel electrode of a display panel.
  • the source-drain metal layer 370 can serve as a transfer layer, so that the first electrode 391 of the array substrate is electrically connected to the drain electrode 372 of the driving transistor. Since the thickness of the electrode layer 390 is greater than 1 micrometer, the square resistance of the electrode layer 390 is small, and the voltage drop on the second electrode 501 can be reduced.
  • the electrode layer 390 may further include a power supply lead 502 for transmitting the power supply voltage. Since the thickness of the electrode layer 390 is greater than 1 ⁇ m, the square resistance of the electrode layer 390 is small, so that the power supply lead 502 has a small resistance. Pressure drop is reduced.
  • the electrode layer 390 may further include data leads for transmitting data signals. Since the thickness of the electrode layer 390 is greater than 1 micrometer, the square resistance of the electrode layer 390 is small, so that the voltage drop of the data leads is reduced.
  • the electrode layer 390 may further include bonding pads for bonding with the driver.
  • the source-drain metal layer 370 may further include a first source-drain lead, wherein part of the first source-drain lead is connected to the power lead 502 , so that the voltage drop of the power lead 502 can be further reduced. Part of the first source-drain leads can be connected to the data leads, so that the voltage drop of the data leads 503 can be further reduced. Part of the first source-drain leads can be connected to the second electrode 501 , so that the voltage drop of the second electrode 501 can be further reduced. Parts of the first source-drain leads may be connected to the bonding pads.
  • the electrode layer 390 includes a first seed metal layer 411 and a first electroplating metal layer 412 , wherein the first seed metal layer 411 is provided on the planarization layer 380 away from the base substrate 110
  • the thickness of the first seed metal layer 411 is not greater than 1 micron
  • the first electroplating metal layer 412 is provided on the side of the first seed metal layer 411 away from the base substrate 110
  • the thickness of the first electroplated metal layer 412 is 1-20 microns
  • the functional device 141 is electrically connected to the first electroplated metal layer 412 .
  • the first seed metal layer 411 can be formed by sputtering, and the first electroplated metal layer 412 can be formed by electroplating.
  • the first seed metal layer 411 includes an MTD alloy (molybdenum-titanium-nickel alloy) layer and a copper layer sequentially stacked on the side of the planarization layer 380 away from the base substrate 110 , wherein the thickness of the MTD alloy layer is 30-50 Nanometer, the thickness of the copper layer is 200 to 400 nanometers.
  • MTD alloy mobdenum-titanium-nickel alloy
  • the material of the first electroplated metal layer 412 may be copper, and the thickness of the first electroplated metal layer 412 may be 2-5 microns.
  • the electrode layer 390 may be formed by the following methods: forming a first seed metal material layer on the side of the planarization layer 380 away from the base substrate 110; A removable pattern-defining layer is formed on the surface of the layer away from the base substrate 110, the removable pattern-defining layer is provided with lead openings, and the lead openings expose part of the first seed metal material layer; electroplating processes are used to form the first seed metal material layer in the lead openings. A first electroplating metal material layer on the surface of a seed metal material layer; removing the removable pattern defining layer; removing the part of the first seed metal material layer not covered by the first electroplating metal material layer to form a source-drain metal layer 370 .
  • the first electroplated metal material layer may be used as a mask, and the part of the first seed metal material layer that is not covered by the first electroplated metal material layer may be removed by etching; The remaining portion forms the first seed metal layer 411 , and the remaining portion of the first electroplating metal material layer forms the first electroplating metal layer 412 .
  • the electrode layer 390 can be prepared by adopting the strategy of “forming the whole surface seed layer—defining the electroplating pattern—electroplating metal—patterning the seed layer”, which can improve the morphology of the first electroplating metal layer 412 .
  • the array substrate may further include a first passivation layer 601 , and the first passivation layer 601 is located between the planarization layer 380 and the electrode layer 390 for protecting the electrodes layer 390 to prevent the active metal (eg copper) in the electrode layer 390 from being eroded.
  • the thickness of the first passivation layer 601 is 100-200 nanometers, and the material may be silicon oxynitride.
  • the array substrate may further include a second passivation layer 602 , and the first passivation layer 601 is located on the side of the electrode layer 390 away from the base substrate 110 for protecting the electrode layer 390 , to prevent the active metal (eg copper) in the electrode layer 390 from being corroded.
  • the thickness of the second passivation layer 602 is 100-200 nanometers, and the material may be silicon oxynitride.
  • the source-drain metal layer 370 is connected to the electrode layer 390 as a transfer layer.
  • part of the first source-drain leads in the source-drain metal layer 370 may also be connected in parallel with the conductive structure on the electrode layer 390, so as to reduce the square resistance of the conductive structure on the electrode layer 390, reduce the impedance of the signal and provide large current.
  • this embodiment increases the thickness of the electrode layer 390 through the electroplating process, thereby reducing the number of layers of the stacking of the source-drain structure, which can reduce the masking during the preparation of the array substrate. The number of membrane plates is reduced, thereby reducing the preparation process of the array substrate and reducing the preparation cost of the array substrate.
  • the source-drain metal layer 370 is also directly connected to the functional device 141 .
  • the source-drain metal layer 370 may further include a second source-drain lead of the driving circuit layer 130 , and the second source-drain lead may include a power lead for transmitting a power supply voltage, a second source-drain lead for transmitting a common voltage One or more of two electrodes, data leads for transmitting data signals, and the like.
  • the power lead may be electrically connected to the source 371 of the driving transistor, one end of the functional device 141 may be connected to the drain 372 of the driving transistor, and the other end may be connected to the second electrode.
  • the source-drain metal layer 370 may also be formed with bonding pads, and the bonding pads are used for bonding the array substrate and the driver.
  • the thickness of the source-drain metal layer 370 can be greater than 1 micron, so that each second source-drain lead has a larger thickness, which reduces the square resistance of the second source-drain lead and reduces the amount of each signal on the second source-drain lead. pressure drop.
  • the source-drain metal layer 370 may include a second seed metal layer 421 and a second electroplating metal layer 422 stacked on a side of the interlayer dielectric layer 360 away from the base substrate 110 .
  • the second seed metal layer 421 is disposed on the side of the interlayer dielectric layer 360 away from the base substrate 110 and is connected to the active layer 331 of the driving transistor; the thickness of the second seed metal layer 421 is not greater than 1 ⁇ m; the second electroplating The metal layer 422 is disposed on the side of the second seed metal layer 421 away from the base substrate 110 ; the thickness of the second electroplated metal layer 422 is 1-20 ⁇ m.
  • the second seed metal layer 421 may be formed by sputtering, and the second electroplated metal layer 422 may be formed by electroplating.
  • the second seed metal layer 421 includes an MTD alloy (molybdenum-titanium-nickel alloy) layer and a copper layer sequentially stacked on the side of the interlayer dielectric layer 360 away from the base substrate 110 , wherein the thickness of the MTD alloy layer is 30 ⁇ 30. 50 nanometers, and the thickness of the copper layer is 200 to 400 nanometers.
  • MTD alloy mobdenum-titanium-nickel alloy
  • the material of the second electroplated metal layer 422 may be copper, and the thickness of the second electroplated metal layer 422 may be 2 ⁇ 5 ⁇ m.
  • the source-drain metal layer 370 may be formed by the following methods: forming a second seed metal material layer on the side of the interlayer dielectric layer 360 away from the base substrate 110; A removable pattern-defining layer is formed on the surface of the seed metal material layer away from the base substrate 110, the removable pattern-defining layer is provided with lead openings, and the lead openings expose a portion of the second seed metal material layer; electroplating process is used in the lead openings forming a second electroplating metal material layer on the surface of the second seed metal material layer; removing the removable pattern defining layer; removing the part of the second seed metal material layer not covered by the second electroplating metal material layer to form a source and drain Metal layer 370 .
  • the second electroplated metal material layer may be used as a mask, and the part of the second seed metal material layer that is not covered by the second electroplated metal material layer may be removed by etching; The remaining portion forms the second seed metal layer 421 , and the remaining portion of the second electroplating metal material layer forms the second electroplating metal layer 422 .
  • the array substrate may further include a third passivation layer 603 , and the third passivation layer 603 is located on the side of the source-drain metal layer 370 away from the base substrate 110 for protection
  • the source-drain metal layer 370 prevents the active metal (eg copper) in the source-drain metal layer 370 from being corroded.
  • the thickness of the third passivation layer 603 is 100-200 nanometers, and the material may be silicon oxynitride.
  • the source-drain metal layer 370 is directly connected to the functional device 141 .
  • the electrode layer 390 for electrical connection with the functional device 141 on the side of the source-drain metal layer 370 away from the base substrate 110 , which can further reduce the number of film layers of the array substrate and the preparation process, especially further The number of mask processes is reduced, the fabrication cost of the array substrate is reduced, and the thinning of the array substrate is facilitated.
  • the first driving circuit 200 may further include a storage capacitor; as shown in FIG. 2 and FIG. 3 , the first gate layer 310 further includes a first electrode plate 312 for storing capacitors, and the second gate layer 350 further includes a storage capacitor The second electrode plate 352 of the capacitor.
  • the storage capacitor can be formed by the first gate layer 310 and the second gate layer 350, without the need to form the storage capacitor by the source-drain metal layer 370, the shape of the source-drain metal layer 370 can be simplified, and the preparation of the array substrate is facilitated; not only that , compared with the technical solution of using the source-drain metal layer 370 to prepare the storage capacitor, this solution has smaller parasitic capacitance, which can reduce the influence of the parasitic capacitance on the performance of the array substrate.
  • the second electrode plate 352 of the storage capacitor can be electrically connected to the second gate 351 of the driving transistor, for example, the two can reuse the same electrode plate, or through an electrode located on the second gate
  • the gate connection leads of the layers are connected to each other.
  • the gate bridge lead 373 may not be directly connected with the second gate 351 of the driving transistor, but may be connected with the second electrode plate 352 of the storage capacitor or the gate connecting lead, so that the gate The bridge lead 373 is electrically connected to the second gate 351 of the driving transistor.
  • the first electrode plate 312 of the storage capacitor may be connected to the source-drain metal layer 370 , so that the first electrode plate is directly or indirectly connected to the source or drain of the driving transistor through the source-drain metal layer 370 .
  • the first driving circuit 200 further includes a switch transistor; referring to FIG. 15 , the semiconductor layer 330 further includes an active layer 332 of the switch transistor, and the active layer 332 of the switch transistor has a channel region 3321 of the switch transistor.
  • a channel region of the driving transistor width W D 3311 is greater than the width of the channel region of the switching transistor is W S 3321.
  • the driving transistor 210 has a channel region with a larger width, which can increase the saturation current of the driving transistor 210 and further improve the ability of the driving transistor 210 to drive the functional device 141 .
  • the width of the channel region refers to the size of the channel region along the direction perpendicular to the carrier migration in the plane where the semiconductor layer 330 is located.
  • the first driving circuit 200 may include one or more switching transistors according to functional requirements.
  • the switching transistors may include a data writing transistor for controlling the writing of data signals into the driving circuit, for controlling whether to The enabling transistor (EM) for forming the driving current, the reset transistor for controlling the reset signal, the initialization transistor for controlling the initialization of some nodes of the first driving circuit 200 , etc., will not be described in detail in this disclosure. .
  • a first driving circuit 200 is exemplarily provided, so as to further explain and illustrate the structure and principle of the array substrate provided by the present disclosure.
  • the exemplary first driving circuit 200 is a driving circuit with a 2T1C (2 transistors and 1 storage capacitor 220 ) structure, which includes a driving transistor 210 and a switching transistor serving as a data writing transistor 230 and a storage capacitor 220.
  • the source of the drive transistor is connected to the power supply lead 502 and the first electrode plate of the storage capacitor, the drain of the drive transistor is used to connect to the functional device 141, and the first and second gates of the drive transistor 210 are connected to the storage capacitor connected to the second electrode plate.
  • the source of the switch transistor is connected to the data lead 503, the gate of the switch transistor is connected to the scan lead 354, and the drain of the switch transistor is connected to the second electrode plate of the storage capacitor.
  • the driving circuit layer 130 includes a first gate layer 310 , a first gate insulating layer 320 , a semiconductor layer 330 , a second gate insulating layer 340 , a second gate insulating layer 340 , a second gate insulating layer The gate layer 350 , the interlayer dielectric layer 360 and the source-drain metal layer 370 .
  • the first gate layer 310 includes a first gate electrode 311 of a driving transistor and a first electrode plate 312 of a storage capacitor.
  • the first gate insulating layer 320 (not shown in FIGS. 17 and 18 ) covers the first gate layer 310 .
  • the semiconductor layer 330 includes an active layer 331 of a driving transistor and an active layer 332 of a switching transistor; wherein, the active layer 331 of the driving transistor includes a source contact region, a drain contact region and a trench channel region, the orthographic projection of the channel region of the driving transistor on the first gate layer 310 is located in the first gate 311 , and at least part of the first gate 311 and the active layer 331 of the driving transistor are in the first gate layer 310 The orthographic projections do not overlap; the active layer 332 of the switching transistor includes a source contact region, a drain contact region, and a channel region.
  • the second gate insulating layer 340 (not shown in FIGS. 17 and 19 ) covers the semiconductor layer 330 .
  • the second gate layer 350 is disposed on the side of the second gate insulating layer 340 away from the base substrate 110 , and includes the scan lead 354 , the second gate 351 of the driving transistor, and the storage capacitor.
  • the second electrode plate 352 and the gate connection lead 353 are connected.
  • the orthographic projection of the scan line 354 on the semiconductor layer 330 overlaps with the channel region 3321 of the switch transistor, so that the scan line 354 can be multiplexed as the gate of the switch transistor 230 .
  • the orthographic projection of the second gate 351 of the driving transistor on the semiconductor layer 330 covers the channel region 3311 of the driving transistor; the orthographic projection of the second electrode plate 352 of the storage capacitor on the first electrode layer 390 is the same as that of the storage capacitor.
  • An electrode plate 312 at least partially overlaps; the gate connecting lead 353 connects the second gate 351 of the driving transistor and the second electrode plate 352 of the storage capacitor.
  • An interlayer dielectric layer 360 (not shown in FIG. 17 and FIG. 21 ) is provided on the side of the second gate layer 350 away from the base substrate 110 , wherein the interlayer dielectric layer 360 is provided with eight via holes.
  • the positions of eight via holes are shown in FIGS. 17 and 21 , wherein the first via hole 701 penetrates through the interlayer dielectric layer 360 , the second gate insulating layer 340 and the first gate insulating layer 320 , exposing the driving transistors.
  • the second via 702 penetrates through the interlayer dielectric layer 360 and the second gate insulating layer 340, exposing at least part of the second gate 351 of the driving transistor;
  • the third via 703 penetrates The interlayer dielectric layer 360 and the second gate insulating layer 340 expose at least part of the source contact region 3322 of the switching transistor;
  • the fourth via 704 penetrates the interlayer dielectric layer 360 and the second gate insulating layer 340 and exposes the switch At least part of the drain contact region 3323 of the transistor;
  • the fifth via hole 705 penetrates through the interlayer dielectric layer 360, exposing at least part of the second electrode plate 352 of the storage capacitor;
  • the sixth via hole 706 penetrates through the interlayer dielectric layer 360,
  • the second gate insulating layer 340 and the first gate insulating layer 320 expose at least part of the first electrode plate 312 of the storage capacitor;
  • the seventh via hole 707 penetrates through the interlayer dielectric layer 360 and the second gate insulating layer 340, At least part of
  • the source-drain metal layer 370 is disposed on the side of the interlayer dielectric layer 360 away from the base substrate 110 , and includes a second conductive seed layer and a second electroplating metal layer 422 stacked in sequence.
  • the source-drain metal layer 370 includes a data lead 503, a power lead 502, a second electrode 501, a gate bridge lead 373, the source 374 of the switching transistor, the drain 375 of the switching transistor, the source 371 of the driving transistor, and the drain of the driving transistor Pole 372.
  • the gate bridge lead 373 is connected to the first gate 311 of the driving transistor through the first via 701 , the gate bridge lead 373 is connected to the second gate 351 of the drive transistor through the second via 702 ; the data lead 503 is connected The source 374 of the switching transistor; the source 374 of the switching transistor is connected to the source contact region 3322 of the switching transistor through the third via 703; the drain 375 of the switching transistor is connected to the source contact 3322 of the switching transistor through the fourth via 704 , and is connected to the second electrode plate 352 of the storage capacitor through the fifth via hole 705 ; the power lead 502 is connected to the source electrode 371 of the driving transistor; the source electrode 371 of the driving transistor is connected to the first electrode plate 312 of the storage capacitor through the sixth via hole 706 ; The source 371 of the drive transistor is connected to the source contact region 3312 of the drive transistor through the seventh via 707 ; the drain 372 of the drive transistor is connected to the drain contact region 3313 of the drive transistor through the eighth via 708 .
  • the functional device layer 140 is provided on the side of the driving circuit layer 130 away from the base substrate 110 , which may include functional devices 141 distributed in an array, for example, including light-emitting devices for emitting light, It is used for an ultrasonic emitting device for emitting ultrasonic waves, a heating device for generating heat, or other current-driven functional devices 141 .
  • the functional device 141 is electrically connected to the driving circuit layer 130 through the conductive connector 142 .
  • the material of the conductive connector 142 can be conductive glue, solder paste or other conductive materials with adhesive ability.
  • the functional device 141 may be an LED, a Mini LED or a Micro LED, and the Mini LED or the Micro LED may be electrically connected to the driving circuit layer 130 through solder paste.
  • Embodiments of the present disclosure further provide a display panel, which includes any of the array substrates described in the foregoing array substrate embodiments, wherein the functional device 141 of the array substrate is a light-emitting device.
  • the display panel may be an OLED display panel, a Micro LED display panel, a Mini LED display panel or other types of display panels. Since the display panel has an array substrate in which any one of the functional devices 141 described in the foregoing array substrate embodiments is a light-emitting device, it has the same beneficial effects, and details are not described herein again.
  • the functional device 141 may be a Micro LED or a Mini LED.
  • the present disclosure also provides a method for preparing an array substrate, the method for preparing an array substrate includes sequentially forming a driving circuit layer 130 and a functional device layer 140 on one side of the base substrate 110 : wherein the driving circuit layer 130 is provided with a first driving circuit In the circuit 200, the first drive circuit 200 at least includes a drive transistor 210; as shown in FIG. 23, forming the drive circuit layer 130 includes:
  • Step S110 as shown in FIG. 5 , a first gate layer 310 is formed on one side of the base substrate 110 , and the first gate layer 310 includes a first gate 311 of the driving transistor;
  • Step S120 as shown in FIG. 5 , a first gate insulating layer 320 is formed on the side of the first gate layer 310 away from the base substrate 110 ;
  • a semiconductor layer 330 is formed on the side of the first gate layer 310 away from the base substrate 110.
  • the semiconductor layer 330 includes the active layer 331 of the driving transistor, and the active layer 331 of the driving transistor has a driving The channel region 3311 of the transistor; the orthographic projection of the first gate 311 of the driving transistor on the semiconductor layer 330 at least partially overlaps the channel region 3311 of the same driving transistor;
  • Step S140 as shown in FIG. 6 , a second gate insulating layer 340 is formed on the side of the semiconductor layer 330 away from the base substrate 110 ;
  • Step S150 as shown in FIG. 6 , a second gate layer 350 is formed on the side of the second gate insulating layer 340 away from the base substrate 110 , and the second gate layer 350 includes the second gate 351 of the driving transistor; driving The orthographic projection of the second gate 351 of the transistor on the semiconductor layer 330 at least partially overlaps with the channel region 3311 of the same driving transistor; the first gate 311 of the same driving transistor can be electrically connected to the second gate;
  • Step S160 as shown in FIG. 7 , an interlayer dielectric layer 360 is formed on the side of the second gate layer 350 away from the base substrate 110 ;
  • Step S170 as shown in FIG. 8 or FIG. 10 , a source-drain metal layer 370 is formed on the side of the interlayer dielectric layer 360 away from the base substrate 110 , the source-drain metal layer 370 is connected to the active layer 331 of the driving transistor, and the source-drain metal layer 370 is The metal layer 370 includes the source electrode 371 and the drain electrode of the driving transistor.
  • the method for preparing an array substrate can prepare any one of the array substrates described in the above-mentioned embodiments of the array substrate.
  • the details, principles and effects of each step of the manufacturing method of the array substrate have been described and introduced in detail in the above-mentioned embodiments of the array substrate, or can be clearly deduced from the description of the above-mentioned embodiments of the array substrate. It is not repeated here.
  • forming the interlayer dielectric layer 360 on the side of the second gate layer 350 away from the base substrate 110 includes:
  • a patterning operation is performed to form an interlayer dielectric material layer on the side of the second gate layer 350 away from the base substrate 110 to form a first via hole 701 exposing at least a partial region of the first gate electrode 311 of the driving transistor and to form a patterning operation.
  • a second via hole 702 exposing at least a partial region of the second gate electrode 351 of the driving transistor;
  • Forming the source-drain metal layer 370 on the side of the interlayer dielectric layer 360 away from the base substrate 110 includes:
  • a source-drain metal material layer is formed on the side of the interlayer dielectric layer 360 away from the base substrate 110;
  • the source-drain metal material layer is patterned to form the source electrode 371, the drain electrode and the gate bridge lead 373 of the driving transistor, wherein the gate bridge lead 373 is connected to the first via hole 701 and the first The gate is connected, and the gate bridge lead 373 is connected to the second gate through the second via hole 702 .
  • forming the driving circuit layer 230 may further include:
  • a third passivation layer 603 is formed on the side of the source-drain metal layer 370 away from the base substrate.
  • forming the driving circuit layer 230 may further include:
  • a planarization layer 380 is formed on the side of the source-drain metal layer 370 away from the base substrate;
  • an electrode layer 390 is formed on the side of the planarization layer 380 away from the base substrate;
  • a second passivation layer 602 is formed on the side of the electrode layer 390 away from the base substrate.

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Abstract

一种阵列基板及其制备方法、显示面板。该阵列基板包括依次层叠的衬底基板（110）、驱动电路层（130）和功能器件层（140）：其中，驱动电路层设置有第一驱动电路（200），第一驱动电路至少包括驱动晶体管（210）；驱动电路层包括依次层叠于衬底基板的一侧的第一栅极层（310）、第一栅极绝缘层（320）、半导体层（330）、第二栅极绝缘层（340）、第二栅极层（350）、层间电介质层（360）和源漏金属层（370）。第一栅极层包括驱动晶体管的第一栅极（311），半导体层包括驱动晶体管的沟道区（3311），第二栅极层包括驱动晶体管的第二栅极（351），驱动晶体管的第一栅极和驱动晶体管的第二栅极电连接。该阵列基板能够提高驱动晶体管的饱和电流。

Description

阵列基板及其制备方法、显示面板
交叉引用
本公开要求于2020年6月29日提交的申请号为202010610164.1、名称均为“阵列基板及其制备方法、显示面板”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
背景技术
驱动Micro LED(微发光二极管)等电流驱动的发光器件时需要较大的驱动电流。然而，现有的显示面板的驱动电路难以提供较大的驱动电流，尤其是驱动晶体管容易受到浮体效应的影响而导致饱和电流降低。这制约了Micro LED显示面板的显示质量的提升。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种阵列基板及其制备方法、显示面板，提高驱动晶体管的饱和电流。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种阵列基板，包括依次层叠的衬底基板、驱动电路层和功能器件层：其中，所述驱动电路层设置有第一驱动电路，所述第一驱动电路至少包括驱动晶体管；
所述驱动电路层包括依次层叠于所述衬底基板的第一栅极层、第一栅极绝缘层、半导体层、第二栅极绝缘层、第二栅极层、层间电介质层和源漏金属层；其中，所述第一栅极层包括所述驱动晶体管的第一栅极； 所述半导体层包括所述驱动晶体管的有源层，所述驱动晶体管的有源层具有所述驱动晶体管的沟道区；所述驱动晶体管的第一栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；所述第二栅极层包括驱动晶体管的第二栅极；所述驱动晶体管的第二栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；所述源漏金属层包括所述驱动晶体管的源极和漏极；
其中，同一所述驱动晶体管的第一栅极和第二栅极通过所述源漏金属层电连接；所述功能器件层包括功能器件，所述功能器件与所述驱动晶体管的漏极电连接。
在本公开的一种示例性实施例中，所述源漏金属层还包括所述驱动晶体管的栅极桥接引线；同一所述驱动晶体管中，所述第一栅极和所述第二栅极均与所述栅极桥接引线连接。
在本公开的一种示例性实施例中，所述驱动电路层包括第一过孔和第二过孔；
所述第一过孔贯穿所述层间电介质层、所述第二栅极绝缘层和所述第一栅极绝缘层，且暴露所述驱动晶体管的第一栅极的至少部分区域；所述第二过孔贯穿所述层间电介质层和所述第二栅极绝缘层，且暴露所述驱动晶体管的第二栅极的至少部分区域；
所述栅极桥接引线通过所述第一过孔与所述第一栅极连接，且通过所述第二过孔与所述第二栅极连接。
在本公开的一种示例性实施例中，所述第一驱动电路还包括存储电容；所述第一栅极层还包括所述存储电容的第一电极板，所述第二栅极层还包括所述存储电容的第二电极板。
在本公开的一种示例性实施例中，所述第一驱动电路还包括开关晶体管；所述半导体层还包括所述开关晶体管的有源层，所述开关晶体管的有源层具有所述开关晶体管的沟道区；所述驱动晶体管的沟道区的宽度，大于所述开关晶体管的沟道区的宽度。
在本公开的一种示例性实施例中，所述半导体层的材料包括低温多晶硅。
在本公开的一种示例性实施例中，所述半导体层的厚度为30～60纳 米。
在本公开的一种示例性实施例中，所述驱动电路层还包括：
平坦化层，设于所述源漏金属层远离所述衬底基板的一侧；
电极层，设于所述平坦化层远离所述衬底基板的一侧，且厚度大于1微米；所述电极层包括第二电极和所述第一驱动电路的第一电极；同一所述第一驱动电路中，所述第一电极与所述驱动晶体管的漏极连接；
所述功能器件连接所述第二电极和所述第一电极。
在本公开的一种示例性实施例中，所述电极层包括：
第一种子金属层，设于所述源漏金属层远离所述衬底基板的一侧，且与所述驱动晶体管的漏极连接；所述第一种子金属层的厚度不大于1微米；
第一电镀金属层，设于所述第一种子金属层远离所述衬底基板的一侧；所述第一电镀金属层的厚度为1～20微米；
所述功能器件与所述第一电镀金属层连接。
在本公开的一种示例性实施例中，所述电极层还包括电源引线，所述电源引线与所述驱动晶体管的源极连接。
在本公开的一种示例性实施例中，所述源漏金属层包括：
第二种子金属层，设于所述层间电介质层远离所述衬底基板的一侧且与所述驱动晶体管的有源层连接；所述第二种子金属层的厚度不大于1微米；
第二电镀金属层，设于所述第二种子金属层远离所述衬底基板的一侧；所述第二电镀金属层的厚度为1～20微米。
在本公开的一种示例性实施例中，源漏金属层还包括第二电极和电源引线；所述电源引线与所述驱动晶体管的源极连接，所述功能器件连接所述第二电极和所述驱动晶体管的漏极。
根据本公开的第二个方面，提供一种显示面板，包括上述的阵列基板。
根据本公开的第三个方面，提供一种阵列基板的制备方法，包括在衬底基板的一侧依次形成驱动电路层和功能器件层：其中，所述驱动电路层设置有第一驱动电路，所述第一驱动电路至少包括驱动晶体管；形 成所述驱动电路层包括：
在所述衬底基板的一侧形成第一栅极层，所述第一栅极层包括所述驱动晶体管的第一栅极；
在所述第一栅极层远离所述衬底基板的一侧形成第一栅极绝缘层；
在所述第一栅极层远离所述衬底基板的一侧形成半导体层，所述半导体层包括驱动晶体管的有源层，所述驱动晶体管的有源层具有所述驱动晶体管的沟道区；所述驱动晶体管的第一栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；
在所述半导体层远离所述衬底基板的一侧形成第二栅极绝缘层；
在所述第二栅极绝缘层远离所述衬底基板的一侧形成第二栅极层，所述第二栅极层包括驱动晶体管的第二栅极；所述驱动晶体管的第二栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；同一所述驱动晶体管的所述第一栅极能够与所述第二栅极电连接；
在所述第二栅极层远离所述衬底基板的一侧形成层间电介质层；
在所述层间电介质层远离所述衬底基板的一侧形成源漏金属层，所述源漏金属层与所述驱动晶体管的有源层连接，所述源漏金属层包括所述驱动晶体管的源极和漏极。
在本公开的一种示例性实施例中，在所述第二栅极层远离所述衬底基板的一侧形成层间电介质层包括：
在所述第二栅极层远离所述衬底基板的一侧形成层间电介质材料层；
对所述在所述第二栅极层远离所述衬底基板的一侧形成层间电介质材料层进行图案化操作，以形成暴露所述驱动晶体管的第一栅极的至少部分区域的第一过孔和形成暴露所述驱动晶体管的第二栅极的至少部分区域的第二过孔；
在所述层间电介质层远离所述衬底基板的一侧形成源漏金属层包括：
在所述层间电介质层远离所述衬底基板的一侧形成源漏金属材料层；
对所述源漏金属材料层进行图案化操作，以形成所述驱动晶体管的源极、漏极和栅极桥接引线，其中，所述栅极桥接引线通过所述第一过孔与所述第一栅极连接，所述栅极桥接引线通过所述第二过孔与所述第二栅极连接。
本公开提供的阵列基板及其制备方法、显示面板中，驱动电路层包括依次层叠于衬底基板的一侧的第一栅极层、第一栅极绝缘层、半导体层、第二栅极绝缘层、第二栅极层、层间电介质层和源漏金属层。其中，驱动晶体管的沟道区位于驱动晶体管的第一栅极和驱动晶体管的第二栅极之间，可以避免或者减弱驱动晶体管的浮体效应，消除浮体效应导致的驱动晶体管的饱和电流的降低，使得驱动晶体管具有更大的饱和电流。如此，该第一驱动电路可以为功能器件提供更大的驱动电流，避免驱动电流不足对功能器件的性能的影响，提高阵列基板性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1为本公开的一种实施方式中的阵列基板的结构示意图。
图2为本公开的一种实施方式中的阵列基板的结构示意图。
图3为本公开的一种实施方式中的阵列基板的结构示意图。
图4为本公开的一种实施方式中的驱动晶体管的第一电极、有源层和第二电极的俯视结构示意图。
图5为本公开的一种实施方式中形成半导体层的结构示意图。
图6为本公开的一种实施方式中形成第二栅极层的结构示意图。
图7为本公开的一种实施方式中形成层间电介质层的结构示意图。
图8为本公开的一种实施方式中形成源漏金属层的结构示意图。
图9为本公开的一种实施方式中形成第三钝化层的结构示意图。
图10为本公开的一种实施方式中形成源漏金属层的结构示意图。
图11为本公开的一种实施方式中形成平坦化层和第一钝化层的结构示意图。
图12为本公开的一种实施方式中形成电极层的结构示意图。
图13为本公开的一种实施方式中形成第二钝化层的结构示意图。
图14为本公开的一种实施方式中驱动晶体管的有源层的结构示意 图。
图15为本公开的一种实施方式中开关晶体管的有源层的结构示意图。
图16为本公开的一种实施方式中一种第一驱动电路的等效电路图。
图17为本公开的一种实施方式中第一栅极层、半导体层、第二栅极层和源漏金属层的俯视示意图。
图18为本公开的一种实施方式中第一栅极层的俯视示意图。
图19为本公开的一种实施方式中半导体层的俯视示意图。
图20为本公开的一种实施方式中第二栅极层的俯视示意图。
图21为本公开的一种实施方式中源漏金属层的俯视示意图。
图22为本公开的一种实施方式中，沿图17中的AA＇进行剖切时阵列基板的结构示意图。
图23为本公开的一种实施方式中驱动电路层的制备方法的流程示意图。
图24为单栅型晶体管和双栅型晶体管的输出曲线比较图。
图中主要元件附图标记说明如下：
110、衬底基板；120、缓冲层；130、驱动电路层；140、功能器件层；141、功能器件；142、导电连接件；200、第一驱动电路；210、驱动晶体管；220、存储电容；230、开关晶体管；310、第一栅极层；311、驱动晶体管的第一栅极；312、存储电容的第一电极板；320、第一栅极绝缘层；330、半导体层；331、驱动晶体管的有源层；3311、驱动晶体管的沟道区；3312、驱动晶体管的源极接触区；3313、驱动晶体管的漏极接触区；332、开关晶体管的有源层；3321、开关晶体管的沟道区；3322、开关晶体管的源极接触区；3323、开关晶体管的漏极接触区；340、第二栅极绝缘层；350、第二栅极层；351、驱动晶体管的第二栅极；352、存储电容的第二电极板；353、栅极连接引线；354、扫描引线；360、层间电介质层；370、源漏金属层；371、驱动晶体管的源极；372、驱动晶体管的漏极；373、栅极桥接引线；374、开关晶体管的源极；375、开关晶体管的漏极；380、平坦化层；390、电极层；391、第 一电极；411、第一种子金属层；412、第一电镀金属层；421、第二种子金属层；422、第二电镀金属层；501、第二电极；502、电源引线；503、数据引线；601、第一钝化层；602、第二钝化层；603、第三钝化层；701、第一过孔；702、第二过孔；703、第三过孔；704、第四过孔；705、第五过孔；706、第六过孔；707、第七过孔；708、第八过孔。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种阵列基板，如图1所示，该阵列基板包括依次层叠的衬底基板110、驱动电路层130和功能器件层140：其中，驱动电路层130设置有第一驱动电路200，第一驱动电路200至少包括驱动晶体管210。
图2和图3进一步示意了阵列基板的结构。其中，在图2和图3中，尽管驱动晶体管的第二栅极351呈现为不相连的两部分，但这是驱动晶体 管的第二栅极351在特定的剖切位置呈现的断面状态；可以理解的是，驱动晶体管的第二栅极351为一个连续地整体结构，当一些选择其他的剖切位置时，驱动晶体管的第二栅极351的断面为不分割的整体结构。
如图2和图3所示，驱动电路层130包括依次层叠于衬底基板110的一侧的第一栅极层310、第一栅极绝缘层320、半导体层330、第二栅极绝缘层340、第二栅极层350、层间电介质层360和源漏金属层370；其中，第一栅极层310包括驱动晶体管的第一栅极311；半导体层330包括驱动晶体管的有源层331。如图4和图14所示，驱动晶体管的有源层331具有驱动晶体管的沟道区3311；驱动晶体管的第一栅极311在半导体层330的正投影，与同一驱动晶体管的沟道区3311至少部分重合；第二栅极层350包括驱动晶体管的第二栅极351；驱动晶体管的第二栅极351在半导体层330的正投影，与同一驱动晶体管的沟道区3311至少部分重合；源漏金属层370与驱动晶体管的有源层331连接，源漏金属层370包括驱动晶体管的源极371和漏极372；
其中，同一驱动晶体管的第一栅极311和第二栅极351通过源漏金属层370电连接；功能器件层140包括功能器件141，功能器件141与驱动晶体管的漏极372电连接。
本公开提供的阵列基板中，驱动电路层130包括依次层叠于衬底基板110的一侧的第一栅极层310、第一栅极绝缘层320、半导体层330、第二栅极绝缘层340、第二栅极层350、层间电介质层360和源漏金属层370。其中，驱动晶体管的沟道区3311位于驱动晶体管的第一栅极311和驱动晶体管的第二栅极351之间，可以避免或者减弱驱动晶体管210的浮体效应，消除浮体效应导致的驱动晶体管210的饱和电流的降低，使得驱动晶体管210具有更大的饱和电流。如此，该第一驱动电路200可以为功能器件141提供更大的驱动电流，避免驱动电流不足对功能器件141的性能的影响，提高阵列基板性能。不仅如此，第一栅极311和第二栅极351之间通过源漏金属层370电连接，可以无需在制备第二栅极层350之前对第二栅极绝缘层340进行图案化操作，可以减少阵列基板制备过程中的图案化操作，减少掩膜板的数量，进而降低阵列基板的制备成本。
其中，本公开中，驱动晶体管210的饱和电流指的是，当驱动晶体管 210完全导通时，饱和晶体管的漏电流。
下面，结合附图对本公开提供的阵列基板的结构、原理和效果做进一步地解释和说明。
衬底基板110可以为无机材料的衬底基板110，也可以为有机材料的衬底基板110。举例而言，在本公开的一种实施方式中，衬底基板110的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板110的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板110也可以为柔性衬底基板110，例如衬底基板110的材料可以为聚酰亚胺(polyimide，PI)。衬底基板110还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板110可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
可选地，如图2和图3所示，在衬底基板110的一侧还可以设置有缓冲层120，驱动电路层130设于缓冲层120远离衬底基板110的一侧。缓冲层120可以包括无机绝缘材料，例如可以包括氮化硅、氧化硅、氮氧化硅等。举例而言，在本公开的一种实施方式中，缓冲层120包括依次层叠于衬底基板110的氮化硅层和氧化硅层，其中，氮化硅层的厚度为40～60纳米，氧化硅层的厚度为180～220纳米。
如图1所示，驱动电路层130可以具有多个第一驱动电路200，任意一个第一驱动电路200可以具有驱动晶体管210。如图4所示，驱动晶体管210可以包括有源层331、第一栅极311、第二栅极351、源极371(图4中未示出)和漏极372(图4中未示出)，其中，有源层331和第一栅极311之间被第一栅极绝缘层320隔离，有源层331和第二栅极351之间被第二栅极绝缘层340隔离。有源层331可以包括沟道区3311以及位于沟道区3311两侧的源极接触区3312和漏极接触区3313，源极接触区3312 与源极371电连接，漏极接触区3313与漏极372电连接。由于第一栅极311和第二栅极351相互电连接，第一栅极311和第二栅极351之间可以具有相同的电压，能够有效的隔离有源层351和衬底基板110，避免有源层351与衬底基板110之间形成电容和产生电荷累积，进而可以减弱或者消除驱动晶体管210的浮体效应。当第一栅极311和第二栅极351加载有与数据电压相关的驱动信号时，第一栅极311和第二栅极351所产生的电场可以同时作用于驱动晶体管的沟道区3311，使得沟道区3311能够更有效、更准确地响应数据电压而输出驱动电流。不仅如此，第一栅极311和第二栅极351相互电连接，还可以避免第一栅极311和第二栅极351之间形成寄生电容，避免寄生电容对第一驱动电路200的影响。
图24给出了一些单栅型晶体管的输出曲线和双栅型晶体管的输出曲线。单栅型晶体管只具有一个栅极，该栅极可以位于有源层远离衬底基板的一侧或者位于有源层靠近衬底基板的一侧。双栅型晶体管在有源层的两侧均有栅极，且沟道区夹设于两个栅极之间。示例性地，本公开的驱动晶体管为双栅型晶体管。在图24中，DG-25/5和DG-500/25为双栅型晶体管；其中，DG-25/5的沟道区的宽度为25微米，长度为5微米；DG-500/25的沟道区的宽度为500微米，长度为25微米。TG-25/5和TG-500/25为单栅型晶体管；其中，TG-25/5的沟道区的宽度为25微米，长度为5微米；TG-500/25的沟道区的宽度为500微米，长度为25微米。根据图24可以看出，在沟道区具有相同的宽(W)长(L)比的条件下，双栅型晶体管的饱和电流大于单栅型晶体管。
驱动晶体管的漏极372与功能器件141电连接。如此，第一驱动电路200可以通过驱动晶体管210驱动与之连接的功能器件141。在本公开的一种实施方式中，功能器件141可以为Micro LED、Mini LED等电流驱动的自发光器件，这些功能器件141可以形成阵列基板的子像素；则该第一驱动电路200可以作为驱动这些自发光器件的像素驱动电路。可以理解的是，在一些实施方式中，驱动电路层130还可以包括其他驱动电路，例如还可以包括用于指纹识别的第二驱动电路、用于触控的第三驱动电路等，本公开对驱动电路层130中是否包括其他驱动电路以及其他驱动电路的数量和种类等，不做特殊的限制。
可选地，第一栅极层310的材料可以选自导电材料，例如可以选择金属、导电性金属氧化物、导电性高分子、导电性复合材料或其组合。示例性的，金属可以选自铂、金、银、铝、铬、镍、铜、钼、钛、镁、钙、钡、钠、钯、铁、锰或其组合。示例性的，导电性金属氧化物可以选自氧化铟、氧化锡、铟锡氧化物、掺氟的氧化锡、掺铝的氧化锌、掺镓的氧化锌或其组合。示例性的，导电性高分子可以选自聚苯胺、聚吡咯、聚噻吩、聚乙炔、聚(3,4-伸乙基二氧噻吩)/聚苯乙烯磺酸(PEDOT/PSS)或其组合，导电性高分子中还可以添加有酸(例如盐酸、硫酸、磺酸等)、路易斯酸(例如氟化磷、氟化砷、氯化铁等)、卤素、碱金属等掺杂剂。示例性的，导电性复合材料可以选自分散有碳黑、石墨粉、金属微粒子等的导电性复合材料。
第一栅极层310可以为一层导电材料，也可以为多层导电材料的层叠。举例而言，在本公开的一种实施方式中，第一栅极层310可以包括依次层叠的第一导电材料层、第二导电材料层和第一导电材料层，即呈现三明治结构。其中，第一导电材料层可以选用耐腐蚀的金属或者合金，例如可以选用钼或者钛；第二导电材料层可以选用高导电率的金属或者合金，例如可以选用铜、铝、银等。再举例而言，在本公开的另一种实施方式中，第一栅极层310可以包括一层导电材料，例如第一栅极层310的材料可以为钼。第一栅极层310的厚度可以为30～100nm；可选地，栅极层的厚度可以为50nm。
可选地，可以先在衬底基板110的一侧形成第一栅极材料层，然后对第一栅极材料层进行图案化操作，以形成第一栅极层310。可选地，可以通过磁控溅射的方法形成第一栅极材料层。当然的，在一些其他实施方式中，还可以通过丝网印刷等方法直接形成第一栅极层310。
第一栅极绝缘层320设于第一栅极层310远离衬底基板110的一侧，其可以采用有机或者无机绝缘材料。可选地，第一栅极绝缘层320的材料可以为氧化硅、氮化硅、氮氧化硅或者其他无机绝缘材料。举例而言，在本公开的一种实施方式中，第一栅极绝缘层320的材料可以为氧化硅，厚度可以为60～150纳米。
可选地，可以通过物理气相沉积法、化学气相沉积法、旋涂法、丝网 印刷或者其他方法形成第一栅极绝缘层320，本公开对此不做限制。举例而言，在本公开的一种实施方式中，可以通过等离子体增强化学的气相沉积法(PECVD)，在第一栅极层310远离衬底基板110的一侧沉积一层二氧化硅，以形成第一栅极绝缘层320。
半导体层330设于第一栅极绝缘层320远离衬底基板110的一侧，其可以包括非晶硅半导体材料、低温多晶硅半导体材料、单晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型半导体材料。
可选地，在本公开的一种实施方式中，半导体层330的材料可以包括低温多晶硅。进一步地，半导体层330的厚度为30～60纳米，以避免厚度太小而降低驱动晶体管210的饱和电流。
在本公开的一种实施方式中，如图4所示，驱动晶体管的沟道区3311在第一栅极层310上的正投影，位于驱动晶体管的第一栅极311内；驱动晶体管的沟道区3311在第二栅极层350上的正投影，位于驱动晶体管的第二栅极351内。如此，驱动晶体管的沟道区3311可以受到第一栅极和第二栅极的完全控制，可以消除驱动晶体管210的浮体效应，保证驱动晶体管210具有大的饱和电流。
可选地，可以先在第一栅极绝缘层320远离衬底基板110的一侧形成一层低温多晶硅材料层，然后对低温多晶硅材料层进行图案化处理，以形成半导体层330。可选地，可以先通过等离子体增强化学的气相沉积法，在第一栅极绝缘层320远离衬底基板110的一侧形成一层非晶硅层，然后利用准分子激光扫描非晶硅层，使得非晶硅层晶化为非晶硅层。
第二栅极绝缘层340设于半导体层330远离衬底基板110的一侧，用于隔离半导体层330和第二栅极层350。第二栅极绝缘层340的材料和厚度，可以跟第一栅极绝缘层320相同，也可以不同。
在本公开的一种实施方式中，第二栅极绝缘层340的材料为氧化硅，厚度为60～200纳米。可以通过等离子体增强化学的气相沉积法形成第二栅极绝缘层340。
第二栅极层350设于第二栅极绝缘层340远离衬底基板110的一侧。第二栅极层350的材料和厚度，可以跟第一栅极层310相同，也可以不同。可选地，第二栅极层350的厚度大于第一栅极层310的厚度，以方便在第 二栅极层350制备阵列基板所需的栅极引线，并降低栅极引线的方阻。
在本公开的一种实施方式中，第二栅极层350的材料为钼，厚度为300～400纳米。
在本公开的一种实施方式中，可以通过磁控溅射的方法在第二栅极绝缘层340远离衬底基板110的一侧形成第二栅极材料层，然后对第二栅极材料层进行图案化处理，以形成第二栅极层350。
在本公开的一种实施方式中，第二栅极层350除了包括驱动晶体管的第二栅极351外，还可以包括用于向第一驱动电路200传输各种栅极信号的栅极引线，例如还可以包括用于传输扫描信号的扫描引线、用于传输复位信号的复位引线、用于传输初始化信号的初始化引线等引线中的一种或者多种。
层间电介质层360设于第二栅极层350远离衬底基板110的一侧，用于隔离第二栅极层350和源漏金属层370。可选地，层间电介质层360的材料可以为无机绝缘材料。
层间电介质层360可以包括一层绝缘材料，也可以包括多层层叠的绝缘材料。举例而言，在本公开的一种实施方式中，层间电介质层360可以包括依次层叠于第二栅极层350远离衬底基板110一侧的氮化硅层和氧化硅层，其中，氮化硅层的厚度为150～250纳米，氧化硅层的厚度为250～350纳米。
可选地，可以先在第二栅极层350远离衬底基板110的一侧形成层间电介质材料层，然后对层间电介质材料层进行图案化处理，以形成层间电介质层360。可选地，可以通过等离子体增强化学的气相沉积法形成层间电介质材料层。
在本公开的一种实施方式中，如图7所示，在形成层间电介质层360时，还可以形成暴露驱动晶体管的第一栅极311的至少部分区域的第一过孔701和形成暴露驱动晶体管的第二栅极351的至少部分区域的第二过孔702。换言之，在对层间电介质材料层进行图案化处理时，可以形成第一过孔701和第二过孔702，其中，第一过孔701贯穿层间电介质层360、第一栅极绝缘层320和第二栅极绝缘层340，第一过孔701在第一栅极层310上的正投影，位于驱动晶体管的第一栅极311上。第二过孔702贯穿 层间电介质层360和第二栅极绝缘层340，第二过孔702在第二栅极层350上的正投影，位于驱动晶体管的第二栅极351上。
如此，如图8和图10所示，在形成源漏金属层370时，可以使得源漏金属层370还包括驱动晶体管210的栅极桥接引线373；同一驱动晶体管210中，栅极桥接引线373通过第一过孔701连接第一栅极311，通过第二过孔702连接第二栅极351，使得第一栅极311和第二栅极351均与栅极桥接引线373电连接。如此，驱动晶体管的第一栅极311和第二栅极351可以通过栅极桥接引线373实现电连接。
不仅如此，如图5和图6所示，第一栅极绝缘层320和第二栅极绝缘层340可以无需进行图案化处理，而是在层间电介质材料层进行图案化时，一起进行图案化。如此，可以减少阵列基板制备过程中的图案化操作，进而降低阵列基板的制备成本。
可以理解的是，层间电介质层360还可以包括其他过孔，例如包括使得驱动晶体管的源极371、漏极372与驱动晶体管的有源层331连接的过孔等，本公开对此不做一一详述。
源漏金属层370设于层间电介质层360远离衬底基板110的一侧，包括驱动晶体管的源极371和漏极372。源漏金属层370可以直接与功能器件141连接，也可以作为转接层与功能器件141间接连接，本公开对此不做特殊的限制。
在一些实施方式中，如图2所示，源漏金属层370可以作为转接层与功能器件141间接连接。如图10所示，源漏金属层370可以包括驱动晶体管的源极371、驱动晶体管的漏极372、数据转接电极、电源转接电极等。
可选地，源漏金属层370的厚度可以不大于1微米，以方便通过磁控溅射的方法制备。举例而言，可以通过磁控溅射的方法在层间电介质层360远离衬底基板110的一侧沉积金属材料，以形成源漏金属材料层；然后对源漏金属材料层进行图案化，以形成源漏金属层370。
进一步地，源漏金属层370可以为一层金属材料，也可以为多层金属材料的层叠。举例而言，源漏金属层370可以包括依次层叠的第一导电材料层、第二导电材料层和第一导电材料层，即呈现三明治结构。其中，第 一导电材料层可以选用耐腐蚀的金属或者合金，例如可以选用钼或者钛；第二导电材料层可以选用高导电率的金属或者合金，例如可以选用铜、铝、银等。在本公开的一种实施方式中，源漏金属层370可以包括依次层叠设置的钛层、铝层和钛层。
如图2所示，驱动电路层130还可以包括平坦化层380和电极层390，其中，平坦化层380设于源漏金属层370远离衬底基板110的一侧；电极层390设于平坦化层380远离衬底基板110的一侧，且厚度大于1微米；电极层390包括第二电极501和第一驱动电路200的第一电极391；同一第一驱动电路200中，第一电极391与驱动晶体管的漏极372连接；功能器件141连接第二电极501和第一电极391。在本公开的一种实施方式中，第二电极501可以为公共电极；第一电极391可以为用于加载驱动信号的电极，例如可以为显示面板的像素电极。
如此，源漏金属层370可以作为转接层，使得阵列基板的第一电极391与驱动晶体管的漏极372电连接。由于电极层390的厚度大于1微米，因此电极层390的方阻小，可以减小第二电极501上的压降。
可选的，如图2所示，电极层390还可以包括用于传输电源电压的电源引线502，由于电极层390的厚度大于1微米，因此电极层390的方阻小，使得电源引线502的压降减小。
可选的，电极层390还可以包括用于传输数据信号的数据引线，由于电极层390的厚度大于1微米，因此电极层390的方阻小，使得数据引线的压降减小。
可选地，电极层390还可以包括用于与驱动器绑定的绑定焊盘。
进一步地，源漏金属层370还可以包括有第一源漏引线，其中，部分第一源漏引线与电源引线502连接，如此，可以进一步降低电源引线502的压降。部分第一源漏引线可以与数据引线连接，如此，可以进一步降低数据引线503的压降。部分第一源漏引线可以与第二电极501连接，如此，可以进一步降低第二电极501的压降。部分第一源漏引线可以与绑定焊盘连接。
可选地，如图2和图12所示，电极层390包括第一种子金属层411和第一电镀金属层412，其中，第一种子金属层411设于平坦化层380远 离衬底基板110的一侧，且与驱动晶体管的漏极372连接；第一种子金属层411的厚度不大于1微米；第一电镀金属层412设于第一种子金属层411远离衬底基板110的一侧；第一电镀金属层412的厚度为1～20微米；功能器件141与第一电镀金属层412电连接。如此，可以采用溅射的方法形成第一种子金属层411，采用电镀的方法形成第一电镀金属层412。
可选地，第一种子金属层411包括依次层叠于平坦化层380远离衬底基板110的一侧MTD合金(钼钛镍合金)层和铜层，其中，MTD合金层的厚度为30～50纳米，铜层的厚度为200～400纳米。
可选地，第一电镀金属层412的材料可以为铜，第一电镀金属层412的厚度可以为2～5微米。
示例性地，在本公开的一种实施方式中，可以通过如下方法形成电极层390：在平坦化层380远离衬底基板110的一侧形成第一种子金属材料层；在第一种子金属材料层远离衬底基板110的表面形成可移除的图案限定层，可移除的图案限定层设置有引线开口，引线开口暴露部分第一种子金属材料层；采用电镀工艺在引线开口内形成位于第一种子金属材料层表面的第一电镀金属材料层；移除可移除的图案限定层；去除第一种子金属材料层未被第一电镀金属材料层覆盖的部分，以形成源漏金属层370。可选地，可以以第一电镀金属材料层为掩膜板，通过刻蚀的方法去除第一种子金属材料层未被第一电镀金属材料层覆盖的部分；其中，第一种子金属材料层的剩余部分形成第一种子金属层411，第一电镀金属材料层的剩余部分形成第一电镀金属层412。如此，该电极层390可以采用“形成整面种子层-限定电镀图案-电镀金属-对种子层进行图案化”的策略进行制备，可以改善第一电镀金属层412的形貌。
可选地，如图2、图11和图12所示，阵列基板还可以包括第一钝化层601，第一钝化层601位于平坦化层380与电极层390之间，用于保护电极层390，避免电极层390中的活泼金属(例如铜)被侵蚀。可选地，第一钝化层601的厚度为100～200纳米，材料可以为氮氧化硅。
可选地，如图2和图13所示，阵列基板还可以包括第二钝化层602，第一钝化层601位于电极层390远离衬底基板110的一侧，用于保护电极层390，避免电极层390中的活泼金属(例如铜)被侵蚀。可选地，第二 钝化层602的厚度为100～200纳米，材料可以为氮氧化硅。
在上述所描述的实施方式中，源漏金属层370作为转接层而与电极层390连接。在一些情形下，源漏金属层370中的部分第一源漏引线还可以与电极层390上的导电结构并联，以便降低电极层390上的导电结构的方阻，减小信号的阻抗并提供大的电流。相较于相关技术中多层源漏结构层叠的技术方案，该实施方式通过电镀工艺增大电极层390的厚度，进而减少源漏结构的层叠的层数，可以减少阵列基板制备过程中的掩膜板数量，进而减少阵列基板的制备工序和降低阵列基板的制备成本。
在另外的一些实施方式中，源漏金属层370还直接与功能器件141连接。其中，如图3所示，源漏金属层370还可以包括驱动电路层130的第二源漏引线，第二源漏引线可以包括用于传输电源电压的电源引线、用于传输公共电压的第二电极、用于传输数据信号的数据引线等中的一种或者多种。其中，电源引线可以与驱动晶体管的源极371电连接，功能器件141的一端可以连接驱动晶体管的漏极372，另一端可以连接第二电极。进一步地，源漏金属层370还可以形成有绑定焊盘，绑定焊盘用于使得阵列基板与驱动器绑定。
进一步的，源漏金属层370的厚度可以大于1微米，以使得各个第二源漏引线具有较大的厚度，降低第二源漏引线的方阻，减小各个信号在第二源漏引线上的压降。
进一步地，如图3和图8所示，源漏金属层370可以包括层叠于层间电介质层360远离衬底基板110的一侧的第二种子金属层421和第二电镀金属层422。其中，第二种子金属层421设于层间电介质层360远离衬底基板110的一侧且与驱动晶体管的有源层331连接；第二种子金属层421的厚度不大于1微米；第二电镀金属层422设于第二种子金属层421远离衬底基板110的一侧；第二电镀金属层422的厚度为1～20微米。如此，可以采用溅射的方法形成第二种子金属层421，采用电镀的方法形成第二电镀金属层422。
可选地，第二种子金属层421包括依次层叠于层间电介质层360远离衬底基板110的一侧MTD合金(钼钛镍合金)层和铜层，其中，MTD合金层的厚度为30～50纳米，铜层的厚度为200～400纳米。
可选地，第二电镀金属层422的材料可以为铜，第二电镀金属层422的厚度可以为2～5微米。
示例性地，在本公开的一种实施方式中，可以通过如下方法形成源漏金属层370：在层间电介质层360远离衬底基板110的一侧形成第二种子金属材料层；在第二种子金属材料层远离衬底基板110的表面形成可移除的图案限定层，可移除的图案限定层设置有引线开口，引线开口暴露部分第二种子金属材料层；采用电镀工艺在引线开口内形成位于第二种子金属材料层表面的第二电镀金属材料层；移除可移除的图案限定层；去除第二种子金属材料层未被第二电镀金属材料层覆盖的部分，以形成源漏金属层370。可选地，可以以第二电镀金属材料层为掩膜板，通过刻蚀的方法去除第二种子金属材料层未被第二电镀金属材料层覆盖的部分；其中，第二种子金属材料层的剩余部分形成第二种子金属层421，第二电镀金属材料层的剩余部分形成第二电镀金属层422。
可选地，如图3和图9所示，阵列基板还可以包括有第三钝化层603，第三钝化层603位于源漏金属层370远离衬底基板110的一侧，用于保护源漏金属层370，避免源漏金属层370中的活泼金属(例如铜)被侵蚀。可选地，第三钝化层603的厚度为100～200纳米，材料可以为氮氧化硅。
在上述所描述的实施方式中，源漏金属层370直接与功能器件141连接。如此，可以无需在源漏金属层370远离衬底基板110的一侧再制备用于与功能器件141电连接的电极层390，可以进一步减少阵列基板的膜层数量并和制备工序，尤其是进一步减少掩膜工艺次数，降低阵列基板的制备成本并便于阵列基板的轻薄化。
可选地，第一驱动电路200还可以包括存储电容；如图2和图3所示，第一栅极层310还包括存储电容的第一电极板312，第二栅极层350还包括存储电容的第二电极板352。如此，可以通过第一栅极层310和第二栅极层350形成存储电容，无需借助源漏金属层370形成存储电容，可以简化源漏金属层370的形状，便于阵列基板的制备；不仅如此，相较于采用源漏金属层370制备存储电容的技术方案，该方案具有更小的寄生电容，可以减小寄生电容对阵列基板性能的影响。
进一步地，同一第一驱动电路200中，存储电容的第二电极板352可 以与驱动晶体管的第二栅极351电连接，例如两者可以复用同一电极板，或者通过一位于第二栅极层的栅极连接引线相互连接。如此，在一些实施方式中，栅极桥接引线373也可以不与驱动晶体管的第二栅极351直接连接，而是可以与存储电容的第二电极板352或者栅极连接引线连接，使得栅极桥接引线373与驱动晶体管的第二栅极351电连接。
存储电容的第一电极板312可以与源漏金属层370连接，使得第一电极板通过源漏金属层370直接或者间接连接至驱动晶体管的源极或者漏极。
可选地，第一驱动电路200还包括开关晶体管；参见图15，半导体层330还包括开关晶体管的有源层332，开关晶体管的有源层332具有开关晶体管的沟道区3321。驱动晶体管的沟道区3311的宽度W D，大于开关晶体管的沟道区3321的宽度W S。如此，驱动晶体管210具有更大宽度的沟道区，可以提高驱动晶体管210的饱和电流，进一步提高驱动晶体管210驱动功能器件141的能力。本公开中，沟道区的宽度指的是，在半导体层330所在的平面内，沿垂直于载流子迁移的方向，沟道区的尺寸。
可以理解的是，第一驱动电路200可以根据功能要求而包括一个或者多个开关晶体管，示例性地，开关晶体管可以包括用于控制数据信号写入驱动电路的数据写入晶体管、用于控制是否形成驱动电流的使能晶体管(EM)、用于控制复位信号的复位晶体管、用于控制对第一驱动电路200的部分节点进行初始化的初始化晶体管等等，本公开对此不做一一详细描述。
下面，示例性的提供一种第一驱动电路200，以便对本公开提供的阵列基板的结构和原理做更进一步地解释和说明。
如图16所示，该示例性的第一驱动电路200为一个2T1C(2个晶体管和1个存储电容220)架构的驱动电路，其包括一个驱动晶体管210、一个作为数据写入晶体管的开关晶体管230和一个存储电容220。其中，该驱动晶体管的源极连接电源引线502和存储电容的第一电极板，驱动晶体管的漏极用于与功能器件141连接，驱动晶体管210的第一栅极和第二栅极与存储电容的第二电极板连接。开关晶体管的源极与数据引线503连接，开关晶体管的栅极与扫描引线354连接，开关晶体管的漏极与存储电容的第二电极板连接。
示例性地，如图17和图22所示，驱动电路层130包括依次层叠的第一栅极层310、第一栅极绝缘层320、半导体层330、第二栅极绝缘层340、第二栅极层350、层间电介质层360和源漏金属层370。
如图17和图18所示，第一栅极层310包括驱动晶体管的第一栅极311和存储电容的第一电极板312。第一栅极绝缘层320(图17和图18中未示出)覆盖第一栅极层310。
如图17和图19所示，半导体层330包括驱动晶体管的有源层331和开关晶体管的有源层332；其中，驱动晶体管的有源层331包括源极接触区、漏极接触区和沟道区，驱动晶体管的沟道区在第一栅极层310的正投影位于第一栅极311内，且至少部分第一栅极311与驱动晶体管的有源层331在第一栅极层310的正投影不交叠；开关晶体管的有源层332包括源极接触区、漏极接触区和沟道区。第二栅极绝缘层340(图17和图19中未示出)覆盖半导体层330。
如图17和图20所示，第二栅极层350设于第二栅极绝缘层340远离衬底基板110的一侧，包括有扫描引线354、驱动晶体管的第二栅极351、存储电容的第二电极板352和栅极连接引线353。其中，扫描引线354在半导体层330上的正投影与开关晶体管的沟道区3321交叠，使得扫描引线354可以复用为开关晶体管230的栅极。驱动晶体管的第二栅极351在半导体层330上的正投影，覆盖驱动晶体管的沟道区3311；存储电容的第二电极板352在第一电极层390上的正投影，与存储电容的第一电极板312至少部分交叠；栅极连接引线353连接驱动晶体管的第二栅极351和存储电容的第二电极板352。
层间电介质层360(图17和图21中未示出)设于第二栅极层350远离衬底基板110的一侧，其中，层间电介质层360设置有八个过孔。图17和图21中示出了八个过孔的位置，其中，第一过孔701贯穿层间电介质层360、第二栅极绝缘层340和第一栅极绝缘层320，暴露驱动晶体管的第一栅极311的至少部分区域；第二过孔702贯穿层间电介质层360和第二栅极绝缘层340，暴露驱动晶体管的第二栅极351的至少部分区域；第三过孔703贯穿层间电介质层360和第二栅极绝缘层340，暴露开关晶体管的源极接触区3322的至少部分区域；第四过孔704贯穿层间电介质层 360和第二栅极绝缘层340，暴露开关晶体管的漏极接触区3323的至少部分区域；第五过孔705贯穿层间电介质层360，暴露存储电容的第二电极板352的至少部分区域；第六过孔706贯穿层间电介质层360、第二栅极绝缘层340和第一栅极绝缘层320，暴露存储电容的第一电极板312的至少部分区域；第七过孔707贯穿层间电介质层360和第二栅极绝缘层340，暴露驱动晶体管的源极接触区3312的至少部分区域；第八过孔708贯穿层间电介质层360和第二栅极绝缘层340，暴露驱动晶体管的漏极接触区3313的至少部分区域。
如图17和图21所示，源漏金属层370设于层间电介质层360远离衬底基板110的一侧，其包括依次层叠的第二导电种子层和第二电镀金属层422。源漏金属层370包括数据引线503、电源引线502、第二电极501、栅极桥接引线373、开关晶体管的源极374、开关晶体管的漏极375、驱动晶体管的源极371和驱动晶体管的漏极372。
其中，栅极桥接引线373通过第一过孔701与驱动晶体管的第一栅极311连接，栅极桥接引线373通过第二过孔702与驱动晶体管的第二栅极351连接；数据引线503连接开关晶体管的源极374；开关晶体管的源极374通过第三过孔703连接开关晶体管的源极接触区3322；开关晶体管的漏极375通过第四过孔704连接开关晶体管的源极接触区3322，且通过第五过孔705连接存储电容的第二电极板352；电源引线502连接驱动晶体管的源极371；驱动晶体管的源极371通过第六过孔706连接存储电容的第一电极板312；驱动晶体管的源极371通过第七过孔707连接驱动晶体管的源极接触区3312；驱动晶体管的漏极372通过第八过孔708连接驱动晶体管的漏极接触区3313。
可选地，如图1所示，功能器件层140设于驱动电路层130远离衬底基板110的一侧，其可以包含有阵列分布的功能器件141，例如包括用于发光的发光器件、用于发出超声波的超声波发射器件、用于产生热量的加热器件或者其他电流驱动的功能器件141。
可选的，如图2和图3所示，功能器件141通过导电连接件142与驱动电路层130电连接。该导电连接件142的材料可以为导电胶、锡膏或者其他具有粘合能力的导电材料。
示例性地，功能器件141可以为LED、Mini LED或者Micro LED，Mini LED或者Micro LED可以通过锡膏与驱动电路层130电连接。
本公开实施方式还提供一种显示面板，该显示面板包括上述阵列基板实施方式所描述的任意一种阵列基板，其中，阵列基板的功能器件141为发光器件。该显示面板可以为OLED显示面板、Micro LED显示面板、Mini LED显示面板或者其他类型的显示面板。由于该显示面板具有上述阵列基板实施方式所描述的任意一种功能器件141为发光器件的阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
在本公开的一种实施方式中，功能器件141可以为Micro LED或者Mini LED。
本公开还提供一种阵列基板的制备方法，该阵列基板的制备方法包括在衬底基板110的一侧依次形成驱动电路层130和功能器件层140：其中，驱动电路层130设置有第一驱动电路200，第一驱动电路200至少包括驱动晶体管210；如图23所示，形成驱动电路层130包括：
步骤S110，如图5所示，在衬底基板110的一侧形成第一栅极层310，第一栅极层310包括驱动晶体管的第一栅极311；
步骤S120，如图5所示，在第一栅极层310远离衬底基板110的一侧形成第一栅极绝缘层320；
步骤S130，如图5所示，在第一栅极层310远离衬底基板110的一侧形成半导体层330，半导体层330包括驱动晶体管的有源层331，驱动晶体管的有源层331具有驱动晶体管的沟道区3311；驱动晶体管的第一栅极311在半导体层330的正投影，与同一驱动晶体管的沟道区3311至少部分重合；
步骤S140，如图6所示，在半导体层330远离衬底基板110的一侧形成第二栅极绝缘层340；
步骤S150，如图6所示，在第二栅极绝缘层340远离衬底基板110的一侧形成第二栅极层350，第二栅极层350包括驱动晶体管的第二栅极351；驱动晶体管的第二栅极351在半导体层330的正投影，与同一驱动晶体管的沟道区3311至少部分重合；同一驱动晶体管的第一栅极311能够与第二栅极电连接；
步骤S160，如图7所示，在第二栅极层350远离衬底基板110的一侧形成层间电介质层360；
步骤S170，如图8或者图10所示，在层间电介质层360远离衬底基板110的一侧形成源漏金属层370，源漏金属层370与驱动晶体管的有源层331连接，源漏金属层370包括驱动晶体管的源极371和漏极。
本公开提供的阵列基板的制备方法，能够制备出上述阵列基板实施方式所描述的任意一种阵列基板。该阵列基板的制备方法的各个步骤的细节、原理和效果，已经在上述阵列基板实施方式中进行了详细的描述和介绍，或者可以根据上述阵列基板实施方式的描述而明确地推导出来，本公开在此不再赘述。
在本公开的一种实施方式中，在第二栅极层350远离衬底基板110的一侧形成层间电介质层360包括：
在第二栅极层350远离衬底基板110的一侧形成层间电介质材料层；
对在第二栅极层350远离衬底基板110的一侧形成层间电介质材料层进行图案化操作，以形成暴露驱动晶体管的第一栅极311的至少部分区域的第一过孔701和形成暴露驱动晶体管的第二栅极351的至少部分区域的第二过孔702；
在层间电介质层360远离衬底基板110的一侧形成源漏金属层370包括：
在层间电介质层360远离衬底基板110的一侧形成源漏金属材料层；
对源漏金属材料层进行图案化操作，以形成驱动晶体管的源极371、漏极和栅极桥接引线373，其中，栅极桥连引线栅极桥接引线373通过第一过孔701与第一栅极连接，栅极桥接引线373通过第二过孔702与第二栅极连接。
在本公开的一种实施方式中，形成驱动电路层230还可以包括：
如图8和图9所示，在形成源漏金属层370后，在源漏金属层370远离衬底基板的一侧形成第三钝化层603。
在本公开的一种实施方式中，形成驱动电路层230还可以包括：
如图10和图11所示，在形成源漏金属层370后，在源漏金属层370远离衬底基板的一侧形成平坦化层380；
如图12所示，在平坦化层380远离衬底基板的一侧形成电极层390；
如图13所示，在电极层390远离衬底基板的一侧形成第二钝化层602。需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (15)

  1. 一种阵列基板，包括依次层叠的衬底基板、驱动电路层和功能器件层：其中，所述驱动电路层设置有第一驱动电路，所述第一驱动电路至少包括驱动晶体管；
    所述驱动电路层包括依次层叠于所述衬底基板的第一栅极层、第一栅极绝缘层、半导体层、第二栅极绝缘层、第二栅极层、层间电介质层和源漏金属层；其中，所述第一栅极层包括所述驱动晶体管的第一栅极；所述半导体层包括所述驱动晶体管的有源层，所述驱动晶体管的有源层具有所述驱动晶体管的沟道区；所述驱动晶体管的第一栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；所述第二栅极层包括驱动晶体管的第二栅极；所述驱动晶体管的第二栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；所述源漏金属层包括所述驱动晶体管的源极和漏极；
    其中，同一所述驱动晶体管的第一栅极和第二栅极通过所述源漏金属层电连接；所述功能器件层包括功能器件，所述功能器件与所述驱动晶体管的漏极电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述源漏金属层还包括所述驱动晶体管的栅极桥接引线；同一所述驱动晶体管中，所述第一栅极和所述第二栅极均与所述栅极桥接引线连接。
  3. 根据权利要求2所述的阵列基板，其中，所述驱动电路层包括第一过孔和第二过孔；
    所述第一过孔贯穿所述层间电介质层、所述第二栅极绝缘层和所述第一栅极绝缘层，且暴露所述驱动晶体管的第一栅极的至少部分区域；所述第二过孔贯穿所述层间电介质层和所述第二栅极绝缘层，且暴露所述驱动晶体管的第二栅极的至少部分区域；
    所述栅极桥接引线通过所述第一过孔与所述第一栅极连接，且通过所述第二过孔与所述第二栅极连接。
  4. 根据权利要求1所述的阵列基板，其中，所述第一驱动电路还包括存储电容；所述第一栅极层还包括所述存储电容的第一电极板，所述第二栅极层还包括所述存储电容的第二电极板。
  5. 根据权利要求1所述的阵列基板，其中，所述第一驱动电路还包括开关晶体管；所述半导体层还包括所述开关晶体管的有源层，所述开关晶体管的有源层具有所述开关晶体管的沟道区；所述驱动晶体管的沟道区的宽度，大于所述开关晶体管的沟道区的宽度。
  6. 根据权利要求1所述的阵列基板，其中，所述半导体层的材料包括低温多晶硅。
  7. 根据权利要求6所述的阵列基板，其中，所述半导体层的厚度为30～60纳米。
  8. 根据权利要求1所述的阵列基板，其中，所述驱动电路层还包括：
    平坦化层，设于所述源漏金属层远离所述衬底基板的一侧；
    电极层，设于所述平坦化层远离所述衬底基板的一侧，且厚度大于1微米；所述电极层包括第二电极和所述第一驱动电路的第一电极；同一所述第一驱动电路中，所述第一电极与所述驱动晶体管的漏极连接；
    所述功能器件连接所述第二电极和所述第一电极。
  9. 根据权利要求8所述的阵列基板，其中，所述电极层包括：
    第一种子金属层，设于所述源漏金属层远离所述衬底基板的一侧，且与所述驱动晶体管的漏极连接；所述第一种子金属层的厚度不大于1微米；
    第一电镀金属层，设于所述第一种子金属层远离所述衬底基板的一侧；所述第一电镀金属层的厚度为1～20微米；
    所述功能器件与所述第一电镀金属层连接。
  10. 根据权利要求8所述的阵列基板，其中，所述电极层还包括电源引线，所述电源引线与所述驱动晶体管的源极连接。
  11. 根据权利要求1所述的阵列基板，其中，所述源漏金属层包括：
    第二种子金属层，设于所述层间电介质层远离所述衬底基板的一侧且与所述驱动晶体管的有源层连接；所述第二种子金属层的厚度不大于1微米；
    第二电镀金属层，设于所述第二种子金属层远离所述衬底基板的一侧；所述第二电镀金属层的厚度为1～20微米。
  12. 根据权利要求11所述的阵列基板，其中，源漏金属层还包括第二电极和电源引线；所述电源引线与所述驱动晶体管的源极连接，所述功 能器件连接所述第二电极和所述驱动晶体管的漏极。
  13. 一种显示面板，包括权利要求1～12任意一项所述的阵列基板。
  14. 一种阵列基板的制备方法，包括在衬底基板的一侧依次形成驱动电路层和功能器件层：其中，所述驱动电路层设置有第一驱动电路，所述第一驱动电路至少包括驱动晶体管；形成所述驱动电路层包括：
    在所述衬底基板的一侧形成第一栅极层，所述第一栅极层包括所述驱动晶体管的第一栅极；
    在所述第一栅极层远离所述衬底基板的一侧形成第一栅极绝缘层；
    在所述第一栅极层远离所述衬底基板的一侧形成半导体层，所述半导体层包括驱动晶体管的有源层，所述驱动晶体管的有源层具有所述驱动晶体管的沟道区；所述驱动晶体管的第一栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；
    在所述半导体层远离所述衬底基板的一侧形成第二栅极绝缘层；
    在所述第二栅极绝缘层远离所述衬底基板的一侧形成第二栅极层，所述第二栅极层包括驱动晶体管的第二栅极；所述驱动晶体管的第二栅极在所述半导体层的正投影，与同一所述驱动晶体管的沟道区至少部分重合；同一所述驱动晶体管的所述第一栅极能够与所述第二栅极电连接；
    在所述第二栅极层远离所述衬底基板的一侧形成层间电介质层；
    在所述层间电介质层远离所述衬底基板的一侧形成源漏金属层，所述源漏金属层与所述驱动晶体管的有源层连接，所述源漏金属层包括所述驱动晶体管的源极和漏极。
  15. 根据权利要求14所述的阵列基板的制备方法，其中，在所述第二栅极层远离所述衬底基板的一侧形成层间电介质层包括：
    在所述第二栅极层远离所述衬底基板的一侧形成层间电介质材料层；
    对所述在所述第二栅极层远离所述衬底基板的一侧形成层间电介质材料层进行图案化操作，以形成暴露所述驱动晶体管的第一栅极的至少部分区域的第一过孔和形成暴露所述驱动晶体管的第二栅极的至少部分区域的第二过孔；
    在所述层间电介质层远离所述衬底基板的一侧形成源漏金属层包括：
    在所述层间电介质层远离所述衬底基板的一侧形成源漏金属材料层；
    对所述源漏金属材料层进行图案化操作，以形成所述驱动晶体管的源极、漏极和栅极桥接引线，其中，所述栅极桥接引线通过所述第一过孔与所述第一栅极连接，所述栅极桥接引线通过所述第二过孔与所述第二栅极连接。
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