WO2023226127A1 - 一种显示面板及其制备方法、拼接显示装置 - Google Patents

一种显示面板及其制备方法、拼接显示装置 Download PDF

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Publication number
WO2023226127A1
WO2023226127A1 PCT/CN2022/100798 CN2022100798W WO2023226127A1 WO 2023226127 A1 WO2023226127 A1 WO 2023226127A1 CN 2022100798 W CN2022100798 W CN 2022100798W WO 2023226127 A1 WO2023226127 A1 WO 2023226127A1
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Prior art keywords
base substrate
layer
display panel
driving circuit
display
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PCT/CN2022/100798
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English (en)
French (fr)
Inventor
罗传宝
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Priority to US17/789,567 priority Critical patent/US20230420624A1/en
Publication of WO2023226127A1 publication Critical patent/WO2023226127A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel, a preparation method thereof, and a splicing display device.
  • M-LED Sub-millimeter light-emitting diodes
  • M-LED display technology has entered a stage of accelerated development in recent years. Compared with OLED screens, M-LED displays can achieve lower cost, contrast, and high Better performance in brightness and thinner form factor.
  • M-LED display technology due to the size limitations of back-end transfer equipment, the current M-LED transfer substrate types are all small and medium-sized. In order to realize its large-size commercial display applications, seamless splicing technology needs to be developed accordingly.
  • the current M-LED splicing method is mainly realized through side printing or side physical vapor deposition (PVD) film formation, which is difficult and costly. Moreover, since side printing and side PVD film formation are both The circuit structure is formed on the side, so it is difficult to achieve seamless splicing, and during the splicing process, the circuit structures on the side are easily scratched due to mutual extrusion, resulting in a decrease in yield.
  • PVD physical vapor deposition
  • This application provides a display panel, a preparation method thereof, and a splicing display device, which can effectively solve the problems of existing M-LED splicing displays that are difficult to achieve seamless splicing and have a low splicing yield rate.
  • the display panel, its preparation method, and the splicing display device of this application adopt the following technical solutions.
  • this application provides a display panel, which includes:
  • a driving circuit layer is provided on one side of the base substrate, the driving circuit layer includes a plurality of thin film transistors;
  • a plurality of light-emitting units arranged on a side of the driving circuit layer facing away from the base substrate;
  • a plurality of scan lines and a plurality of data lines are provided on a side of the base substrate facing away from the driving circuit layer;
  • the display panel has a plurality of display areas arranged in an array, and each display area is provided with one of the light-emitting units, and a light-emitting unit, the scanning line, and the data line respectively. Electrically connected thin film transistors.
  • the display panel further has a gap area disposed between the plurality of display areas, wherein the display panel further includes a buffer layer disposed between the base substrate and the driving circuit layer. , the buffer layer is provided with grooves in the gap area.
  • the display panel further includes an encapsulation layer disposed on a side of the light-emitting unit facing away from the driving circuit layer.
  • the encapsulation layer includes an encapsulation cover plate, and the hardness of the encapsulation cover plate is greater than that of the substrate. The hardness of the substrate.
  • the surface roughness of the side of the base substrate away from the driving circuit layer is greater than the surface roughness of the side of the base substrate facing the driving circuit layer
  • the display panel further includes A flat layer, the flat layer is disposed on the surface of the side of the base substrate facing away from the driving circuit layer, and the data lines and the scanning lines are located on a side of the flat layer facing away from the base substrate. side.
  • the display panel further includes a plurality of via holes penetrating the base substrate and the flat layer, and the data lines and the scan lines are respectively electrically connected to the thin film transistor through the via holes. , wherein in the direction of the base substrate away from the driving circuit layer, the opening area of the via hole gradually increases.
  • the display panel further includes a first metal layer disposed on a side of the flat layer facing away from the base substrate, and an interlayer disposed on a side of the first metal layer facing away from the flat layer.
  • the present application also provides a method for manufacturing a display panel.
  • the method for manufacturing a display panel includes the following steps:
  • a plurality of light-emitting units are formed on a side of the driving circuit layer facing away from the base substrate;
  • a plurality of data lines and a plurality of scan lines are formed on the side of the base substrate away from the driving circuit layer, thereby forming a display panel;
  • the display panel has a plurality of display areas arranged in an array, and each display area is provided with one of the light-emitting units, and a light-emitting unit, the scanning line, and the data line respectively. Electrically connected thin film transistors.
  • the display panel also has a gap area disposed between the plurality of display areas, the buffer layer is disposed between the base substrate and the drive circuit layer, and the groove is located in the gap area.
  • a flat layer is formed on the surface of the side of the base substrate away from the driving circuit layer, and a plurality of via holes are formed through the flat layer and the base substrate.
  • the present application also provides a spliced display device, which includes: a casing and a plurality of display panels as described in any one of the above, wherein the casing forms an accommodation space, and the A plurality of display panels are arranged in an array in the accommodation space, and two adjacent display panels are in contact with each other.
  • This application provides a display panel, its preparation method, and a display device.
  • This application divides the display panel into multiple display areas based on light-emitting units, and each display area is provided with a light-emitting unit, a scanning line, and a data unit. Thin film transistors connected electrically.
  • the scanning lines used to transmit scanning signals and the data lines used to transmit data signals to the thin film transistors in each display area are transferred from the original driving circuit layer to the side of the substrate away from the driving circuit layer. This avoids problems such as a larger frame width of the display panel, easier scratching of the circuit structure, and lower yield caused by forming a circuit structure on the side of the display panel.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of a display panel in a display area provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the position distribution of thin film transistors on the buffer layer in multiple display areas according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of forming a base substrate and a buffer layer on one side of a carrier plate according to an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of forming a driving circuit layer on the side of the base substrate away from the carrier plate according to an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of a light-emitting unit formed on the side of the driving circuit layer facing away from the base substrate according to an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of forming an encapsulation layer on the side of the driving circuit layer and the light-emitting unit facing away from the base substrate according to an embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of forming a flat layer on the surface of a base substrate away from the driving circuit layer according to an embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional view of forming data lines and scanning lines on the side of the flat layer facing away from the base substrate according to an embodiment of the present application.
  • the inventor of this application conducted research and found that the current M-LED splicing method is mainly realized through side printing or side PVD film formation, which is difficult and costly. Moreover, due to side printing and side PVD The film formation all forms circuit structures on the sides, which results in a display panel frame with a large width, making it difficult to achieve seamless splicing. In addition, during the splicing process, the circuit structures on the sides are easily scratched due to mutual extrusion, resulting in a decrease in yield.
  • the display panel, its preparation method, and the splicing display device provided by this application are intended to solve the above technical problems of the prior art.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view of a display panel in a display area provided by an embodiment of the present application.
  • an embodiment of the present application provides a display panel.
  • the display panel includes: a base substrate 10; a driving circuit layer 30, which is disposed on one side of the base substrate 10.
  • the driving circuit layer 30 It includes a plurality of thin film transistors 31; a plurality of light-emitting units 50, disposed on the side of the driving circuit layer 30 away from the base substrate 10; a plurality of scanning lines 81 and a plurality of data lines 111, disposed on the substrate The side of the substrate 10 facing away from the driving circuit layer 30; wherein, the display panel has a plurality of display areas P arranged in an array, and each display area P is provided with one of the light-emitting units 50, and one Thin film transistors 31 are electrically connected to the light-emitting unit 50, the data line 111, and the scanning line 81 respectively.
  • the display panel is divided into a plurality of display areas P based on the light-emitting unit 50, and each display area P is provided with a light-emitting unit 50, the data line 111, and the
  • the scan lines 81 are electrically connected to the thin film transistors 31.
  • This application uses the scan lines 81 for transmitting scanning signals to the thin film transistors 31 in each of the display areas P and the data lines 111 for transmitting data signals.
  • the driving circuit layer 30 is transferred to the side of the base substrate 10 away from the driving circuit layer 30, thereby avoiding the formation of a circuit structure on the side of the display panel, which causes the display panel frame to be wider and the circuit structure to be easily scratched. , low yield and other issues.
  • the display panel is an M-LED display panel; the substrate substrate 10 is made of flexible material, such as polyimide.
  • the driving circuit layer 30 includes a plurality of thin film transistors 31, and the thin film transistors 31 are at least one of amorphous silicon thin film transistors, low-temperature polysilicon thin film transistors, and metal oxide thin film transistors,
  • the thin film transistor 31 includes a gate electrode 314, a source electrode 312, a drain electrode 313 and an active layer 311 including a channel.
  • the source electrode 312, the drain electrode 313 and the active layer 311 are arranged in the same layer, so
  • the gate electrode 314 is located above the channel, and the gate insulating layer 32 is located between the active layer 311 and the gate electrode 314 .
  • the driving circuit layer 30 includes a source-drain electrode and an active layer 311 arranged in the same layer, and a gate insulating layer 32, a gate layer, a protective layer 33 and a A binding electrode layer, wherein the source and drain electrodes include the source electrode 312 and the drain electrode 313, and the source and drain electrodes can be formed by conducting conduction through the active layer 311;
  • the gate electrode layer includes a gate electrode 314 and a drain electrode 313.
  • Adapter line 315 the scan line 81 is electrically connected to the gate 314 through the adapter line 315 ;
  • the binding electrode layer includes a first binding electrode 34 and a second binding electrode 35 .
  • the light-emitting unit 50 is a Mini LED chip or a Micro LED chip, and includes a first electrode 51 and a second electrode 52.
  • the first electrode 51 is one of a positive electrode and a negative electrode, so The second electrode 52 is the other one of the positive electrode and the negative electrode.
  • the first electrode 51 is electrically connected to the first binding electrode 34 through solder 40
  • the second electrode 52 is electrically connected to the second binding electrode 35 through solder 40 .
  • FIG. 3 is a schematic diagram of the position distribution of thin film transistors on the buffer layer in multiple display areas according to an embodiment of the present application.
  • the display panel has a plurality of display areas P arranged in an array.
  • the display areas P for example, correspond one-to-one to the pixel areas of the display panel. , that is, only one light-emitting unit 50 is provided in each display area P.
  • at least one thin film transistor 31 is provided in each display area P, in which a gate electrode 314, a source electrode 312 and a drain electrode 313 of one of the thin film transistor 31 are respectively connected to one of the scanning lines 81 and one of the thin film transistors 31.
  • the data line 111 is electrically connected to the first electrode 51 of one of the light-emitting units 50 .
  • the gate electrode 314, the source electrode 312 and the drain electrode 313 of the thin film transistor 31 are electrically connected to the scan line 81, the data line 111 and the first electrode 51 of the light emitting unit 50 through via holes respectively.
  • the base substrate 10 is made of flexible material, it is possible to reduce the difficulty of opening via holes on the base substrate 10 and facilitate the connection between the gate electrode 314 and the source electrode 312 of the thin film transistor 31 and the scanning.
  • Line 81 and the data line 111 are electrically connected.
  • the display panel further has a gap area G disposed between the plurality of display areas P, wherein the display panel further includes a gap area G disposed between the base substrate 10 and the
  • the buffer layer 20 between the driving circuit layers 30 is provided with a groove 21 in the gap area G between the display areas P.
  • the substrate substrate 10 is made of flexible material, during the production process, the substrate substrate 10 will be placed on a hard bearing plate to facilitate subsequent installation on the substrate.
  • the driving circuit layer 30 is formed on the side of the base substrate 10 away from the carrier board and the light-emitting unit 50 is bound thereto.
  • the production process of the display panel also includes the step of combining the base substrate 10 and the data lines 111.
  • the stress generated during the separation process will have adverse effects on the driving circuit layer 30 and the light-emitting unit 50.
  • the gap area G between the buffer layer 20 corresponding to the display area P is The groove 21 is provided to effectively release the stress generated during the separation process of the base substrate 10 and the carrier plate, and prevent the thin film transistor 31 and the light-emitting unit 50 in each display area P from being affected by the stress. produce quality problems.
  • the depth of the groove 21 is 3000 ⁇ 6000 angstroms; the groove 21 includes two opposite side walls, and the distance between the side walls is 10 ⁇ 20 ⁇ m.
  • any two adjacent display areas P (including horizontally adjacent, vertically adjacent and diagonally adjacent) form a display area group, and each display area group Grooves 21 are provided in the gap area G, so that the area of the groove 21 in the gap area G can be maximized, and the separation process of the substrate substrate 10 and the carrier plate can be better released. stress generated in.
  • this application does not limit the specific position of the groove 21 in the buffer layer 20.
  • the groove 21 may be provided only in the gap area G in part of the display area group.
  • the display panel further includes an encapsulation layer 60 disposed on a side of the light-emitting unit 50 away from the driving circuit layer 30 .
  • the encapsulation layer 60 includes an encapsulation cover.
  • the encapsulation The cover plate is located at the outermost side of the packaging layer 60 , and the hardness of the packaging cover plate is greater than the hardness of the base substrate 10 .
  • the packaging cover is a glass cover, and the hardness of the glass cover is greater than the hardness of the base substrate 10 .
  • the base substrate 10 needs to be turned upside down, and due to the packaging layer
  • the hardness of the encapsulation layer 60 is greater than the hardness of the base substrate 10 . Therefore, the encapsulation layer 60 can provide a good supporting effect and facilitate the film forming operation after the inversion step.
  • the surface roughness of the side of the base substrate 10 away from the driving circuit layer 30 is greater than the surface roughness of the side of the base substrate 10 facing the driving circuit layer 30
  • the display panel further includes a flat layer 70
  • the flat layer 70 is disposed on the surface of the base substrate 10 on a side facing away from the driving circuit layer 30, the data lines 111, the scan lines 81 are located on the side of the flat layer 70 away from the base substrate 10 .
  • the production process of the display panel includes a process of separating the base substrate 10 and the carrier board, such as a laser lift-off process, and the laser lift-off process will cause the base substrate 10 to be away from the driving circuit layer.
  • the surface roughness on one side of the substrate 30 increases.
  • a flat layer 70 is provided on the surface of the side of the base substrate 10 facing away from the driving circuit layer 30, so as to provide a smooth surface for the subsequent data lines 111 and 30.
  • the arrangement of the scanning lines 81 creates flattening conditions, which is beneficial to improving the film formation quality of the film layer on the side of the base substrate 10 away from the driving circuit layer 30 .
  • the thickness of the flat layer 70 is 1 ⁇ 3 ⁇ m.
  • the display panel further includes a plurality of via holes penetrating the base substrate 10 and the flat layer 70 , and the data lines 111 and the scan lines 81 pass through the via holes respectively.
  • the hole is electrically connected to the thin film transistor 31 , wherein the opening area of the via hole gradually increases in the direction of the base substrate 10 away from the driving circuit layer 30 .
  • the base substrate 10 needs to be inverted.
  • the film formation direction and the shape of the via holes formed by etching will also change accordingly. Therefore, in the In the direction of the base substrate 10 away from the driving circuit layer 30 , the opening area of the via hole penetrating the base substrate 10 and the flat layer 70 gradually increases.
  • the via holes penetrating the base substrate 10 and the flat layer 70 include a first via hole 01 and a second via hole 02 , and the data line 111 passes through the first via hole 01 and the source of the thin film transistor 31
  • the scan line 81 is electrically connected to the gate electrode 314 of the thin film transistor 31 through the second via hole 02 and the transfer line 315 .
  • the first via hole 01 and the second via hole 02 have a diameter of 6 to 10 ⁇ m, and the etching process is dry etching.
  • the display panel further includes VDD traces and VSS traces 112 , and the VDD traces and VSS traces 112 are also provided on the substrate substrate 10 away from the driving circuit layer 30
  • the via hole penetrating the base substrate 10 and the flat layer 70 also includes a third via hole 03
  • the VSS trace 112 passes through the third via hole 03 and connects to the third via hole 03 of the light emitting unit 50 .
  • the two electrodes 52 are electrically connected.
  • the display panel further includes a via hole, such as a fourth via hole 04 , located in the driving circuit layer 30 , and the first electrode 51 of the light emitting unit 50 passes through a first bonding hole.
  • the fixed electrode 34 and the fourth via hole 04 are electrically connected to the drain electrode 313 of the thin film transistor 31 . Wherein, in the direction of the base substrate 10 away from the driving circuit layer 30 , the opening area of the fourth via hole 04 gradually decreases.
  • the scan lines 81 and the data lines 111 are respectively located in different film layers.
  • the display panel also includes a first metal layer 80, an interlayer insulating layer 90 and a second metal layer 110 located on the side of the flat layer 70 facing away from the base substrate 10.
  • the scan lines 81 and One of the data lines 111 is patterned and formed by the first metal layer 80
  • the other of the scanning line 81 and the data line 111 is patterned and formed by the second metal layer 110 .
  • the display panel includes a first metal layer 80 disposed on a side of the flat layer 70 facing away from the base substrate 10
  • a first metal layer 80 disposed on a side of the first metal layer 80 facing away from the flat layer 70 is disposed on a side of the first metal layer 80 facing away from the flat layer 70 .
  • the interlayer insulating layer 90 and the second metal layer 110 provided on the side of the interlayer insulating layer 90 facing away from the first metal layer 80 , wherein the first metal layer 80 includes the scan line 81 ,
  • the second metal layer 110 includes the data line 111 .
  • FIG. 4 is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of the present application. Referring to FIGS. 1-4 , the method for manufacturing a display panel includes the following steps:
  • S01 Provide a carrier plate, and form a base substrate 10 on one side of the carrier plate;
  • S04 Form an encapsulation layer 60 on the side of the driving circuit layer 30 and the light-emitting unit 50 away from the base substrate 10, thereby forming a display substrate on the carrier board;
  • S06 Form a plurality of data lines 111 and a plurality of scan lines 81 on the side of the base substrate 10 away from the driving circuit layer 30, thereby forming a display panel;
  • the display panel has a plurality of display areas P arranged in an array, each of the display areas P is provided with one of the light-emitting units 50, and one of the light-emitting units 50 and the data line 111 respectively. , the thin film transistor 31 electrically connected to the scan line 81 .
  • step S01 includes: step S01 : Provide a carrier plate 100, and form a base substrate 10 on the carrier plate 100; Step S01-2: Form a buffer including a groove 21 on the side of the base substrate 10 away from the carrier plate 100 Layer 20; wherein the display panel also has a gap area G disposed between the plurality of display areas P, and the buffer layer 20 is disposed between the base substrate 10 and the drive circuit layer 30, And the groove 21 is located in the gap area G.
  • FIG. 6 is a schematic cross-sectional view of forming a driving circuit layer on the side of the substrate away from the carrier plate provided by an embodiment of the present application.
  • the step S02 includes: A driving circuit layer 30 is formed on the base substrate 10 .
  • the driving circuit layer 30 includes a plurality of thin film transistors 31.
  • the thin film transistors 31 include an active layer 311, a source electrode 312, a drain electrode 313 and a gate electrode 314.
  • the driving circuit layer 30 also includes a plurality of first The binding electrode 34 and a plurality of second binding electrodes 35 are electrically connected to the drain electrode 313 of the thin film transistor 31 through the fourth via hole 04 formed in the driving circuit layer 30 . connect.
  • Figure 7 is a schematic cross-sectional view of forming a light-emitting unit on the side of the driving circuit layer away from the base substrate provided by an embodiment of the present application.
  • the step S03 includes: placing a to-be-transferred A plurality of light-emitting units 50 arranged in an array on the substrate are transferred to the driving circuit layer 30 , and the first electrode 51 of each light-emitting unit 50 is bound and electrically connected to the first binding electrode 34 through solder 40 , the second electrode 52 of each light-emitting unit 50 is bound and electrically connected to the second binding electrode 35 through the solder 40 .
  • Figure 8 is a schematic cross-sectional view of forming an encapsulation layer on the side of the driving circuit layer and the light-emitting unit facing away from the substrate according to an embodiment of the present application.
  • the step S04 includes: An encapsulation layer 60 is formed on the driving circuit layer 30 and the light-emitting unit 50 , thereby forming a display substrate on the carrier board 100 .
  • the packaging layer 60 includes a packaging cover.
  • Figure 9 is a cross-sectional schematic diagram of forming a flat layer on the surface of a substrate away from the driving circuit layer provided by an embodiment of the present application.
  • the step S05 includes: step S05 -1: The display substrate is peeled off from the carrier plate 100 by laser peeling. Since the laser energy is strong, the surface of the side of the base substrate 10 facing away from the driving circuit layer 30 forms a plurality of uneven microstructures, so that the side of the base substrate 10 facing away from the driving circuit layer 30 The surface roughness is greater than the surface roughness of the side of the base substrate 10 facing the driving circuit layer 30 .
  • step S05 also includes step S05-02: turning the display substrate upside down, and forming a flat layer 70 on the surface of the base substrate 10 on the side away from the driving circuit layer 30, and A plurality of via holes are formed through the flat layer 70 and the base substrate 10 , wherein the data lines 111 and the scan lines 81 pass through the flat layer 70 and the base substrate 10 .
  • the via hole is electrically connected to the thin film transistor 31 , and the opening area of the via hole gradually increases in the direction of the base substrate 10 away from the driving circuit layer 30 .
  • an organic photoresist is coated on the surface of the base substrate 10 away from the driving circuit layer 30 and thermally cured, thereby forming the flat layer 70 .
  • Figure 10 is a schematic cross-sectional view of forming data lines and scan lines on the side of the flat layer away from the base substrate provided by an embodiment of the present application.
  • the step S06 includes: Step S06-1: Form a first metal layer 80 on the side of the flat layer 70 away from the base substrate 10, and pattern the first metal layer 80 to form a scan line 81, wherein The scan line 81 is electrically connected to the transfer line 315 through the second via hole 02 penetrating the flat layer 70 and the base substrate 10 , and then is electrically connected to the gate 314 of the thin film transistor 31 through the transfer line 315 ;
  • Step S06-2 Form an interlayer insulating layer 90 on the side of the first metal layer 80 away from the flat layer 70, and etching holes in the interlayer insulating layer 90;
  • Step S06-3 In A second metal layer 110 is formed on the side of the interlayer insulating layer 90 away from the first metal layer 80 , and the second metal layer 110 is patterned to form
  • the data line 111 is electrically connected to the source electrode 312 of the thin film transistor 31 through the first via hole 01 that penetrates the flat layer 70 and the base substrate 10; the VSS line 112 passes through the The flat layer 70 and the third via hole 03 of the base substrate 10 are electrically connected to the second binding electrode 35, and then are connected to the second electrode of the light emitting unit 50 through the second binding electrode 35. 52 electrical connection.
  • the present application also provides a spliced display device, which includes a housing and a plurality of display panels as described in any one of the above, wherein the housing forms an accommodation space, and the plurality of display panels Display panels are arranged in an array in the accommodation space, and two adjacent display panels are in contact with each other.
  • the present application provides a display panel, a preparation method thereof, and a splicing display device.
  • the display panel includes: a base substrate; and a driving circuit layer, which is disposed on one side of the base substrate.
  • the driving circuit layer includes a plurality of thin film transistors.
  • a plurality of light-emitting units arranged on the side of the driving circuit layer facing away from the base substrate; a plurality of scanning lines and a plurality of data lines, arranged on a side of the base substrate facing away from the driving circuit layer; wherein, the display panel has an array arrangement There are multiple display areas, and each display area is provided with a light-emitting unit, and a thin film transistor that is electrically connected to the light-emitting unit, the scanning line, and the data line respectively.
  • the scanning lines and data lines used to transmit scanning signals and data signals to thin film transistors are arranged on the side of the substrate away from the driving circuit layer, thereby avoiding the large splicing gap caused by arranging line structures on the side of the display panel. , the problem of low production yield has greatly improved the display effect of the splicing display device.

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Abstract

一种显示面板及其制备方法、拼接显示装置，显示面板包括：衬底基板(10)；驱动电路层(30)，驱动电路层(30)包括多个薄膜晶体管(31)；发光单元(50)；多条扫描线(81)和多条数据线(111)，设于衬底基板(10)背离驱动电路层(30)的一侧，显示面板具有多个显示区域(P)，每个显示区域(P)内设有一个发光单元(50)，和一个分别与发光单元(50)、扫描线(81)、数据线(111)电性连接的薄膜晶体管(31)。

Description

一种显示面板及其制备方法、拼接显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制备方法、拼接显示装置。
 背景技术
次毫米发光二极管（Mini LED）和微米发光二极管（Micro LED）统称为M-LED，M-LED显示技术在近年进入加速发展阶段，相较OLED屏幕，M-LED显示可以在成本、对比度、高亮度和轻薄外形上表现出更佳性能。在M-LED显示技术中，受制于后段转移设备尺寸限制，目前M-LED转移基板类型均为中小尺寸，为实现其大尺寸商用显示应用，需求对应开发无缝拼接技术。
而目前的M-LED拼接方式主要通过侧面印线或侧面物理气相沉积（PVD）成膜的方式实现，其制程难度较大，成本较高；并且，由于侧面印线和侧边PVD成膜均是在侧面形成线路结构，因而难以实现无缝拼接，且拼接过程中侧面的线路结构的还容易因相互挤压而产生刮伤，造成良率下降。
 技术问题
本申请提供一种显示面板及其制备方法、拼接显示装置，能够有效解决现有的M-LED拼接显示难以实现无缝拼接且拼接良率低的问题。
 技术解决方案
为了实现上述目的，本申请的显示面板及其制备方法、拼接显示装置采取了以下技术方案。
一方面，本申请提供一种显示面板，所述显示面板包括：
衬底基板；
驱动电路层，设置于所述衬底基板的一侧，所述驱动电路层包括多个薄膜晶体管；
多个发光单元，设置于所述驱动电路层背离所述衬底基板的一侧；
多条扫描线和多条数据线，设置于所述衬底基板背离所述驱动电路层的一侧；
其中，所述显示面板具有阵列排布的多个显示区域，每个所述显示区域内对应设置有一个所述发光单元，和一个分别与所述发光单元、所述扫描线、所述数据线电性连接的薄膜晶体管。
可选的，所述显示面板还具有设置于所述多个显示区域之间的间隙区域，其中，所述显示面板还包括设置于所述衬底基板和所述驱动电路层之间的缓冲层，所述缓冲层在所述间隙区域设置有凹槽。
可选的，所述显示面板还包括设置于所述发光单元背离所述驱动电路层的一侧的封装层，所述封装层包括封装盖板，所述封装盖板的硬度大于所述衬底基板的硬度。
可选的，所述衬底基板背离所述驱动电路层的一侧的表面粗糙度大于所述衬底基板朝向所述驱动电路层的一侧的表面粗糙度，其中，所述显示面板还包括平坦层，所述平坦层设置于所述衬底基板背离所述驱动电路层的一侧的表面上，所述数据线、所述扫描线均位于所述平坦层背离所述衬底基板的一侧。
可选的，所述显示面板还包括多个贯穿所述衬底基板和所述平坦层的过孔，所述数据线和所述扫描线分别通过所述过孔与所述薄膜晶体管电性连接，其中，在所述衬底基板背离所述驱动电路层的方向上，所述过孔的开口面积逐渐增大。
可选的，所述显示面板还包括设置于所述平坦层背离所述衬底基板的一侧的第一金属层、设置于所述第一金属层背离所述平坦层的一侧的层间绝缘层、设置于所述层间绝缘层背离所述第一金属层的一侧的第二金属层，其中，所述第一金属层包括所述扫描线，所述第二金属层包括所述数据线。
另一方面，本申请还提供一种显示面板的制备方法，所述显示面板的制备方法包括以下步骤：
提供一承载板，在所述承载板的一侧形成一衬底基板；
在所述衬底基板背离所述承载板的一侧形成一驱动电路层；
在所述驱动电路层背离所述衬底基板的一侧形成多个发光单元；
在所述驱动电路层、所述发光单元背离所述衬底基板的一侧形成一封装层，从而在所述承载板上形成一显示基板；
将所述显示基板从所述承载板上剥离；
在所述衬底基板背离所述驱动电路层的一侧形成多条数据线和多条扫描线，从而形成一显示面板；
其中，所述显示面板具有阵列排布的多个显示区域，每个所述显示区域内对应设置有一个所述发光单元，和一个分别与所述发光单元、所述扫描线、所述数据线电性连接的薄膜晶体管。
可选的，在所述承载板的一侧形成一衬底基板之后，还包括以下步骤：
在所述衬底基板背离所述承载板的一侧形成一包括凹槽的缓冲层；
其中，所述显示面板还具有设置于所述多个显示区域之间的间隙区域，所述缓冲层设置于所述衬底基板和所述驱动电路层之间，且所述凹槽位于所述间隙区域。
可选的，将所述显示基板从所述承载板上剥离之后，还包括以下步骤：
在所述衬底基板背离所述驱动电路层的一侧的表面上形成一平坦层，并形成贯穿所述平坦层和所述衬底基板的多个过孔。
再一方面，本申请还提供一种拼接显示装置，所述拼接显示装置包括：壳体和上述任一项所述的多个显示面板，其中，所述壳体形成一容置空间，所述多个显示面板在所述容置空间阵列设置，且相邻的两个所述显示面板之间相互接触。
 有益效果
本申请提供一种显示面板及其制备方法、显示装置，本申请将显示面板以发光单元为单位划分成多个显示区域，且每个显示区域内设置有一个分别与发光单元、扫描线、数据线电性连接的薄膜晶体管。本申请通过将用于向各个显示区域内的薄膜晶体管传递扫描信号的扫描线、传递数据信号的数据线，从原本的驱动电路层中转移到衬底基板背离所述驱动电路层的一侧，从而避免了在显示面板的侧边形成线路结构而导致的显示面板边框宽度较大、线路结构容易刮伤、良率较低等问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的平面示意图。
图2为本申请实施例提供的一个显示区域内的显示面板的剖面示意图。
图3为本申请实施例提供的多个显示区域内缓冲层上的薄膜晶体管的位置分布示意图。
图4为本申请实施例提供的显示面板的制备方法的流程示意图。
图5为本申请实施例提供的在承载板的一侧形成衬底基板和缓冲层的剖面示意图。
图6为本申请实施例提供的在衬底基板背离承载板的一侧形成驱动电路层的剖面示意图。
图7为本申请实施例提供的在驱动电路层背离衬底基板的一侧形成发光单元的剖面示意图。
图8为本申请实施例提供的在驱动电路层、发光单元背离衬底基板的一侧形成封装层的剖面示意图。
图9为本申请实施例提供的在衬底基板背离所述驱动电路层的表面上形成平坦层的剖面示意图。
图10为本申请实施例提供的在平坦层背离所述衬底基板的一侧形成数据线和扫描线的剖面示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。以下分别进行详细说明，需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请的发明人进行研究发现，目前的M-LED拼接方式主要通过侧面印线或侧面PVD成膜的方式实现，其制程难度较大，成本较高；并且，由于侧面印线和侧边PVD成膜均是在侧面形成线路结构，因而导致显示面板边框宽度较大，难以实现无缝拼接，且拼接过程中侧面的线路结构的还容易因相互挤压而产生刮伤，造成良率下降。
本申请提供的显示面板及其制备方法、拼接显示装置，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。
图1为本申请实施例提供的显示面板的平面示意图；图2为本申请实施例提供的一个显示区域内的显示面板的剖面示意图。参照图1-2，本申请实施例提供一种显示面板，所述显示面板包括：衬底基板10；驱动电路层30，设置于所述衬底基板10的一侧，所述驱动电路层30包括多个薄膜晶体管31；多个发光单元50，设置于所述驱动电路层30背离所述衬底基板10的一侧；多条扫描线81和多条数据线111，设置于所述衬底基板10背离所述驱动电路层30的一侧；其中，所述显示面板具有阵列排布的多个显示区域P，每个所述显示区域P内对应设置有一个所述发光单元50，和一个分别与所述发光单元50、所述数据线111、所述扫描线81电性连接的薄膜晶体管31。
本申请将所述显示面板以所述发光单元50为单位划分成多个显示区域P，且每个所述显示区域P内设置有一个分别与所述发光单元50、所述数据线111、所述扫描线81电性连接的薄膜晶体管31，本申请通过将用于向各个所述显示区域P内的所述薄膜晶体管31传递扫描信号的扫描线81、传递数据信号的数据线111，从原本的驱动电路层30中转移到衬底基板10背离所述驱动电路层30的一侧，从而避免了在显示面板的侧边形成线路结构而导致的显示面板边框宽度较大、线路结构容易刮伤、良率较低等问题。
在本申请的一些实施例中，所述显示面板为M-LED显示面板；所述衬底基板10为柔性材质，如聚酰亚胺。
在本申请的一些实施例中，所述驱动电路层30包括多个薄膜晶体管31，所述薄膜晶体管31为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管、金属氧化物薄膜晶体管中的至少一种，所述薄膜晶体管31包括栅极314、源极312、漏极313以及包括沟道的有源层311，所述源极312、所述漏极313与所述有源层311同层设置，所述栅极314位于所述沟道的上方，所述栅极绝缘层32位于所述有源层311和所述栅极314之间。进一步的，所述驱动电路层30包括同层设置的源漏极和有源层311，以及在所述有源层311上依次层叠设置的栅极绝缘层32、栅极层、保护层33和绑定电极层，其中，所述源漏极包括所述源极312和漏极313，所述源漏极可以通过所述有源层311导体化形成；所述栅极层包括栅极314和转接线315，所述扫描线81通过所述转接线315与所述栅极314电性连接；所述绑定电极层包括第一绑定电极34和第二绑定电极35。
在本申请的一些实施例中，所述发光单元50为Mini LED芯片或Micro LED芯片，并包括第一电极51和第二电极52，所述第一电极51为正极和负极中的一个，所述第二电极52为正极和负极中的另一个。所述第一电极51通过焊料40与所述第一绑定电极34电性连接，所述第二电极52通过焊料40与所述第二绑定电极35电性连接。
图3为本申请实施例提供的多个显示区域内缓冲层上的薄膜晶体管的位置分布示意图。结合图1-图3所示，在本申请的一些实施例中，所述显示面板具有阵列排布的多个显示区域P，所述显示区域P例如与所述显示面板的像素区域一一对应，也即，每个所述显示区域P内仅设置有一个所述发光单元50。进一步的，每个所述显示区域P内设置有至少一个所述薄膜晶体管31，其中一个所述薄膜晶体管31的栅极314、源极312和漏极313分别与一条所述扫描线81、一条所述数据线111和一个所述发光单元50的第一电极51电性连接。其中，所述薄膜晶体管31的栅极314、源极312和漏极313分别通过过孔连接的方式与所述扫描线81、所述数据线111和所述发光单元50的第一电极51电性连接，而由于所述衬底基板10为柔性材质，从而可以降低在所述衬底基板10上开设过孔的难度，方便所述薄膜晶体管31的栅极314、源极312与所述扫描线81、所述数据线111电性连接。
在本申请的一些实施例中，所述显示面板还具有设置于所述多个显示区域P之间的间隙区域G，其中，所述显示面板还包括设置于所述衬底基板10和所述驱动电路层30之间的缓冲层20，所述缓冲层20在所述显示区域P之间的间隙区域G设置有凹槽21。本申请提供的所述显示面板中，由于所述衬底基板10为柔性材质，生产过程中，会将所述衬底基板10设置在一硬质的承载板上，以便于后续在所述衬底基板10背离所述承载板的一侧形成所述驱动电路层30和绑定所述发光单元50。但由于所述衬底基板10背离所述驱动电路层30的一侧还需要形成扫描线81和数据线111，因此，所述显示面板的生产流程还会包括将所述衬底基板10和所述承载板分离的流程，分离过程中产生的应力会对所述驱动电路层30和发光单元50产生不良影响，而本申请通过在所述缓冲层20对应显示区域P之间的间隙区域G上设置凹槽21，从而能够有效释放所述衬底基板10和所述承载板分离过程中产生的应力，避免各个所述显示区域P中的所述薄膜晶体管31、发光单元50受应力的影响而产生质量问题。进一步的，所述凹槽21的深度为3000~6000埃；所述凹槽21包括两个相对设置的侧壁，所述侧壁之间的间距为10~20μm。
在本申请的一些实施例中，任意相邻的两个所述显示区域P（包括水平方向相邻、竖直方向相邻和对角线方向相邻）组成一个显示区域组，各个显示区域组中的间隙区域G内均设置有凹槽21，从而能够使所述凹槽21在所述间隙区域G中的面积最大化，更好的释放所述衬底基板10和所述承载板分离过程中产生的应力。但本申请对所述凹槽21在缓冲层20中的具体位置不作限制，在本申请的其他实施例中，所述凹槽21可以仅设置在部分显示区域组中的间隙区域G内。
在本申请的一些实施例中，所述显示面板还包括设置于所述发光单元50背离所述驱动电路层30的一侧的封装层60，所述封装层60包括封装盖板，所述封装盖板位于所述封装层60的最外侧，所述封装盖板的硬度大于所述衬底基板10的硬度。具体的，所述封装盖板为玻璃盖板，所述玻璃盖板的硬度大于所述衬底基板10的硬度。在生产过程中，当在所述衬底基板10背离所述驱动电路层30的一侧上形成数据线111、扫描线81时，需要将所述衬底基板10倒置，而由于所述封装层60的硬度大于所述衬底基板10的硬度，因此，所述封装层60能够提供很好的支撑作用，方便了倒置步骤后的成膜作业。
在本申请的一些实施例中，所述衬底基板10背离所述驱动电路层30的一侧的表面粗糙度大于所述衬底基板10朝向所述驱动电路层30的一侧的表面粗糙度，其中，所述显示面板还包括平坦层70，所述平坦层70设置于所述衬底基板10背离所述驱动电路层30的一侧的表面上，所述数据线111、所述扫描线81均位于所述平坦层70背离所述衬底基板10的一侧。如前所述，所述显示面板的生产流程包括将所述衬底基板10和所述承载板分离的流程，如激光剥离工艺，而激光剥离工艺会使得衬底基板10背离所述驱动电路层30的一侧的表面粗糙度增大，因此，本申请通过在所述衬底基板10背离所述驱动电路层30的一侧的表面上设置平坦层70，从而为后续所述数据线111和所述扫描线81的设置创造平坦化的条件，有利于提高所述衬底基板10背离所述驱动电路层30的一侧的膜层成膜质量。进一步的，所述平坦层70的厚度为1~3μm。
在本申请的一些实施例中，所述显示面板还包括多个贯穿所述衬底基板10和所述平坦层70的过孔，所述数据线111和所述扫描线81分别通过所述过孔与所述薄膜晶体管31电性连接，其中，在所述衬底基板10背离所述驱动电路层30的方向上，所述过孔的开口面积逐渐增大。具体的，如前所述，形成所述平坦层70前，需要将所述衬底基板10进行倒置，相应的，成膜方向和蚀刻形成的过孔形状也会相应改变，因此，在所述衬底基板10背离所述驱动电路层30的方向上，贯穿所述衬底基板10和所述平坦层70的所述过孔的开口面积逐渐增大。贯穿所述衬底基板10和所述平坦层70的过孔包括第一过孔01和第二过孔02，所述数据线111通过所述第一过孔01与所述薄膜晶体管31的源极312电性连接，所述扫描线81通过所述第二过孔02、以及转接线315与所述薄膜晶体管31的栅极314电性连接。进一步的，所述第一过孔01、所述第二过孔02的孔径大小为6~10μm，所述蚀刻的工艺为干法蚀刻。
在本申请的一些实施例中，所述显示面板还包括VDD走线和VSS走线112，所述VDD走线和VSS走线112也设置在所述衬底基板10背离所述驱动电路层30的一侧，贯穿所述衬底基板10和所述平坦层70的过孔还包括第三过孔03，所述VSS走线112通过所述第三过孔03与所述发光单元50的第二电极52电性连接。
在本申请的一些实施例中，所述显示面板还包括位于所述驱动电路层30中的过孔，如第四过孔04，所述发光单元50的所述第一电极51通过第一绑定电极34、所述第四过孔04与所述薄膜晶体管31的漏极313电性连接。其中，在所述衬底基板10背离所述驱动电路层30的方向上，所述第四过孔04的开口面积逐渐减小。
在本申请的一些实施例中，所述扫描线81和所述数据线111分别位于不同的膜层中。具体的，所述显示面板还包括位于所述平坦层70背离所述衬底基板10的一侧的第一金属层80、层间绝缘层90和第二金属层110，所述扫描线81和所述数据线111中的其中之一由所述第一金属层80图案化形成，所述扫描线81和所述数据线111中的另一由所述第二金属层110图案化形成。进一步的，所述显示面板包括设置于所述平坦层70背离所述衬底基板10的一侧的第一金属层80、设置于所述第一金属层80背离所述平坦层70的一侧的层间绝缘层90、设置于所述层间绝缘层90背离所述第一金属层80的一侧的第二金属层110，其中，所述第一金属层80包括所述扫描线81，所述第二金属层110包括所述数据线111。通过将所述扫描线81和所述数据线111分层设置，能够使实现不同信号在不同的金属层中传输，并降低走线设计难度。
另一方面，本申请还提供一种显示面板的制备方法。图4为本申请实施例提供的显示面板的制备方法的流程示意图，参照图1-图4，所述显示面板的制备方法包括以下步骤：
S01：提供一承载板，在所述承载板的一侧形成一衬底基板10；
S02：在所述衬底基板10背离所述承载板的一侧形成一驱动电路层30；
S03：在所述驱动电路层30背离所述衬底基板10的一侧形成多个发光单元50；
S04：在所述驱动电路层30、所述发光单元50背离所述衬底基板10的一侧形成一封装层60，从而在所述承载板上形成一显示基板；
S05：将所述显示基板从所述承载板上剥离；
S06：在所述衬底基板10背离所述驱动电路层30的一侧形成多条数据线111和多条扫描线81，从而形成一显示面板；
其中，所述显示面板具有阵列排布的多个显示区域P，每个所述显示区域P内对应设置有一个所述发光单元50，和一个分别与所述发光单元50、所述数据线111、所述扫描线81电性连接的薄膜晶体管31。
图5为本申请实施例提供的在承载板的一侧形成衬底基板和缓冲层的剖面示意图，参照图3和图5，在本申请的一些实施例中，所述步骤S01包括：步骤S01：提供一承载板100，在所述承载板100上形成一衬底基板10；步骤S01-2：在所述衬底基板10背离所述承载板100的一侧形成一包括凹槽21的缓冲层20；其中，所述显示面板还具有设置于所述多个显示区域P之间的间隙区域G，所述缓冲层20设置于所述衬底基板10和所述驱动电路层30之间，且所述凹槽21位于所述间隙区域G。
图6为本申请实施例提供的在衬底基板背离承载板的一侧形成驱动电路层的剖面示意图，参照图6，在本申请的一些实施例中，所述步骤S02包括：在所述衬底基板10上制备形成一驱动电路层30。其中，所述驱动电路层30包括多个薄膜晶体管31，所述薄膜晶体管31包括有源层311、源极312、漏极313和栅极314，所述驱动电路层30还包括多个第一绑定电极34和多个第二绑定电极35，所述第一绑定电极34通过形成于所述驱动电路层30中的第四过孔04与所述薄膜晶体管31的漏极313电性连接。
图7为本申请实施例提供的在驱动电路层背离衬底基板的一侧形成发光单元的剖面示意图，参照图7，在本申请的一些实施例中，所述步骤S03包括：将一待转移基板上的阵列设置的多个发光单元50转移到所述驱动电路层30上，并通过焊料40将各所述发光单元50的第一电极51与所述第一绑定电极34绑定电连接，通过焊料40将各所述发光单元50的第二电极52与所述第二绑定电极35绑定电连接。
图8为本申请实施例提供的在驱动电路层、发光单元背离衬底基板的一侧形成封装层的剖面示意图，参照图8，在本申请的一些实施例中，所述步骤S04包括：在所述驱动电路层30和所述发光单元50上形成一封装层60，从而在所述承载板100上形成一显示基板。其中，所述封装层60包括封装盖板。
图9为本申请实施例提供的在衬底基板背离所述驱动电路层的表面上形成平坦层的剖面示意图，参照图9，在本申请的一些实施例中，所述步骤S05包括：步骤S05-1：利用激光剥离的方式将所述显示基板从所述承载板100上剥离。由于激光能量较强，因此所述衬底基板10背离所述驱动电路层30的一侧表面形成凹凸不平的多个微结构，使得所述衬底基板10背离所述驱动电路层30的一侧表面粗糙度大于所述衬底基板10朝向所述驱动电路层30的一侧表面粗糙度。因此，所述步骤S05还包括步骤S05-02：将所述显示基板进行翻转倒置，并在所述衬底基板10背离所述驱动电路层30的一侧的表面上形成一平坦层70，并形成贯穿所述平坦层70和所述衬底基板10的多个过孔，其中，所述数据线111和所述扫描线81通过贯穿所述平坦层70和所述衬底基板10的所述过孔与所述薄膜晶体管31电性连接，在所述衬底基板10背离所述驱动电路层30的方向上，所述过孔的开口面积逐渐增大。进一步的，将所述显示基板翻转倒置后，在所述衬底基板10背离所述驱动电路层30的一侧的表面上涂布有机光阻，并进行热固化，从而形成所述平坦层70。
图10为本申请实施例提供的在平坦层背离所述衬底基板的一侧形成数据线和扫描线的剖面示意图，参照图10，在本申请的一些实施例中，所述步骤S06包括：步骤S06-1：在所述平坦层70背离所述衬底基板10的一侧形成一第一金属层80，并对所述第一金属层80进行图案化，形成扫描线81，其中，所述扫描线81通过贯穿所述平坦层70和所述衬底基板10的第二过孔02与转接线315电性连接，再通过所述转接线315与薄膜晶体管31的栅极314电性连接；步骤S06-2：在所述第一金属层80背离所述平坦层70的一侧形成层间绝缘层90，并对所述层间绝缘层90进行蚀刻开孔；步骤S06-3：在所述层间绝缘层90背离所述第一金属层80的一侧形成第二金属层110，并对所述第二金属层110进行图案化，形成数据线111、VDD走线和VSS走线112，其中，所述数据线111通过贯穿所述平坦层70和所述衬底基板10的第一过孔01与薄膜晶体管31的源极312电性连接；所述VSS走线112通过贯穿所述平坦层70和所述衬底基板10的第三过孔03与所述第二绑定电极35电性连接，再通过所述第二绑定电极35与所述发光单元50的第二电极52电性连接。
再一方面，本申请还提供一种拼接显示装置，所述拼接显示装置包括壳体和上述任一项所述的多个显示面板，其中，所述壳体形成一容置空间，所述多个显示面板在所述容置空间阵列设置，且相邻的两个所述显示面板之间相互接触。
综上所述，本申请提供一种显示面板及其制备方法、拼接显示装置，显示面板包括：衬底基板；驱动电路层，设置于衬底基板的一侧，驱动电路层包括多个薄膜晶体管；多个发光单元，设置于驱动电路层背离衬底基板的一侧；多条扫描线和多条数据线，设置于衬底基板背离驱动电路层的一侧；其中，显示面板具有阵列排布的多个显示区域，每个显示区域内对应设置有一个发光单元，和一个分别与发光单元、扫描线、数据线电性连接的薄膜晶体管。本申请将用于向薄膜晶体管传输扫描信号、数据信号的扫描线、数据线设置在衬底基板背离驱动电路层的一侧，从而避免了在显示面板的侧面设置线路结构而导致的拼接缝隙大、生产良率低的问题，大大提升了拼接显示装置的显示效果。
以上对本申请实施例所提供的一种显示面板及其制备方法、拼接显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板的一侧，所述驱动电路层包括多个薄膜晶体管；
    多个发光单元，设置于所述驱动电路层背离所述衬底基板的一侧；
    多条扫描线和多条数据线，设置于所述衬底基板背离所述驱动电路层的一侧；
    其中，所述显示面板具有阵列排布的多个显示区域，每个所述显示区域内对应设置有一个所述发光单元，和一个分别与所述发光单元、所述扫描线、所述数据线电性连接的薄膜晶体管。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还具有设置于所述多个显示区域之间的间隙区域，其中，所述显示面板还包括设置于所述衬底基板和所述驱动电路层之间的缓冲层，所述缓冲层在所述间隙区域设置有凹槽。
  3. 根据权利要求2所述的显示面板，其中，任意相邻的两个所述显示区域组成一个显示区域组，各个所述显示区域组中的间隙区域内均设置有所述凹槽。
  4. 根据权利要求2所述的显示面板，其中，任意相邻的两个所述显示区域组成一个显示区域组，部分所述显示区域组中的间隙区域内设置有所述凹槽。
  5. 根据权利要求2所述的显示面板，其中，所述显示面板还包括设置于所述发光单元背离所述驱动电路层的一侧的封装层，所述封装层包括封装盖板，所述封装盖板的硬度大于所述衬底基板的硬度。
  6. 根据权利要求2所述的显示面板，其中，所述衬底基板背离所述驱动电路层的一侧的表面粗糙度大于所述衬底基板朝向所述驱动电路层的一侧的表面粗糙度，其中，所述显示面板还包括平坦层，所述平坦层设置于所述衬底基板背离所述驱动电路层的一侧的表面上，所述数据线、所述扫描线均位于所述平坦层背离所述衬底基板的一侧。
  7. 根据权利要求6所述的显示面板，其中，所述显示面板还包括多个贯穿所述衬底基板和所述平坦层的过孔，所述数据线和所述扫描线分别通过所述过孔与所述薄膜晶体管电性连接，其中，在所述衬底基板背离所述驱动电路层的方向上，所述过孔的开口面积逐渐增大。
  8. 根据权利要求6所述的显示面板，其中，所述显示面板还包括设置于所述平坦层背离所述衬底基板的一侧的第一金属层、设置于所述第一金属层背离所述平坦层的一侧的层间绝缘层、设置于所述层间绝缘层背离所述第一金属层的一侧的第二金属层，其中，所述第一金属层包括所述扫描线，所述第二金属层包括所述数据线。
  9. 一种显示面板的制备方法，其中，包括以下步骤：
    提供一承载板，在所述承载板的一侧形成一衬底基板；
    在所述衬底基板背离所述承载板的一侧形成一驱动电路层；
    在所述驱动电路层背离所述衬底基板的一侧形成多个发光单元；
    在所述驱动电路层、所述发光单元背离所述衬底基板的一侧形成一封装层，从而在所述承载板上形成一显示基板；
    将所述显示基板从所述承载板上剥离；
    在所述衬底基板背离所述驱动电路层的一侧形成多条数据线和多条扫描线，从而形成一显示面板；
    其中，所述显示面板具有阵列排布的多个显示区域，每个所述显示区域内对应设置有一个所述发光单元，和一个分别与所述发光单元、所述扫描线、所述数据线电性连接的薄膜晶体管。
  10. 根据权利要求9所述的显示面板的制备方法，其中，在所述承载板的一侧形成一衬底基板之后，还包括以下步骤：
    在所述衬底基板背离所述承载板的一侧形成一包括凹槽的缓冲层；
    其中，所述显示面板还具有设置于所述多个显示区域之间的间隙区域，所述缓冲层设置于所述衬底基板和所述驱动电路层之间，且所述凹槽位于所述间隙区域。
  11. 根据权利要求9所述的显示面板的制备方法，其中，将所述显示基板从所述承载板上剥离之后，还包括以下步骤：
    在所述衬底基板背离所述驱动电路层的一侧的表面上形成一平坦层，并形成贯穿所述平坦层和所述衬底基板的多个过孔。
  12. 一种拼接显示装置，其中，所述拼接显示装置包括壳体和多个显示面板，其中，所述壳体形成一容置空间，所述多个显示面板在所述容置空间阵列设置，且相邻的两个所述显示面板之间相互接触；其中，所述显示面板包括：衬底基板；驱动电路层，设置于所述衬底基板的一侧，所述驱动电路层包括多个薄膜晶体管；多个发光单元，设置于所述驱动电路层背离所述衬底基板的一侧；多条扫描线和多条数据线，设置于所述衬底基板背离所述驱动电路层的一侧；其中，所述显示面板具有阵列排布的多个显示区域，每个所述显示区域内对应设置有一个所述发光单元，和一个分别与所述发光单元、所述扫描线、所述数据线电性连接的薄膜晶体管。
  13. 根据权利要求12所述的拼接显示装置，其中，所述显示面板还具有设置于所述多个显示区域之间的间隙区域，其中，所述显示面板还包括设置于所述衬底基板和所述驱动电路层之间的缓冲层，所述缓冲层在所述间隙区域设置有凹槽。
  14. 根据权利要求13所述的拼接显示装置，其中，任意相邻的两个所述显示区域组成一个显示区域组，各个所述显示区域组中的间隙区域内均设置有所述凹槽。
  15. 根据权利要求13所述的拼接显示装置，其中，任意相邻的两个所述显示区域组成一个显示区域组，部分所述显示区域组中的间隙区域内设置有所述凹槽。
  16. 根据权利要求13所述的拼接显示装置，其中，所述显示面板还包括设置于所述发光单元背离所述驱动电路层的一侧的封装层，所述封装层包括封装盖板，所述封装盖板的硬度大于所述衬底基板的硬度。
  17. 根据权利要求13所述的拼接显示装置，其中，所述衬底基板背离所述驱动电路层的一侧的表面粗糙度大于所述衬底基板朝向所述驱动电路层的一侧的表面粗糙度，其中，所述显示面板还包括平坦层，所述平坦层设置于所述衬底基板背离所述驱动电路层的一侧的表面上，所述数据线、所述扫描线均位于所述平坦层背离所述衬底基板的一侧。
  18. 根据权利要求17所述的拼接显示装置，其中，所述显示面板还包括多个贯穿所述衬底基板和所述平坦层的过孔，所述数据线和所述扫描线分别通过所述过孔与所述薄膜晶体管电性连接，其中，在所述衬底基板背离所述驱动电路层的方向上，所述过孔的开口面积逐渐增大。
  19. 根据权利要求17所述的拼接显示装置，其中，所述显示面板还包括设置于所述平坦层背离所述衬底基板的一侧的第一金属层、设置于所述第一金属层背离所述平坦层的一侧的层间绝缘层、设置于所述层间绝缘层背离所述第一金属层的一侧的第二金属层，其中，所述第一金属层包括所述扫描线，所述第二金属层包括所述数据线。
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